Control Processor

Test Specification
Magellan Document: N/A
Version: N/A

DDME Dataset: XSNQ03BG FM00

Stream: 01
Issue: 02

Authour: Larry Hum

Release Date: March 28, 2007

WARNING: The data herein are not to be used or disclosed without the consent of Nortel
Networks. This note is a working paper intended for limited circulation and discussion. No
departmental or corporate approval or commitment is implied, unless such approval or
commitment is expressly given in a covering document.

© Copyright Nortel Networks, 2007.

This document contains 9 pages.
This document was processed 2007-03-28 15:40.
Control Processor Test Specification

Table of Contents
Publication History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Required Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. In-circuit test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2. Processor module test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Functional test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.1. VCXO Accuracy and Network Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4. System test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

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Control Processor Test Specification

Publication History

STR/ISS Reason for Change

01/01 Initial release based on XSBP14BA FM00 01/01 with add test
specification for the VCXO.
01/02 Update test specifications to apply only to CP/BITS and CP/BITS/SETS
cards.
Update test specifications for VCXO from 4.6 ppm to account for NEW
and AGED VCXO as per device specification.

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Control Processor Test Specification Introduction

1. Introduction
1.1. Applications
The purpose of this document is to outline the test procedure for the MSS control processor (CP/
BITS, and CP/BITS/SETS - PEC NTNQ03xx). The tests outlined in this document should be
applied to every CP/BITS, and CP/BITS/SETS prior to shipment. The testing procedure has been
broken into four general groups
• In-circuit test
• Processor module test
• Functional test
• System test
The in-circuit test and the processor module test are performed on the individual printed circuit
boards (PCB) before they are mated. The functional and system testing is performed on the fully
assembled Control Processor pack. The following sections will outline the objective of each
group of tests and the functionality that is verified.

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Control Processor Test Specification Required Tests

2. Required Tests
This chapter describes, and outlines the objectives of, the tests that are performed on the CP/BITS
or CP/BITS/SETS.

2.1. In-circuit test

The objective of the In-circuit test is to detect manufacturing faults and defective components.
The completed circuit module (PM, FP, or CP) is placed into an in-circuit fixture (bed of nails)
that probes pre-determined test points on the PCB. Test suites are then run which check for:
• shorts and opens
• traditional in-circuit tests of analog parts
• per pin CRC check of all SSI/MSI devices
Following the in circuit test, the circuit module is known to be free of solder shorts/opens, and
non-functional or incorrectly inserted components.
The in circuit test should cover at least 85% of the pins. Discrete components should be verified.
Power should be applied to components where applicable and outputs verified while injecting test
vectors.

2.2. Processor module test

The test procedure for the processor module is described in the document XSBP13EA.

2.3. Functional test

The functional test verifies that all the systems on the Control Processor operate correctly. At this
stage the CP is complete, and consists of a CP interface module (IM), a PM, and a disk drive. The
objective of this test is to find incorrectly mated components, and any functional deficiencies that
escape the in-circuit test. The functional test process for the CP is as follows:
• boot-up self tests
• real time clock self tests
• ethernet port functionality (pings through network)
• SBIC self tests
• bus control system self tests
• back plane card to card communication (pings across X & Y busses on backplane)
• disk access
• disk copy (image copy through ethernet port)
• disk read verification
• VCXO accuracy.
Functional testing should cover at least 95% of the pins. While running production SW, and using

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Control Processor Test Specification Required Tests

custom SW and scripts where applicable, each of the boards separate circuits should be verified.
Following the functional test the individual circuit pack is known to be operating within its design
specifications.

2.3.1. VCXO Accuracy and Network Synchronization

The objective of this test is to ensure that the frequency of the VCXO on the circuit pack is within
the manufacturer’s specification and that the CP will lock onto a BITS timing source that is
traceable to a STRATUM 2 or higher clock.
Connect a BITS timing source (framed E1, framed DS1, or 2048 kHz clock) to one or both of the
BITS port on of the CP. Provision the CP for external timing as based on the BITS source with the
primary network synchronization set to the BITS port. Insert the CP into slot 0 and wait for the
Network to synchronized. Then read consecutively, 10 times, the contents in the PLL/DAC and
Phase Difference registers. The address and acceptable values for these registers are listed in
Table 1 on page 6 and Table 2 on page 6, respectively.
.
Table 1: CP PLL/DAC Register

Parameter Value Comment

Address BA000028.h
Centre f xxxx6666.h ‘x’ denotes don’t care
Min(1) xxxx5532.h -2.1 ppm limit for new device
Max(1) xxxx7799.h +2.1 ppm limit for new device
Min(2) xxxx40B7.h -4.6 ppm limit for aged device
Max(2) xxxx8C14.h +4.6 ppm limit for aged device

Table 2: CP Phase Difference Register

Parameter Value Comment

Address BA000024.h
Min xxxxx000.h 0° phase difference; ‘x’ denotes don’t care
Max xxxxx9FF.h 360° phase difference; ‘x’ denotes don’t care
Deviation ±3 All values must be within ±1.5 of the average

2.4. System test

The object of the system test is to ensure that no unprotected interactions exist between the
various components of the MSS switch, and to identify any components which are prone to infant
mortality. The CP is operated in a MSS 7480, MSS 7560, MSS 7440, or MSS 7420 with a full
complement of FPs for a period of 18 hours at ambient room temperature. System test verifies the

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Control Processor Test Specification Required Tests

following on the CP:

• operator port functionality
• ability to crossload all CPs/FPs across backplane
• shelf bus test (self tests, clock source tests, broadcast tests, ping tests)
• ability to read the MAC address range from the terminator card
• disk synchronization
• monitoring of all cards in shelf during testing (port management and shelf card tests)
• alarm reporting (minor and major alarms)
After system test the pack is ready to be shipped to the customer site. At this stage the
functionality of the pack has been verified and any marginal components should have been
spotted.

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Control Processor Test Specification References

3. References
1. “Control Processor IIE General Specification”, Nortel Networks, July 2002, MD-1997.0517,
GSNQ03BG FM00 str:01 iss:01.
2. “CP IM (NTBP14BA) TEST SPECIFICATION”, Nortel Networks, May 1996, XSBP14BA
FM00 str:01 iss:01
3. “Passport- NTFP60AA (CFP1) Interface Module Hardware Test Specification”, Nortel
Networks, February 1997, XSFP60AA FM00 str:01 iss:01.
4. “Control and Function Processor (CFP1) Test Specification”, Nortel Networks, January 2007,
XSNN02AA FM00 str:01 iss:01.
5. CR Q01482391, discussions and various attachments linked to the CR report
6. NPS25085-76, Crystal Oscillators Temperature Compensated, Voltage Controlled STRATUM
3.

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Control Processor Test Specification

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