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1. It is a small fast array of memory placed between the processor core and main memory that
store portions of recently referenced main memory.
a. Cache
b. Main memory
c. Registers
a. Capacity
b. Location
c. Performance
3. This is the time it takes to perform a read and write operation, that is, the time from the instant
that an address is presented to the memory to the instant that data have been stored or made
available for use.
4. This is the rate at which data can be transferred into or out of a memory unit.
6. It is a memory characteristic which information decays naturally or lost when electrical power is
switched off.
a. Volatile Memory
b. Nonvolatile Memory
c. ROM
7. It is a type of access method which starts at the beginning and read through in order.
8. It is a type of access method which individual blocks or records have unique address based on
physical location.
a. Cache
b. Registers
c. RAM
a. Main Memory
b. Physical Cache
c. Logical Cache
11. A mapping technique that maps each block of main memory into only one possible cache line.
a. Direct Mapping
b. Associative Mapping
c. Set-Associative Mapping
a. Addressable Units
b. Word
c. Unit of Transfer
13. It is the physical arrangement of bits to form word.
a. Physical Characteristics
b. Performance
c. Organization
14. This occurs when the information or data needed by the CPU is available in Cache.
a. Cache Hit
b. Cache Miss
c. Victim Cache
15. This occurs when the information or data needed by the CPU is not available in Cache.
a. Cache Hit
b. Cache Miss
c. Victim Cache
II
1. What is the general relationship among access time, memory cost, and capacity?
Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater capacity, slower
access time.
2. What are the differences among direct mapping, associative mapping, and set associative mapping?
In a cache system, direct mapping maps each block of main memory into only one possible cache line.
Associative mapping permits each main memory block to be loaded into any line of the cache. In set-
associative mapping, the cache is divided into a number of sets of cache lines; each main memory
block can be mapped into any line in a particular set.
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