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Features Applications
• USB-2.0 Device Controller • Serial Attached Devices
• On-Chip USB-2.0 PHY • Modems, Serial Mouse, Generic Serial
• On-Chip Voltage Regulators Devices
• Four 16c450/16c550 compatible UARTs • Serial-Port Server
• Supports SIR IrDA Mode on any/all ports • Data Acquisition System
• Supports RS-232, RS-485 and RS-422 • POS Terminal & Industrial PC
Serial Ports
• 5, 6, 7 & 8-bit Serial Data support Application Note
• Hardware and Software Flow Control • AN-7840
• Serial Port speeds from 50 bps to 6 Mbps
• Custom BAUD Rates supported through Evaluation Board
external clock and/or by programming the • MCS7840-EVB
internal PLL
• On-Chip 512-Byte FIFOs for upstream and Package
downstream data transfers for each Serial • 64-pin LQFP Package
Port
• Supports Remote Wakeup and Power Driver Support
Management features • Windows
• Serial Port Transceiver Shut-Down (98SE / ME / 2000 / XP / 2003 Server)
support • Linux Kernel 2.6.5 and above
• Two-Wire I2C Interface for EEPROM • MAC 10.2 & above
• EEPROM read/write through USB • Windows CE5.0
• iSerial feature support with EEPROM • Windows Vista
• One Bi-directional multi-function GPIO
• On-Chip buffers for Serial Port signals to
operate without external Transceivers over Utility Support
short cable lengths • Windows based EEPROM Tool
• Bus-Powered Device • Mass Production Utility
General Description
The MCS7840 is a USB-2.0 to Quad-Serial Port
device. It has been developed to connect a wide
range of standard serial devices to a USB host.
MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708
MCS7840
USB-2.0 to Four Serial Ports
Block Diagram
SCL SDA
Interrupt-In
2
I C EEPROM Block
Controller
Wake-Up
Serial Port DTR
Block
x4
RTS
TXD
Tx
Buffer
DP Bulk
In
DM FIFOs
RXD
USB-2.0 Rx
XTAL OUT USB-2.0 DCD
Device Bridge Buffer
PHY Controller CTS
Bulk RI
XTAL IN Out DSR
FIFOs
VSPEC_CMD_
Processor
Clock
Recovery Resets
BAUD Clock
Generator
x4
Ext_Clock
PLL
Pin-Out Diagram
50 EXT_CLOCK
62 DCD_3_N
54 DCD_2_N
61 DSR_3_N
53 DSR_2_N
57 DTR_3_N
63 CTS_3_N
55 CTS_2_N
58 RTS_3_N
60 RI_3_N
52 RI_2_N
59 RXD_3
56 TXD_3
49 GNDK
51 Vcc3IO
64 VccK
GNDK 1 48 RXD_2
USB_XSCI 2 47 RTS_2_N
USB_XSCO 3 46 DTR_2_N
VccA 4 45 TXD_2
GNDA 5 44 EE_SDA
USB_RREF 6 43 EE_SCL
USB_DM 7 42 RESET
USB_DP 8 41 GPIO
VccA
MCS7840CV 40 VCC3IO
9
GNDA 10 39 VccK
VccK 11 38 GND18A_PLL
TEST_MODE 12 37 Vcc18A_PLL
TXD_4 13 36 REG02_V18
DTR_4_N 14 35 GND5A
RTS_4_N 15 34 VCC5A
RXD_4 16 33 REG06_VCC33
RI_4_N 17
DSR_4_N 18
DCD_4_N 19
CTS_4_N 20
TXD_1 21
DTR_1_N 22
RTS_1_N 23
RXD_1 24
RI_1_N 25
VccK 26
GNDK 27
Vcc3IO 28
DSR_1_N 29
DCD_1_N 30
CTS_1_N 31
SHTD_1_N 32
Pin Assignments
Overview
The UARTs are high performance serial ports that comply with the 16c550 specification. All UARTs are similar
in operation and function, and are described in this section. The function of a single UART is described below.
Operation Modes
The UARTs are backward compatible with 16c450 and 16c550 devices. The operation of the port depends
upon the mode settings, which are described throughout the rest of this section. The modes, conditions and
corresponding FIFO depth are tabulated below.
The transmitter and receiver FIFOs (referred to as In 16c550 mode, the device has the following
the “Transmitter Holding Register” and “Receiver features:
Holding Register” respectively) have a depth of • RTS/CTS hardware flow control or
one. DSR/DTR hardware flow control
• Infrared IrDA format transmit & receive
This mode of operation is known as “Byte Mode”. mode
• Deeper (16-Byte) FIFOs
The UART has 10 registers, but only three address lines to access those registers. The mapping of the
registers is dependent upon the Line Control Register (LCR).
The following table gives the various UART registers and their offsets.
Register
Offset R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Name
THR 0 W Data to be transmitted ( Transmitter Holding Register)
RHR 0 R Data to be received (Receiver Holding Register)
Rx
Modem Tx Rdy Rx Rdy
Sleep Stat
IER 1 R/W Reserved Int Int Int
Mode Int
Mask Mask Mask
Mask
RHR Flush Flush FIFO
FCR 2 W Reserved Reserved
Trigger Level THR RHR Enable
FIFOs Interrupt
ISR 2 R Reserved Interrupt Priority
Enabled Pending
Tx Force Odd/Even Parity Stop
LCR 3 R/W DLE Data Length
Break Parity Parity Enable Bits
DTR – DSR/ RTS/CTS
MCR 4 R/W DCD Flow Loop Unused RTS DTR
Flow Control Control
Data Tx THR Rx Framing Parity Overrun Rx
LSR 5 R
Error Empty Empty Break Error Error Error Rdy
MSR 6 R DCD RI DSR CTS ΔDCD Teri ΔDSR ΔCTS
SPR 7 R/W Scratch Pad Register
Additional standard registers - these are accessed when LCR[7] = 1
DLL 0 R/W Divisor Latch bits[7:0]
DLM 1 R/W Divisor Latch bits[15:8]
Transmitter Holding Register & Receiver Holding Register (THR & RHR):
Data is written into the bottom of the THR queue & read from the top of the RHR queue completely
asynchronously to the operation of the transmitter & receiver. The size of the FIFOs is dependent upon the
setting of the FCR register.
Data written to the THR when it is full, is lost. Data read from the RHR when it is empty, is invalid. The empty
and full status of the FIFOs is indicated in the Line Status Register.
Register: THR
Description: Data to be transmitted
Offset: 0
Permissions: Write Only
Access Condition: LCR[7] = 0
Default Value: (unknown) – based on memory
Register: RHR
Description: Data to be received
Offset: 0
Permissions: Read Only
Access Condition: LCR[7] = 0
Default Value: (unknown) – based on memory
Register: IER
Description: Interrupt Enable Register
Offset: 1
Permissions: Read/Write
Access Condition: LCR[7] = 0
Default Value: 0x0C
Register: FCR
Description: FIFO Control Register
Offset: 2
Permissions: Write
Access Condition:
Default Value: 0x00
Register: ISR
Description: Interrupt Status Register
Offset: 2
Permissions: Read
Access Condition:
Default Value: 0x00
Register: LCR
Description: Line Control Register
Offset: 3
Permissions: Read/Write
Access Condition:
Default Value: 0x00
Register: LSR
Description: Line Status Register
Offset: 5
Permissions: Read
Access Condition:
Default Value: 0x00
Register: MCR
Description: Modem Control Register
Offset: 4
Permissions: Read/Write
Access Condition:
Default Value: 0x00
550 Mode
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
CTS/RTS Internal
DTR-DSR/DCD
Flow Loop Back Reserved Reserved RTS DTR
Flow Control
Control Enable
Register: MSR
Description: Modem Status Register
Offset: 6
Permissions: Read
Access Condition:
Default Value: 0x00
Register: SPR
Description: Scratch Pad Register
Offset: 7
Permissions: Read/Write
Access Condition:
Default Value: 0x00
After the hardware reset, the BAUD Rate used by the transmitter & receiver is given by:
BAUD Rate = Input Clock / (16 * Divisor)
where divisor is given by (256 * DLM) + DLL.
Register: DLL
Description: Divisor Latch (Least Significant Byte)
Offset: 0
Permissions: Read/Write
Access Condition: LCR[7] = 1
Default Value: 0x01
Register: DLM
Description: Divisor Latch (Most Significant Byte)
Offset: 1
Permissions: Read/Write
Access Condition: LCR[7] = 1
Default Value: 0x00
RS-485 RS-422
The RS-485 mode can be set using the Scratch This is the full duplex mode.
Pad Register bit[6] and bit[7] for each serial port.
This mode will work without the use of the DTR
This mode is a half duplex mode and the external signal for external transceiver control.
transceiver is controlled for transmission or
reception using the enable signal.
This is the
1 1
default
selection when
RS485 mode
is selected
through driver
property sheets.
Configuration Options
Four serial ports can be configured for operation.
To program and access the serial ports via software, endpoint numbers have been assigned so that serial
ports can be configured from the USB side.
Size (Bytes)
Endpoint Type Function
(USB-1.1 / USB-2.0)
0 Control Endpoint Default Functionality 8 / 64
1 Bulk-In Serial Port – 1 64 / 512
2 Bulk-Out Serial Port – 1 64 / 512
3 Bulk-In Serial Port – 2 64 / 512
4 Bulk-Out Serial Port – 2 64 / 512
5 Bulk-In Serial Port – 3 64 / 512
6 Bulk-Out Serial Port – 3 64 / 512
7 Bulk-In Serial Port – 4 64 / 512
8 Bulk-Out Serial Port – 4 64 / 512
9 Interrupt Status Endpoint 5 or 13 *
* Controlled by DCR1 bit-6
Wvalue specifies the application number and data to be written (ww = data).
• 0x01ww is the application number for Serial Port-1
• 0x02ww is the application number for Serial Port-2
• 0x03ww is the application number for Serial Port-3
• 0x04ww is the application number for Serial Port-4
• 0x09ww is the application number for EEPROM Write/Read
• 0x00ww is the application number provided for accessing the Control Registers which control the
UARTs. It is possible to enable higher BAUD rates, and features like auto hardware flow control using
the Control Registers
Note: “N” in Wvalue and Register Name columns indicate the corresponding serial port number.
Register
bmrequestType Brequest Wvalue Windex Wlength
Name
0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_RHR
0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_IER
0xC0 0x0D 0x0N00 0x0002 0x0001 SPN_IIR
Get Application 0xC0 0x0D 0x0N00 0x0003 0x0001 SPN_LCR
Vendor Specific 0xC0 0x0D 0x0N00 0x0004 0x0001 SPN_MCR
Command
(Serial Port -N) 0xC0 0x0D 0x0N00 0x0005 0x0001 SPN_LSR
0xC0 0x0D 0x0N00 0x0006 0x0001 SPN_MSR
0xC0 0x0D 0x0N00 0x0007 0x0001 SPN_SPR
0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_DLL
0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_DLM
Register
bmrequestType Brequest Wvalue Windex Wlength
Name
0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_THR
0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_IER
0x40 0x0E 0x0Nww 0x0002 0x0001 SPN_FCR
Set Application
Vendor Specific 0x40 0x0E 0x0Nww 0x0003 0x0001 SPN_LCR
Command 0x40 0x0E 0x0Nww 0x0004 0x0001 SPN_MCR
(Serial Port -N) 0x40 0x0E 0x0Nww 0x0005 0x0001 SPN_LSR
0x40 0x0E 0x0Nww 0x0006 0x0001 SPN_MSR
0x40 0x0E 0x0Nww 0x0007 0x0001 SPN_SPR
0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_DLL
0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_DLM
Configuration
Index Data
Descriptor
BLength 0 8’h09
BDescriptorType 1 8’h02
WtotalLength(L) 2 8’h51
USB WtotalLength(M) 3 8’h00
Configuration
Descriptors BNumInterfaces 4 8’h01
BConfigurationValue 5 8’h01
IConfiguration 6 8’h00
BmAttributes 7 8’hA0
8’h32
BMaxPower 8
(100 mA)
Configuration
Index Data
Descriptor
BLength 0 8’h09
BDescriptorType 1 8’h04
BInterfaceNumber 2 8’h00
USB
Interface BAlternateSetting 3 8’h00
Descriptors BNumEndpoints 4 8’h09
BInterfaceClass 5 8’hFF
BInterfaceSubClass 6 8’h00
BInterfaceProtocol 7 8’hFF
IInterface 8 8’h00
Bytes 4, 5, 6 and 22-30 form twenty-four 8-bit DCR Registers. These Bytes are read from the EEPROM, and
loaded into the Global Device Configuration Registers after Power-On Reset. They can be programmed by
software using the following application number and register indexes as shown in the table.
The following tables describe the function of each bit in the DCR registers. There are three DCR registers
for each Serial Port (IrDA). In the absence of an EEPROM, the default values are taken from the Device
Configuration Registers.
DCR0 Default
Name Definition
Bit Value
RS-232 / RS-422 / RS-485
Transceiver Shut-Down Mode:
DCR1 Default
Name Definition
Bit Value
These two bits set the output current
of the GPIO lines:
GPIO_I_
[1:0] 00: 6 mA 01
PMG
01: 8 mA (Default)
10: 10 mA
11: 12 mA
These two bits set the output current
of Serial output signals TxD, DTR_n and RTS_n:
Tx_I_
[3:2] 00: 6 mA 01
PMG
01: 8 mA (Default)
10: 10 mA
11: 12 mA
RW_INH Remote Wake Inhibit:
RW_
4 0
INHB 0: Enable the USB Remote Wakeup function
1: Inhibit the USB Remote Wakeup function
PLL_
Power-Down 0: Enables PLL Power-Down
5 0
Bypass 1: Disables PLL Power-Down
Control
Interrupt IN 0: Interrupt Endpoint returns 5 Bytes of data.
6 Endpoint 1: Interrupt Endpoint returns 5 Bytes + 8 Bytes of the Bulk-In/Out 0
Status memory controller status
7 Reserved Reserved 1
DCR2 Default
Name Definition
Bit Value
Enable Wake Up Trigger on CTS:
EWU_
0 0
CTS 0: Disabled
1: Enable Wake Up Trigger on CTS State Changes.
Enable Wake Up Trigger on DCD:
EWU_
1 0
DCD 0: Disabled
1: Enable Wake Up Trigger on DCD State Changes.
Enable Wake Up Trigger on RI:
EWU_
2 1
RI 0: Disabled
1: Enable Wake Up Trigger on RI State Changes.
Enable Wake Up Trigger on DSR:
EWU_
3 0
DSR 0: Disabled
1: Enable Wake Up Trigger on DSR State Changes.
Enable Wake Up Trigger on RXD:
EWU_
4 0
Rx 0: Disabled
1: Enable Wake Up Trigger on RXD State Changes.
Remote Wakeup Mode:
Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0.
DCR0 Default
Name Definition
Bit Value
RS-232 / RS-422 / RS-485
Transceiver Shut-Down Mode:
DCR1 Default
Name Definition
Bit Value
[1:0] Reserved Reserved 00
These two bits set the output current
of Serial output signals TxD, DTR_n and RTS_n:
Tx_I_
[3:2] 00: 6 mA 01
PMG
01: 8 mA (Default)
10: 10 mA
11: 12 mA
RW_INH Remote Wake Inhibit:
RW_
4 0
INHB 0: Enable the USB Remote Wakeup function
1: Inhibit the USB Remote Wakeup function
5 Reserved Reserved 0
6 Reserved Reserved 0
7 Reserved Reserved 1
DCR2 Default
Name Definition
Bit Value
Enable Wake Up Trigger on CTS:
EWU_
0 0
CTS 0: Disabled
1: Enable Wake Up Trigger on CTS State Changes.
Enable Wake Up Trigger on DCD:
EWU_
1 0
DCD 0: Disabled
1: Enable Wake Up Trigger on DCD State Changes.
Enable Wake Up Trigger on RI:
EWU_
2 1
RI 0: Disabled
1: Enable Wake Up Trigger on RI State Changes.
Enable Wake Up Trigger on DSR:
EWU_
3 0
DSR 0: Disabled
1: Enable Wake Up Trigger on DSR State Changes.
Enable Wake Up Trigger on RXD:
EWU_
4 0
Rx 0: Disabled
1: Enable Wake Up Trigger on RXD State Changes.
Remote Wakeup Mode:
Note: Wake up defined above can work only when DCR0[6] = 0 and DCR1[4] = 0.
Electrical Specifications
Operating Conditions:
HE
64 49
1 48
16 33
17 32
D
HD
e b
A2
A1
c
Millimeters
Symbol
MIN TYP MAX
A1 0.05 0.15
A2 1.35 1.45
b 0.17 0.27
c 0.09 0.20
64-Pin “CV” LQFP
e 0.50
Package Dimensions
L 0.45 0.75
HD 11.75 12.25
D 9.90 10.10
HE 11.75 12.25
E 9.90 10.10
IMPORTANT NOTICE
MosChip Semiconductor Technology, LTD products are not authorized for use as critical components in life
support devices or systems. Life support devices are applications that may involve potential risks of death,
personal injury or severe property or environmental damages. These critical components are semiconductor
products whose failure to perform can be reasonably expected to cause the failure of the life support systems
or device, or to adversely impact its effectiveness or safety. The use of MosChip Semiconductor Technology
LTD’s products in such devices or systems is done so fully at the customer risk and liability.
As in all designs and applications it is recommended that the customer apply sufficient safeguards and guard
bands in both the design and operating parameters. MosChip Semiconductor Technology LTD assumes no
liability for customer’s applications assistance or for any customer’s product design(s) that use MosChip
Semiconductor Technology, LTD’s products.
MosChip Semiconductor Technology, LTD warrants the performance of its products to the current specifications
in effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip
Semiconductor Technology, LTD imposes testing and quality control processes that it deems necessary to
support this warranty. The customer should be aware that not all parameters are 100% tested for each device.
Sufficient testing is done to ensure product reliability in accordance with MosChip Semiconductor Technology
LTD’s warranty.
MosChip Semiconductor Technology, LTD believes the information in this document to be accurate and reliable
but assumes no responsibility for any errors or omissions that may have occurred in its generation or printing.
The information contained herein is subject to change without notice and no responsibility is assumed by
MosChip Semiconductor Technology, LTD to update or keep current the information contained in this document,
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Revision History