Ee6602 Esd Notes

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SYLLABUS
EE6602 EMBEDDED SYSTEMS LT P C 3 0 0 3
UNIT I INTRODUCTION TO EMBEDDED SYSTEMS 9

Introduction to Embedded Systems – The build process for embedded systems-
Structural units in Embedded processor , selection of processor & memory devices-
DMA – Memory management methods- Timer and Counting devices, Watchdog Timer,
Real Time Clock, In circuit emulator, Target Hardware Debugging.
UNIT II EMBEDDED NETWORKING 9
Embedded Networking: Introduction, I/O Device Ports & Buses– Serial Bus
communication protocols - RS232 standard – RS422 – RS485 - CAN Bus -Serial
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Peripheral Interface (SPI) – Inter Integrated Circuits (I2C) –need for device drivers.
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UNIT III EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT
Embedded Product Development Life Cycle- objectives, different phases of
9
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EDLC, Modelling of EDLC; issues in Hardware-software Co-design, Data Flow Graph,
state machine model, Sequential Program Model, concurrent Model, object oriented
Model. En
UNIT IV
gi RTOS BASED EMBEDDED SYSTEM DESIGN
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Introduction to basic concepts of RTOS- Task, process & threads, interrupt
9
r
routines in RTOS, Multiprocessing and Multitasking, Preemptive and non-preemptive
ing
scheduling, Task communication shared memory, message passing-, Inter process
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Communication – synchronization between processes-semaphores, Mailbox, pipes,
priority inversion, priority inheritance, comparison of Real time Operating systems: Vx
Works, чC/OS-II, RT Linux.
UNIT V EMBEDDED SYSTEM APPLICATION DEVELOPMENT
t 9
Case Study of Washing Machine- Automotive Application- Smart card System
Application,.
TOTAL: 45 PERIODS
TEXT BOOKS:
1. Rajkamal, ‗Embedded System-Architecture, Programming, Design‘, Mc Graw Hill,
2013.
2. Peckol, ―Embedded system Design‖, John Wiley & Sons,2010
3. Lyla B Das,‖ Embedded Systems-An Integrated Approach‖, Pearson, 2013
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REFERENCES:
1. Shibu. K.V, ―Introduction to Embedded Systems‖, Tata Mcgraw Hill,2009.
2. Elicia White,‖ Making Embedded Systems‖, O‘ Reilly Series,SPD,2011.
3. Tammy Noergaard, ―Embedded Systems Architecture‖, Elsevier, 2006.
4. Han-Way Huang, ‖Embedded system Design Using C8051‖, Cengage
Learning,2009.
5. Rajib Mall ―Real-Time systems Theory and Practice‖ Pearson Education, 2007.
Web resources
http://nptel.iitk.ac.in/courses/Webcourse-
ww contents/IIT%20Kharagpur/Embedded%20systems/New_index1.html
http://www.ecs.umass.edu/ece354/ECE354HomePageFiles/Labs_files/01bigPic
w. E ture.pdf
http://patricklam.ca/ece155/lectures/
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http://studentsblog100.blogspot.in/2013/02/embedded-systems-notes-anna-
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university.html
Aim:
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1. Aim &Objective of the subject
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skills. r
To understand the basic concepts and to develop the embedded system designing
ing
Objective:
 To introduce the building blocks of embedded systems. .ne
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 To make the students understand I/O interfacing and bus communication.
 To impart knowledge in various program modeling concepts.
 To educate the designing of RTOS based embedded systems.
 To make the students study the hardware and software designing of real
time applications.
2. Need and Importance for study of the subject
Embedded system is essential for doing the final year projects and also nowadays embedded
system plays a vital role in various disciplines.
3. Course outcomes
At the end of the course the student should be able to
 Recognize the key features of embedded systems

 Become aware of the concepts of embedded networking

 Utilize a modular design process to complete a embedded system design
project .
 Design, test and critically evaluate embedded solutions to real world situations using
digital components
 Analyze various examples of embedded systems
4. Industrial Connectivity and latest development
Industrial Connectivity:
 Automotive industries
 Networking field
 Mobile phones
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 Automotives, and Smart card
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 Robotics
Latest development:
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 Unmanned air vehicle
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 Structural health monitoring
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EE6602 EMBEDDED SYSTEMS
DETAILED COURSE PLAN
TEXT BOOKS:
T1. Rajkamal, ‗Embedded System-Architecture, Programming, Design‘, Mc Graw Hill,
2013.
T2. Peckol, ―Embedded system Design‖, John Wiley & Sons,2010
REFERENCEBOOKS:
R1. Shibu. K.V, ―Introduction to Embedded Systems‖, Tata Mcgraw Hill,2009
R3. Tammy Noergaard, ―Embedded Systems Architecture‖, Elsevier, 2006.
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Sl.
No of Cumulative
Hours
Boo
k
w. E
No.
UNIT Topics Hour
s No.
asy
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UNIT I INTRODUCTION TO EMBEDDED SYSTEMS
1
gi Introduction
Systems
to Embedded
nee
1 1
T1
2
The build process for embedded
systems r 1
ing 2
T2
3
Structural units in Embedded
1 .ne
3
T1
UNIT 1
processor
selection of processor & memory

t T1
4 1 4
devices
5 DMA 1 5 T1
6 Memory management methods 1 6 T1
Timer and Counting devices, T1

7 1 7
Watchdog Timer

No of Cumulative Boo
Sl. Hours k
UNIT Topics Hour
No.
s No.
Real Time Clock, In circuit T1

8 1 8
emulator
9 Target Hardware Debugging 1 9 T1
UNIT II EMBEDDED NETWORKING
ww
10
Embedded
Introduction,
Networking:
1 10 R3
11w. E I/O Device Ports & Buses 1 11 R3
12
asy Serial Bus communication
1 12
R3
En protocols
13
14
gi RS232 standard
RS422 – RS485 nee

1
1
13
14
R3
T1
15
UNIT 2
CAN Bus r 1
ing 15 R3
16 Serial Peripheral Interface (SPI). 1

.ne
16 R3
17
18
Inter Integrated Circuits (I2C)
Need for device drivers

1
1
17
18
t T1
R3
UNIT III EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT
Embedded Product
19 Development Life Cycle- 1 19 R1
UNIT 3 objectives.
Different phases of EDLC T1,R

20 1 20
1

Sl. Hours k
UNIT Topics Hour
No.
s No.
21 Modeling of EDLC 1 21 R1
Issues in Hardware-software Co-

22 1 22 T1
design,
23 Data Flow Graph, 1 23 T1
24 State machine model, 1 24 T1
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25 Sequential Program Model, 1 25 T1
26
w. E Concurrent Model, 1 26 T1
27
asy Object oriented Model. 1 27 T1
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UNIT IV RTOS BASED EMBEDDED SYSTEM DESIGN
28 gi Introduction to basic concepts of

RTOS nee 1 28 R1
29 Task, process & threads

r 1
ing 29 R1
30 Interrupt routines in RTOS 1

.ne
30 R1
31
Multiprocessing
Multitasking,
and
1 31
t T1,R
1,
R3
Preemptive and non-preemptive R1

32 1 32
scheduling
Task communication shared T

33 1 33
memory
UNIT 4
34 Message passing 1 34 T2

Sl. Hours k
UNIT Topics Hour
No.
s No.
35 Inter process Communication 1 35 T2
Synchronization between T1
36 processes- semaphores, 1 36
Mailbox, pipes
Priority inversion, Priority

37 1 37 T1
inheritance
ww Comparison of Real time

T1,R
38
w. E Operating systems: Vx Works ,
чC/OS-II
1 38
1
39
asy RT Linux 1 39
T1,R
En 1
40
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UNIT V EMBEDDED SYSTEM APPLICATION DEVELOPMENT
Case Study of Washing Machine nee 2 41 R1
41 UNIT 5 Automotive Application r 2 ing 43 T1
42 Smart card System Application 2 .ne

45 T1

INDEX
UNIT Q.NO TITLE PAGE
NO.
1-15 PART A 1
PART B
1 Build process 3
2 Structural units 6
I
3 DMA &Memory management 10
4 ICE & Timer/Counter 13
5 Selection of processor 17
6 Target Hardware debugging 21
1-13 PART A 26
PART B
1 SPI protocol and Interface 27
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II 2
3
I2C Bus
CAN Bus
29
31
w. E 4
5
RS232&RS485
IO ports & UART
33
37
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1-10 PART A
PART B
43
III
1
2En Objectives of EDLC
Phases of EDLC
44
46
3
4
5
giApproaches of EDLC
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Issues in hardware and software co-design
Computational models
51
55
57
1-15 PART A
PART B r ing 61
1
2
Pre-emptive and non pre-emptive scheduling
Interrupt routines .ne 62
65
IV
3
4
5
Process, Threads and Tasks
Multitasking
Semaphore, Mailbox and Pipes
t 69
72
75
6 Shared memory, message passing, priority inheritance 79
and priority inversion
7 µC/OS – II,Vx-Works and RT Linux 85
1-10 PART A 98
PART B
V 1 Washing machine design 99
2 Automotive application 104
3 Design and interface of smart card system 108
University Question 114

UNIT-1 - INTRODUCTION TO EMBEDDED SYSTEMS

PART A (2 marks)
1. Define Embedded System. What are the components of embedded system?
An Embedded system is one that has computer hardware with software embedded in it
as one of its most important component. The three main components of an embedded
system are (i) Hardware (ii) Main application software (iii) RTOS
2. What are the types of embedded system?
Small scale embedded systems
Medium scale embedded systems
Sophisticated embedded systems
3. Name some of the hardware parts of embedded systems.
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w. E Clock oscillator circuit

Timers
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Memory units
DAC and ADC
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LCD and LED displays
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Keyboard/Keypad
4. Give the characteristics of embedded system.
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Single-functioned
Tightly constrained r ing
Reactive and real time
5. What are the steps involved in the build process. .ne
The steps involved are
Preprocessing
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Compiling
Linking
Locating
6. What is a compiler and a cross compiler?
Compiler: Compiler is a program that creates an object file from the source codes. It
checks the language grammar/semantics. For eg: tcc. It converts high level language
codes into machine codes.

Cross Compiler: A compiler that runs on one computer platform and produces code for
another is called a cross-compiler. The use of a cross-compiler is one of the defining
features of embedded software development.
7. List the important considerations when selecting a processor.
Instruction set
Maximum bits in an operand
Clock frequency
Processor ability
8. Classify the processors in embedded system.
a. General purpose processor
Microprocessor
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w. EEmbedded processor
Digital signal processor
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Media processor
b. Application specific system processor
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c. Multiprocessor system using GPP and ASSP GPP core or ASIP core integrated into
VLSI chip.
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either an ASIC or a VLSI circuit or an FPGA core integrated with processor unit in a
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9. What are the various types of memory in embedded systems?
RAM (internal External) r ing
ROM/PROM/EEPROM/Flash
Cache memory .ne
10. What are the two essential units of a processor on a embedded system?
(i) Program Flow control Unit. (ii) Execution Unit
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11. What are the different modes of DMA transfer? Which one is suitable for
embedded system?
 Single transfer at a time and then release of the hold on the system bus.
 Burst transfer at a time and then release of the hold on the system bus. A burst
may be of a few kB.
 Bulk transfer and then release of the hold on the system bus after the transfer
is completed.

12. Define ROM image and RAM.

ROM image: Final stage software is also called as ROM image .The final implement
able software for a product embeds in the ROM as an image at a frame. Bytes at each
address must be defined for creating the image.
RAM: RAM refers Random Access Memory. It is a memory location that can be
accessed without touching the other locations.
13. What are the uses of timers?
 The time intervals between two events can be computed
 Initiating an event after a preset time delay.
 Capturing the count value
 Watch dog timer
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14. What is a watch dog timer?
The watch dog timer is a timing device that resets the system after a predefined
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timeout. It is activated within the first few clock cycles after power-up. It has a number of
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applications. Example: Mobile phone display turnoff in case of no interactions takes
place within a specified time.
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15. Define Real Time Clock.
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Real time clock is a clock which once the system starts does not stop and cannot
be reset and its count value cannot be reloaded.
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UNIT – 1
PART B (16 marks)
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1. Explain the build process for embedded system.
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The build is often referred either to the process of converting source code files into
stand alone software artifacts that can be run on a computer or the result of doing so.
The process of converting the source code representation of the embedded software
into an executable binary image involves three distinct steps.
Each of the source files must be compiled or assembled into an object file.
All of the object files that result from the first step must be linked together to
produce a single object file called the re-locatable program.
Physical memory addresses must be assigned to the relative offsets within the
relocatable program in a process called relocation.
The result of the final step is a file containing an executable binary image that is ready
to run on the embedded system.

C/C++
Compiler Pre-processor
Object
Linker
Re-locatable
Locator
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asy Figure: The Build Process Flowchart Chart
GCC (GNU compiler collection) is a compiler takes care of the compilation
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stages or builds process by calling appropriate programs. The compiler, assembler,
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linker and locator run on a host computer rather than on the embedded system itself.
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These tools combine their efforts to produce an executable binary image that will
execute properly only on the target embedded system.
>Led.c
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Embedded system
>Led.asm
>Led.o .ne
>Led.exe
Processor
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Target
Host computer
Pre-processing: A C program has the following pre-processor structural elements
1. Include directive for the file inclusion
2. Definitions for preprocessor global variables (global means throughout the
program module)
3. Definitions of constants
4. Declarations for global data type, type declaration and data structures,
macros and functions.
4

Preprocessor constants, variables and inclusion of configuration files, text files,

header files and library functions are used in embedded C programs. A pre-processor
directive starts with a sharp hash (#) sign.
Line begins with # symbol are called commands of pre-processor. GCC includes
a pre-processor called CPP (C pre-processor) Example: #define, #include etc. during
compilation, it is started with the pre-processing directives. The pre-processor is a
separate program in reality but it is invoked by a compiler.
Example:
livesimple.c Program
#include<stdio.h> //Preprocessor directives
int main()
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Printf(―LIVESIMPLE!‖);
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Both pre-processor directives and livesimple.c combined together to form livesimple.i
file.
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Syntax: [root@host ~] # CPP livesimple.c> livesimple.i
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Compilation: Compiler uses the complete set of codes. It may also include codes,
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functions and expressions from the library routines. It creates a file called object file.
Compilation involves both gcc compiler and assembler. First, the gcc compiler
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converts the livesimple.i file into livesimple.s file. The file livesimple.s contains assembly
code. The gcc conversion command is
Syntax: [root@host~]#gcc –s livesimple.i
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assembly code without creating the object file. t
The option – s tells the gcc compiler to convert the preprocessed code to
Second, the assembler translates the livesimple.s file into machine language format and
creating an object file called livesimple.o
Syntax: [root@host`]# as livesimple.s – o livesimple.o
The option – o converts the assembly file into object file.
Linking: A linker links the compiled codes of application software, object codes from
library and OS kernel. Linking is necessary because there are number of codes to be
linked for the final binary file. The linker file in the binary for run on a computer is
commonly known as executable file or simply ‗.exe‘ file.
This process converts the object file into a new object file that is a special
relocatable copy of the program. No memory addresses have been assigned to the
5

code until this process. An object file needs to be linked with many C run time library
files, system functions etc., to form an executable object file. For example: in
livesimple.c program, printf statement is needed. So printf.o file must be linked. The
linker (Id) will perform all those tasks.
Syntax: [root@host~] # Id – dynamic-linker/
Locating: The tool that performs the conversion from relocatable program to
executable binary image is called a locator. In embedded systems, the next step after
linking is the use of locator for the program – codes and data in place of the loader. The
features of locator are,
The locator is specified by the programmer the available addresses at the RAM
and ROM in target. The programmer has to define the available addresses to
ww load and create file for permanently locating codes using a device programmer.
It uses cross-assembler output, a memory allocation map and provides the
w. E locator program output file. It is the final step of software design process for the
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embedded system.
The locator locates the I/O tasks and hardware device – driver codes at the
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addresses without reallocation. This is because the port and device addresses
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for these are fixed for a given system.
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The locator program reallocates the linked file and creates a file for permanent
location of codes in a standard format.
Output:
Syntax : [root@host~] # ./ livesimple
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The output is
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LIVESIMPLE!
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In windows, the executable file is denoted as livesimple.exe but there is no need of .exe
extension file in Linux environment.
2. Discuss in detail about the structural units in embedded processor.
Address
Memory
Processor Data
Control
Figure: Bus Interface between Processor and Memory

STRUCTURAL UNIT IN A PROCESSOR:

1. Memory Address Register (MAR): It holds the address of the byte or word to
ww be fetched from external memories. Processor issues the address of instruction

or data to MAR before it initiates fetch cycle.
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2. Memory Data Register (MDR): It holds a byte or word fetched (or to sent) from
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an external memory or IO address.
3. System Buses:
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a. Internal Bus: It internally connects all the structural units inside the processor.
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Its width can be 8, 18, 32, 48 or 64 bits.
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b. Address Bus: An external bus that carries the address from MAR to memory
as well as to IO devices and other units of system.
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c. Data Bus: An external bus that carries, during a read or write operation, the
bytes for instruction or data from or to an address. The address is determined
by MAR.
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memory or device. t
d. Control Bus: An external set of signals to carry control signals to processor or
4. Bus Interface Unit (BIU): An interface unit between processor‘s internal units
and external buses.
5. Instruction Register (IR): It sequentially takes instruction codes (opcode) to
execution unit of processor.
6. Instruction Decoder (ID): It decodes the instruction received at the IR and
passes it to processor CU.
7. Control Unit (CU): It controls all the bus activities and unit functions needed for
processing.
8. Application Register Set (ARS)

a. A set of on chip registers used during processing of instructions of an

application program.
b. A register window.
c. A subset of registers with each subset storing static variables of a software
routine or
d. A register file associated to a unit such as ALU or FLPU.
9. Arithmetic Logic Unit (ALU): A unit to execute arithmetic or logic instructions
according to the current instruction present at IR.
10. Program Counter (PC):
It generates an instruction cycle by sending the address defined by it to memory
through MAR. It auto increments as the instructions are fetched regularly and
ww sequentially. It is called instruction pointer in 80 x 86 processors.

11. Stack Pointer (SP): A pointer for an address, which corresponds to a stack-top
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in memory.
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ADVANCED PROCESSOR’S STRUCTURAL UNITS:
Advanced processor circuits consist of RISC architecture.
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It executes most of the instruction in single clock cycle by using multiple
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register sets, windows and files and by reducing the dependency on the
external memory access for data.
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It contains the floating point unit. r
A RISC has only few addressing modes for arithmetic and logic instructions.
ing
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Pipelining allows a processor to overlap the execution of several instructions,
so that more instructions can be executed in the same period of time.
Example: DSP processors TMS320C6000, Davinci processor, OMAP
processor etc.
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1. Instruction Level Parallelism Unit (ILP):
For instruction level parallelism, the multistage pipeline processing, multiline
superscalar processing and dual, quad or multicore processing speeds up the
performance from one instruction per clock cycle.
2. Instruction Queue (IQ):
It is a queue of instruction so that the IR does not have to wait for the next
instruction after one has been processed.
3. Prefetch Control Unit (PFCU):

A unit that controls the fetching of data into the I and D. caches in advance from
the memory units. The instructions and data are delivered when needed by the
processor‘s execution units. The processor does not have to fetch data just
before executing the instruction. Pre-fetching unit improves performance by
fetching instruction and data in advance for processing.
4. Instruction Cache (I-Cache):
It sequentially stores, like an instruction queue, the instruction in FIFO mode. It
lets the processor execute instructions at great speed using PFCU compare to
external system memories, which are accessed at relatively much slower
speeds.
5. Branch Target Cache (BT Cache):
ww It facilitates ready availability of the next instruction – set when a branch

instruction like jump, loop or call is encountered. Its fetch unit foresees a
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branching instruction at the I-Cache.
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6. Data Cache (D-Cache):
It stores the pre-fetched data from external memory. A data cache generally
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holds both the key (address) and value (word) together at a location. It also
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stores write through data when so configured. Write through data means data
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from the execution unit that transfer through the cache to external memory
addresses.
7. Memory Management Unit (MMU):
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It manages the memories such that the instructions and data are readily available
for processing.
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8. System Register Set (SRS):
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It is a set of registers used while processing the instructions of the supervisory
system program.
9. Floating Point Processing Unit (FLPU):
A unit separate from ALU for floating point processing, which is essential in
processing mathematical function fast in a microprocessor or DSP.
10. Floating Point Register set (FRS):
A register set dedicated for storing floating point numbers in a standard format
and used by FLPU for its data and stack.
11. Multiply and Accumulate Unit (MAC):
There is also a MAC unit for multiplying coefficients of a series and accumulating
these during computations.
9

12. Atomic Operation Unit (AOU):

It lets a user (compiler) instruction, when broken into a number of processor
instruction called atomic operations, finish before an intercept of a process
occurs. This prevents problems from arising out of shared data between various
routines and tasks.
3. Write short note on (i) DMA (ii) Memory Management.
(i) DMA (DIRECT MEMORY ACCESS):
Definition: A direct memory access (DMA) is an operation in which data is copied from
one resource to another resource in a computer system without the involvement of the
CPU. The task of a DMA controller (DMAC) is to execute the copy operation of data
from one resource location to another. The copy of data can be performed from:
ww I/O device memory

Memory to I/O device
w. E Memory to Memory
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Figure: Logical Structure of System with DMA
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DMAC is an independent resource of a computer added for the
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concurrent execution of DMA operations. The first two operation modes are ‗read from‘
and ‗write to‘ transfers of an I/O device to the main memory, which are the common
operation of a DMA controller.
The DMAC replaces the CPU for the transfer task of data from I/O device
to the main memory, otherwise it is executed by the CPU using the programmed input
output mode (PIO). The ‗memcopy’ is used for PIO operation. The DMAC is a
master/slave resource on the system bus, because it supply the address for the
resources involved in a DMA transfer. It requests the bus whenever a data is available
for transport, which is signalled from the device by ―REQ‖ signal.
DMA Operation: There are many modes of operation such as,
Single block transfer (most commonly used)
10

Chained block transfers

Linked block transfers
Fly- by transfers
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w. E Figure: DMA Operation
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Execution of a DMA – Operation (Single block Transfer)
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For DMA operation, the CPU prepares the construction of a descriptor (1). It
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contains all information for the DMAC to independently perform the DMA operation. It
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initializes the operation by writing a command to a register in a DMAC (2a) or to a
command area, where the DMAC can poll for the command and/or the descriptor (2b).
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Then the DMAC addresses the device data register (3) and read the data into a
temporary data register (4). In another bus transfer cycle, it addresses the memory
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block (5) and writes the data from the temporary data register to the memory block (6).
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The DMAC increments the memory block address and continue with this loop
until the block length is reached. The completion of the DMA operation is signalled to
the processor by sending an IRQ signal.
(ii) MEMORY MANAGEMENT:

When a process is created, the memory manager allocates the memory addresses to it
by mapping the process address space. Threads of a process share the memory space
of the process.
Memory Leak: A memory allocation that does not have a corresponding de-allocation.
11

A memory leak is a gradual loss of available computer memory, when a program

repeatedly fails to return memory that it has obtained for temporary use. Due to memory
leak, run out of memory problem will occur.
Stack overflow means that the stack exceeds the allocated memory block when
there is no provision for additional stack space. Memory manager controls the memory
leaks and stack overflows.
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Memory Management strategies are
1. Fixed blocks allocation: Memory address space is divided into blocks with
w. Eprocesses of small address spaces getting a lesser number of blocks and

processes of big address spaces getting a large number of blocks.
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2. Dynamic block allocation: Memory manager allocates variable size blocks
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dynamically allocated from a free list of memory blocks description table at
different phases of a process.
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3. Dynamic Page Allocation: Memory has fixed sized blocks called pages and the
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memory management unit allocates the pages dynamically with a page
descriptor table.
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4. Dynamic data memory allocation: The manager allocates memory dynamically
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to different data structures like the nodes of a list, queues and stacks.
5. Dynamic address relocation: The manager dynamically allocates the addresses
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bound to the relative address. It adds the relative address to address with
relocation register. This is also called run-time dynamic address binding.
6. Multiprocessor Memory Allocation: it adopts the tight coupling or loose coupling
between two or more processors.
7. Memory protection to OS functions: It means that the system call and function
call in user space are distinct. The memory of kernel functions is distinct and can
be addressed only by the system calls. The memory space is called kernel
space.
8. Memory Protection among the tasks: Read and write operations are not
permitted to the particular memory space allocated to another task. This
12

protection increases the memory requirement for each task and also the
execution time of the code of the task.
The Manager optimizes the memory needs and memory utilization. The memory
manages the following:
1. Use of memory addresses space.
2. Mechanism to share memory space
3. Mechanism to restrict sharing of a given memory space.
4. Optimization of memory.
4. Write short note on (i) ICE (ii) Timer & Counter.
(i) IN – CIRCUIT EMULATOR (ICE):
In- circuit emulation is the use of a hardware device of in-circuit emulator
ww used to debug the software of an embedded system. It operates by using –

processor with the additional ability to support debugging operations as well as to
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carry out the main function of the system.
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ICE is a computer chip that is used to emulate a microprocessor, so that embedded
system software can be tested by developers. It allows a programmer to charge or
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debug the software in an embedded system. The ICEs gives the option of debugging by
gi
single stepping.
nee
r ing
.ne
t
Working Principle:
The programmer uses the emulator to load programs into the embedded system,
run them, step through them slowly and view and change data used by the
system‘s software. It imitates the central processing unit of the embedded
system‘s computer.
The house of Microchip offers in circuit emulators are of 3 types: MPLAB ICE
2000, MPLAB ICE 4000, REAL ICE.
13

ICE consists of a small dual port pod. One port is a probe that plugs into the
microprocessor socket of the target system. The second port is interfaced to a
computer (or) workstation.
Limitations of ICE:
Availability and cost
On chip functions
Transparency
Features and capabilities of ICE are
1. Ability to map resources between target and host.
2. Ability to run and test code in real time without target hardware.
3. Ability to step or run programs from/to specified states or break points.
ww 4. Ability to observe and modify microprocessor registers.
w. E 5. Ability to Observe and modify memory contents.

6. Ability to trace program execution using internal Logic Analyzers.
asy
(ii) TIMERS AND COUNTERS:
Timer is a very common and useful peripheral. It is a device that counts the
En
regular interval (δT) clock pulse at its input. The counts are stored and incremented on
gi
each pulse. It has output bits for the period of counts. The counts multiplied by interval
δT gives the time.
nee
Number of counting the interval x δT = Time
r ing
Timer is a programmable device, (i.e) the time period can be adjusted by writing
specific bit patterns to some of the registers called timer-control registers.
.ne
A counter is more general version of the timer. It is a device that counts the input
t
for events that may occur at irregular or regular intervals. The count gives the number of
input events or pulses, since it was last read.
The simple timer has a 16 bit up counter which increments with each input clock
pulse is shown in figure (a). Thus the output value ‗Cnt‘ represents the number of
pulses, since the counter was last reset to zero. An additional output ‗top‘ indicates
when the terminal count has been reached. It may go high for a predetermined time as
set by the programmable control word inside the timer unit. The count can be loaded by
the external program.
14

The figure (b) provides the structure of another timer where a multiplexer is used
ww
to choose between an internal clock and external clock. The mode bit when set or reset
decided the selection. For internal clock (Clk) it behaves like the timer in Figure (a). For
w. E
the external coun- in (Cnt-in) it just counts the number of occurrences.
asy
En
gi nee
r ing
Figure (c): Timer with a terminal count
.ne
t
The figure (c) shows a timer with the terminal count. This can generate an event
if a particular interval of time has been elapsed. The counter restarts after every
terminal count. For example, in 8051 microcontroller, there is a presence of two bit
timer/counter registers, Timer 0 and Timer 1.
In timer mode, register is incremented after every machine cycle.
1 machine cycle = 12 Oscillator periods
So count rate = 1/12 of Oscillator frequency.
If crystal frequency is 12 MHz, then timer clock frequency is 1 MHz.
In counter mode, Register is incremented in response to 1 to 0 transition at the
corresponding external input pin T0 and T1.
15

Blind Counting Synchronisation:

A blind counting free running counter with prescaling, compare and capture
registers has a number of applications. It is useful for action or initiating a chain of
actions and processor interrupts at the present instances as well as for noting the
instances of occurrences of the events and processor intercepts for requesting the
processor to use the captured counts on the events for future actions.
Watch dog Timer:
ww It is a timing device that resets the system after a predefined time out. It starts
after a few clock cycles from power up. After restart, system works normally, if any
w. E
failure occurs in past.
A watch dog timer is a piece of hardware that can be used to automatically
asy
detect software abnormalities and reset the processor if any. It is based on the counter
that counts down from some initial value to zero.
En
The watchdog timer is a chip external to the processor. However, it could also be
gi
included within the same chip as the CPU. This is done in many microcontrollers.
nee
The process of restarting the watch dog timer‘s counter is sometimes called
“Kicking the dog”.
r ing
.ne
t
Real Time Clock (RTC):
It is a clock that keeps track of the time even when computer is turned off. Real
time clocks (RTC) run on a special battery that is not connected to the normal power
supply. In contrast, clocks that are not real time do not function when the computer is
off. Do not confuse a computer‘s real time clock with its CPU clock. The CPU clock
regulates the execution of instructions.
Real time clock provides system clock and it has a number of applications. It is a
clock that generates system interrupts at preset intervals. An Interrupt Service Routine
(ISR) executes on each tick or timeout or overflow of this clock. Once the device
16

started, it never resets or never reloaded to another value. Example: DS1307 chip is a
real time clock integrated circuit.
Consider the block diagram shown below. The Arduino UNO is used for reading
time from DS1307 and display it on 16X2 LCD. DS1307 sends time/data using 2 lines to
Arduino. A buzzer is also used for alarm indication, which beeps when alarm is
activated.
ww
5. How to select the processor based upon its architecture and applications?
PROCESSOR:
w. E A processor is the heart of the embedded system. For an embedded system

designer, knowledge of microprocessors and microcontrollers is a prerequisite.
asy
PROCESSOR IN A SYSTEM:
En
A processor has 2 essential units.
gi
1. Program flow Control Unit (CU)
2. Execution Unit (EU)
nee
The CU includes a fetch unit for fetching instructions from the memory. The EU has
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circuits that implement the instructions pertaining to data transfer operations and data
conversions from one form to another. The EU includes the Arithmetic and Logic Unit
.ne
(ALU) and also the circuits that execute instructions for a program control task, say halt,
or branch to another program and for a call to a function. t

interrupt or jump to another set of instructions. It can also execute instructions for a call
A processor runs the cycles of fetch and execute. The instructions defined in the
processor instruction set are executed in the sequence that they are fetched from the
memory. An embedded system processor chip can be one of the following:
1. General Purpose Processor (GPP)
 Microprocessor
 Microcontroller
 Embedded Processor
 Digital Signal Processor (DSP)
 Media Processor
2. Application Specific System Processor (ASSP) as additional processor.
17

3. Multiprocessor System using General Purpose Processor (GPP) and

Application Specific Instruction Processor (ASIP)
4. GPP cores or ASIP cores integrated into an Application Specific
Integrated circuit (ASIC), a Very Large Scale Integrated Circuit (VLSI)
circuit, or an FPGA core integrated with processor units in a VLSI (ASIC)
chip.
SELECTION OF PROCESSOR:
Most embedded systems need some type of processor. For a system designer,
the following are important considerations when selecting a processor.
1. Instruction set
2. Maximum bits in an operand
ww 3. Clock frequency in MHz

4. Processing speed in Million Instructions Per Second (MIPS)
w. E 5. Processing ability to solve the complex algorithms used in meeting the
asy deadlines for their processing.

6. Register – windows provides fast context switching in a multitasking system.
En
7. Power efficient embedded system requires a processor that has auto-shut
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down feature for its units and programmability for disabling use of caches
nee
when the processing need for a function or instruction set does not have
constraint of execution time. It is also required to have stop, sleep, and wait
r
instructions. It may alsi require special cache design
ing
8. Burst mode accesses external memories fast, reads fast and writes fast.
.ne
9. Atomic operation unit provides hardware solution to shared data problem,
t
when designing embedded software or else special programming skills and
efforts are to be made when sharing the variables among the multiple tasks.
10. A processor may also be configured at the initial program stage big-endian or
Little endian storage of words. Eg: ARM processors.
11. The strong ARM family processors from Intel and Tiger SHARC from Analog
devices have high power efficiency features.
SELECTION OF MICROCONTROLLER VERSION:
A version and microcontroller is selected for embedded system design as per the
application as well as its cost.
1. Embedded system in an automobile requires CAN controller and CAN
transceiver.
18

2. 8051 has only 2 timers Times 0 & Times 1, but 8052 has an additional timer
– Timer 2, which is used for the development of Real Time Operating
System.
3. Some Microcontrollers support master slave mechanism with the features of
I2C and SPI supported in-built pins.
4. 8051 family member 83C152JA has two direct memory access (DMA)
channels on-chip.
5. For interfacing more number of devices, we need more pins in
microcontrollers to develop a particular application.
6. 80196KC has a PTS (Peripheral Transactions Server) that supports DMA
functions.
ww
MICROPROCESSORS:
w. E
asy
En
gi
Microprocessor is a single VLSI chip that has a CPU and may have some other
nee
units. Example: caches, floating point processing, arithmetic unit, pipelining etc. RAM,
ROM and I/O units will not present within a CPU chip itself. Microprocessor accepts
r ing
binary data as input & process data according to the instructions given and provides
results as output. CPU has two basic functional units such as Control unit and
Arithmetic Logic Unit (ALU). Example: 8085, 8086. .ne
MICROCONTROLLER:
t
Microcontroller is a device, which integrates a number of the components of a

microprocessor system onto a single microchip. It combines the CPU core, memory
(ROM & RAM) and some parallel digital I/O ports onto the same microchip. Program
memory is ROM and Data Memory is RAM. Example: 8051, PIC18F, PIC19F.
19

A microcontroller is a single chip VLSI unit, through which having limited

computational capabilities, possesses enhanced input- output capabilities and a number
of on-chip functional units.
MECHANISM IN MICROCONTROLLERS:
ww
STEPS:
w. E
1. CPU gets the Instruction (MOV,MVI) from ROM.
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2. CPU also gets the data (A=5, B=6) from RAM or from Peripheral Registers.
3. Now CPU registers are having the data and send data to the ALU unit to perform
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the mathematical or logical operation.
gi
4. Finally the results are returned back to the CPU registers. In the turn CPU
nee
registers send the data to RAM or to peripheral devices.
PROCESSOR ARCHITECTURES:
r ing
A processor is the logic circuitry that responds to and processes the basic
instructions that drive a system. The term processor has generally replaced the term
.ne
central processing unit. The processor in a personal computer or embedded in small
t
devices is often called a microprocessor. The presence of Microprocessor and Memory
within a single chip is called as Microcontroller. The various processor architectures are
1. Von Neumann Architecture
2. Harvard Architecture
3. Super Harvard Architecture
4. Layered Architecture
VON NEUMANN ARCHITECTURE
Fig: Von Neumann Architecture

20

Single memory and single bus for transferring the data into and out of the CPU.
Multiplication of two numbers require atleast three clock cycles.
HARVARD ARCHITECTURE
Seperate memory for data and program with separate buses for each. Both
program instructions and data values can be fetched at the same time. Operational
speed is higher than Von Neumann architecture.
ww Examples:
w. E 8051 Microcontroller is a Harvard Architecture with CISC Instruction Set

PIC Microcontroller is a Harvard Achitecture with RISC Instruction Set
asy
SUPER HARVARD ARCHITECTURE (DSP Processors)
DSP algorithms spend their most of the time in loops. So instruction cache is
En
added. DSP processors are capable of processing many high frequency signals in real
operation gi
time. The significant feature present in the DSP processor is Multiply – Accumulate
Example: a <- a+(B X C) nee

r ing
.ne
t
By using this feature this mathematical part will performed in a single clock cycle.
Applications performed in this processor are fixed point & floating point operations,
matrix operations, convolution, correlation, parallelism etc.
21

Examples: C5000, C6000 single core processor families are manufactured by

Texas Instruments.
C6000 processor fetch eight 32 bit instructions per clock cycle.
ARCHITECTURE OF EMBEDDED SYSTEMS:
ww The combination of hardware, operating software and application software leads

to the very effective embedded systems.
w. E
Case studies
Case-I : When the processor instruction cycle time is 1 microsecond
asy
On chip devices and memory is sufficient. A microcontroller can be selected.
En
Examples : Automatic chocolate vending machine,56kbps modem, Robots, Data
gi
acquisition systems like an ECG recorder, Weather recorder, Multipoint temperature
nee
and pressure recorder and realtime Robotic controller.
Case-II : When the processor instruction cycle time is 10 to 40 nanosecond
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On chip devices and memory is not sufficient. A microprocessor is required.
Examples : 52Mbps router, image processing, voice data acquisition,voice and video
compression and adaptive cruise control.
.ne
Case-III : When the processor instruction cycle time is 5 to 10 nanosecond
t
High MIPS(Million Instruction per second) or MFLOP (Million Floating Point IPS) multi
processor system is required,
Examples : Multi port 100Mbps network transceiver, fast 100 Mbps switches, routers,
multichannel fast encryptions and decryptions system.
Case-IV : When the processor instruction cycle time is 1 nanosecond
Microprocessor and DSP based multiprocessor system is needed.
Examples : Voice and video processing, real time audio and video processing and
mobile phone systems.
6. Discuss in detail about Target hardware Debugging.
Most of these debugging techniques can be applied to any microcontroller since they do
not use any specific tools.
22

There are many ways to debug hardware, they are,

1. ICE (In Circuit Emulator)
2. ICD (In Circuit Debug)
3. Simulation
4. Serial RS-232
5. LCD
6. LED
7. Hardware pins
8. Logic Analyzer
ICE (In Circuit Emulator): In Circuit Emulator is the most expensive way to debug your
hardware. It takes a special processor that physically takes place of the normal
ww
processor. This special processor allows software access to the internal operation of the
processor.
w. E
ICD (In Circuit Debug): The next best thing to ICE is ICD (In Circuit Debug). This is for
asy
PIC microcontroller. BDM (Background Debug Mode) is for non PIC microcontroller. For
ICD the processor has a small amount of built-in hardware that can halt the processor
En
when the program reaches a specific address. The software can then read back all the
gi
registers and processor state.
nee
Simulation: With a source code simulator you can step through the high level language
code and see its effect on memory and variables without having to look at the
r ing
assembler code directly. This let you focus on high level language operation and let you
concentrate on the problem you are trying to solve. One great advantage of simulator is
.ne
that you do not have to wait to download and program the target processor. So you can
cut out the time consuming programming just by using the simulator.
t
Serial RS232: New microcontrollers have a built-in UART which gives virtually free
debug tool that uses minimum resources and need very little software coding. For
debug output you need to connect the UART output in TX to a suitable level translator
circuit a MAX 232 chip. You may even get away with direct connection to the input of
your PC serial port – using a translator chip will always work.
Advantages: Minimal coding, simple to use, minimal extra hardware.
Disadvantage: a) Takes long time to output a character (~1ms)
b) Takes even longer for blocks of characters (~10sf ms)
c) Need extra hardware.
Even though it takes time to output a character, it is a useful debug tool as you can
output the value of variable to see what the microcontroller is really doing.
23

LCD: An LCD (Liquid crystal Display) gives a convenient way of displaying debugging
information. It is also useful for many different applications that need a text display
output. It is a module that displays text characters and a common screen size is 2 rows
of 16 characters. Most LCD modules use the HD44780 controller chip which is why LCD
routines built into high level language always work.
Advantage: a) Very quick update (40 µs 4 bit data bus)
b) Useful in many projects as the main display interface.
c) Simple to interface to an 8-bit port (only needs six of the 8-bits)
Disadvantage: a) Uses up an 8-bit port
b) Hardware is more expensive (Example: compared to a serial port chip)
LED: Using an LED as a microcontroller ―alive‖ indicator. Even though it is such a
ww
simple thing to blink an LED on and off it is extremely useful as a debugging tool as you
can tell at a glance whether the code you just downloaded is working sometimes you
w. E
can will incorrectly set parameter on the programming software or compiler which will
asy
stop the code dead.
The LED indicator gives a quick health check for your microcontroller which is easy to
see.
En
gi
Pin Debugging: This is the simplest and rudest debugging method using any available
nee
port pin. Simply set and reset this pin at any point in the code that you want to monitor.
It has minimal impact on the code speed or size and can give you the following
information.
You can tell if the code is active.
r ing
It gives you the repetition rate
.ne
t
It gives you the routine time length (if you set the pin at the start and reset it at
the end).
Logic Analyzer: This tool attaches to the pins you want to observe and captures the
waveforms displaying multiple traces on a single display. It uses a trigger module that
can be set to activate the combinations of the input signals or on their length. So you
can trigger on specific patterns or on glitches or both.
For non-microcontroller based systems where the data and address bus are exposed, a
logic analyzer can show the address and data organised into hex words i.e. readable.
Some can disassemble the instruction showing what the processor was doing at the
trigger point.
24

For a microcontroller based system the logic analyzer can be useful in examining
peripheral operation. Example: for debugging the SPI or I2C buses some logic analyzers
also have built in support for these protocols.
Another use of the logic analyzer is to capture output over a long period of time
depending on the memory capacity of the logic analyzer.
ww
w. E
asy
En
gi nee
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t
25

UNIT-2 - EMBEDDED NETWORKING

PART-A( 2 marks)
1. Differentiate synchronous communication and Iso-synchronous

communication.
Synchronous communication: When a byte or a frame of the data is received or
transmitted at constant time intervals with uniform phase difference, the communication
is called synchronous communication.
Iso-synchronous communication: Iso-synchronous communication is a special case
when the maximum time interval can be varied.
2. What are the two characteristics of synchronous communication?
ww  Bytes maintain a constant phase difference

 The clock is not always implicit to the synchronous data receiver.
w. E
3. What are the three ways of communication for a device?
asy
Iso-synchronous communication
Synchronous communication
En
Asynchronous communication
gi
4. Define half-duplex communication and full duplex communication.
nee
Half-duplex communication: Transmission occurs in both the direction, but not
simultaneously.
r ing
Full duplex communication: Transmission occurs in both the direction, simultaneously
6. Expand a) SPI b) SCI
.ne
SPI—Serial Peripheral Interface, SCI—Serial Communication Interface
7. What is I2C?
t
I2C is a serial bus for interconnecting ICs .It has a start bit and a stop bit like an
UART. It has seven fields for start,7 bit address, defining a read or a write, defining byte
as acknowledging byte, data byte, NACK and end.
8. What is a CAN bus? Where is it used?
CAN is a serial bus for interconnecting a central Control network. It is mostly
used in automobiles. It has fields for bus arbitration bits, control bits for address and
data length data bits, CRC check bits, acknowledgement bits and ending bits.
9. What is meant by status flag?
Status flag is the hardware signal to be set when the timer reaches zeros.
10. State the special features on I2C?
Low cost
26

Easy implementation
Moderate speed (upto 100 kbps).
11. What are disadvantages of I2C?

 Slave hardware does not provide much support
 Open collector drivers at the master leads to be confused
12. Draw the data frame format of CAN?
ww
13. Define device driver.
A device driver is software for controlling, receiving and sending byte or a stream of
w. E
bytes from or to a device.
asy UNIT-2
En PART B (16 marks)
gi
1. Explain SPI protocol and describe its interface.
SYNCHRONOUS PERIPHERAL INTERFACE (SPI):
nee
r ing
.ne
t
SPI was defined by Motorola on the MC68HCXX line of microcontrollers.
It is a full duplex communication.
It supports 1. Full master mode, 2. Slave mode (with general address call)
Addressing each device is not needed.
SPI is a 3 wire communication such as MOSI, MISO and SCLK.
 MOSI - Master output slave input
 MISO - Master Input slave output
 SCLK - Serial Clock
27

If SS pin is set as 1, then the particular SPI device acts as a Master.

If SS pin is set as 0, then the particular SPI device acts as a Slave.
It supports 8 bit transmission and Reception
Generally, SPI is faster than I2C which is capable of several Mbps. Bus
Arbitration logic is needed.
A master sends a clock signal and upon each clock pulse it shifts one bit out to
the slave and one bit in, coming from the slave.
ww
w. E
asy
SSP BUF - Synchronous Serial Port Buffer
En
SSP SR - Synchronous Serial Port Shift Register
gi
Bus Configuration:
nee
1. Parallel configuration (or) using separate chip selects:
For the parallel connection, each device on the bus should have a separate CS
r ing
line, while SCK, SDI and SDO lines are connected in parallel as shown in Figure.
.ne
t
28

2. Daisy chain configuration:
In this configuration CS and SCK lines connected in parallel and each SDO pin of
previous chip is connected to SDI pin.
ww
w. E Figure: Daisy chain selection
asy
Applications of SPI:
 SPI is used in EEPROM, Flash, and real time clocks.
En
 Better suited for data streams in ADC converters etc.
gi
 Full duplex capability (i.e.) communication between a CODEC and digital signal
processor.
nee
2. Explain I2C bus operation and describe its interface.
INTER INTEGRATED CIRCUIT (I2C):
r ing
.ne
I2C Bus developed by Philips Semiconductor for TV sets in the 1980's
t
I2C is a 2 wire communication such as SDA (serial data) and SCL (serial clock).
It performs half-duplex and synchronous communication.
I2C Supports:
1. Master Mode
2. Slave Mode
3. Multi Master Mode
Addressing is needed for each slave device. For example: In PIC microcontroller
- MSSP Address Register is used for addressing.
No chip select or Arbitration logic is required.
29

I2C Data Transfer:
Steps:
Master sends start condition (S) and controls the clock signal.
ww Master sends a unique 7-bit slave device address.
w. E Master sends read / write bit (R/W) as 0 for slave receive and 1 for slave
transmit.
asyWait for (or) send an acknowledge bit (A).

Send (or) receive the data byte (8 bits) (DATA).
En
Expect / send acknowledge bit (A)
gi
Send the stop bit (P).
nee
r ing
.ne
t
Figure: Application diagram
Application of I2C:
Used as a control interface to signal processing devices that has separate data
interfaces.
Example RF tuners, video decoders and encoders and Audio processor.
30

3. Explain the CAN bus protocol with suitable diagrams.

CAN BUS:
The Controller Area Network (CAN) is a serial bus communication protocol,
which was originally developed for automotive applications by Bosch in 1980.
A controller Area Network refers to a Network of Independent controllers. It is a
Serial Communication protocol that efficiently supports distributed real time
control with a very high level of security.
CAN is a data link layer protocol internationally standardized as ISO-11898-1 and
ISO-11519.
ww The data on CAN bus is differential and can be in two states: dominant and
w. Erecessive. The bus defines a logic bit 0 as a dominant bit and a logic bit 1 as a
recessive bit.
asy
CAN bus uses 2 dedicated wires for communication such as CAN H and CAN L.
When the CAN bus is in idle mode, both the lines carry 2.5V. When data bits are
En
transmitted. CAN high line goes to 3.75V and CAN low drops to 1.25V. There by
gi
generating a 2.5V differential between the lines.
nee
CAN protocol is a message based protocol, not an address based protocol. CAN
provides two communication services, the sending of a message (Data Frame
r ing
Transmission) and the requesting of a Message (Remote Transmission Request)
RTR.
.ne
Each node is able to send and receive messages, but not simultaneously. A
t
message consists primarily of an ID (Identifier), which represents the priority of
the message and up to 8 data bytes. Signal pattern is NRZ (Non - return to zero)
Baud rate is 1 Mbps and it is a Multi-master broadcast serial bus standard.
Priority based bus arbitration mechanism is employed here.
31

There are basically four message frames in CAN:

Data, Remote, Error and over head. The data and remote frames need to be set
by the user. The other two are set by the CAN hardware.
ww
1. Data Frame:
w. E Data frame consists of fields such as start of frame (SOF), Arbitration field,
Control field, Data field, CRC (Cyclic Redundancy Check) field, ACK (Acknowledge)
asy
field and EOF (End of Frame). If RTR is 1, then the packet is a data to the receiver, if
RTR is 0, then the packet is a request for the data from the receiver.
En
gi nee
2. Remote Frame: r ing
.ne
The remote frame is used by the receiving unit to request transmission of a
Message from the transmitting unit. It consists of 6 fields: Start of Frame (SOF)
t
Arbitration field, Control field, CRC field, ACK field and End of frame (EOF) field.
3. Over Load frame:

The overload frame is used by the receiving unit to indicate that it is not get ready
to receive frames. This frame consists of an overhead flag and an overload delimiter.
The overload flag consists of 6 dominant bits and the overload delimiter consists of 8
recessive bits.
32

4. Error frame:
Error frames are generated and transmitted by the CAN hardware and are used
to indicate when an error has occurred during transmission. This frame consists of an
Error flag and an Error delimiter. Error Flag has 2 types.
1. Active with 6 dominant
2. Passive with 6 Recessive bits
The error delimiter consists of 8 Recessive bits.
ww
CAN BUS Interface:
w. E
There are 2 Models of Interfaces depending upon the features present in Micro
asy
controller.
En
gi nee
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t
4. Compare RS232 & RS485 in detail.
RS 232 C STANDARD:
RS 232 C was defined by Electronic Industries Association (EIA) for data
interchange. RS232 is an interfacing signal standard. It is a point to point
interface.
33

It provides communication between DTE and DCE. It follows the

asynchronous UART protocol.
Receiver end voltage level from -3V to -25V denotes logic 1 and voltage
ww level from +3V to +25V denotes 0.
w. E Transmitter end voltage level from -5V to -15V denotes logic 1 and from
+5 to +15V denotes logic 0.
asy Commonly used Band rate for asynchronous serial communication with
UART mode is 9600.
En The RS232 C standard allows data to be sent and received at the same
gi
time. (full duplex)
nee
RS232 C standard defines two types of lines such as DB9 and DB 25 for
real world applications.
The RS232 C standard defines, r ing
o The Mechanical aspects of interface.
o The characteristics of electrical signals. .ne
o The functional aspects of the interchange.
RS232 C Connections:
t
DTE DCE DCE
Acrony
DTE DB-25M
Description DB-9M Direction DB-9F DE-25F
m Pin#
Pin# Pin# Pin#
Transmit TXD 2 3 2 3
Receive Data RXD 3 2 3 2
Request to
RTS 4 7 8 5
send
Clear to send CTS 5 8 7 4
Data set ready DSR 6 6 4 20
34

Data carrier
DCD 8 1 1 8
detect
Data terminal
DTR 20 4 6 6
ready
Ring indicator RI 22 9 9 22
Signal ground SG 7 5 5 7
RS232 C connections (DTE):
ww
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asy
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RS232 C connections (DTE to DCE):
r ing
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35

RS232 C NULL MODEL (DTE TO DTE):
RS232 C 3 wire DTE to DTE:
ww
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asy
RS485:
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RS-485 allows multiple devices (up to 32) to communicate at half-duplex and full
gi
duplex at distances up to 1200 meters .
nee
Both the length of the network and the number of nodes can easily be extended
using a variety of repeater.
r ing
Data is transmitted differentially on two wires twisted together, referred to as a
twisted pair.
A 485 network can be configured two ways, two-wire or four-wire .ne
t
In a two-wire network the transmitter and receiver of each device are connected
to a twisted pair.
Four-wire networks have one master port with the transmitter connected to each
of the slave receivers on one twisted pair. The slave transmitters are all
connected to the master receiver on a second twisted pair.
In either configuration, devices are addressable, allowing each node to be
communicated to independently.
Only one device can drive the line at a time, so drivers must be put into a high-
impedance mode (tri-state) when they are not in use.
Two-wire 485 networks have the advantage of lower wiring costs and the ability
for nodes to talk amongst themselves. But is limited to half-duplex.
36

Four-wire networks allow full-duplex operation, but are limited to master-slave

situations. Slave nodes cannot communicate with each other.
RS485 communication is half duplex. Each communicating element on an RS485
interface is called a node. One of the nodes is called the master while all other
nodes are called slaves. Each node has a unique ID number. Node #0 is
generally assigned to the master.
RS485 features are
o Very noise immune
o Maximum cable length of 4000 feet
o Data rate up to 10 Mbps
o Capable of supporting a multi-master configuration.
ww
w. E
asy
En o
gi nee
r ing
.ne
5. Write short Note on (i) Input and output ports (ii) UART
(i) INPUT AND OUTPUT PORTS:
t
Ports:
A port is a device to receive the bytes from external peripherals for reading them
later using instructions executed on the processor (or) to send the bytes to external
peripheral or device or processor using instructions executed on processor A part
connects to the processor using address decoder and system buses.
The processor uses the addresses of the port registers for programming the port
functions or modes, reading port status and for writing or reading bytes.
Example:
Serial Peripheral Interface (SPI) in 68 HCII.
37

Ports PO, P1, P2 and P3 in 8051.

COM1 & COM2 ports in an IBM PC.
Types of Serial Ports:
Synchronous Serial input
Synchronous Serial output
Asynchronous serial UART input
Asynchronous serial UART output
Both as Input and as output. Example: Modem
1. Synchronous Serial input Device:
The sender along with the serial bits also sends the clock pulses SCLK to the
receiver port pin. The port synchronized the serial data input bits with clock bits.
ww Synchronization means separation by a constant interval (or) phase difference. If
w. Eclock period = T, then each byte at the port is received at Input in period = 8T.
The data transfer rate is (1/T) bps (bits per second).
asy
Serial data and clock pulses are sent either on a same input line or separate
input line.
En
The peripheral saves the byte at port register from where the Microprocessor
gi
reads the byte.
nee
MOSI (Master output slave Input), when the SCLK is sent from the sender to the
the inputs from master clock. r

receiver and slave is forced to synchronize sent inputs from the master as per
ing
.ne
MISO (Master Input Slave Output) when the SCLK is sent to the sender from the
receiver and slave is forced to synchronize for sending the inputs to master as
per the master clock outputs.
t
Synchronous Serial input is used for inter processor transfers, audio inputs and
streaming data inputs.
38

2. Synchronous Serial output Device:

Each bit in each byte sent in synchronization with a clock.
Bytes sent at constant rates. If clock period is T, then data transfer rate is (1/T)
ww bps.
Sender either sends the clock pulses at SCLK pin or sends the serial data output
w. Eand clock pulse input through same output line with clock pulses either suitably
modulate (or) encode the serial output bits.
asy
The peripheral at the port sends the byte through a shift register at the port to
En
where the microprocessor writes the byte.
gi
Synchronous serial output is used for inter processer transfers, audio outputs
and streaming data outputs.
Synchronous Serial Input / Output: nee
r ing
Each bit in each byte is in Synchronization at input and each bit in each byte is in
synchronization at output with the master clock output.
The bytes are sent or received at constant rates.
.ne
t
The processing element at the port sends and receives the byte at a port register
to or from where the microprocessor writes or reads the byte.
3. Asynchronous Serial Input: (Serial Reception)
39

Each RXD (Receive data) bit is received in each byte at fixed intervals but each
received byte is not in synchronisation.
It does not receive clock Information along with the data bytes.
Bytes are received at variable Intervals (or) phase differences. Asynchronous
serial input is also called as UART Input.
A 1 to 0 transition indicates the reception of a byte.
Time period for 1 byte is 10 T, which includes the one start bit, 8 data bits and
one step bit.
The peripheral saves the byte at a port register from where the microprocessor
reads the byte.
Examples: Keyboard Input & Modem Inputs in Computer.
ww
w. E
asy
En
gi nee
4. Asynchronous Serial Output: (Serial Transmission)
r ing
Each bit in each byte is sent at fixed intervals but each output byte is not in
synchronization and its line is denoted by TXD (transmit data)
.ne
Bytes are transmitted at variable Intervals (or) phase differences. Asynchronous
serial output is also called as UART output.
It does not send clock information along with the data bytes.
t
The peripheral sends the byte at a port register to where the microprocessor is to
write the byte.
Examples: Modem & Printer Inputs from computer.
5. Half Duplex and Full Duplex:
Half Duplex: Both the nodes can be able to transmit and receive, but not at the same
time.
Full duplex: Both the nodes can be able to transmit and receive, but not at the same
time.
Types of Parallel ports:
40

1. Parallel port one bit Input:

Example: Filling of a liquid up to a fixed level
2. Parallel port one bit output:
Example:
PWM output for a DAC.
Pulses to an external circuit.
Control signal to an external circuit.
3. Parallel port Multi bit input:
Example:
ADC Input from Liquid level measuring sensor or temperature sensor (or)
pressure sensor (or) Speed Sensor.
ww Encoder inputs for bits for angular position of a rotating shift or a linear
w. E displacement of an object.
4. Parallel port Multi bit output:
asy
Example:
Print controller output
En
Stepper Motor coil driving bits.
Example: gi
5. Parallel port input - output:
nee
PPI 8255
Touch Screen in Mobile Phone. r ing
(ii) UART (UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER): .ne
Baud Rate:
t
It is assumed that the receiver knows how fast each bit is being transmitted. This
transmission rate is known as the baud rate. The term ―Baud‖ is spelled only in the
asynchronous communication.
UART Mode is as Follows:
Non return to zero (NRZ) state denotes logic state is 1 at serial line.
Start of serial bits is signaled by 1 to 0 transitions on the line for a period equal to
reciprocal of baud rate.
Transmission of a byte consists of one start bit, eight data bits, one parity bit and
one stop bit.
41

ww
w. E
Stop bit is denoted by the logic one.
1 bit time = δT
asyTherefore 10 bit time = 10δT

Programmable bit (P.bit) is used for parity detection (or) to specify the purpose of
En
serial data bits.
gi
For transmission and reception, UART 16550 has a 16 byte FIFO buffer.
nee
r ing
.ne
t
42

UNIT-3
EMBEDDED FIRMWARE DEVELPOMENT ENVIRONMENT
PART – A( 2 marks)
1. What is EDLC?
Embedded Product Development Life Cycle (EDLC) is an analysis – Design –
Implementation based standard problem solving approach for embedded product
development. EDLC defines the interaction and activities among various groups of a
product development sector including project management, system design and
development, system testing, release management and quality assurance.
2. What is Model?
The Life cycle of a product development is commonly referred as Models and a Model
ww
defines the various phases involved in a product‘s life cycle. The Embedded product life
cycle model contains the phases: Need, Conceptualization, Analysis, Design,
w. E
Development and testing, Deployment, Support, Upgrades and Retirement/Disposal.
3.
asy
Define conceptualization phase.
Conceptualization phase is the phase dealing with product concept development. It
En
includes activities like product feasibility analysis, cost benefit analysis, product scoping
4. gi
and planning for next phases.
Name three categories of product development.
 The 3 categories are nee
 New or custom product development
 Product Re-engineering
r ing
 Product maintenance
.ne
5. What are the models used in EDLC?
The models are:
t
 The linear or waterfall models
 Iterative or incremental or fountain models
 Prototyping or Evolutionary Models
 Spiral Models
6. Define Spiral Model.

Spiral Model is the EDLC model combining linear and prototyping model to give the
best possible risk minimization in product development.
7. Define data flow model.
43

Data flow is a type of process network model. In data flow, a program is specified by a
directed graph. The nodes of the graph represent computational functions that map
input data into output data. Data is represented by a circle and data flow is represented
using arrows.
8. Define deployment phase.
The deployment phase deals with the launching of the product. Product deployment
notification, training plan execution, product installation, product post implementation
review, etc., are the activities performed during deployment phase.
9. Define product design space and development phase.
Design phase – It deals with the implementation aspects of the required functionalities
for the product
ww
Development Phase – It transforms the design into a realizable product. The detailed
specifications generated during the design phase are translated into hardware and
w. E
firmware during the development phase.
asy
10. What are the differences between data flow model and state machine model?
Both data flow and finite state machine are models of computation. The data flow
En
model of computation is used in signal processing design and modeling of DSP
gi
algorithms. On the other hand FSMs have been developed to solve a different class of
nee
problems, namely sequential control. FSMs are an appropriate modeling approach for
control-dominant applications. Mixing data flow with FSMs is a good solution for
r ing
representing a system, which requires both signal processing and control. This
integrated is very useful to eradicate the drawbacks.
UNIT-3
.ne
1. Discuss the Objective of EDLC?
PART-B(16 marks)
t
EMBEDDED PRODUCT DEVELOPMENT LIFE CYCLE (EDLC)
EDLC is an Analysis – Design – Implementation based problem solving approach for
the product development.
 Analysis – what product needs to be developed?
 Design – Good approach for building it
 Implementation – To develop it
ESSENTIALITY OF EDLC:
The necessity and importance of EDLC is to understand the scope and complexity of
the work involved in any embedded product development. EDLC defines the interaction
44

and activities among various groups of a product development sector including project
management, system design & development, system testing, release management &
quality assurance. EDLC standards are needed to design for the product development,
which provides the uniformity in development approaches.
OBJECTIVES OF EDLC:
The aim of any product development is the Marginal benefit. Generally, marginal
benefit is expressed as ―Return on Investment‖ (ROI). The investment for a
product development includes initial investment, manpower investment &
infrastructure investment etc.
A developed product needs to be acceptable by the end user that it has to meet
the requirements of the end user in terms of quality, reliability & functionality.
ww EDLC helps in ensuring all these requirements by following 3 objectives:
w. EEnsure that high quality products are delivered to end user.

Risk minimization & defect prevention in product development through project
asy
management
Maximize the productivity
En
Ensuring High quality for products:
gi
The primary definition of quality in any embedded product development is return
nee
on investment achieved by the product. In order to survive in market, quality is
the most important factor to be taken care of while developing the product.
r ing
Qualitative attributes depends on the budget of the product, because budget
.ne
allocation is very important.
Budget allocation might have done after analyzing the market, trends &
requirements of product, competition etc.
t
EDLC must ensure that the development of the product has taken account of all
the quantitative & qualitative attributes of the embedded system.
Risk minimization & defect prevention through management:
The project management is essential in product development and it needed more
significance.
Project management adds an extra cost on the budget but it is essential for
ensuring the development process is going in the right direction and the
schedules of the development activity are meeting.
45

Projects which are complex and requires timeliness should have a dedicated &
skilled project management part & hence they are said to be ―Highly‖ bounded to
project management.
Project management is essential for predictability, coordination and risk
minimization
The time frame may be expressed in number of person days (PDS)
Predictability – Analyze the time to finish the product.
Coordination – Developers are needed to do the job
Risk management – 1. Backup of resources to overcome critical situation
2. Ensuring defective product is not developed
Increased Productivity:
ww
Productivity is a measure of efficiency as well as Return on Investment. Different ways
w. E
to improve the productivity are:
Saving the manpower effort will definitely result increased productivity
asy
Use of automated tools wherever is required
Work which has been done for the previous product can be used, when there is a
En
presence of similarities between the previous and present product. This is called
gi
as ―Re-usable effort‖.
nee
Usage of resource persons with specific set of skills, which exactly matches the
requirements of the product. This reduces the time in training the resource.
r ing
Example: resource with expertise in zigbee wireless technology for developing a
.ne
wireless interface for the product. This kind of resource does not need training.
2. What are the different phases of EDLC?

t
A life cycle of a product development is commonly referred as the ―Model‖
A sample model contains 5 Phases
 Requirement Analysis
 Design
 Development and test
 Deployment
 Maintenance
Complexity depends on number of phases involved in EDLC
46

Need:
Any embedded product may evolve as an output of a need. Need may come from an
ww
individual or from public or from company (generally from an end user or client). Need
initiate the concept proposal. The human resource management and funding agency
w. E
reviews the concept proposal and provides the approval. Then it goes to a product
development team. The product development need can be visualized in any one of the
a) asy
following three needs.
New or Custom Product Development:
En
The need for a new product which does not exist in the market or a product which acts
gi
as a competitor to an existing product in the current market will lead to the development
nee
of completely new product. Example: Various manufacturers act as competitors in
r
developing the mobile phones.
b) Product Re-engineering:
ing
.ne
The process of making changes in an existing product design and launching it as a new
version is known as re-engineering a product. It is termed as product upgrade. Re-
engineering an existing product comes as a result of the following needs.
Change in business requirements
t
User interface enhancements
Technology upgrades
c) Product Maintenance:
The technical support provides to the end user for an existing product in the market is
―Product Maintenance need‖. It has two categories 1. Corrective Maintenance deals
with making corrective actions following a failure or non-functioning. 2. Preventive
maintenance is the scheduled maintenance to avoid the failure or non-functioning of the
product.
Conceptualization:
47

This is the product concept development phase and it begins immediately after a
concept proposal is approved. This phase defines the scope of the concept, performs
cost benefit analysis and feasibility study and prepares project management and risk
management plans.
ww
w. E
asy
En
The conceptualization phase involves 2 types of activities namely,
1.
2.
gi
Planning Activity
Analysis and study Activity
nee
r
Feasibility study – examines the need for the product and analyses the
ing
technical as well as financial feasibility of the product under construction.
.ne
Cost Benefit Analysis (CBA) – It examines and total up the equivalent money
value of the benefits and costs of the product under consideration and provide an idea
about the worthwhile of the product. Some principles of CBA are:
1.
t
Common unit of measurement – Marginal profit is expressed in terms of common
currency. Example: Indian Rupee or US dollar
2. Market choice based benefit measurement – value of money
3. Target end users.
Product Scope – deals with what is in scope and what is not in the scope.
Planning Activities – It contains plans for product development. It also contains
recommendation such as
o The product is feasible and proceeds to the next phase of the product life cycle.
o If the Product is not feasible, scrap the product.
Analysis:
48

Requirement analysis phase provides emphasis on determining ‗what functions

must be performed by the product‘ rather than how to perform those functions.
ww
w. E Analysis and documentation – this activity consolidates the business needs of
the product under development and analyses the purpose of the product. The various
asy
requirement are:
o
o En
Functional Capabilities
Operational and non-operational quality parameters
o
o
gi
Data Requirements
User manuals nee
o
o
Operational requirements
Maintenance requirements r ing
.ne
Interface Definition And Documentation – This activity should clearly analyze
document it. It is for proper flow of data throughout the life cycle. t
on the physical interface as well as data exchange through the interfaces and should
Defining test plan and Procedures – Master test plan consist of various type of
testing in a product development. They are: Unit testing, Integration testing and System
testing.
Design:
This deals with the entire design of the product taking the requirements into
consideration and focuses on how the functionalities can be delivered. Preliminary
design consists of the list are,
Inputs and Outputs are defined here
49

Product will look like a black box

Preliminary design document is sent for review to the client.
After the client review, detailed design architecture is generated.
This design also needs to be reviewed and get approved by the end user.
ww
w. E
asy
En
gi nee
Development and testing:
r ing
Development phase transforms the design into realizable product.
Design is transformed into hardware and firmware. .ne
Look and feel of the device is very important.
Testing phase can be divided into,
t
 Unit Testing – independent testing of Hardware and firmware
 Integration Testing - testing after integrating Hardware and firmware
 System Testing – Testing of whole system on functionality and non-functionality
basis
 User acceptance testing – testing of the product against the criteria mentioned
by the end user or client.
 Test reports.
Deployment:
50

A process of launching fully functional model into the market is called deployment. It is
also known as first customer shipping. The essential tasks performed during the
deployment phase are,
 Notification of product deployment
 Execution of training plan
 Product installation
 Product Post – Implementation Review
Support:
This deals with the operation and maintenance of the product. Support should be
providing to the end user to fix the bugs of the product. The various activities involved in
the support phase are:
ww


Setup a dedicated support wing. Example: Customer Care.
Identification of bugs and Areas of improvement.
w. E
Upgrades:
 asy
It deals with
Releasing of new version for the product which is already exist in the market.

En
Releasing of major bug fixes. (Firmware up gradation)
gi
Retirement/Disposal:
nee
Everything in the world changes, the technology you feel as the most advanced
and best today may not be the same tomorrow. Due to this reason, the product cannot
r ing
sustain for a long time in the market. It has to be disposed on right time before it causes
the loss. The disposition of the product is essential due to the following reason.
1. Rapid technological advancements.
.ne
2. Increased user needs.
3. Mention and explain the approaches of EDLC?
MODELLING OF EDLC: (EDLC APPROACHES)
t
The various approaches in modelling the EDLC are:
Linear or water fall model:
In this model, each phase of EDLC is executed in sequence and the flow is
unidirectional with output of one phase serving as the input to the next
phase. The feedback of each pulse is available locally and only after they are
executed.
51

ww
w. E
asy

En
Review mechanisms are employed to ensure that the process flow in right
direction.
 gi nee
Bugs are not fixed immediately and they are postponed to support phase.
Advantages:


Rich documentation
Easy project management
r ing
 Good control over cost & schedule .ne
Drawbacks:
 Analysis can be done without any design
t
 Risk analysis is performed only once throughout the development
 Bugs are fixed only at support phase
Iterative / Incremental / Fountain EDLC Model:

The iterative model can be viewed as a cascaded series of linear models.
Do some analysis, follow some design, the some implementation, evaluate it and
based on short comings, cycle back through and conduct more analysis, opt for
new design and implementation.
Repeat the cycles until the requirements are met.
52

The incremental model is a superset of iterative model where the requirements

are known at the beginning.
ww
w. E
asy
En
Advantages:
Fig: Fountain model

previous
gi nee
Feedback is at each function. So each cycle can act as a maintenance phase for
cycle

 r ing
Risk is spread across each individual cycle and can be minimized easily
Project management as well as testing is much simpler to the linear model
 Product development can be stopped at any stage
.ne
Drawbacks:


Extensive review requirement at each cycle t
Training is required for each new deployment at the end of each development
cycle.
Prototyping / Evolutionary Model:

 This model is similar to the iterative model and the product is developed in
multiple cycles
 The only difference is the model produces more refined prototype of the product
at each cycle instead of just adding the functionality at each cycle like in interval
model
53

 The short comings of the protomodel after each cycle are evaluated and it is
ww
fixed in the

next cycle
After the initial requirement analysis, design is made and development process is
w. E
started. Then this prototype is sent to the customer for evaluation. The customer
provides the feedback to the developer for further improvement.

asy
Then the developer repeat the process with some additional features and finally
delivered to the outside world
En
Advantages:


gi
Feedback after each implementation and fire tuning is also possible
nee
By using the prototype model, the risk is spread across each proto development
cycle & it
Drawbacks:
is under control
r ing

 .ne
Deviations from expected cost and schedule due to requirements refinement.
Increased project management

t
Minimal documentation on each prototype may create problems in backward
prototype traceability
 Increased configuration management activities
Spiral Model:
 Spiral model is best suited for the development of complex embedded products &
situations where the requirements are changing from customer side
 Risk evaluation in each stage helps in reducing risk
54

 Spiral model is best suited for the development of complex embedded products &
situations where the requirements are changing from customer side
ww


Risk evaluation in each stage helps in reducing risk
It is the combination of linear & prototype models to give the best possible risk
w. E minimized EDLC model. The activities in the spiral model present in the 4
asy
quadrants are:
o Determine objectives, alternatives, constraints
Eno Evaluate alternatives, identity & resolve risks
gi
o Develop & test
o Plan
nee
4. What are the fundamental issues in Hardware-Software co-design?
Co design
r ing
The meeting of system-level objectives by exploiting the trade-offs between hardware
and software in a system through their concurrent design
.ne
o
Key concepts
Concurrent: t
hardware and software developed at the same time on parallel
paths
o Integrated: interaction between hardware and software developments to
produce designs that meet performance criteria and functional specifications
Fundamental issues:
The problem statement is hardware software co-design and its issues. Some of the
issues are:
Selecting the model:
 A model is a formal system consisting of objects & composition rules. It is hard to
make a decision on which model should be followed in a particular system design
 Models are used for capturing & describing the system characteristics
55

 Designers switch between a variety of models, because the objective varies with
each phase
Selecting the architecture:
The architecture specifies how a system is going to implement in terms of the
number & types of different components and the interconnection among them. Some
type of architecture falls into application specific architecture class, while others fall into
either general purpose architecture class or parallel processing class. The commonly
used architectures is system design are:
1. The controller Architecture – implements the finite state machine model using a
state register holds the present state and the combinational circuits holds the next state
& output
ww
2. The data path architecture – suitable for implementing the data flow graph model.
A datapath represents a channel between the input and output. The datapath contains
w. E
registers, counters, memories & ports. Ports connect the datapath to multiple buses.
The finite state machine datapath – this architecture combines the controller
3.
asy
architecture with datapath architecture. The controller generates the control input,
En
whereas the datapath processes the data.
4.
gi
The complex instruction set computing (CISC) – this architecture uses an
nee
instruction set for solving complex operations. The use of a single complex instruction in
place of multiple simple instructions greatly reduces the program memory access &
r ing
program memory size requirement. On the other hand, Reduced Instruction Set
Computing (RISC) architecture uses the multiple RISC instructions to perform a
complex operation. RISC architecture supports extensive pipelining
.ne
5.
units in the datapath
6.
t
The Very Long Instruction Word (VLIW) – this architecture implements functional
Parallel processing architecture – implements multiple concurrent processing

elements and each processing element may associate a datapath containing register &
local memory. Single Instruction Multiple Data (SIMD) & Multiple Instruction Multiple
Data (MIMD) architectures are examples for parallel processing architecture. SIMD –
eg: Reconfigurable process, MIMD – eg: Multiprocessor systems
Selecting the language:
A programming language captures a ‗Computational Model‘ and maps it into
architecture. A model can be captured using multiple programming languages like C,
C++, C#, Java, etc. for software implementations and languages like VHOL, system C,
56

verilog, etc. for hardware implementations. C++ is a good language for capturing an
object oriented model.
Partitioning system requirements into hardware & software:
Various hardware software trade-offs are used for making a decision on the
hardware-software portioning.
5. Discuss about the various computational models in embedded design.
COMPUTATIONAL MODELS IN EMBEDDED DESIGN
The commonly used computational models in embedded system design are
(i) Data flow graph model(DFG):
This model translates the data processing requirement into a data flow graph. It is a
data model. This model emphasis on the data and operations on the data which
ww
transforms the Input data to output data. In DFG model, Data is represented by a circle
data flow is represented arrows.An inward arrow to the process denotes the output
w. E
data. Data driven Embedded are modeled using DFG.
asy
En
gi nee
r ing
.ne
t
A DFG model is said to be either acyclic DFG (does not contain multiple input values &
multiple output values) or non-acyclic DFG (output is feedback to the input).
(ii) State machine model:
The state machine model explains the system behaviours with states, events, actions
and transitions. The representation of a state is current situation. An event is an input to
the state. The event acts as stimulus for state transition. The activity evolved in state
machine is action. This model is used for event driven embedded systems. Eg: control
and industrial applications.
A Finite State Machine (FSM) model is one in which the number of states are finite.
Consider the FSM model for automatic seat belt warning system as an example.
57

Motor control software design is another example for state machine model.
ww
w. E
asy
En
(iii)
gi
Sequential Program Model:
nee
The functions are executed in a sequential order, which is same as the conventional
r
procedural programming. The program instructions are iterated and executed with
ing
condition and the data gets transformed through a series of operations. The tools for
.ne
sequential program model are FSM & flowcharts. Consider an example ‗Seat Belt
warning system‘ programming.
# define ON 1
# define OFF 0
t
# define YES 1
# define NO 0
Void seatbelt_caution ()
{
Waiting ( );
If (checkIgnition ( ) = = ON)
{
If (checkseat belt ( ) = = OFF)
{
58

SetTimes (3);
Start Alarm ( );
While ((check seat belt ( ) = = OFF) && (check Ignition ( ) = = OFF) &&(Timer Expire ( )
= = NO));
Stop Alarm ( );
}
}
}
Flow chart Approach:
ww
w. E
asy
En
gi nee
r ing
(iv) Concurrent Process model:
.ne
t
This model executes the processes concurrently. It is easier to implement than the
conventional sequential execution. Sequential execution leads to poor processor
utilization. Concurrent processing model requires additional overheads in task
scheduling, task synchronization and communication. Now consider the example of seat
belt warning system in concurrent processing model. We can split the tasks into:
1. Timer task for waiting 10 seconds
2. Task for checking the ignition key status
3. Task for checking the seat belt status
4. Task for starting & stopping the alarm
5. Alarm timer task for waiting 3 seconds
These tasks are needed to synchronize.
59

ww
w. E
asy
Figure: Concurrent Processing program model for seat belt warning system.
The concurrent processing model is commonly used for the modeling of real time
system.
En
(v)


gi
Object – oriented model:
It is an object based model
nee
It splits the complex software requirement into well defined pieces called objects


r ing
It brings re-usability, maintainability & productivity in system design
Each object is characterized by a set of unique behavior & state. A class is an
abstract of a set of objects.
.ne

t
A class represents the state of an object through member variables and object
behavior through member functions.
 The member variables can be public, private or protected
 Private member access within the class and public member access within the
class as well as outside the class.
 The concept of object & class brings abstraction, holding and protection.
60

UNIT 4
RTOS BASED EMBEDDED SYSTEM DESIGN
Part- A ( 2 marks)
1. Define process.
Process is a computational unit that processes on a CPU under the control of a
scheduling kernel of an OS. It has a process structure, called Process control block. A
process defines a sequentially executing program and its state.
2. What are the states of a process?
a. Running b. Ready c. Waiting
3. What is a thread?
Thread is a concept in Java and UNIX and it is a light weight sub process or
ww
process in an application program. It is controlled by the OS kernel. It has a process
structure, called thread stack, at the memory. It has a unique ID .It have states in the
w. E
system as follows: stating, running, blocked and finished.
asy
4. Define scheduling.
This is defined as a process of selection which says that a process has the right
En
to use the processor at given time.
gi
5. What are the types of scheduling?
1. Time division multiple access scheduling.
nee
6. Define round robin scheduling and priority scheduling
2. Round robin scheduling.
r ing
Round robin scheduling: This type of scheduling also employs the hyper period as an
interval. The processes are run in the given order.
.ne
Priority scheduling: A simple scheduler maintains a priority queue of processes that
are in the run able state.
7. Give the different styles of inter process communication.
1. Shared memory. 2. Message passing.
t
8. Differentiate pre-emptive and non pre-emptive multitasking.
Preemptive multitasking differs from non-preemptive multitasking in that the operating
system can take control of the processor without the task‘s cooperation
9. What is meant by PCB?
Process Control Block‘ is abbreviated as PCB.PCB is a data structure which
contains all the information and components regarding with the process.
10. Define Semaphore and mutex.
Semaphore provides a mechanism to let a task wait till another finishes. It is a
way of synchronizing concurrent processing operations. When a semaphore is taken by
61

a task then that task has access to the necessary resources. When given the resources
unlock. Mutex is a semaphore that gives at an instance two tasks mutually exclusive
access to resources.
11. Define priority inversion & priority inheritance.
Priority inversion: A problem in which a low priority task inadvertently does not
release the process for a higher priority task is called as Priority inversion.
Priority Inheritance: Priority inversion problems are eliminated by using a method
called priority inheritance. The process priority will be increased to the maximum priority
of any process which waits for any resource which has a resource lock. This is the
programming methodology of priority inheritance.
12. What is RTOS?
ww An RTOS is an OS for response time controlled and event controlled processes.

RTOS is an OS for embedded systems, as these have real time programming issues to
w. E
solve.
asy
13. What are the real time system level functions in UC/OS II? State some.
1. Initiating the OS before starting the use of the RTOS functions.
En
2. Starting the use of RTOS multi-tasking functions and running the states.
gi
3. Starting the use of RTOS system clock.
14. Name any two mailbox related functions.
a.OS_Event *OSMboxCreate(void *mboxMsg) nee
b.Void *OSMboxAccept(OS_EVENT *mboxMsg)
r ing
15. Name any two queue related functions for the inter task communications.
a.OS_Event OSQCreate(void **QTop,unsigned byte qSize)
.ne
b.Unsigned byte OSQPostFront(OS_EVENT *QMsgPointer,void *qmsg).
UNIT – 4
t
PART B(16 marks)
1. Discuss deeply about the pre-emptive & non –pre-emptive scheduling with
suitable diagrams.
NON – PREEMPTIVE SCHEDULING:
Non- Preemptive scheduling is employed in non-preemptive multitasking systems. In
this scheduling type, the currently executing task/process is allowed to run until it
terminates or enters the wait state waiting for an I/O or system resource. The various
types of non-preemptive scheduling algorithms are,
62

1. First Come First Served (FCFS)

FCFS also known as first in first out (FIFO) is the simplest scheduling policy.
Arriving jobs are inserted into the tail (rear) of the ready queue and process to be
executed next is removed from the head (front) of the queue.
FCFS performs better for long jobs. Relative importance of jobs measured only
by arrival time. A long CPU bound job may hog the CPU and may force shorter jobs to
wait prolonged periods. This in turn may lead to a lengthy queue of ready jobs and
hence to the convoy effect.
Turnaround Time = Waiting Time + Service Time
ww
w. E
asy
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Advantages:
1.
2.
gi
Better for long process
Simple method nee
3. No starvation
Disadvantages:
r ing
1. .ne
Convoy effect occurs. Even very small process should wait for its turn to come to
2. Throughput is not emphasized.

t
utilize the CPU. Short process behind long process results in lower CPU utilization.
2. Shortest Job First Scheduling (SJF):

This algorithm associated with each process the length of the next CPU burst. Shortest
job first scheduling is also called shortest process next (SPN). The process with the
shortest expected processing time is selected for execution among the available
process in the ready queue. Thus, a short process will jump to the head of the queue
over long jobs.
If the next CPU bursts of two processes are the same then FCFS scheduling is cued to
break the tie. SJF scheduling algorithm is probably optimal. It gives the minimum
average time for a given set of processes. It cannot be implemented at the level of short
63

term CPU scheduling. There is no way of knowing the shortest CPU burst. SJF can be
preemptive or non-preemptive.
A preemptive SJF algorithm will preempt the currently executing process, if the next
CPU burst of newly arrived process may be shorter than what is left to the currently
executing process.
A non-preemptive SJF algorithm will allow the currently running process to finish.
Preemptive SJF scheduling is sometimes called shortest remaining time first algorithm.
ww
w. E
asy
Advantages:
1.
En
It gives superior turnaround time performance to shortest process next because
2. gi
a short job is given immediate preference to a running longer job.
Throughput is high.
Disadvantages: nee
1.
r ing
Elapsed time must be recorded, it results an additional overhead on the
processor.
2. Starvation may be possible for the longer processes.
.ne
PRE-EMPTIVE SCHEDULING:
t
In preemptive mode, currently running process may be interrupted and forces the
currently active process to release the CPU on certain events such as a clock interrupt,
some I/O interrupts or a system call and they moved to the ready state by the OS.
When a new process arrives or when a interrupt occurs, preemptive policies may
incur greater overhead than non-preemptive version but preemptive version may
provide better results.
It is desirable to maximize CPU utilization and throughput and to minimize
turnaround time, waiting time and response time.
The various types of pre-emptive scheduling are
1. Priority – Based Scheduling:
64

Each process is assigned a priority. The ready list contains an entry for each
process ordered by its priority. The process at the beginning of the list (highest priority)
is picked first.
A variation of this scheme allows preemption of the current process when a
higher priority process arrives.
Another variation of the policy adds an aging scheme, whether the priority of a
process increases as it remains in the ready queue. Hence, this will eventually execute
to completion.
If the equal priority process is in running state, after the completion of the present
running process CPU is allocated to this, even though one more equal priority process
is to arrive.
ww
w. E
asy
En
Advantage:
of it.
gi nee
Very good response for the highest priority process over non-pre-emptive version
Disadvantage:
r ing
Starvation may be possible for the lowest priority processes.
.ne
2. Write about the interrupt routines in RTOS.
t
Interrupts is a mechanism for alleviating the delay caused by uncertainty and for
maximizing system performance.
Interrupt Mechanism
Instead of polling the device or entering a wait state, the CPU continuously
executing its instruction and performing useful work.
When the I/O device is ready to transfer data, it sends an interrupt request
to the CPU. This is done via a dedicated signal on the control bus.
65

Scenario of Interrupt service Routine in RTOS:

Embedded application running on top of real time operating systems require
Interrupt Service Routines (ISRs) to handle interrupt generated by external event.
External events can be caused by just about anything, form an asynchronous
character arrival on a UART to a periodic timer interrupt. ISRs have the
ww
responsibility of acknowledging the hardware condition and provide the initial
handling of data sent or received as required by the interrupt.
w. E
An ISR often is responsible for providing the RTOS with information necessary
provide services to application threads. Examples include moving data into a buffer
to
asy
for processing, adding an entry to a queue for processing, setting a value to
En
indicate that an event has occurred and so on.
Since application code execution is interrupted during the execution of an ISR,
gi
most application minimize the amount of code in the ISR and rely instead on
nee
non- ISR code (Thread or Task) to complete the processing. This allows the
r
highest priority application code to be executed as quickly as possible and
ing
delayed as little as possible, even in situations with intense interrupt activity.
.ne
Interrupt Routines in RTOS Environment and Handling of Interrupt source calls:
ISRS have the higher priorities over the RTOS function and the tasks. So
ISR should not wait for a semaphore, mailbox, message or queue message.
An ISR should not also wait for
t
mutex else it has to wait for other
critical section code to finish before the critical codes in the ISR can run.
Only the IPC accept function for these events can be used, not the post
function.
There are 3 alternative systems for the RTOS is to respond to the
hardware source calls from the interrupts.
1. Direct call to an ISR by an interrupting source and ISR sending an
ISR Enter message:
On an interrupt, the process running at the CPU is interrupted and the
ISR corresponding to that source starts executing (1).
66

A hardware source calls an ISR directly. The ISR just sends an ISR enter
message to the RTOS. ISR enter message is to inform the RTOS than an ISR
has taken control of the CPU (2).
ww
The case involves the two function such as ISR and OS function in two memory
block.
w. E ISR code can send into a mailbox or message queue(3), but the task
asy
waiting for a mailbox or message queue does not start before the return from
the ISR (4).
En
When ISR finishes, it sends Exit message to OS.
gi
On return from ISR by retrieving saved context, the RTOS later on returns to the
interrupted process or reschedules the process.
nee
RTOS action depends on the event messages, whether the task waiting for the
r ing
event messages from the ISR is a task of higher priority than the interrupted task on the
interrupt.
.ne
The special ISR semaphore used in this case is OSISRSemPost ( ) which
t
executes the ISR. OS ensures that OSISRSemPost is returned after any system call
from the ISR.
2. RTOS first interrupting on an interrupt, then RTOS calling the
corresponding ISR:
On interrupt of a task, say, Nth task, the RTOS first gets itself the hardware
source call (1) and initiates the corresponding ISR after saving the present processor
status (2).
Then the ISR (3) during execution then can post one or more outputs (4) for the
events and messages into the mail boxes or queues.
67

Figure: System 2 (Three memory blocks)

This case involves the one ISR function (ISRk) and two processes (OS and pth task) in
three memory blocks other than the interrupted Nth task.
When the interrupt source k is interrupted (1), OS finishes the critical code till the
ww
pre emption point and calls the ISR routine for interrupt k called as ISR k (3) after saving
w. E
the context of a previous task N onto a stack (2)
After executing the ISRk routine, the ISR in step (4) can post the event or
asy
message to the OS for initiating the Nth or Pth task after the return (5) from the ISR and
after retrieving the Nth or Pth task context.
En
The OS initiates the Nth or Pth task based upon their priorities.
3.
gi
The ISR must be short and it must put post the messages for another task.
nee
RTOS First Interrupting on an Interrupt, then RTOS initiating the ISR and
then an ISR:
r ing
The two levels of ISR in RTOSes are Fast Level ISR (FLISR) and Slow Level ISR
.ne
(SLISR). FLISR is also called as hardware interrupt ISR and SLISR is also called as
software interrupt ISR. FLISR is just the ISR in RTOS and SLISR is called as Interrupt
Service Thread (IST).
t
FLISR reduces the interrupt latency and jitter for an interrupt service. A k th IST is
a thread to service an kth interrupt source call. An IST function is referred as deferred
procedure call of the ISR.
68

When an interrupt source k is interrupted (1), OS finishes the critical code till the
pre emption point and calls the ISR routine for interrupt k called as ISR k (3) after saving
ww
the context of a previous task N onto a stack (2)
w. E The ISR during execution can send one or more outputs for the events and
messages into the mailboxes or queues for the ISTs (4). The IST executes the device
asy
and platform independent code.
The ISR just before the end enables further pre-emption from the same or other
En
hardware sources (5). The ISR can post messages into the FIFO for the ISTs after
gi
recognizing the interrupt source and its priority. The ISTs in the FIFO that have received
nee
the messages from the ISR executes (6) as per their priorities on return (5) from the
ISR.
r ing
The ISR has the highest priority and preempts all pending ISTs and tasks, when
.ne
no ISR or IST is pending execution in the FIFO, the interrupted task runs on return (7).
3) Write brief notes on i) Process ii) Threads iii) Tasks
i) PROCESS
t
Defn: Process is defined as a computational unit that processes on a CPU and whose
state changes under the control of kernel of an OS. It has a state ,which at an instance
defines by the process status(running, blocked or finished),process structure –its data,
objects and resources and process control block.
A process runs on scheduling by OS (kernel) which gives the control of CPU to
the process. Process runs instructions and the continuous changes of its state take
place as the Program counter changes.
69

Fig: Processes
Process control block
PCB is a data structure having the information using which the OS controls the process
state. The PCB stores in the protected memory addresses at kernel.The PCB consists
of the following information about the process state.
1. Process ID,process priority,parent process,child process and address to the next
process PCB which will run next.
2. Allocated program memory address blocks in physical memory and in secondary
ww
memory for the process codes.
3. Allocated process-specific data address blocks.
w. E
4. Allocated process heap addresses.
asy
5. Allocated process stack addresses for the functions called during running of the
process.
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6. Allocated addresses of the CPU register
gi
7. Process-stae sugnal mask.
8. Signals dispatch table
9. OS-allocated resources descriptors nee
10. Security restrictions and permissions.
ii) THREAD
r ing
.ne
Application program can be said to consist of a number of threads or a number of
processes and threads
t
1.A thread consists of sequentially executable program(codes) under state-control by an
OS.
2.The state of information of a thread is represented by thread- state(started, running,
blocked or finished),thread structure –its data, objects and a subset of the process
resources and thread-stack.
3. A thread is a light weight entity
Defn: A thread is a process or sub process within a process that has its own PC, its
own SP and stack ,its own priority and its own variables that load into the processor
registers on context switching and is processed concurrently along with other threads.
70

Fig :Threads
A multiprocessing OS runs more than one process. When a process consists of
multiple threads, it is called multithreaded process.
A thread can be considered as a daughter process.
A thread defines a minimum unit of a multithreaded process that an OS
ww
schedules onto the CPU and allocates the other system resources.
w. E Different threads of a process may share a common process structure.

Multiple threads can share the data of the process.
asy
Thread is a concept used in Java or Unix.
Thread is a process controlled entity
En
iii) TASKS
gi
Task is the term used for the process in the RTOSes for the embedded systems. A task
is similar to a process or thread in an OS.
nee
Defn: Task is defined as an embedded program computational unit that runs on a CPU
r ing
under the state-control of kernel of an OS. It has a state, which at an instance defines
by status ( running, blocked or finished),structure – its data, objects and resources and
control block. .ne
t
Fig: Tasks
A task consists of a sequentially executable program under a state-control by an
OS.
The state information of a task is represented by the task state (running, blocked
or finished),structure – its data, objects and resources and task control block.
Embedded software for an application may consist of a number of tasks .
Each task is independent in that it takes control of the CPU as scheduled by the
scheduler at the OS.
A task is an independent process
71

No task can call another task

The task can send signals and messages that can let another task waiting for this
signal.
Task states
1. Idle(created)state
2. Ready(active)state
3. Running state
4. Blocked(waiting)state
5. Deleted(finished)state
4) Explain briefly on how embedded processors have improved efficiency with
use of multitasking.
ww
Embedded OSs manages all embedded software using tasks, and can be either
unitasking or multitasking.
w. E In unitasking environments, only one task can exist at any given time.
asy In multitasking OS, multiple tasks are allowed to exist simultaneously.

In multitasking environment each process remain independent of others and do
En
not affect other process.
for gi
Some multitasking OSs also provides threads as an additional alternative means
encapsulating an instance of a program.
nee
Threads are created within the context of a task and depending on the OS the
task can own one or more threads
r ing
.ne
Threads of a task share the same resources like working directories, files, I/O
devices, etc., but have their own PCs, stack and scheduling information.
space or can
t
A task can contain at least one thread executing one program in one address
contain many threads executing different portions of one program in
one address space.
Multitasking OS
Task 1
Program1
Task 1 Registers
Program 1 Task 1 Stack
Program 2 OS
Process 2
Tasks and threads Program1
Task 2 Registers
….. Task 2 Stack
Program 1
72
Process 3
Program 2
Task
Downloaded 3 Registers
From : www.EasyEngineering.net
Task 3 Stack
Thread 1
Part of Program1
Thread 1
Task 1 Registers
Thread 2
Program1 Task 1 Stack
Part of Program1
Program 1 Task 1 Thread 2
Registers Memor
Registers
Thread 3
Task 1 Stack y
Program 2 OS Taskof
Part 1 Stack
Program1
Thread 3
Process 2
Registers
Program1
Task 1 Stack
….. Task 2
Registers
Program 1
Task 2 Stack
Process 3
Program 2
Task 3
Registers
wwMultitasking and process management

Task 3 Stack
w. E When an OS allows multiple tasks to coexist, one master processor or an
asy
embedded board can only execute one task or thread at any given time.
Therefore multitasking embedded OSs must find some way of allocating each
En
task a certain amount of time to use the master CPU and switching the master
processor
task
gi between the various tasks
communication. nee
This is done through task implementation, scheduling, synchronization and inters
r
Gives an illusion that single processors simultaneously run multiple tasks.
ing
Interleaving tasks
.ne
Time
process1
process2
process3
t
process1
Process 1 Process 2 Process 3
process2
Process 4 OS process3
process1
process3
process1
process4
process3
process4
process3
73

Task hierarchy
OS Initial Task
Task Task Task
Task Task Task Task
ww
w. E Tasks are structured as a hierarchy of parent and child tasks and when an
asy
embedded kernel starts up only one task exists.
All tasks create their child task through system calls.
En
The OS gains control and creates the Task Control Block (TCB)
gi
Memory is allocated for the new child task ,its TCB and the code to be executed
by the child task.
nee
After the task is set up to run, the system call returns and the OS releases control
back to the main program.
Types of Multitasking:
r ing
.ne
Multitasking involves the switching of execution among multiple tasks. It can be
classified into different types.
1. Cooperative multitasking – this is the most primitive form of multitasking in t
which a task/process gets a chance to execute only when the currently executing
task/process voluntarily relinquishes the CPU. In this method, any task/process
can hold the CPU as much time as it wants. Since this type of implementation
involves the mercy of the tasks each other for getting the CPU time for execution,
it is known as cooperative multitasking. If the currently executing task is non-
cooperative, the other tasks may have to wait for a long time to get the CPU.
2. Preemptive multitasking: This ensures that every task gets a chance to
execute. When and how much time a process gets is dependent on the
implementation of the preemptive scheduling. In preemptive scheduling, the
74

currently running task is pre empted to give a chance to other tasks to execute.
The preemption of task may be based on time slots or task/process priority.
3. Non-Preemptive Multitasking: In non- preemptive multitasking, the task which
is currently given the CPU time is allowed to execute until it terminates or enters
the Blocked/wait state waiting for an I/O or system resource. The cooperative
and non-preemptive multitasking differs in their behavior when they are in the
blocked/wait state.
In cooperative multitasking, the currently executing process/task need not relinquish
the CPU when it enters the ‗Blocked/wait‘ state waiting for an I/O or a shared resource
access or an event to occur where as in non-preemptive multitasking the currently
executing task relinquishes the CPU when it waits for an I/O or system resource or an
wwevent to occur.
w. E
5) Explain briefly about inter process communication. A) Semaphores B) Mailbox C)
Pipe
asy
SEMAPHORE
En
Suppose that there are two trains. Assume that they use an identical track. When
gi
the first train A is to start on the track, a signal or token for A is set and the signal or
token for the other train B is reset.
nee
Semaphore is used for signaling or notifying of a certain action and also for
notifying the acceptance of the notice or signal.
r ing
Release of a token is the occurrence of the event and acceptance of the token is
taking note of that event.
.ne
Let a Boolean variable, s represent a semaphore.
t
s increments from 0 to 1 for signaling or notifying occurrence of an event from a
section of codes in a task or thread.
s decrements from 1 to 0 when the event is taken note by a section in another
task waiting for that event and the waiting task codes start at another action
75

ww
w. E
asy
En
gi
Fig: Action on the function call in a program, Action on pre-emption of task A by B,
nee
program counter assignments
Binary Semaphore r ing

.ne
A semaphore is called binary semaphore when its value is 0, it is assumed that it has
been taken or accepted and when it is 1, it is assumed that it has been released or sent
or posted and no task has taken it yet.
t
An ISR can release the token, A task can release the token as well accept the
token or wait for taking the token.
Example
Consider an Automatic Chocolate Vending Machine(ACVM).After the task delivers the
chocolate , it has to notify to the display task to run a waiting section of the code to
display , ―Collect the nice chocolate, Thank you, Visit Again‖. The waiting section for the
display of the thank you message takes this notice and then it starts the display of thank
you message.
MAILBOX
76

A message mailbox is for an IPC message that can be used only by a

single destined task.
The mailbox message is a message pointer or can be a message.
The source(mail sender) is the task that sends the message pointer to a
created mailbox .
The destination is the place where the OSMBoxPend function waits for the
mailbox message and reads it when received.
Example:
A mobile phone LCD display task
In the mailbox, when the time and data message from a clock-process
ww arrives , the time is displayed at side corner on top line.
w. E When the message is from another task to display a phone number, it is

displayed at the middle.
asy When the message is to display the signal strength of the antenna, it is
displayed at the vertical bar on the left.
En
Mailbox types at the different operating systems (OSes)
1.
2. gi Multiple Unlimited Messages Queueing up
One message per mailbox
nee
3. Multiple messages with a priority parameter for each message
r ing
A queue may be assumed a special case of a mailbox with provision for
.ne
multiple messages or message pointers.
An OS can provide for queue from which a read can be on a FIFO basis
t
Or an OS can provide for multiple mailbox messages with each message
having a priority parameter.
Even if the messages are inserted in a different priority, the deletion is as per
the assigned priority parameter.
OS functions for the Mailbox
Create
Write(Post)
Accept
Read(Pend)
Query
77

RTOS functions for the Mailbox

1. OSMBoxCreate : Creates a box and initializes the mailbox contents with a NULL
pointer
2. OSMBoxPost: Sends a message to the box
3. OSMBoxAccept: Reads the current message pointer after checking the
presence yes or no.Deletes the mailbox when read.
4. OSMBoxWait:Waits for a mailbox message , which is read when received.
5. OSMBoxQuery: Queries the mailbox when read and not needed later.
PIPE
A message-pipe is a device for inserting (writing) and deleting(reading) from that
between two given interconnected tasks or two set of tasks. Writing and reading from a
ww
pipe is like using a C command fwrite with a file name to write into a named file, and
fread with a file name to read from the named file. Pipes are also like Java
w. E
PipeInputOutputStreams.
asy
1. fwrite task can insert(write) to a pipe at the back pointer address,*pBACK
2. fread task can delete (read) from a pipe at the front pointer address,*pFRONT
En
3. In a pipe there are no fixed number of bytes per message, but there is a end
gi
pointer. Pipe can have a variable number of bytes per message between the
initial and final pointers.
nee
4. Pipe is unidirectional. One thread or task inserts into it and the other one deletes
from it.
Functions at Operating systems
r ing
The OS functions for pipe are the following :
.ne
1. pipeDevCreate : Create a device which functions as pipe.
t
2. open( ) :Opening the device to enable its use from beginning of its allocated
buffer
3. connect( ) :Connecting a thread or task by inserting bytes to the thread or task
and deleting bytes from the pipe.
4. write ( ) :Inserting from the bottom of the empty memory space in the buffer
allotted to it.
5. read( ) :Deleting from the bottom of the unread memory spaces in the buffer filled
after writing into the pipe.
6. close( ) :Closing the device to enable its use from beginning of its allocated
buffer only after opening it.
78

ww
w. E
Fig: a) Function at operating system and use of write and read function by
task A and task B, b)Pipe messages in a message buffer
asy
En
6. Write short notes on i) shared memory, ii) message passing, iii) priority
inheritance iv) priority inversion.
gi
Shared Memory:
nee
Shared Memory is an efficient means of passing data between programs. One
r
program will create a memory portion which other processes can access.
ing
A shared memory is an extra piece of memory that is attached to some address
.ne
spaces for their owners to use. As a result, all of these processes share the same
t
memory segment and have access to it. Consequently, race conditions may occur if
memory accesses are not handled properly. The following figure shows two process
and their address spaces. The rectangle box is a shared memory attached to both
address spaces and both process 1 and process 2 can have access to this shared
memory as if the shared memory is past of its own address space. In some sense, the
original address space is ''extended" by attaching this shared memory.
79

Shared memory is a feature supported by UNIX system 5, including Linux, Sun

OS and Solaris. One process must explicitly ask for an area, using a key to be shared
by other processes. This process will be called the server. All other processes, the
clients that know the shared area can access it. However, there is no protection to a
shared memory and any process that knows it can access it freely. To protect a shared
memory from being accessed at the same time by several processes, a synchronization
protocol must be setup.
A shared memory segment is identified by a unique integer, the shared memory
ID. The shared memory itself is described by a structure of type shmid-ds in header file
sys / shm.h. To use this file, files sys / types.h and sys / ipc.h must be included.
Therefore, your program should start with the following lines:
ww
# include <sys / types.h>
# include <sys / ipc.h>
w. E
# include <sys / shm.h>
asy
A general scheme of using shared memory is the following:
For aserver, it should be started before any client. The server should perform the
En
following tasks:
gi
1. Ask for a shared memory with a memory key and memorize the returned
nee
shared memory ID. This is performed by system call shmget ().
2. Attach this shared memory to the server's address space with system call
shmat ().
r
3. Initialize the shared memory, if necessary. ing
4. Do something and wait for all client's completion.
.ne
5. Detach the shared memory with system call shmdt ().
6. Remove the Shared memory with system call shmctl ().
For the client part, the procedure is almost the same:
t
1. Ask for a shared memory with the same memory key and memorize the
returned shared memory ID.
2. Attach this shared memory to the client's address space.
3. Use the memory.
4. Detach all shared memory segments, if necessary.
5. Exit.
Message Passing:
Most general purpose OS actually copy messages as twice as they transfer there from
task to task via a message queue. In RTOS, the OS copies a pointer to the message,
80

delivers the pointer to the message - receiver task and then deletes the copy of the
pointer with message sender task.
Message Passing is an asynchronous / synchronous information exchange

mechanism used for Inter process or thread communication. The major difference
ww
between shared memory and message passing technique is that, through shared
memory lots of data can be shared where as only limited amount of info / data is passed
w. E
through message passing. Also message passing is relatively fast and free from the
synchronisation overheads compared to shared memory.
asy
Message passing constructs:
En
There are 2 basic message passing primitives such as send and receive.
Send primitive: Sends a message on a specified channel from one process to
another, gi nee
Receive primitive: Receives a message on a specified channel from other
processes.
r ing
Message passing is classified into message queue, Mail box and signalling.
Message Queue:
.ne
t
The process which wants to talk to another process posts the message to a First-
In-First-Out queue called message queue, which stores the messages temporarily in a
system defined memory object to pass it to the desired process.
Messages are sent and received through send and receive methods. the
messages are exchanged through a message queue.
The message mechanism is classified into synchronous and asynchronous
based on the behaviour of the message posting thread. In asynchronous
messaging, the message posting thread just posts the message to the queue
and it will not wait for an acceptance from the thread to which the message is
posted.
In synchronous messaging, the thread which posts a message enters waiting
state and waits for the message result from the thread to which the message is
81

posted.
The features of a message queue IPC are
1. An OS provides for inserting and deleting the message pointers or messages.
2. Each queue for the message needs initialization before using functions in
kernel for the queue.
3. Each Created queue has an ID.
4. Each queue has a user defined size.
5. When an OS call is to insert a message into the queue, the bytes are as per
the pointed number of bytes.
6. When a queue becomes full, there is error handling function to handle that.
There is a presence of two pointers for queue head and tail memory locations are.
ww Q HEAD and
Q TAIL
w. E
The µC/OS - II Functions for a queue are
asy
1. OSQ Create 2. OSQ POST 3. OSQ PEND 4. OSQ ACCEPT 5. OSQ FLUSH 6.
OSQ QUERY 7. OSQ POST Front.
En
gi nee
r ing
.ne
Figure: OS functions for Queue between task 1 and task 2
Priority Inversion
t
Priority inversion is the byproduct of the combination of blocking based process
synchronization and preemptive priority scheduling. Priority inversion is the condition in
which a high priority task needs to wait for a low priority task to release a resource
which is share between the high priority task and the low priority task and a medium
priority task which doesn‘t require the shared resource continue its execution by pre
emptying the low priority task.
Priority based preemptive scheduling technique ensures that a high priority task
is always executed first, whereas the lock based process synchronization mechanism
ensures that a process will not access a shared resource, which is currently in use by
82

another process. The synchronization technique is used to avoid conflients in the

concurrent access of the shared resources.
Let process A, process B and process C be three processes with priorities High,
Medium and Low respectively. Process A and Process C share a variable X and
the access to this variable is synchronized through a mutual exclusion
mechanism like Binary semaphore.
Imagine a situation where process C is ready and is picked up for execution by
the schedules and Process C tries to access the shared variable X.
Immediately after process C acquires the semaphore S, Process B enters the
Ready state. Since Process B is of higher priority compared to process C.
Process C is preempted and Process B starts executing.\
ww Now process A is of higher priority than process B, Process B is preempted and
w. Eprocess A is scheduled for execution. Process A tries to access shared variable

X which is currently accessed by process C. So Process A will not be able to
asy
access if and then it enters into the blocked state.
Now process B gets the CPU and it continued its execution until it relinquishes
En
the CPU voluntarily or enters a wait state or preempted by another high priority
task.
gi nee
Process A has to wait till process C gets a chance to execute and release the
semaphore. This produces unwanted delay in the execution of the high priority
r ing
task which is supposed to be executed immediately when it was ready.
Priority Inversion may be sporadic in nature but can lead to potential damages as
a result of missing critical dead lines. .ne
t
83

Priority Inheritance
A low-priority task that is currently accessing (by holding the lock) a shared
resource requested by high priority task temporarily ‗inherits‘ the priority of that high-
priority task, from the moment the high-priority task raises the request Boosting the
priority of the low priority task to that of the priority of the task which requested the
shared resource holding by the low priority task eliminates the preemption of the low
priority task by other task whose priority are below that of the task requested the shared
resource and thereby reduces the delay in waiting to get the resource requested by the
high priority task. The priority of the low priority task which is temporarily boosted to high
is brought to the original value when it relaeases the shared resource. Implementation
of priority inheritance work around in the priority inversion problem discussed for
ww
process A, Process B and process C example will change the execution sequence as
shown in figure.
w. E Priority inheritance is only a work around and it will not eliminate the delay in
asy
waiting the high priority task to get the resource from the low priority task. The only thing
is that it helps the low priority task to continue its execution and release the shared
En
resource as soon as possible. The moment, at which the low priority task releases the
gi
shared resource, the high priority task kicks the low priority task out and grabs the CPI –
nee
A true form of selfishness. Priority inheritance handles priority inversion at the cost of
run-time overhead at schedules. It imposes the overhead of checking the priorities of all
tasks which tries to access shared resources and adjust.
r ing
.ne
t
84

7. Write about the features of µC/OS- II , Vx Works and RT Linux .

i) µC/OS – II
µC/OS – II is a highly portable, ROMable, very scalable, preemptive real time,
deterministic, multitasking kernel.
It can manage up to 64 tasks (56 uses task available)
It has connectivity with µc/GUI and µc/ FS (GUI and file systems for µc/OS – II)
It is ported to more than 100 microprocessors and microcontrollers.
It is simple to use and simple to implement but very effective compared to the
price/performance ratio.
It supports all type of processors from 8-bit to 64-bit.
Task Management Services:
ww Task features
w. E Task creation
Task stack and stack checking
asyTask deletion
Change a task‘s priority
En
Suspend and resume a task
gi
Get information about a task
Task feature:
nee
µc/OS- II can manage up to 64 tasks.
r ing
The four highest priority tasks and the four lowest priority tasks are reserved for
its own use. This leaves us with 56 application tasks.
.ne
The lower the value of the priority, the higher the priority of the task.
The task priority number also serves as the task identifier.
Rate monotonic scheduling:
t
In rate monotonic scheduling tasks with the highest rate of execution are given
the highest priority.
Assumptions
1. All tasks are periodic
2. Tasks do not synchronize with one another, share resources, etc.
3. Preemptive scheduling is used (always runs the highest priority task that is
ready)
85

Under these assumptions, let n be the number of tasks, Ei be the execution time
of task i, and Ti be the period of task i. Then, all deadlines will be met if the
following inequality is satisfied.
ΣEi/Ti ≤ n(21/n – 1)
Example: suppose we have 3 tasks. Task 1 runs at 100Hz and task 2 ms. Task 2
runs at 50Hz and takes 1ms. Task 3 runs at 66.7 Hz and takes 7 ms. Apply
RMS theory.
(2/10) + (1/20) + (7/15) = 0.707 ≤ 3(21/3 – 1) = 0.780
Thus, all the deadlines will be met.
General solution:
As n goes infinity, the right hand side of the inequality goes to in (2) = 0.6931.
ww
Thus you should design your system to use less than 60 – 70% of the CPU.
Task creation:
w. E Two functions for creating a task are

o
o asy OS task create ( )
OS task create E X t ( )
En
Task Management:
gi nee
r ing
.ne
data.
t
After the task is created, the task has to get a stack in which it will store its
A stack must consist of contiguous memory locations.

It is necessary to determine how much stack space a task actually uses.
Deleting a task means the task will be returned to its dormant state and does
not mean that the code for the task will be deleted. The calling task can delete itself.
If another task tries to delete the current task, the resources are not freed and
thus are lost. So the task has to delete itself after it uses its resources.
Priority of the calling task or another task can be changed at run time.
A task can suspend itself or another task; a suspended task can resume itself.
86

A task can obtain information about itself or other tasks. This information can
be used to know what the task is doing at a particular time.
Memory Management:
The memory management includes:
1. Initializing the memory manager
2. Creating a memory partition
3. Obtaining status of a memory partition
4. Obtaining a memory block
5. Returning a memory block
6. Waiting for memory blocks from a memory partition.
Each memory partition consists of several fixed – sized memory blocks.
ww A task obtains memory blocks from the memory partition.
w. E
A task must create a memory partition before it can be used.
Allocation and de-allocation of these fixed – sized memory blocks is done in
asy
constant time and is deterministic.
Multiple memory partitions can exist, so a task can obtain memory blocks of
En
different sizes.
gi
A specific memory block should be returned to its memory partitions from which it
came.
nee
Time management:
r ing
Clock Tick: A clock tick is a periodic time source to keep track of time delays and
time outs.
o Time intervals: 10~100 ms .ne
t
o The faster the tick rate, the higher the overhead imposed on the system.
Whenever a clock ticks occurs, µC/OS – II increments a 32 – bit counter.
o The counter starts at zero and rolls over to 232-1 ticks.
A task can be delayed and a delayed task can be also be resumed.
Five services:
o OSTime_DLY ( )
o OSTime_DLYHMSM ( )
o OSTime_DLYResume ( )
o OSTime_GET ( )
o OSTime_Set ( )
Inter task communication:
87

Inter task or inter process communication in µC/OS takes place using,

Semaphore
Message mailbox
Message queues
Tasks and interrupt service routines (ISR) can interact with each other through an ECB
(Event Control Block)
Single task waiting:
ww
w. E
asy
Multiple tasks waiting and signalling:
En
gi nee
r ing
Tasks can wait and signal along with an optional time out. .ne
t
µC/OS-II semaphores consist of two elements

o 16 – bit unsigned integer count.
o List of tasks waiting for semaphore.
µC/OS – II provides
Create, post, pend accept and query services.
88

µC/OS – II message mailbox: an µC/OS – II object that allows a task or ISR to

send a pointer sized variable (pointing to a message) to another task.
ww
w. E
asy
En
µC/OS – II message – queues
Available services: create, post (FIFO), postfront (LIFO), pend, accept – query,
flush.
gi nee
N = Addition of entries in the queue: queue full if post or post front called N times before
a pend or accept.
r ing
.ne
t
µC/OS – II message – queue organized at circular buffers.
89

ii) Vx Works RTOS:

Introduction:
Vx works is a real time operating system developed as proprietary software by wind
river systems. It in a high performance, Unix like, scalable RTOS and supports ARM,
ww
Pentium, Intel X-scale, super H and other popular processors for embedded system
w. E
design. Vx works design is hierarchical and well suited for real time applications. It
support kernel mode execution of tasks for fast execution of application codes. Vx
asy
works is supported with powerful development tools that make it easy and efficient to
use.
En
Many simulation tools, time performance analysis tools, debug and test tools are
gi
provided. Making Vx works as an RTOS that supports development of almost any
nee
embedded application, providing a complete solution for all stages of the design cycle.
The latest version Vx works 6.9 in the first commercial grade RTOS to fully support both
32-bit and 64-bit processing on Intel Architecture.
Basic Features:
r ing
1. Multi tasking environment using standard POSIX scheduler. .ne
2.
3.
t
Ability to run two concurrent operating systems on a single processing layer.
Multiple file systems and systems that enable advanced multimedia functionality.
4. Synchronization using a full range of IPC option.
5. Different context saving mechanisms for the tasks and ISRs.
6. Virtual IO devices including pipes and sockets.
7. Victual memory management functions.
8. Power management functions to enhance the ability to control power
consumption.
9. Interconnecting functions that support large number of protocols.
10. Pipe drivers for DPCS.
11. Network transparent sockets.
90

12. Network derivers for shared memory and Ethernet.

13. RAM dist drivers for memory resident files.
14. Processor arbitration layer to enable application system design by user when
using new versions of processor architecture.
Architecture:
Vx Works was initially a development and network environment for VRTX. Later wind
River systems developed. Their own micro kernal. So the Vx works is of "client-server"
architecture from the beginning. The heart of the Vx works run-time system is the wind
microkernel. This micro kernel supports a full range of real-time features including multi-
tasking, scheduling. Inter task synchronization communication and memory
management. All the other functionality is implemented as processes.
ww
Vx Works is highly scalable. By including or excluding various models, Vx works can be
configured for the use in small embedded system with tough memory constraints to
w. E
complex systems where more functions are needed. Furthermore, individual modules
asy
themselves are scalable. Individual functions may be removed from the library or
specific kernel synchronization objects may be omitted if they are not required by the
En
application.
gi nee
r ing
.ne
t
Task Management:
The Vx works real-time kernels provides a basic multitasking environment. Vx works
offers both posix and a proprietary scheduling mechanisms. Both preemptive priority
and round robin scheduling mechanism are available. The difference between POSIX
and wind scheduling is that wind scheduling is that wind scheduling mechanism are
available.
91

The difference between a POSIX and wind scheduling is that wind scheduling applies
the scheduling algorithm on a system wide basis, whereas POSIX scheduling
algorithms are applied on a process by process basis.
In Vx works, the states encountered by the task are of 8 different types.
1. Suspended: Idle state just after creation or stated where execution is inhibited.
2. Ready: Waiting for running and CPU access in case scheduled by the scholar but
not waiting for a message through IPC.
3. Pending: The task is blocked as it waits for a message from the IPC or from a
resource only then will the CPO be able to process further.
4. Delayed: Send to sleep for a certain time interval.
5. Delayed + suspended: Delayed and then suspended if it is not pre-emptied
ww
during the delay period.
6. Pended for an IPC _ suspended: Pended and then suspended if the blocked
w. E
state does not change.
7.
asy
Pended for an IPC + delayed: Pended and than pre-emptied after the delayed
time interval.
8.
En
Pended for an IPC + suspended: Pended and suspended after delayed time
interval.
gi nee
Kernel library functions are included in the header file 'Vx works.h' and 'kernel Lib.h'.
Task and system library functions are included in 'task Lib.h' and 'sys Lib.h' User task
r ing
priorities are between 101 and 255. Lowest priority means task of highest priority
number (255). System tasks have the priorities from 0 to 99. For tasks, the highest
priority is 100 by default..
.ne
The functions involved in task management:
t
1. Task Spawn function: It is used for creating and activating a task. Prototype is
unsigned int task ID = task spawn (name, priority, options, stack size, main, argo, art1,
arg2, ... arg9).
2. Task suspending and Resuming functions: Task suspend (task ID): inhibits the
execution of task indentified by task Id.
Task Resume (task ID): Resumes the execution of the task identified by task ID.
Task Restart (task ID): First terminates a task and then spawn again with its original
assignes arguments.
3. Task deletion and deletion protection function: Task Delete (task Id): this
permanently inhibits the execution f the task identified by task Id and cancels the
allocations of the memory block for the task stack and TCB.
92

Many time each task should itself execute the codes for the following:
Memory de-allocation.
Ensure that the waiting task gets the desired IPC
Close a file, which was opened there.
Delete child tasks when the parent task executes the exit ( ) function.
4. Delaying a task to let a lower priority task get access:
intSysClkRateGet ( ) returns the frequency of the system ticks. Therefore to delay by
0.25 seconds, the function task Delay (SysclkRateGet ( ) /4) is used.
Memory Management:
In Vx works, all systems and all application tasks share the same address space. This
means that faulty application could accidently access system resources and
ww
compromise the stability of entire system. An optional tool named Vx VMI is available
w. E
that can be used to allow each task to have its own address space. Default physical
page size used is 8 KB. Virtual memory support is available with Vx VMI tool. Vx works
asy
does not offer privilege protection. The privilege level is always 0.
Interrupts:
En
To achieve the fastest possible response to external interrupts, Interrupt service routines
gi
in Vx works run in a special context outside of any thread's context, so that there are no
nee
thread context switches involved. The C function that the user attaches to a interrupt
vector is not actual ISR. Interrupts cannot directly vector to C functions.
r ing
The ISR's address is stored in the interrupt vector table and is called directly from the
hardware. The ISR performs some initial work and then calls the C function that was
.ne
attached by the user. For this reason, we use the term interrupt handler to designate the
t
user installed C handler function. Vx Works uses an ISR design that is different from a
task design.
The features of the ISR in Vx works are:
1. ISRs have the highest priorities and can pre-empt any running task.
2. An ISR inhibits the execution of tasks till return.
3. An ISR does not execute like a task and does not have regular task context.
4. An ISR should not use mutex semaphore.
5. ISR should just write the required data at the memory or buffer.
6. ISR should not use floating – point functions as these take longer time to
execute.
Performance:
93

Real time performance: Capable of dealing with the most demanding time
constraints, Vx works is a high-performance RTOS tuned for both determinism and
responsiveness.
Reliability: A high – reliability RTOS, Vx works provides certification evidence
required by strict security standard. Even for non-safety – critical systems, Vx works is
counted on to run forever, error free.
Scalability: An indispensable RTOS foundation for very small – scale devices,
large scale networking systems and everything in between, Vx works is the first RTOS
to provide full 64-bit processing to support the over growing data requirements for
embedded real time systems. Vx works is scalable in terms of memory foot print and
functionality so that it can be tuned as per the requirements of the project.
ww Interrupt latencies: The time elapsed between the execution of the last instruction
w. E
of the interrupted thread and the first instruction in the interrupts handler to the next task
scheduled to run is interrupt dispatch latency. Vx works exhibits an Interrupt latency of
asy
1.4 to 2.6 micro seconds and dispatch latency of 1.6 to 2.4 ----s
Priority inheritance: Vx works has a priority inheritance mechanism that exhibits
En
an optimal performance, which is essential for an RTOS.
gi
Foot print: Vx works has a completely configurable and tunable small memory
nee
foot print for today's memory – constrained systems. The user can control how much of
the operating system he needs.
Applications:
r ing
Vx Works RTOS is widely used in the market, for a great variety of applications.
.ne
Its reliability makes it a popular choice for safety critical applications Vx works has been
t
success fully used in both military and civilian avionics, including the Apache Attack
Helicopter, Boeing 787, 747-8 and Airbus A 400 M. It is also used in on ground avionic
systems such as in both civilian and military radar stations. Another safety critical
application that entrusts Vx works is BMW's i – Drive system.
However, Vx works is also widely used in non-safety – critical applications where
performance is at premium. The xerox phasor, a post – script printer is controlled by a
Vx works powered platform link sys wireless routers use Vx works for operating
switches.
Vx works has been used in several space application's. In space crafts, where design
challenges are greatly increased by the need of extremely low power consumption and
lack of access to regular maintenance, Vx works RTOs can be chosen as the operating
94

system for on Board Computer (OBC). For example 'clementine' launched in 1994 is
running Vx works 5.1 on a MIPS – based CPU responsible for the star Tracker and
image processing algorithms. The 'spirt' and opportunity mars exploration rovers were
installed with Vx works. Vx works is also used as operating system in several industrial
robots and distributed control systems.
Summary:
The need to develop for real-time embedded applications is always a challenge,
especially when expensive hardware is at risk. The complex nature of such systems
require many special design considerations an understanding of physical systems, and
efficient Management of limited resources perhaps one of the most difficult choice the
embedded system designers have to make in which operating system they are going ot
ww
use. It is critical to have operating system that will be able to be fail-safe, secure,
scalable, fast and robust in multi task management, while being friendly to the
w. E
application developers, Vx works is an RTOs which meets almost all of these
iii) asy
requirements.
RT Linux
En
RT linux is a hard real time RTOS microkernel that runs the entire linux operating
gi
system as a fully preemptive process. It was developed by Victor Yodaiken, Michael
nee
Barabanov and others at the New Mexico Institute of Mining and Technology and then
as a commercial product at FSM Labs. FSM Labs has 2 editions of RT Linux.
r ing
RT Linux pro and RT Linux free. RT Linux pro is the priced edition and RT Linux
is the open source release. RT Linux support hard real time applications. The Linux
.ne
kernel has been modified by adding a layer of software between the hardware and the
required for RT Linux. t

Linux kernel. This additional layer is called ‗Virtual Machine‘. A footprint of 4 MB is
The new layer, RT Linux layer has a separate task Scheduler. This task scheduler
assigns lowest priority to the standard to the standard Linux kernel. Any task that has to
met real-time constraints will run under RT Linux. Interrupts from Linux are disabled to
achieve real time performance.
95

In RT Linux location of the various files are:
ww
version
RT Linux will be installed in the directory/usr/rtlinux-XXX, where XXX is the
name.
w. E /usr/rtlinux/include contains all the include files necessary for development

project.
asy
/usr/doc/rtlinux/man contains the manual pages for the RT Linux.
En
/usr/rtlinux/modules contains the core RT Linux modules
The two important aspects while doing programming in RT linux are:
points unit.
gi
By default, the RT Linux tasks do not have access to the computer‘s floating
nee
Hence need to explicitly set the permissions for every RT Linux task.
It cannot pass arguments from the command prompt.
RT Linux Modules: r ing
.ne
RT Linux programe are not created as stand-alone units, they are created as
t
modules. Which are loaded into the linux kernel space. The C source files are complied
into object files using the gcc command with the argument C flag. In the C file the main (
) function gets replced with the following lines.
Int init-module ( ).
Void cleanup_module ( ).
Init-module is called when the module is first loaded into the kernel. This function
returns O if the module is successfully loaded. It returns a negative value in case of
failure. When the module is loaded is to be unloaded, the cleanup_module ( ) is called.
Executing the RT Linux Modules:
In RT Linux, Load and stop user modules are using the RT Linux command.
Using this command, we can obtain status information about RT Linux modules. The
command syntax is:
96

$ rtlinux start my-program

$ rtlinux stop my-program
$ rtlinux status my-program
Creating RT Linux POSIX Threads
A real time program generally consists of a number of threads. Each thread
share a common address space. Pthread_create () function is used to create a new
real-time thread. The corresponding header file is
# include <pthread.h>
To achieve real time performance, the various POSIX compliant API function
calls are used. There function calls are related to create and cancel semaphores.
To implement mutex, we have to include the header file <rtl-mutex.h) in the C
ww
program.
w. E To cancel a thread, the system call is pthread cancel.

Timer Management
asy
A number of internal clocks are available in RT Linux to manage the timers. The
current clock reading is obtained using command is:
En
Clock-set time ( ) function
gi
Clock-id gives the identification of the clock to be read.
nee
r ing
.ne
t
97

UNIT-5
EMBEDDED SYSTEM APPLICATION DEVELOPMENT
PART-A(2 marks)
1. What is Multi-state system?
A system that can exist in multiple states (one-state at a time) and transition from one
state to another state is known as multistate system. There are 3 types of multi state
system:
 Timed multi state system
 Input – based multi state system
 Input – based / Timed multi state system
2. What is a motor driver?
ww
A motor driver is a little current amplifier. The function of motor drivers is to take a low
current control signal and then turn it into a higher current signal that can drive a motor.
w. E
3. Define RTC
asy
A real time clock is a computer clock that keeps track of the current time even when
the computer is turned off. Real Time Clock (RTC) runs on a special battery that is not
En
connected to the normal power supply.
PIC gi
4. Write in brief about the PIC microcontroller.
(Peripheral Interface Controller) is
nee
a family of Harvard
microcontrollers made by Microchip Technology. It has an in built PWM generator,
Architecture
which is very useful to control the motors

5. What is Smart Card?
r ing
.ne
Smart Card stores and process information through electronic circuits embedded in
carries both processing power and information.

6. Define class and objects.
t
the silicon in a plastic substrate body. It is portable and tamper resistant computer. It
Class: A class is a user defined type or data structure declared with keyword class that
has data and functions as its members whose access is governed by the three
accesses specifies private, protected or public. Class is a collection of data member and
member function
Object: Object is a class type variable, objects are also called instance of the class.
Each object contains all members declared in the class.
7. What is synchronization in RTOS?
98

To let each section of codes, tasks and ISRS run and gain access to the CPU one after
the other sequentially or concurrently, following a scheduling strategy, so that there is a
predictable operation at any instance.
8.List the characteristics of multi – state system.
The system will operate in two or m ore states.
Each state may be associated with one or more function calls.
Transitions between states may be controlled by the passage of time, by
system inputs or by a combination of time and inputs.
Transition between states may also involve function calls.
9. What is an adaptive control algorithm?
An adaptive control algorithm refers to algorithm parameters which adapt to the present
wwstatus of the control inputs in place of a constant set of mathematical parameters in
w. E
algorithmic equations.
10. What are the task functions for a smart card?
asy resetTask
task_Read Port
En task_PW
gi task_Appl
UNIT – 5
nee
PART-B(16 marks)
1. r ing
Discuss in deeply about the case study of washing machine design.
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Automatic washing machine is a Multi-state Input/Timed system. The characteristics of
multi state system are:
The system will operate in two or more states.
Each state may be associated with one or more functional calls.
t
Transitions between states may be controlled by the passage of time, by system
Inputs or by a combination of time and inputs.
Transitions between states may also involve function calls.
99

Outline design of inputs and outputs:
Start
Water
Switch
Value
Water
Selector Heater
Dial
Washing Water
Machine Pump
Water
Controller
level
Sensor Drum
Motor
Temperature
sensor Detergent LED or LCD
Hatch indicators
ww Figure: Outline Design

Microcontroller based washing machine design:
w. E PIC18F series microcontroller acts as a washing machine controller. Single
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phase motor is considered for the design. Front panel consists of a keypad and LCD
display. Keypad provides automatic and manual wash options to the user. LCD display
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is convenient to convey machine information to user. Modern washing machines are
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designed with BLDC motors owing to efficiency and energy conversation. But in his
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case, single phase universal motor has been used to design prototype.
Design Specifications:
1.
r
This include both hardware and software specifications.
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The system should provide fully automatic mode, semi automatic mode and
manual mode. Modes should be selected by a keypad.
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2. Under fully automatic mode, user intervention requirement should be zero.
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Once the system is started in this mode, it should perform its work independently and
after the completion of work it should notify the user about the completion of work. This
mode instantaneously should sense cloth quality and requirement of water, water
temperature, detergent, load, wash cycle time and perform operation accordingly.
3. In semi – automatic mode also, user requirement should be nil. But user has to
choose any one of the semi automatic mode in which washing conditions are
predefined. Once the predefined mode is started, the system should perform its job and
after completion, it should inform the user.
4. In manual mode, continuous intervention of user is required. For example, a
user needs to choose wash mode, wash time, amount of water and the load. After these
data are entered, the user should start the machine.
100

5. When the lid is open, system should not work. If door is accidently opened in
between wash operation, then the system should stop working in minimum possible
time.
6. The system should provide all the basic features of a washing machine like
washing, rinsing, spinning, drying, cold wash, hot wash etc.
7. The system should provide easy option for upgrading the new features.
8. The system should work on single phase AC from 190V AC to 250V AC. The
system should protect itself from power supply voltage variations.
9. In the event of power failure, the washing machine should automatically start
its cycle from the point of interruption when power is resumed.
Hardware Design:
ww PIC18F452 is a heart of the system. Most of the peripheral features have been
utilized to implement the design. Controlling the motor is very crucial part of the design.
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The PWM feature of the microcontroller controls motor speed. PWM output is feed to
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driver circuit and then to motor.
To rotate the motor in two different directions forward and reverse direction,
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control blocks are used. Motor speed sensor is interfaced to microcontroller.
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Microcontroller reads the speed of the motor and approximately controls the speed of
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the motor in different phases of washing using PWM output. Door sensor, pressure
sensor, keypad are also interfaced to microcontroller. EEPROM and RTC are interfaced
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to MSSP module of controller. In-circuit serial programming facility is provided for quick
and easy programming and debugging.
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101

Washing machine parameters are stored in external EEPROM and internal

EEPROM of the PIC.
RTC (Real Time Clock) is interfaced to SPI (Serial Peripheral Interface) port of the
microcontroller. It is used as a timing reference for all timing calculation of machine.
Door sensor is connected to external interrupt 0. High priority is assigned to this
interrupt. Thus opening of the door causes triggering of INT0 and INT0 ISR
immediately to stop the machine and informs the user.
All the sensor outputs are connected to the analog pins of PIC (AN0, AN1, AN2 etc.)
Keypad is connected to port D. when any of the keys is pressed; output becomes
high and INT1 triggers. Int1 ISR does a keypad scan and approximately performs
the operation.
ww Motor speed sensor is given to T1, CLK which is an external clock input to timer 1 /
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timer 3.
calculated by
Timer is configured in counter mode for calculating the speed. Speed is
counting pulse output from the sensor for one second.
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Motor driver circuit determines the direction of the motor corresponding to the output
obtaining from the microcontroller.
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Speed of the motor is controlled by the PWM generation from the microcontroller.
The duty
gi cycle of PWM pulses are changed according to the output obtained from
the speed sensor to
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maintain the desired response during wash cycles.
Dedicated LCD with 3 wire interface is used, which consist of data line, clock and
chip select. Backlight control is also provided. r ing
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t
Software Design:
A provisional list of functions that could be used to develop a washing machine
are:
Read_Select_Dial ( )
Read_Start_Switch ( )
102

Read_Water_Level ( )
Read_Water_Temperature ( )
Control_Detergent_Hatch ( )
Control_Door_Lock ( )
Control_Motor ( )
Control_Pump ( )
Control_Water_Heater ( )
Control_Water_Valve ( )
Frame Work:
1. System states – Initialization, start, fill drum, heat water, Wash 1, Wash 2,
Error.
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2. User defined data – a) Maximum Fill duration – 1000 seconds. b) Maximum
3.w. E
water heat duration – 1000 seconds. c) Maximum wash 1 duration – 3000 seconds.
Functions involved in each state or function call
 asyInitialization:
Control_Motor (OFF)

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Control_Pump (OFF)

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Control_Water_Heater (OFF)
Control_Water_Valve (OFF)
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 Read_Select_Dial (ON)
Now switch on to start state.
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Start:
 Control_Door_Lock (ON)


Control_Water_Valve (ON)
Control_Detergent_Hatch (ON)
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Now switch on to fill drum state.
Fill Drum:
 Read_Water_Level (ON)
 Control_Water_Heater (ON)
Now switch on to either heat water state or Wash 1 state depends upon the
condition.
Heat Water:
Read_Water_Temperature (ON)
Now switch on to Wash 1 state.
103

Wash 1:
 Control_Motor (ON)
After the completion of duration, the system switches to the wash 2 state.
Wash 2:
In Wash 2 state, the system performs the washing operation until its duration is expired.
Error:
In any crash or error happens between the states, the system goes to the
default state called error state. It restarts the particular state, where the error occurs.
4. Function definitions:
Thus the software design is clearly explained with states and functions.
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2) Explain the case study of an embedded system for an automotive application.
Present day automobiles have many embedded systems. A car contains many
w. E
control systems. One among them is ACC(Adaptive Cruise Control) which automatically
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controls the car speed.
Requirements
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1. Purpose
2. Inputs
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3. Signals, events and notifications
4. Outputs nee
5. Control panel
6. Functions of the system
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7. Design metrices
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a.
b.
c.
Power source and dissipation
Resolution
Performance
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d. Process deadlines
e. User interfaces
f. Extendibility
g. Engineering cost
h. Manufacturing cost
8. Test and validation conditions
ACC (Adaptive Cruise Control)
104

This control method is used to maintain constant speed in cruise mode and to
decelerate when a vehicle comes in front at a distance less than safe and to accelerate
again to cruise mode by using adaptive control algorithm.
Adaptive Control algorithm
An adaptive control algorithm refers to an algorithm parameters in which adapt to
the present status of the control inputs in place of a constant set of mathematical
parameters in the algorithmic equations. Parameters adapt dynamically.
For an ACC system, an adjustable-system subunit generates output control
signal for throttle valve.
The desired preset cruise velocity vt,desired preset distance dset and safe preset
distance dsafe are the inputs to measuring subunit.
ww The measured velocity v and distance d are inputs to computing unit.
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The comparison and decision subunit sends outputs which are inputs to
adjustable systems.
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Fig : Model for an adaptive control algorithm adaption and functions
Class diagram
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ACC system measurements of front end car range, distance and error estimations and
adaptive control can be modeled by two class diagrams of abstract classes, Task_ACC
and Task_Control
105

.
1.Task_ACC is an abstract class from which extended classes like
Task_Align,Task_Signal,Task_ReadRange, Task_RangeRate and Task_Algorithm are
ww
derived to measure range and errors.
2.Task_Control is an abstract class from which extended classes like
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Task_Brake,Task_Throttle and Task_Speed are derived to measure range and errors.
3.There are two ISR objects ISR_ThrottleControl and ISR_BrakeControl
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ACC Hardware Architecture
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ACC embeds the following hardware units:
port gi
Microcontroller-Runs the service routines and tasks except task_Algorithm.CAN
interfaces with the CAN bus at the car.
Processor with RAM/ROM- To execute task_Algorithm nee
Speedometer
Stepper motor-based alignment unit.
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Stepper motor-based throttle control unit.
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Transceiver –For transmitting pulses through an antenna hidden under the
plastic plates. t
Display panel
Port devices-Five port devices are
Port_Align,Port_Speed,Port_ReadRange,Port_Throttle and Port_Brake
106

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ACC Software Architecture
For the ACC systems Basic Conformance Class I (BCCI) is used.The following table
w. E
lists the BCCI tasks,functions and IPCs
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BCC 1 Task BCC 1 Action IPCs pending
function
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task_Align
Priority
101 Starts an event and send signal to Reset
task_Read
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Port_Align and Port_Ranging
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Disable interrupts,gets signal from Align
Range
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Port.Finds the time difference and
enable interrupts
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task_Speed 105 Start a timer,wait for 10 counts and ---
outputs deltaT from port .ne
task_RangeRa 107
te
Get preset cruising
compare it with current speed
speed Speed t
task_Algorithm 109 Get errors of speed and range, ACC
errors of other vehicles, other
vehicles brake status,present
throttle position.Send throttle
adjust output,signal to Port_Brake
in case of emergency braking
action.Port_Brake transmits the
action needed to other vehicles
also.
107

Synchronization Model
1.The task,task_Align sends the signal to a stepper motor port Port_Align and
Port_Ranging.The stepper motor moves by one step clockwise or anticlockwise.
2.A task,task_ReadRange is for measuring front-end car range.
3.task_Speed gets the port reading at a port Port_Speed.Task sends v, using the
countN and count() interval between the initial and Nth rotation.
4.task_RangeRate sends the rangeNow.Calculates both range and rate errors and
transmits both rangeNow and speedNow.
5.task_Algorithm runs the main adaptive algorithm.It gets inputs from task_RangeRate
and outputs are events to Port_Throttle and brake.Port_Throttle attaches to the vacuum
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actuator stepper motor.
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asy
En
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3. Write about the design and interface of smart card system. .ne
Smart Card Basics:
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Smart card stores and process information through electronic circuits embedded in the
silicon in a plastic substrate body. It is portable and tamper resistant computer. It carries
both processing power and information.
Smart card has an embossed area on one face and magnetic stripe on other, it defines
by ISO7816 standard. To communicate with the outside world, Smart card is placed
inside a card Acceptance device.
108

Requirements:
Assume a contact less smart card for bank transactions. Let it not be magnetic.
Requirements of Smart card communication system with a host are.
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1. Purpose:
Enabling authentication and verification of card and card holder by a host and enabling
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GUI at host machine to interact with the card holder / user for the required transactions:
for example, financial transactions with a bank or credit card transaction.
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2. System Functioning:
1.
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The cards inserts at host machine. The radiations from the host activate a charge
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pump at card.
2.
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On power up, system reset signals reset task to start. The reset task sends the
messages - request Header and request start for waiting task. task_ReadPort.
3.
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task_Read Port sends requests for host identification and reads through the
port_IO the host - identification and reads the request start from host for card
identification.
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4.
system
5.
receives the host identity through Port_IO t
The task_PW sends through Port_IO the requested card identification after
The task_Appl then runs required API. The request Appl close message closes
the application.
6. The card can now be withdrawn and all transactions between card holder user
now takes place through GUIs using at the host control panel.
3. Inputs:
Receives header and messages at IO Port_IO from host through the antenna.
4. Signals and Events and Notifications:
1. On power up by radiation powered charge - pump supply of the card, a signal to
start the system boot program at reset task.
2. Card start request header message to task - Read Port from reset Task.
109

3. Host authentication request start message to task_Read Port from reset Task to
enable request for Port_IO
4. User PW verification message (notification) through Port_IO from host.
5. Card application close request Applcase message to Port_IO
5. Outputs:
Transmitted headers and messages at port_IO through antenna.
6. Control Panel:
No control panel is at the card. The control panel and GUIs activate at the host
machine.
7. Design Metrics:
1. Power source and dissipation: Radiation powered contact - less operation.
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2.
needs
Code Size: Code size generated should be optimum. The card system memory
should not exceed 64 KB Memory.
3.
w. E File System(s): Three layered file system for the data. One file for the master file
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to store all file headers. A header has strings for file status, access conditions and
file-lock. The second file is a dedicated file to hold a file grouping and heads. The third
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file is the elementary file to hold the file header and file data.
4.
length
5.
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File Management: There is either a fixed length file management or variable file
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management with each file with a predefined offset.
Micro controller hardware: Generates distinct coded physical addresses for the
program
6.
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and data logical addresses. Protected once writable memory space.
Validity: System is embedded with expiry date, after which the card
authorizations through the hosts disable.
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7.
authorization of
8.
master control unit. t
Extendibility: The system expiry date is extendable by transactions and
Performance: Less than 1s for transferring control from the card to host machine
9. Process Deadlines: None.
10. User Interfaces: At host machine, graphic at LCD or touch screen display on LCD
and commands for card holder (card user) transactions.
11. Engineering Cost: US $ 50,000 (assumed)
12. Manufacturing Cost: US $ 1 (assumed)
Test and Validation Conditions:
 Tested on different host Machine versions for fail proof card-host communication.
Class Diagram:
An abstract class is Task Communication. The figure shows the class diagram of
110

Task_Card communication. A cycle of actions and card - host synchronization in the

card leads us to the model Task_Card communication for system tasks. Card system
communication to host for identifying host and authentication itself to the host.
ISR1_Port_IO, ISR2_Port_IO and ISR3_Port_IO are interfaces to the tasks. The
task_Appl, taskPW, taskRead port and reset_Task are the objects of Task_appl,
Task_PW, Task_Read Port and Task_Reset, respectively. These classes are extended
classes of abstract class Task_Card communication.
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Task_card communication is an abstract class from which extended is class
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derive to read port and authenticate. The tasks are the instances of the classes
Task_Appl, Task_Reset, Task_Read Port and Task_Reac Range.
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Task_Read Port interfaces ISR1_Port_IO
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The task_PW is object of Task_PW and interfaces ISR2_Port_IO. Task_Appl
interfaces ISR3-Port_IO
Hardware and Software Architecture:
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t
Software using Java card provides one solution. JVM has thread scheduler built in. No
separate multitasking OS in thus needed when using Java because all Java byte codes
run in JVM environment. Java provides the features to support (i) security using class
java.lang. Security Manager, (ii) cryptographic needs. Java provides support to
connections, datagrams, IO streams and network sockets.
111

Java mix is a new technology in which the native applications of the card run in C or
C++ and downloadable applications run in Java Card. The system OS and JVM both.
Smart OS in an assumed hypothetical OS in this example, as RTOS in the card.
Remember that a similar OS function name is used for understanding purpose identical
to MUCOS but actual smart OS has to be different from MUCOS. Its files structure in
different. It has two function as follows.
The function unsigned than ( ) smart OS encrypy (unsigned char * applstr, EnType type)
encrypts as per encryptes method, EnType = "RSA" or "DES" algorithm chosen and
returns the encrypted string.
List of Task functions and IPCs:
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112

Synchronization Model:
Following are the actions on the card places near the host machine antenna in a
machine slot.
Step 1: Receive from the host, on card installation, the radiation of carrier frequency or
clock signals in case of contact with the card. Extract charge for the system power
supply for the modem, processor, memories and port IO device.
Step 2: Execute codes for a boot up task on reset resetTask. Let us code in a similar
way as the codes for First task. The codes begin to execute from the main and the main
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creates and initiates this task and starts the smart OS.
w. E
asy
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113

ww
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114

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115

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EE6602 EMBEDDED SYSTEMS LT P C 3 0 0 3

UNIT I INTRODUCTION TO EMBEDDED SYSTEMS 9

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 Become aware of the concepts of embedded networking

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EE6602 EMBEDDED SYSTEMS

DETAILED COURSE PLAN

selection of processor & memory

6 Memory management methods 1 6 T1

Timer and Counting devices, T1

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Real Time Clock, In circuit T1

9 Target Hardware Debugging 1 9 T1

UNIT II EMBEDDED NETWORKING

11w. E I/O Device Ports & Buses 1 11 R3

RS422 – RS485 nee

16 Serial Peripheral Interface (SPI). 1

Need for device drivers

UNIT III EMBEDDED FIRMWARE DEVELOPMENT ENVIRONMENT

Different phases of EDLC T1,R

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Issues in Hardware-software Co-

23 Data Flow Graph, 1 23 T1

24 State machine model, 1 24 T1

28 gi Introduction to basic concepts of

29 Task, process & threads

30 Interrupt routines in RTOS 1

Preemptive and non-preemptive R1

Task communication shared T

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35 Inter process Communication 1 35 T2

Priority inversion, Priority

ww Comparison of Real time

Case Study of Washing Machine nee 2 41 R1

41 UNIT 5 Automotive Application r 2 ing 43 T1

42 Smart card System Application 2 .ne

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UNIT-1 - INTRODUCTION TO EMBEDDED SYSTEMS

w. E Clock oscillator circuit

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12. Define ROM image and RAM.

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Preprocessor constants, variables and inclusion of configuration files, text files,

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Figure: Bus Interface between Processor and Memory

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STRUCTURAL UNIT IN A PROCESSOR:

ww be fetched from external memories. Processor issues the address of instruction

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a. A set of on chip registers used during processing of instructions of an

ww sequentially. It is called instruction pointer in 80 x 86 processors.

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ww It facilitates ready availability of the next instruction – set when a branch

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12. Atomic Operation Unit (AOU):

ww I/O device memory

asy I/O device to I/O device

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Chained block transfers