FLIPFLOP: (Answer is in
7.On a master-slave flip-flop, when is
BOLD letter)
1.Which statement BEST describes
the operation of a negative-edge-
triggered D flip-flop?
The logic level at the D input
A. is transferred to Q on NGT
of CLK.
The Q output is ALWAYS identical
B. to the CLK input if the D input is
HIGH.
The Q output is ALWAYS identical
C.
to the D input when CLK = PGT.
The Q output is ALWAYS identical
D.
to the D input.
2.How is a J-K flip-flop made to
toggle?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
3.How many flip-flops are in the
7475 IC?
A. 1 B. 2
C. 4 D. 8
4.
How many flip-flops are required to
produce a divide-by-128 device?
A. 1 B. 4
C. 6 D. 7
5.What is the difference between the
enable input of the 7475 and the
clock input of the 7474?
A. The 7475 is edge-triggered.
B. The 7474 is edge-triggered.
6.The phenomenon of interpreting
unwanted signals
on J and K while Cp (clock pulse) is
HIGH is called ________.
A. parity error checking
B. ones catching
C. digital discrimination
D. digital filtering
the master enabled?
A. when the gate is LOW
B. when the gate is HIGH
C. both of the above
D. neither of the above
8. One example of the use of an S-R
flip-flop is as a(n):
A. racer
B. astable oscillator
C. binary storage register
D. transition pulse generator
9. What is the difference between
the 7476 and the 74LS76?
A. the 7476 is master-slave, the
74LS76 is master-slave
B. the 7476 is edge-triggered,
the 74LS76 is edge-triggered
C. the 7476 is edge-triggered,
the 74LS76 is master-slave
D. the 7476 is master-slave,
the 74LS76 is edge-triggered
10. Which of the following is correct
for a gated D flip-flop?
A. The output toggles if one of
the inputs is held HIGH.
B. Only one of the inputs can be
HIGH at a time.
C. The output complement
follows the input when enabled.
D. Q output follows the input
D when the enable is HIGH.
11. With regard to a D latch,
________.
A. the Q output follows the D
input when EN is LOW
B. the Q output is opposite the D
input when EN is LOW
C. the Q output follows the D
input when EN is HIGH
D. the Q output is HIGH
regardless of EN's input state
12. How can the cross-coupled NAND
flip-flop be made to have active-
HIGH S-R inputs?
A. It can't be done.
B. Invert the Q outputs.
C. Invert the S-R inputs.
 19. A J-K flip-flop with J = 1 and K = 1
13. When is a flip-flop said to be has a 20 kHz clock input. The Q
transparent? output is ________.
A. when the Q output is opposite A. constantly LOW
the input B. constantly HIGH
B. when the Q output follows C. a 20 kHz square wave
the input D. a 10 kHz square wave
C. when you can see through the
IC packaging 20. The toggle condition in a master-
slave J-K flip-flop means that Q and
14. Master-slave J-K flip-flops are will switch to their ________ state(s)
called pulse-triggered or level- at the ________.
triggered devices because input data A. opposite, active clock edge
is read during the entire time the B. inverted, positive clock edge
clock pulse is at a LOW level. C. quiescent, negative clock edge
A. True B. False D. reset, synchronous clock edge

15. A J-K flip-flop is in a "no change" 21. On a positive edge-triggered S-R

condition when ________. flip-flop, the outputs reflect the input
A. J = 1, K = 1 condition when ________.
B. J = 1, K = 0 A. the clock pulse is LOW
C. J = 0, K = 1 B. the clock pulse is HIGH
D. J = 0, K = 0 C. the clock pulse transitions
from LOW to HIGH
16. A correct output is achieved from D. the clock pulse transitions
a master-slave J-K flip-flop only if its from HIGH to LOW
inputs are stable while the:
22. What is the hold condition of a
A. clock is LOW flip-flop?
B. slave is transferring A. both S and R inputs activated
C. flip-flop is reset B. no active S or R input
D. clock is HIGH C. only S is active
D. only R is active
17. Which of the following describes
the operation of a positive edge- 23. f an active-HIGH S-R latch has a
triggered D flip-flop? 0 on the S input and a 1 on the R
A. If both inputs are HIGH, the input and then the Q input goes to 0,
output will toggle. the latch will be ________.
B. The output will follow the A. SET B. RESET
input on the leading edge of the C. clear D. invalid
clock.
C. When both inputs are LOW, an 24. Does the cross-coupled NOR flip-
invalid state exists. flop have active-HIGH or active-LOW
D. The input is toggled into the set and reset inputs?
flip-flop on the leading edge of the A. active-HIGH B.
clock and is passed to the output on active-LOW
the trailing edge of the clock.
25. With four J-K flip-flops wired as an
18. What does the triangle on the asynchronous counter, the first
clock input of a J-K flip-flop mean? output change of divider #4
A. level enabled indicates a count of how many input
B. edge-triggered clock pulses?
A. 16 B. 8
C. 4 D. 2
 7. Which of the following is the most
26. What is the significance of the J widely used alphanumeric code for
and K terminals on the J-K flip-flop? computer input and output?
A. There is no known significance
in their designations. A. Gray B. ASCII
B. The J represents "jump," which C. Parity D. EBCDIC
is how the Q output reacts whenever
the clock goes high and the J input is 8. Convert 59.72 to BCD.
also HIGH.
C. The letters were chosen in A. 111011 B.
honor of Jack Kilby, the 01011001.01110010
inventory of the integrated C. 1110.11
circuit. D.0101100101110010
D. All of the other letters of the
alphabet are already in use. 9. Convert 8B3F to binary.

A. 35647B. 011010
NUMBER SYSTEMS: C.1011001111100011
D.1000101100111111
1. Convert hexadecimal value 16 to
decimal. 10. Which is typically the longest:
A. 22 B. 16 bit, byte, nibble, word?
C. 10 D. 20
A. Bit B. Byte
2. Convert the following decimal C. NibbleD. Word
number to 8-bit binary. 187
A.10111011 B. 11011101 11. Convert hexadecimal value C1 to
C.10111101 D. 10111100 binary.

3. Convert binary 111111110010 to A. 11000001 B. 1000111

hexadecimal. C. 111000100 D. 111000001

A. EE2 B. FF2 12. Convert the following octal

C. 2FE D. FD2 number to decimal. 17

4. Convert the following binary A. 51 B. 82

number to decimal. 01011 C. 57 D. 15

A. 11 B. 35 13. The BCD number for decimal 347

C. 15 D. 10 is ________.

5. Convert the binary number A. 1100 1011 1000

1001.0010 to decimal. B. 0011 0100 0111
C. 0011 0100 0001
A. 90.125 B. 9.125 D. 1100 1011 0110
C. 125 D. 12.5
14. The sum of 11101 + 10111
6. One hex digit is sometimes equals ________.
referred to as a(n):
A. 110011 B. 100001
A. byte B. nibble C. 110100 D. 100100
C. grouping D. instruction
15. Convert binary 01001110 to
decimal.
 A. 100 B. 111
A. 4E B. 78 C. 001 D. 110
C. 76 D. 116
24. The binary number
16. Which is not a word size? 11101011000111010 can be written
in hexadecimal as ________.
A. 64 B. 28
C. 16 D. 8 A. DD63A B. 1D63A
C. 1D33A D. 1D631
17. The octal numbering system:
25. Determine the decimal
A. simplifies tasks equivalent of the signed binary
B. groups binary numbers in number 11110100 in 1's
groups of 4 complement.
C. saves time
D. simplifies tasks and saves A. 116 B. –12
time C. –11 D. 128

18. Convert 1100101000110101 to COUNTERS:

hexadecimal.
1.How many flip-flops are required to
A. 121035 B. CA35
make a MOD-32 binary counter?
C. 53AC1 D. 530121
A. 3 B. 45
19. Hexadecimal letters A through F
C. 5 D. 6
are used for decimal equivalent
values from:
2.A MOD-16 ripple counter is holding
A. 1 through 6 the count 10012. What will the count
B. 9 through 14
be after 31 clock pulses?
C. 10 through 15
D. 11 through 17 A. 10002 B. 10102

20. Convert the following decimal C. 10112 D. 11012

number to 8-bit binary.
35
3.The terminal count of a modulus-
A. 00010010 B. 00010011 11 binary counter is ________.
C. 00100011 D. 00100010 A. 1010 B. 1000

21. A decimal 11 in BCD is ________. C. 1001 D. 1100

A. 00001011 B. 00001100 4.Integrated-circuit counter chips are

C. 00010001 D. 00010010 used in numerous applications
including:
22. What is the resultant binary of
the decimal problem 49 + 01 = ? timing operations, counting
A. operations, sequencing, and
A. 01010101 B. 00110101 frequency multiplication
C. 00110010 D. 00110001
timing operations, counting
23. The difference of 111 – 001 B. operations, sequencing, and
equals ________. frequency division
 timing operations, decoding
C. operations, sequencing, and 9.A BCD counter is a ________.
frequency multiplication A. binary counter

data generation, counting B. full-modulus counter

D. operations, sequencing, and
C. decade counter
frequency multiplication
D. divide-by-10 counter
5.Synchronous construction reduces
the delay time of a counter to the 10.How many flip-flops are required
delay of: to construct a decade counter?
A. all flip-flops and gates A. 10 B. 8
all flip-flops and gates after a 3 C. 5 D. 4
B.
count

C. a single gate 11.The terminal count of a typical

modulus-10 binary counter is
D. a single flip-flop and a gate ________.
A. 0000 B. 1010
6.When two counters are cascaded,
C. 1001 D. 1111
the overall MOD number is equal to
the ________ of their individual MOD
numbers. 12.To operate correctly, starting a
A. product B. sum ring counter requires:
clearing one flip-flop and
C. log D. reciprocal A.
presetting all the others.

7.A MOD-12 and a MOD-10 counter B. clearing all the flip-flops.

are cascaded. Determine the output presetting one flip-flop and
frequency if the input clock C.
clearing all the others.
frequency is 60 MHz.
A. 500 kHz D. presetting all the flip-flops.
B. 1,500 kHz
13.The process of designing a
C. 6 MHz synchronous counter that will count
in a nonbinary manner is primarily
D. 5 MHz
based on:
external logic circuits that
8.Which segments of a seven- decode the various states of
segment display would be required A. the counter to apply the
to be active to display the decimal correct logic levels to the J-K
digit 2?
inputs
A. a, b, d, e, and g
modifying BCD counters to change
B. a, b, c, d, and g
B. states on every second input clock
C. a, c, d, f, and g pulse

D. a, b, c, d, e, and f C. modifying asynchronous counters

to change states on every second
 input clock pulse
elimination of the counter stages
and the addition of combinational
D.
logic circuits to produce the
desired counts
14.Select the response that best
describes the use of the Master
Reset on typical 4-bit binary
counters.
When MR1 and MR2 are both
A. HIGH, all Qs will be reset to
zero.
When MR1 and MR2 are both
B.
HIGH, all Qs will be reset to one.
MR1 and MR2 are provided to
C. synchronously reset all four flip-
flops.
To enable the count mode, MR1
D.
and MR2 must be held LOW.
15.For a multistage counter to be
truly synchronous, the ________ of
each stage must be connected to
________.
A. Cp, the same clock input line
B. CE, the same clock input line
C. , the terminal count output
D. , both clock input lines
16.How many different states does a
3-bit asynchronous counter have?
A. 2 B. 4
C. 8 D. 16
17.Once an up-/down-counter begins
its count sequence, it cannot be
reversed.
A. True B. False
18.Three cascaded modulus-5
counters have an overall modulus of
________.
A. 5 B. 25
C.125 D. 500
19.A 4-bit up/down binary counter is
in the DOWN mode and in the 1100
state. To what state does the counter
go on the next clock pulse?
A. 1101 B. 1011
C. 1111 D. 0000
20.The terminal count of a 3-bit
binary counter in the DOWN mode is
________.
A. 000 B. 111
C. 101 D. 010
21.Synchronous (parallel) counters
eliminate the delay problems
encountered with asynchronous
(ripple) counters because the:
input clock pulses are applied only
A.
to the first and last stages.
input clock pulses are applied only
B.
to the last stage.
input clock pulses are applied
C.
simultaneously to each stage.
input clock pulses are not used to
D.
activate any of the counter stages.
22.A counter with a modulus of 16
acts as a ________.
A. divide-by-8 counter
B. divide-by-16 counter
C. divide-by-32 counter
D. divide-by-64 counter
23.A ripple counter's speed is limited
by the propagation delay of:
A. each flip-flop the five output leads on a 74148
octal-to-binary encoder.
B. all flip-flops and gates I0 = 1 I3 = 1 I6 = 1
C. the flip-flops only with gates
I1 = 1 I4 = 0 I7 = 1
D. only circuit gates
I2 = 1 I5 = 1 EI = 0
24.How many natural states will
there be in a 4-bit ripple counter?
GS = L, A0 = L, A1 = L, A2 = H, EO
A. 4 B. 8 A.
=H
C. 16 D. 32
GS = L, A0 = H, A1 = L, A2 = L, EO
B.
=H
25.A modulus-10 counter must have
________. GS = L, A0 = L, A1 = H, A2 = L, EO
C.
A. 10 flip-flops =H
B. flip-flops GS = L, A0 = H, A1 = H, A2 = L,
D.
C. 2 flip-flops EO = H

D. synchronous clocking
5.What is the function of an enable
input on a multiplexer chip?
A. to apply Vcc
CODE CONVERTERS &
MULTIPLEXERS: B. to connect ground

C. to active the entire chip

1.How many outputs are on a BCD
decoder? D. to active one half of the chip
A. 4 B. 16

C. 8 D. 10 6.A basic multiplexer principle can

be demonstrated through the use of
a:
2.In a Gray code, each number is 3 A. single-pole relay
greater than the binary
representation of that number. B. DPDT switch
A. True B. False C. rotary switch

D. linear stepper
3.Which digital system translates
coded characters into a more useful
form? 7.How many inputs will a decimal-to-
A. encoder B. display BCD encoder have?
A. 4 B. 8
C. counter D. decoder
C. 10 D. 16
4.From the following list of input
conditions, determine the state of 8.One multiplexer can take the place
of:
A. several SSI logic gates
B. combinational logic circuits
C. several Ex-NOR gates
several SSI logic gates or
D.
combinational logic circuits
9.How many exclusive-NOR gates
would be required for an 8-bit
comparator circuit?
A. 4 B. 6
C. 8 D. 10
10.A BCD decoder will have how
many rows in its truth table?
A. 10 B. 9
C. 8 D. 3
11.How many possible outputs would
a decoder have with a 6-bit binary
input?
A. 16 B. 32
C. 64 D. 128
12.Most demultiplexers facilitate
which type of conversion?
A. decimal-to-hexadecimal
B. single input, multiple outputs
C. ac to dc
D. odd parity to even parity
13.The inputs/outputs of an analog
multiplexer/demultiplexer are:
A. bidirectional
B. unidirectional
C. even parity
D. binary-coded decimal
14.One application of a digital
multiplexer is to facilitate:
A. data generation
B. serial-to-parallel conversion
C. parity checking
D. data selector
15.The primary use for Gray code is:
coded representation of a
A.
shaft's mechanical position
B. turning on/off software switches
to represent the correct ASCII code
C. to indicate the angular position of
a shaft on rotating machinery
to convert the angular position of
D. a shaft on rotating machinery into
hexadecimal code
16.Why is a demultiplexer called a
data distributor?
The input will be distributed to
A.
one of the outputs.
One of the inputs will be selected
B.
for the output.
The output will be distributed to
C.
one of the inputs.
17.What is the status of the inputs
S0, S1, and S2 of the 74151 eight-line
multiplexer in order for the output Y
to be a copy of input I5?
A. S0 = 0, S1 = 1, S2 = 0
B. S0 = 0, S1 = 0, S2 = 1
C. S0 = 1, S1 = 1, S2 = 0
D. S0 = 1, S1 = 0, S2 = 1
18.One way to convert BCD to binary
using the hardware approach is:
A. with MSI IC circuits
B. with a keyboard encoder
C. with an ALU be determined from the logic
symbol?
D. UART A. A bubble indicates active-HIGH.

B. A bubble indicates active-LOW.

19.How is an encoder different from
a decoder? C. A square indicates active-HIGH.
The output of an encoder is a
A. D. A square indicates active-LOW.
binary code for 1-of-N input.

The output of a decoder is a binary

B. 24.How many select lines would be
code for 1-of-N input.
required for an 8-line-to-1-line
multiplexer?
20.Why is the Gray code more A. 2 B. 3
practical to use when coding the
position of a rotating shaft? C. 4 D. 8
A. All digits change between counts.
A circuit that responds to a specific
B. Two digits change between counts.
set of signals to produce a related
Only one digit changes digital signal output is called a(n):
C. A. BCD matrix
between counts.
B. display driver
21.When two or more inputs are
C. encoder
active simultaneously, the process is
called: D. decoder
A. first-in, first-out processing

B. priority encoding

C. ripple blanking

first-in, first-out processing or

D.
priority encoding

22.In a BCD-to-seven-segment
converter, why must a code
converter be utilized?
to convert the 4-bit BCD into
A.
7-bit code

to convert the 4-bit BCD into 10-

B.
bit code

to convert the 4-bit BCD into Gray

C.
code

D. No conversion is necessary.

23.How can the active condition

(HIGH or LOW) or the decoder output