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A V A I L A B L E
AN20 • AN42–48 • AN50–53 • AN73 • XK9241
X9241
Quad E2POT™ Nonvolatile Digital Potentiometer
FEATURES DESCRIPTION
• Four E2POTsin One Package The X9241 integrates four nonvolatile E2POT digitally
• Two-Wire Serial Interface controlled potentiometers on a monolithic CMOS micro-
• Register Oriented Format circuit.
—Directly Write Wiper Position
—Read Wiper Position The X9241 contains four resistor arrays, each com-
—Store as Many as Four Positions per Pot posed of 63 resistive elements. Between each element
• Instruction Format and at either end are tap points accessible to the wiper
—Quick Transfer of Register Contents to elements. The position of the wiper element on the array
Resistor Array is controlled by the user through the two-wire serial bus
—Cascade Resistor Arrays interface.
• Low Power CMOS Each resistor array has associated with it a wiper counter
• Direct Write Cell register and four 8-bit data registers that can be directly
—Endurance - 100,000 Data Changes per Register written and read by the user. The contents of the wiper
—Register Data Retention - 100 years counter register control the position of the wiper on the
• 16 Bytes of E2PROM memory resistor array.
• 3 Resistor Array Values
—2KΩ to 50KΩ Mask Programmable The data register may be read or written by the user. The
—Cascadable For Values of 500Ω to 200KΩ contents of the data registers can be transferred to the
• Resolution: 64 Taps each Pot wiper counter register to position the wiper. The current
• 20-Lead Plastic DIP, 20-Lead TSSOP and wiper position can be transferred to any one of its
20-Lead SOIC Packages associated data registers.
The arrays may be cascaded to form resistive elements
with 127, 190 or 253 taps.
FUNCTIONAL DIAGRAM
R0 R1 VH0 R0 R1 VH2
WIPER WIPER RESISTOR
COUNTER COUNTER ARRAY
REGISTER REGISTER POT 2
(WCR) VL0 (WCR) VL2
R2 R3 R2 R3
VW0 VW2
SCL
SDA INTERFACE
A0 AND
A1 CONTROL 8
A2 CIRCUITRY
A3 DATA
VH1 VH3
R0 R1 R0 R1
WIPER WIPER RESISTOR
COUNTER RESISTOR COUNTER ARRAY
REGISTER ARRAY REGISTER POT 3
(WCR) POT 1 VL1 (WCR) VL3
R2 R3 R2 R3
VW1 VW3
© Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
3864-2.7 7/1/96 T0/C3/D3 NS 1
X9241
2
X9241
Acknowledge The next four bits of the slave address are the device
Acknowledge is a software convention used to provide address. The physical device address is defined by the
a positive handshake between the master and slave state of the A0-A3 inputs. The X9241 compares the
devices on the bus to indicate the successful receipt of serial data stream with the address input state; a suc-
data. The transmitting device, either the master or the cessful compare of all four address bits is required for
slave, will release the SDA bus after transmitting eight the X9241 to respond with an acknowledge.
bits. The master generates a ninth clock cycle and Acknowledge Polling
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits The disabling of the inputs, during the internal non-
of data. See Figure 7. volatile write operation, can be used to take advantage
of the typical 5ms E2PROM write cycle time. Once the
The X9241 will respond with an acknowledge after stop condition is issued to indicate the end of the
recognition of a start condition and its slave address and nonvolatile write command the X9241 initiates the inter-
once again after successful receipt of the command nal write cycle. ACK polling can be initiated immediately.
byte. If the command is followed by a data byte the This involves issuing the start condition followed by the
X9241 will respond with a final acknowledge. device slave address. If the X9241 is still busy with the
write operation no ACK will be returned. If the X9241 has
Array Description completed the write operation an ACK will be returned
The X9241 is comprised of four resistor arrays. Each and the master can then proceed with the next
array contains 63 discrete resistive segments that are operation.
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical poten- Flow 1. ACK Polling Sequence
tiometer (VH and VL inputs).
NONVOLATILE WRITE
At both ends of each array and between each resistor COMMAND COMPLETED
segment is a FET switch connected to the wiper (VW) ENTER ACK POLLING
output. Within each individual array only one switch may
be turned on at a time. These switches are controlled by
the Wiper Counter Register (WCR). The six least signifi- ISSUE
START
cant bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed ISSUE SLAVE ISSUE STOP
by transferring the contents of one of four associated ADDRESS
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
ACK NO
RETURNED?
Device Addressing
Following a start condition the master must output the YES
address of the slave it is accessing. The most significant
four bits of the slave address are the device type NO
FURTHER
identifier (refer to Figure 1 below). For the X9241 this is OPERATION?
fixed as 0101[B].
Figure 1. Slave Address YES
0 1 0 1 A3 A2 A1 A0
PROCEED PROCEED
DEVICE ADDRESS
3864 FHD F08 3864 ILL F01
3
X9241
The four high order bits define the instruction. The next The Increment/Decrement command is different from
two bits (P1 and P0) select which one of the four the other commands. Once the command is issued and
potentiometers is to be affected by the instruction. The the X9241 has responded with an acknowledge, the
last two bits (R1 and R0) select one of the four registers master can clock the selected wiper up and/or down in
that is to be acted upon when a register oriented instruc- one segment steps; thereby, providing a fine tuning
tion is issued. capability to the host. For each SCL clock pulse (tHIGH)
while SDA is HIGH, the selected wiper will move one
Four of the nine instructions end with the transmission of resistor segment towards the VH terminal. Similarly, for
the instruction byte. The basic sequence is illustrated in each SCL clock pulse while SDA is LOW, the selected
Figure 3. These two-byte instructions exchange data wiper will move one resistor segment towards the VL
between the WCR and one of the data registers. A terminal. A detailed illustration of the sequence and
transfer from a data register to a WCR is essentially a timing for this operation are shown in Figures 5 and 6
write to a static RAM. The response of the wiper to this respectively.
SCL
SDA
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 P1 P0 R1 R0 A S
T C C T
A K K O
R P
T
3864 ILL F10
4
X9241
SCL
SDA
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 P1 P0 R1 R0 A CM DW D5 D4 D3 D2 D1 D0 A S
T C C C T
A K K K O
R P
T
3864 ILL F11
SCL
SDA X X
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 P1 P0 R1 R0 A I I I D D S
T C C N N N E E T
A K K C C C C C O
R 1 2 n 1 n P
T
3864 FHD F12
INC/DEC
CMD
ISSUED tCLWV
SCL
SDA
VW VOLTAGE OUT
5
X9241
SCL FROM
MASTER 1 8 9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START ACKNOWLEDGE
6
X9241
DETAILED OPERATION The WCR is a volatile register; that is, its contents are
lost when the X9241 is powered-down. Although the
All four E2POT potentiometers share the serial interface
register is automatically loaded with the value in R0
and share a common architecture. Each potentiometer
upon power-up, it should be noted this may be different
is comprised of a resistor array, a wiper counter register
from the value present at power-down.
and four data registers. A detailed discussion of the
register organization and array operation follows. Data Registers
Wiper Counter Register Each potentiometer has four nonvolatile data registers.
These can be read or written directly by the host and
The X9241 contains four wiper counter registers (WCR),
data can be transferred between any of the four data
one for each E2POT potentiometer. The WCR can be
registers and the WCR. It should be noted all operations
envisioned as a 6-bit parallel and serial load counter with
changing data in one of these registers is a nonvolatile
its outputs decoded to select one of sixty-four switches
operation and will take a maximum of 10ms.
along its resistor array. The contents of the WCR can be
altered in four ways: it may be written directly by the host If the application does not require storage of multiple
via the Write WCR instruction (serial load); it may be settings for the potentiometer, these registers can be
written indirectly by transferring the contents of one of used as regular memory locations that could possibly
four associated data registers via the XFR Data Register store system parameters or user preference data.
instruction (parallel load); it can be modified one step at
a time by the Increment/ Decrement instruction; finally,
it is loaded with the contents of its data register zero (R0)
upon power-up.
Figure 8. Detailed Potentiometer Block Diagram
8 6 PARALLEL C
BUS O
INPUT U
N
WIPER T
REGISTER 2 REGISTER 3 COUNTER E
REGISTER R
D
E
2 C
INC/DEC O
LOGIC D
IF WCR = 00[H] THEN VW = VL UP/DN
UP/DN E
IF WCR = 3F[H] THEN VW = VH MODIFIED SCL VL
CLK
DW
CASCADE VW
CONTROL
LOGIC
CM
7
X9241
Cascade Mode DW bit of the WCR is set to “0” the wiper is enabled;
The X9241 provides a mechanism for cascading the when set to “1” the wiper is disabled. If the wiper is
arrays. That is, the sixty-three resistor elements of one disabled, the wiper terminal will be electrically isolated
array may be cascaded (linked) with the resistor ele- and float.
ments of an adjacent array. When operating in cascade mode VH, VL and the wiper
Cascade Control Bits terminals of the cascaded arrays must be electrically
connected externally. All but one of the wipers must be
The data byte, for the three-byte commands, contains 6 disabled. The user can alter the wiper position by writing
bits (LSBs) for defining the wiper position plus two high directly to the WCR or indirectly by transferring the
order bits, CM (Cascade Mode) and DW (Disable Wiper). contents of the data registers to the WCR or by using the
The state of CM enables or disables (normal operation) Increment/Decrement command.
cascade mode. When the CM bit of the WCR is set to “0” When using the Increment/Decrement command the
the potentiometer is in the normal operation mode. wiper position will automatically transition between
When the CM bit of the WCR is set to “1” the potentiometer arrays. The current position of the wiper can be deter-
is cascaded with its adjacent higher order potentiometer. mined by reading the WCR registers; if the DW bit is “0”,
For example; if bit 7 of WCR2 is set to “1”, pot 2 will be the wiper in that array is active. If the current wiper
cascaded to pot 3. position is to be maintained, a global XFR WCR to Data
The state of DW enables or disables the wiper. When the Register command must be issued before power-down.
VL0
POT 0
WCR0 VH0
VW0
VL1
POT 1
WCR1 VH1
VW1
VL2
POT 2
WCR2 VH2
VW2
VL3
POT 3
WCR3 VH3
= EXTERNAL
CONNECTION VW3
8
X9241
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
lCC Supply Current (Active) 3 mA fSCL = 100KHz, SDA = Open,
Other Inputs = VSS
ISB VCC Current (Standby) 200 500 µA SCL=SDA=VCC, Addr. = VSS
ILI Input Leakage Current 10 µA VIN = VSS to VCC
ILO Output Leakage Current 10 µA VOUT = VSS to VCC
VIH Input HIGH Voltage 2 VCC + 1 V
VIL Input LOW Voltage –1 0.8 V
VOL Output LOW Voltage 0.4 V IOL = 3mA
3864 PGM T06.3
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper
position when used as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH – VL)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
9
X9241
CAPACITANCE
Symbol Parameter Max. Units Test Conditions
CI/O (5) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(5) Input Capacitance (A0, A1, A2, A3 and SCL) 6 pF VIN = 0V
3864 PGM T08
POWER-UP TIMING
Symbol Parameter Max. Units
tPUR(6) Power-up to Initiation of Read Operation 1 ms
tPUW(6) Power-up to Initiation of Write Operation 5 ms
3864 PGM T09
Must be Will be
steady steady tR
80 RMAX =
CBUS
May change Will change
from LOW from LOW 60 MAX.
RESISTANCE
to HIGH to HIGH
40
May change Will change
from HIGH from HIGH 20
to LOW to LOW MIN.
RESISTANCE
Don’t Care: Changing: 0
Changes State Not 0 20 40 60 80 100 120
Allowed Known
N/A Center Line BUS CAPACITANCE (pF)
is High
Impedance
3864 ILL F17
10
X9241
tHIGH tLOW tF tR
SCL
SDA
(DATA IN)
tBUF
11
X9241
SCL
tAA tDH
SCL
SDA
DATA IN
SCL
CLOCK 8 CLOCK 9 STOP START
tWR
tSTPWV
WIPER
OUTPUT
12
X9241
PACKAGING INFORMATION
1.060 (26.92)
0.980 (24.89)
0.280 (7.11)
0.240 (6.096)
PIN 1 INDEX
PIN 1
0.900 (23.66) —
REF. 0.005 (0.127)
0.195 (4.95)
SEATING 0.115 (2.92)
PLANE
(3.81) 0.150 ––
(2.92) 0.1150 0.015 (0.38)
0.300
(7.62) (BSC)
0.014 (0.356) 0°
0.008 (0.2032) 15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
13
X9241
PACKAGING INFORMATION
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.50)
0.496 (12.60)
0.508 (12.90)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.050 (1.27)
0.012 (0.30)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° – 8° 0.420"
0.007 (0.18)
0.011 (0.28)
0.015 (0.40)
0.050 (1.27)
0.030" Typical
20 Places
FOOTPRINT
14
X9241
PACKAGING INFORMATION
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.010 (.25)
Gage Plane
0° – 8° Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
15
X9241
ORDERING INFORMATION
X9241 Y P T V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 20-Lead Plastic DIP
S = 20-Lead SOIC
V = 20-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
Y = 2K 2K 2K 2K
W = 10K 10K 10K 10K
U = 50K 50K 50K 50K
M = 2K 10K 10K 50K
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
16