IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.

4, APRIL 2010 855

Modeling the Independent Double Gate Transistor in

Accumulation Regime for 1TDRAM Application
Sophie Puget, Germain Bossu, Pascal Masson, Pascale Mazoyer, Rossella Ranica, Alexandre Villaret,
Philippe Lorenzini, Jean-Michel Portal, Denis Rideau, Gérard Ghibaudo, Rachid Bouchakour,
Gilles Jacquemod, and Thomas Skotnicki, Senior Member, IEEE

Abstract—This paper details the modeling of a one- p Hole density (per cubic meter).
transistor dynamic random-access memory (1TDRAM) based on q Absolute value of the electron charge (1.602 ×
an independent double-gate device. A pseudo-2-D compact model 10−19 C).
of memory operations and dynamic behavior of data retention
is proposed. The physical mechanisms involved are calculated QFI Charge at the front interface (in Coulomb per square
through the accumulated charge in the body modulated by meter).
quantum effects related to thin silicon films. The resulting QBI Charge at the back interface (in Coulomb per square
currents from programming operations are detailed. We consider meter).
current leakages, generation/recombination, and band-to-band Qmem Hole stored charge (in Coulomb).
tunneling parasitic effects for data retention.
Qn Electron density (in Coulomb per square meter).
Index Terms—Accumulation regime, capacitorless dynamic T Absolute temperature (in degrees Kelvin).
random-access memory (DRAM), floating-body cell, independent tox1/2 Thickness of the front and back gate oxide, respec-
double-gate (IDG) transistor, kink effect, one-transistor DRAM
(1TDRAM), volatile memory modeling. tively (in meters).
tSi Thickness of silicon film (in meters).
L IST OF S YMBOLS VB Equivalent potential of silicon film (in volts).
VS/D Source/drain voltage (in volts).
Cox1/2 Dielectric capacitors of the front and back gates, VFB1/2 Flatband voltages of the front and back MOS struc-
respectively (in farads per square meter). tures, respectively (in volts).
EFM1/2 Energy levels of the front and back gate “metal,” VG1/2 Front gate G1/back gate G2 voltage (in volts).
respectively (in joules). W Channel width (in meters).
EFN Energy of the quasi-Fermi level for the electrons (in β Thermal potential (q/kT ).
joules). ξ Electric field (in volts per meter).
EFP Energy of the quasi-Fermi level for the holes (in ΦF Bulk potential of silicon film (in volts).
joules). ε0 Absolute permittivity (8.85 × 10−12 Fm−1 ).
EG Silicon band gap (in joules). εox/Si Silicon dioxide dielectric constant (3.82×ε0 Fm−1 )/
Ei Intrinsic energy level in silicon (in joules). silicon dielectric constant (11.9 × ε0 Fm−1 ).
IDS Source-to-drain current (in amperes). μp Hole mobility (in square meter per volt-second).
k Boltzmann’s constant (1.38 × 1023 JK−1 ). μ0 Interface electron mobility (in square meter per volt-
L Channel length (in meters). second).
n Electron density (per cubic meter).
ni Intrinsic carrier density (per cubic meter).
I. I NTRODUCTION

Manuscript received August 14, 2009; revised December 28, 2009. First
published February 25, 2010; current version published April 2, 2010. The
review of this paper was arranged by Editor G.-T. Jeong.
S. Puget, P. Mazoyer, R. Ranica, A. Villaret, D. Rideau, and T. Skotnicki are
with STMicroelectronics, 38926 Crolles, France.
G. Bossu is with Dolphin Integration, 38240 Meylan, France.
P. Masson, P. Lorenzini, and G. Jacquemod are with the Electronics Anten-
nas and Telecommunications Laboratory (LEAT), Université de Nice-Sophia
Antipolis, CNRS, 06560 Valbonne, France.
J.-M. Portal and R. Bouchakour are with Institute of Materials, Microelec-
tronics and Nanosciences of Provence (IM2NP), Université de Marseille, 13451
Marseille, France.
G. Ghibaudo is with the IMEP-LAHC Laboratory, MINATEC–INPG, 38016
Grenoble, France.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2010.2040937
T HIN SILICON films are considered for advanced CMOS
platforms to overcome major drawbacks, such as short-
channel effects (SCEs) and process variations when shrink-
ing dimensions. Independent double-gate (IDG) and FinFET
devices are possible solutions to overcome these issues.
FinFET presents symmetric-gate stack material. IDG offers
more flexibility on film thicknesses and roughness control,
as well as multiple-gate stack configurations. IDG thin-film
transistors can be considered potential one-transistor dynamic
random-access memory (1TDRAM; capacitorless DRAM or
floating-body cell) when two electrically independent gates are
available. The first gate manages the front transistor, and the
second gate allows charge accumulation through body potential
modulation.

0018-9383/$26.00 © 2010 IEEE

856 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

Fig. 1. (a) n-channel IDG transistor. (b) Band diagram: quasi-Fermi levels EFN for electrons and EFP for holes.

Charge inversion is usually considered for circuit modeling and depends on the number of accumulated holes. This allows
by analytical or semianalytical approaches [1]–[4]. Simulation floating-body potential definition in thin films VB . The thin-film
tools do not allow quick evaluation of charge accumulation; bulk potential is given by [6]
therefore, charge accumulation was never considered. For the  
kT NA
first time, to our knowledge, our work proposes a pseudo-2-D ΦF = ln . (1)
model that takes into account the charge accumulated in thin- q ni
film devices, allowing the description of 1TDRAM operations. The relations between local Fermi levels and applied poten-
A basic 1-D model is described in detail and extended through tials are
2-D. A comparison with the Sentaurus Work Bench (SWB) [5]
simulation tool is proposed. The impact of quantum effects, −qVS = EFN (x = 0) − qVD = EFN (x = L)
which is of importance in thin silicon films, is taken into
account for accumulated charge calculation. In this first version, −qVG1 = EFM1 − qVG2 = EFM2 − qVB = EFP .
SCEs and mobility reduction are not described. However, the
model is calibrated with 75-nm-gate-length devices using SWB
tools taking into account these parasitic effects. These mech- A. 1-D Model Development: Classic Approach
anisms and others related to short dimensions could easily be In this section, a set of equations for determining electron and
implemented. hole charges at the back and front interfaces is developed [7].
Programming operations are described with 2-D modeling: The starting point is the Poisson equation resolution in one
Impact ionization only concerns write operations, whereas dimension, i.e.,
diode and recombination currents are involved in both
∂2V ∂ξ q  
write and erase operations. The retention time is evaluated,
2
=− =− p(y) − NA− − n(y) + ND
+
. (2)
considering several leakage mechanisms: diode diffusion, ∂y ∂y εSi
generation/recombination, and band-to-band tunneling (BTBT)
Assuming perfect dielectric layers (i.e., without any parasitic
currents.
charge), solution to the Poisson equation gives constant values
for the electric fields ξox1 and ξox2 related to the front and back
II. T HEORY gates, respectively. The second Poisson equation integration
Fig. 1(a) presents a schematic view of the n-channel IDG gives electrostatic potential at the front and back dielectrics,
MOS transistor, and Fig. 1(b) presents the band diagram con- respectively, i.e.,
sidered in this study. The parameters are labeled 1 and 2 for the
front MOS and the back MOS, respectively. The Fermi level in Ψ = − ξox1 y + VG1 − VFB1 − ξox1 tox1 (3)
the two gates is above the minimum of the conduction band (not Ψ = − ξox2 y + VG2 − VFB2 + ξox2 (tSi + tox2 ) (4)
shown), which induces a huge number of free electrons. The
conduction and valence bands (not specified) are not used in where VFB1 and VFB2 represent the flatband voltages of the
this model. The silicon thin film is fully depleted. In write con- front and back MOS stacks, respectively. The expression in the
ditions, the front interface is in the inversion regime, whereas case of n-degenerated polysilicon gate is given by
the back interface is in the accumulation regime. EC (y) and
EG
EV (y) represent silicon band bending due to acceptor impuri- VFB1 = VFB2 = − − ΦF . (5)
ties. The position of the quasi-Fermi level for electrons in the 2
channel at x = 0 is given by the Fermi level in the N+ source The front-interface charge QFI is supposed to be located
region (and the Fermi level in the N+ drain region for x = L). at the interface (i.e., at y = 0). The Gauss law is written as
The Fermi level variation along the channel corresponds to the follows:
drain-to-source current image IDS . The quasi-Fermi level for
holes is supposed to be uniform in thin films (no hole current) −εox ξ(0− ) + εSi ξ(0+ ) = QFI . (6)
PUGET et al.: MODELING THE IDG TRANSISTOR IN ACCUMULATION REGIME FOR 1TDRAM APPLICATION 857

This hypothesis allows determining the following equation the middle of the thin film (y = tSi /2), the charge at the front
of the potential in the thin film: interface can be expressed as
 
qNA 2 QFI εox t

Si /2
Ψ(y) = y − + ξox1 y
2εSi εSi εSi QFI = q [p(y) − n(y)] dy. (15)
+ VG1 − VFB1 − ξox1 tox1 . (7) 0

Following the same hypothesis, the back-interface charge Following the same hypothesis, the charge expression at the
QBI can be written as back interface is given by
   +
−εSi ξ t−
Si + εox ξ tSi = QBI . (8)
tSi
QBI = q [p(y) − n(y)] dy. (16)
Using (7), (8), the Gauss law in this thin film, and potential
tSi /2
continuity at the back interface, the electric fields in the front
and back dielectrics are given by (9) and (10), shown at the
bottom of the page. From (9)–(14), it is obvious that the value of QFI depends on
The front- and back-interface charges are given by the fol- QBI and QFI . The determination of these charges can be solved
lowing the local electron density equation: using the classical iteration method.
In order to validate our 1-D approach, the model has
 
EFN − Ei (y) been compared to simulations obtained with SWB [5]
n(y) = ni exp (11) from Synopsys. The underlying physics used by SWB are
kT
Boltzmann statistics, constant mobility, a drift diffusion model,
where Ei represents the middle of the silicon band gap and is a Van Overstaeten model for impact ionization, and Auger
given by Shockley–Read–Hall for generation/recombination models.
 The transistor described in Fig. 1 is considered for this
EG study.
Ei (y) = q −Ψ(y) − VFB1 − . (12)
2 The stored charge (or accumulated charge) Qmem is defined
for 1TDRAM application [7], [8]. This hole charge is also given
Integrating (5), (7), and (12) leads to (13), shown at the (in 1-D model) by (18). For a given set of polarizations and
bottom of the page. from the knowledge of Qmem , the unknown parameters are the
With the same approach, the hole local density expression is electron charge and the hole Fermi level position EFP within
given by (14), shown at the bottom of the page. the thin film. The classical dichotomy approach cannot be used
Supposing that the front-interface charge corresponds to the to determine EFP as the presence of exponential equations in
total charge of free carriers between the interface (y = 0) and our model induces an important risk of overflow.

 
qNA 2 qNA tSi tox2 tox2
2εSi tSi + εox tSi tox2 − εSi + εox QFI − εox QBI + VG1 − VG2 − VFB1 + VFB2
ξox1 = εox (9)
tox1 + εSi tSi + tox2
QBI qNA QFI
ξox2 = − tSi + + ξox1 (10)
εox εox εox

⎛     ⎞
qNA 2 QFI εox
EFN + q 2εSi y − εSi + εSi ξox1 y + VG1 − ξox1 tox1 + q E2G
n(y) = ni exp ⎝ ⎠ (13)
kT

⎛     ⎞
qNA 2 QFI εox
EFP + q 2εSi y − εSi + εSi ξox1 y + VG1 − ξox1 tox1 + q E2G
p(y) = ni exp ⎝ ⎠ (14)
kT
858 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010

Fig. 3. Mean error value (in percent) on the hole density model versus SWB
according VG1 /VG2 polarizations. The front interface is pushed in the inver-
sion regime (weak and strong), and the back interface is in the accumulation
regime for VG2 < VFB2 . The transistor parameters are given as follows:
tSi = 16 nm, tox1 = 1.6 nm, tox2 = 1.6 nm, VFB1 = VFB2 = −1.05 V, and
Fig. 2. Algorithm graph set developed to determine the hole quasi-Fermi level NA = 2 × 1024 m−3 .
by an iterative method; the EFP step is +/−0.1 eV.
B. 1-D Model Development: Quantum Approach
Fig. 2 shows the algorithm chosen to solve this problem,
It is well known that carrier confinement in thin silicon
where three procedures labeled A, B, and C are used.
films is significant [9]. Potential confinement is modeled by
A) Initialize EFP with the EFN value, and calculate the
a triangular well, with an infinite Si/SiO2 barrier. With this
corresponding hole charge Qp in the thin film.
approximation, energy levels Ei for electrons and holes can be
B) Qp is compared with the charge target Qmem . If Qp is
evaluated by the airy function
inferior to Qmem , EFP is too high, and the next iteration
 2  13     23
will use the hole quasi-Fermi level decreased by 0.1 eV.  3π 3
Otherwise, EFP is incremented by 0.1 eV. EFP variation Ei = qξeff i+ (19)
2meff 2 4
versus the iteration number is monotone until Qp exceeds
the target value, assuming EFP is obtained. where i represents the energy level. The effective masses of
C) A classical dichotomy method is then used for EFP (= carriers are summarized in Table I. The effective field ξeff
−qVB ) determination. is defined at the front and back interfaces, respectively. The
general expression of the field within the thin film is given by
Fig. 3 presents the mean error value of the hole density using
a derivation of (7), without taking into account charges at the
the device shown in Fig. 1. The mean error value expressed in
interfaces
percent is given by
Qp − QSWB qNA QFI εox
mean_error = 100 (17) ξ(y) = − y+ + ξox1 . (20)
mean(Qp , QSWB ) εSi εSi εSi
The energy levels for longitudinal electrons in the conduction
where QSWB is calculated by SWB simulation, and Qp is
band at the front interface are defined by
calculated by the model

tSi El (i) = Ei − ψ(y = 0) + VFB1 . (21)
Qp = qW L p(y) dy. (18) In the same way, heavy holes in the valence band at the back
0 interface are defined by
Inversion on the front interface and accumulation on the Ehh (i) = Ehh − ψ(y = tSi ) + VFB1 − Eg. (22)
back-interface regime are highlighted by dotted lines in Fig. 3.
In these regions, the mean error value increases with bias A similar formula is considered for transverse electrons and
conditions to reach a maximum of 12% for weak inversion. This light hole densities at the front and back interfaces, respectively.
error is linked to high values of carrier densities being part of For example, the front-interface electron charge density is
the calculation. Combined with 2% error for electron charges, expressed as (23), shown at the bottom of the page.
a good accuracy for the channel current is obtained. Similar expressions can be found for the hole charge density.

 kT   q 
QelecFI = 2mt · m0 ln 1 + exp [EFN − [El (i) − ψSFI ] + VFB1 ]
i
π · hb · hb kT
kT √   q 
+ 4 mt · ml · m0 ln 1 + exp [EFN − [El (i) − ψSFI ] + VFB1 ] (23)
π · hb · hb kT
PUGET et al.: MODELING THE IDG TRANSISTOR IN ACCUMULATION REGIME FOR 1TDRAM APPLICATION
TABLE I
E FFECTIVE M ASSES OF C ARRIERS C ONSIDERED IN T HIS W ORK
Fig. 4. Charge density comparisons between PS [10] and our model: tox1 =
1.2 nm, tox2 = 3 nm, NA = 2 × 1024 m−3 , and VG2 = −1.8 V for the
classic (C) and quantum (Q) approaches. (Symbol) 1-D PS. (Line) Our model.
The model is validated by comparing the results with nu-
merical simulations using 1-D Poisson Schrödinger (PS) [10].
(L)
Charges calculated for tSi = 5 nm and 12-nm silicon films are
shown in Fig. 4. It should be noted that this model does not
use effective oxide thickness to account for quantum effects (as
in [11]); instead, this model directly evaluates charges using a
quantum mechanical description, and it includes coupling be-
tween the front and back gates. Similar accordance is obtained
for different channel doping values. The range of front-gate
bias voltages corresponding to a fully depleted thin film (i.e.,
without mobile charges at the interfaces) increases when taking
into account the quantum effects.
C. 2-D Model Development
Modeling is now considered with a 2-D approach to de-
termine the drain current and charge expressions. Assuming
859
Fig. 5. (Dot) SWB drain current versus (line) the model according to the front-
versus-gate potential VG1 . (a) Linear scale. (b) Logarithm scale VD = 50 mV
and back gate VG2 = −1.2 V for (c). Source potential VS is grounded. The
transistor parameters are given as follows: W = 1 μm, L = 10 μm, μ0 =
200 cm2 V−1 s−1 , tSi = 16 nm, tox1 = 1.6 nm, tox2 = 1.6 nm, VFB1 =
VFB2 = −1.05 V, and NA = 2 × 1024 m−3 .
Shockley’s gradual channel approximation, the source–drain
current IDS is given by the Pao and Sah equation [12], i.e.,
V
W
IDS = − μ0 Qn (V (x)) dV (x) (24)
L
V (0)
where μ0 corresponds to the electron mobility at the channel
interface, and W and L are the width and length of the channel,
respectively. Qn is the total electron charge in the film at
distance x from the source. V (x) corresponds to the evolution
of the potential applied between the source and the drain along
the channel (V (x = 0) = VS and V (x = L) = VD ). Excellent
correlation can be observed between simulations obtained with
SWB and our model (cf. Fig. 5). A long transistor has been
chosen here (L = 10 μm) to avoid any SCEs.
To evaluate the stored charge Qmem , charge repartition along
the channel is considered when the electron current is constant
860
Fig. 6. SWB simulation of the threshold voltage according to the gate length
of the device with the technological parameters tSi = 14 nm, NA = 2 ×
1024 m−3 , tox1 = 3 nm, tox2 = 5 nm, VFB1 = −0.59 V, and VFB2 =
−0.07 V, and electrical parameters VG2 = 0.
and equal to IDS . Then, (24) becomes
V
(x)
W
x=− μ0 Qn (V (x)) dV (x).
IDS
V (0)
Then, the stored charge of the IDG transistor is given by
L
tSi
Qmem = W qp(x, y) dy dx.
0 0
D. SCEs
SCEs are of major importance with transistor dimension re-
ductions. Usually, thin-film devices are undoped to allow good
control of the gate on the film. Our targeted device presents a
doped thin silicon film to favor memory behavior. SCEs have
been evaluated on a typical device of L = 75 nm, tox1 = 3 nm,
tox2 = 5 nm, W = 1 μm, and tSi = 14 nm, with a metallic
front gate (VFB1 = −0.59 V) and (P+)-type polysilicon back
gate (VFB2 = −0.07 V). Results are reported in Fig. 6, and no
bias is applied to the back gate. As our model does not take
into account SCEs, flatband voltages VFB1 and VFB2 have been
adjusted using SWB tools.
III. P ROGRAM AND R ETENTION C URRENTS
IDG 1TDRAM programming can be modeled by the addition
of two currents, as illustrated in Fig. 7. The IDG transistor is
polarized in the saturation regime at the front interface, whereas
the back interface is pushed into the accumulation regime.
1) The hole current Ihole is induced by impact ionization,
i.e., the channel hot electron (CHE) phenomenon. Holes
from the saturation region (the front interface close to the
drain) are flowing to the back interface.
2) Holes are accumulated at the back interface.
3) The direct current of the source diode, in the steady-state
regime, is equal to the hole current resulting from impact
ionization.
The association of drain current Ihole and diode current is
known as parasitic bipolar [13]. To complete the 1TDRAM
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
Fig. 7. SWB cross section of the IDG MOS polarized with the front interface
in the saturation regime and the back interface in the accumulation regime.
The hole current resulting from impact ionization is flowing along arrow 1, the
holes are accumulated in region 2, and the source diode current is flowing along
arrow 3. The device technological parameters are given as follows: L = 75 nm,
tSi = 14 nm, NA = 2 × 1024 m−3 , tox1 = 3 nm, and tox2 = 5 nm. The
electrical parameters are VFB1 = VFB2 = −1.05 V.
(25)
(26)
Fig. 8. Floating-body potential obtained by comparison between SWB and
our model. The device technological parameters are L = 75 nm, tSi = 14 nm,
NA = 2 × 1024 m−3 , tox1 = 3 nm, and tox2 = 5 nm, and the electrical
parameters are VFB1 = VFB2 = −1.05 V.
operation simulation, the generation/recombination current and
the BTBT current are added. BTBT appears when diodes are
pushed into the forward regime in addition to a strong negative
gate polarization.
Leakage currents have been determined with film potential
VB . IDS (VG1 , VDS ) characteristics have been simulated by
SWB. VB is extracted at the middle of the channel at 1 nm
of the back interface. According to SWB simulations, VB is
constant along the back interface. Predominant leakage currents
are located at the back interface between the substrate, drain,
and source. For each polarization, VB is adjusted to obtain the
drain current given by SWB (with an accuracy that is better
than 0.1%) (cf. Fig. 8). A good correlation between these two
approaches can be considered as a validation of our model.
A. Hole Current
The hole current due to CHE depends on the channel current
IDS [14], [15], and it is given by
 
ai −bi
Ihole = IDS (VD − Vsat ) exp (27)
bi VD − Vsat
with ai and bi being the impact ionization coefficients. Vsat ,
at the pinchoff, is the saturation potential. Vsat can be derived
from the potential and inversion charge variations along the
channel. The saturation area appears when the inversion charge
PUGET et al.: MODELING THE IDG TRANSISTOR IN ACCUMULATION REGIME FOR 1TDRAM APPLICATION 861

C. Generation/Recombination Currents
Generation/recombination phenomenon is of major impor-
tance in the 1TDRAM behavior. SWB simulations show [7] that
the thin film can be divided into three parts: the first controlled
by the front and back interfaces and the two others controlled
by the source and drain diodes. The generation/recombination
current is given by [6]

0
0
1 p(x, y)n(x, y) − n2i
IGR_tf = dy · dx (31)
τgr 2ni + p(x, y) + n(x, y)
tSi L

where τgr represents the carrier lifetime.

Fig. 9. Comparison of the hole current due to impact ionization obtained by The generation/recombination current in the source diode is
SWB and our model. The device technological parameters are L = 75 nm,
tSi = 14 nm, NA = 2 × 1024 m−3 , tox1 = 3 nm, and tox2 = 5 nm, and the defined as [15]
electrical parameters are VFB1 = VFB2 = −1.05 V and VG2 = −1.8 V.    
qVBS
qni exp kT − 1
in the channel becomes negligible, compared with the source IGR_dio = Wp W · tSi     (32)
τgr qVBS
inversion charge [15]. For example, when the inversion charge exp kT +1
is lower by a factor (Fac) of 10, compared with the source
inversion charge, Qn (Pinchoff) = Qn (source)/Fac. where WP is the length of the channel controlled by the diode.
We have adjusted the parameters ai(= 0.016 A−1 ), bi(= Replacing VBS by VBD , we obtain the drain diode current.
0.65 V), and Fac(= 30) to fit the hole current due to impact
ionization extracted from SWB. The results presented in Fig. 9
D. BTBT Current
are carried out with a symmetric gate poly-N+ /poly-N+ device.
It shows a good correlation. The GIDL current appears in nMOSFET when the drain
stack (gate/oxide/drain) is pushed into the depletion regime
in the gate-to-drain overlap region and when substrate/drain
B. Diffusion Diode Current diode is in the reverse regime, with the substrate potential being
Classical hole diffusion phenomenon in the source (drain) inferior to the drain potential. In our device, the predominant
N+ area for the diode current characteristic is considered. In phenomenon for GIDL is the BTBT current. Band bending is
order to take into account the strong injection regime, we use larger than the energy gap of silicon EG . The GIDL equation is
the model developed by Flatresse [16], [17] without generation/ given by [18]
recombination contribution. The source diode current is  
V3 Bgidl
given by IGIDL = Agidl ξS 3 BD exp − (33)
  VBD + Cgidl ξS
IS 2qVbi
Idiode = exp where dependence with drain diode polarization has been in-
2 kT
  cluded [19]. Cgidl is a fitting parameter, the GIDL parameters
   
2qVbi qVBS are Agidl and Bgidl , and the electric field is ξS at the front or
× 1 + 4 exp − exp −1 −1 (28) back dielectric interface. These expressions can be found in
kT ηkT
[20]. By replacing VBD by VBS , we obtain the GIDL current
where η is the emission coefficient also known as the ideality at the source terminal.
factor (η = 1 for an abrupt diode). Replacing VBS by VBD , we
obtain the drain diode current. Vbi is the built-in potential that IV. DYNAMIC A SPECT OF C ELL B EHAVIOR
depends on the junction doping levels
  The total hole charge in the film versus time t and Δt time
kT N A · ND step is given by
Vbi = ln . (29)
q n2i
Qmem (t) = Qmem (t − Δt) + (Ihole − Idiode_S − Idiode_D
IS corresponds to the saturation current
− IGR_Dio IGR_tf + IGIDL )Δt . (34)
qn2i Dp
IS = tSi W (30) It reflects the balance between the incoming current and the
N D WN
leakages occurring in the body of the transistor. The evolution
where Dp is the hole diffusion coefficient (= kT μp /q), and of Qmem versus time is now studied for the different states of
ND is the source doping level. WN represents the effective programming. State 1 refers to the fill state or write state by
source region length for hole diffusion. In our device, WN is analogy to standard DRAM, and state 0 refers to the empty state
much lower than the hole diffusion length. or erase state.
862
Fig. 10. Write hole charge time evolution modeling for several front-gate
potential biases with the classic approach. VD = 1 V, VS = 0 V, and
VG2 = −1.8 V. The transistor parameters are W = 1 μm, L = 75 nm,
μ0 = μp = 200 cm2 V−1 s−1 , tSi = 14 nm, tox1 = 3 nm, tox2 = 5 nm,
VFB1 = −0.59 V, VFB2 = −0.07 V, NA = 2 × 1024 m−3 . τGR = 0.1 μs,
μp = μ0 = 200 cm2 V−1 s−1 , η = 1, WN = 30 nm, Wp = 7 nm, ai =
0.016 A−1 , and bi = 0.65 V.
Fig. 11. (a) Write hole charge time evolution modeling and hole cur-
rent for silicon film thickness tSi = 14 nm and 8 nm for the classic and
quantum approaches in write conditions VD = 1.2 V, VS = 0 V, VG1 =
1.2 V, and VG2 = −1.8 V. The transistor parameters are W = 1 μm,
L = 100 nm, μ0 = μp = 200 cm2 V−1 s−1 , tox1 = 1.2 nm, tox2 = 3 nm,
VFB1 = −0.57 V, VFB2 = 0.047 V, NA = 2.1024 m−3 , τGR = 0.1 μs,
μp = μ0 = 200 cm2 V−1 s−1 , η = 1, WN = 30 nm, Wp = 7 nm, ai =
0.016 A−1 , and bi = 0.65 V.
A. Programming: State 1
State-1 cell programming time strongly depends on the hole
current resulting from impact ionization. Fig. 10 shows the
range due to the front-gate potential. Faster writing is obtained,
at a given drain voltage, for high values of the front-gate
voltage. Unfortunately, the stored charge is reduced.
Quantum effects are detailed in Fig. 11(a). The accumulated
charge decreases, and the write programming time increases
due to low impact ionization current [the hole current depends
on VG1 , VD [Fig. 11(b)], and VB (32)]. For thinner films,
quantum effects are more important. A negative impact on
memory amplitude and write time is observed.
B. Retention of State 1
State “1” over time is illustrated in Fig. 12. The diffusion
leakage current (diode) and the diffusion current with recombi-
nation phenomenon (GR) are considered. This graphic clearly
reveals recombination as the principal charge loss mechanism.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
Fig. 12. Modeled reading current during the state-1 retention phase versus
temperature for the classic approach for the following cases: pure diffusion
leakage current (diode) and diffusion current with or without the recombina-
tion phenomenon (GR). During retention, the applied potentials are given as
follows: VD = VS = VG1 = 0 V and VG2 = −1.8 V. During the reading
phase, we applied the following: VD = 0.2 V, VS = 0 V, VG1 = 1.5 V, and
VG2 = −1.8 V. The transistor parameters are given in Fig. 10.
Fig. 13. Modeled reading current during the state-1 retention phase for the
classic and quantum approaches. The applied potentials are given as follows:
VD = VS = VG1 = 0 V, with VG2 = −1.8 V. The reading conditions are
VD = 0.4 V, VS = 0 V, and VG1 = 1.2 V, with VG2 = −1.8 V. The transis-
tor parameters are given in Fig. 10.
This property is reported in many publications [21], [22].
Moreover, recombination in the thin film (IGR−th ) is several
orders of magnitude lower than recombination controlled by the
diode (IGR−dio ) [7].
Fig. 13 reveals, for tSi = 14 nm, a similar charge loss mech-
anism for the quantum and classic approaches (ΔIC = ΔIQ ).
For tSi = 8 nm, charge loss kinetic is less important. The
related area of the junction is proportional to the film thickness.
C. Erasing: State 0
The IDG 1TDRAM cell presents the advantage to manage a
selective erase operation with back-gate biasing. By increasing
the back-gate potential (cf. Fig. 14), the erase operation can be
accelerated. The shortest state-0 programming time is obtained
for the negative value of the back bias. It is an important point
to notice for design development.
Fig. 15 shows, for tSi = 14 nm, a similar charge loss
mechanism for the quantum and classic approaches. Indeed,
the erasing mechanism mainly consists of the diffusion cur-
rent in source and drain diodes, followed by recombination
PUGET et al.: MODELING THE IDG TRANSISTOR IN ACCUMULATION REGIME FOR 1TDRAM APPLICATION
Fig. 14. Modeled erase hole charge time evolution for the classic approach
for different back gate potential values. VD = VS = 0 V, and VG1 = 1.5 V.
The transistor parameters are given in Fig. 10.
Fig. 15. Modeled erase hole charge time evolution for the classic and quantum
approaches. VD = VS = 0 V, VG2 = 0 V, and VG1 = 1.2 V. The transistor
parameters are given in Fig. 10.
(ΔC1 = ΔQ1 and ΔC2 = ΔQ2 ). As for state-1 retention, the
phenomenon is independent of carrier confinement.
D. Retention of State 0
The parasitic BTBT current is of prime importance for hole
charge shift during state-0 retention. During this phase, the
thin film is negatively polarized (i.e., the diode in the forward
regime), and the back-gate potential has a negative value. The
BTBT mechanism appears at the back dielectric interfaces of
the two diodes. As shown in Fig. 16, this parasitic current
is larger than the generation one. It can be noted that the
generation current is equivalent in the thin film controlled by
the gates and the thin film controlled by the diodes. Temperature
impact on retention degradation is also shown in Fig. 16.
Quantum effects (Fig. 17) imply, for tSi = 14 nm, a different
charge loss kinetic (ΔIQ < ΔIC ). Back-interface charge con-
finement plays a major role in the BTBT phenomenon.
V. C ONCLUSION
This model concerns a 1TDRAM built on a 14-nm silicon
film. In this paper, memory operations have been described, and
data retention mechanisms have been involved. The low-bias
operations considered are related to thin oxide thicknesses for
the front and bottom gate oxide.
863
Fig. 16. Modeled reading current during the state-0 retention phase versus
temperature for the classic approach, considering the diffusion and generation
leakage current (diode + GR) with or without BTBT. During retention, the
applied potentials are given as follows: VD = VS = VG1 = 0 V and VG2 =
−1.8 V. During the reading phase, we applied VD = 0.2 V, VS = 0 V, VG1 =
1.5 V, and VG2 = −1.8 V. The transistor parameters are given in Fig. 10:
Agidl = 4.4 × 108 V−1 m, Bgidl = 3.6 MVm−1 , and Cgidl = 17 V3 .
Fig. 17. Modeled reading current during the state-0 retention phase for the
classic and quantum approaches. The applied potentials are VD = VS =
VG1 = 0 V, with VG2 = −1.8 V; the reading conditions are VD = 0.4 V,
VS = 0 V, and VG1 = 1.2 V, with VG2 = −1.8 V. The transistor parameters
are given in Fig. 10.
The programming mechanisms are, for state 1, the hole
current generated by impact ionization and, for state 0, the
diode recombination current.
The data retention mechanisms are driven by, for state 1, the
diode recombination current and, for state 0, the BTBT and the
diode generation current.
Simulated data retention results are in accordance with re-
cently presented works [23].
R EFERENCES
[1] Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic
drain–current model for DG MOSFETs,” IEEE Electron Device Lett.,
vol. 25, no. 2, pp. 107–109, Feb. 2004.
[2] D. Munteanu, J.-L. Autran, X. Loussier, S. Harrison, R. Cerutti, and
T. Skotnicki, “Quantum short-channel compact modeling of drain–current
in double-gate MOSFET,” Solid State Electron., vol. 50, no. 4, pp. 680–
686, Apr. 2006.
[3] X. J. Xi, J. He, M. Dunga, H. Wan, M. Chan, C.-H. Lin, B. Heydari,
A. M. Niknejad, and C. Hu, “BSIM5 MOSFET model,” in Proc. 7th Int.
Conf. Solid-State Integr. Circuits Technol., 2004, vol. 2, pp. 920–923.
[4] M. Reyboz, O. Rouzeau, T. Poiroux, P. Martin, and J. Jomaah, “An
explicit analytical charge-based model of undoped independent double
gate MOSFET,” Solid State Electron., vol. 50, no. 7/8, pp. 1276–1282,
Jul./Aug. 2006.
[5] Sentaurus Work Bench SWB. [Online]. Available: http://www.synopsys.
com/TOOLS/TCAD/Pages/Framework.aspx
864
[6] S. M. Sze, “Physics of semiconductor devices,” in VLSI Technology,
2nd ed. New York: Wiley, 1988.
[7] R. Ranica, “Architecture DRAM innovantes pour les applications CMOS
embarquées à haute densité d’intégration,” Ph.D. thesis, Université de
Provence, Marseille, France, Oct. 27, 2005.
[8] S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata, and G. Ghibaudo,
“Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and
coupling effects,” Solid State Electron., vol. 51, no. 2, pp. 239–244,
Feb. 2007.
[9] M. Ferrier, R. Clerc, L. Lucci, G. Ghibaudo, A. Vandooren, and F. Boeuf,
“Saturation drain current analytical modeling of single gate fully depleted
SOI or SON MOSFETs in the quasi ballistic regime of transport,” in Proc.
IEEE Int. SOI Conf., 2006, pp. 91–92.
[10] D. Rideau, M. Feraille, M. Michaillat, Y. M. Niquet, C. Tavernier, and
H. Jaouen, “On the validity of the effective mass approximation and
the Luttinger k.p model in fully depleted SOI MOSFETs,” Solid State
Electron., vol. 53, no. 4, pp. 452–461, Apr. 2009.
[11] M. J. van Dort, P. H. Woerlee, and A. J. Walker, “A simple model for
quantisation effects in heavily doped silicon MOSFETs at inversion con-
ditions,” Solid State Electron., vol. 37, no. 3, pp. 411–414, Mar. 1994.
[12] H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of
metal-oxide (insulator)-semiconductor transistors,” Solid State Electron.,
vol. 9, no. 10, pp. 927–937, Oct. 1966.
[13] E. P. Ver Ploeg, C. T. Nguyen, S. S. Wong, and J. D. Plummer, “Parasitic
bipolar gain in fully depleted n-channel SOI MOSFETs,” IEEE Trans.
Electron Devices, vol. 41, no. 6, pp. 970–977, Jun. 1994.
[14] S. Tam, P.-K. Ko, and C. Hu, “Lucky electron model of channel
hot electron injection in MOSFETs,” IEEE Trans. Electron Devices,
vol. ED-31, no. 9, pp. 1116–1125, Sep. 1984.
[15] R. Laffont, P. Masson, S. Bernardini, R. Bouchakour, and J. M. Mirabel,
“A new floating compact model applied to flash memory cell,” J. Non-
Crystalline Solids, vol. 322, no. 1–3, pp. 250–255, Jul. 2003.
[16] P. Flatresse, “Etude du comportement physique et électrique de dispositifs
0.2 μm en technologie silicium sur isolant,” Ph.D. thesis, Institut National
Polytechnique de Grenoble, Grenoble, France, Mar. 1992.
[17] A. Villaret, R. Ranica, P. Malinge, P. Masson, P. Mazoyer, P. Candelier,
and T. Skotnicki, “Further insight on the modeling and characterization of
triple-well capacitorless DRAMs,” IEEE Trans. Electron Devices, vol. 52,
no. 11, pp. 2447–2454, Nov. 2005.
[18] J. Chen, T. Y. Chan, I. C. Chen, and P. K. Ko, “Subbreakdown drain
leakage current in MOSFET,” IEEE Electron Device Lett., vol. ED-8,
no. 11, pp. 515–517, Nov. 1987.
[19] W. Liu, MOSFET Models for SPICE Simulation Including BSIM3v3 and
BSIM4. New York: Wiley-Interscience, 2001.
[20] L. Lopez, P. Masson, D. Née, and R. Bouchakour, “Temperature and drain
voltage dependence of gate induce drain leakage,” Microelectron. Eng.,
vol. 72, no. 1–4, pp. 101–105, Apr. 2004.
[21] D.-I. Bae, S. Kim, and Y.-K. Choi, “Retention mechanism in double-gate
1 T capacitorless DRAM by using PiFet structure,” in Proc. IEEE Silicon
Nano Workshop, 2007, pp. 75–76.
[22] N. Z. Butt and M. A. Alam, “Scaling limits of double-gate and surround-
gate Z-RAM cells,” IEEE Trans. Electron Devices, vol. 54, no. 9,
pp. 2255–2262, Sep. 2007.
[23] I. Ban, U. E. Avci, U. Shah, C. E. Barns, D. L. Kencke, and P. Chang,
“Floating body cell with independently-controlled double gates for high
density memory,” in IEDM Tech. Dig., 2006, pp. 21–25.
Sophie Puget was born in Castelnaudary, France,
in 1982. She received the M.S. degree in nanotech-
nologies from the University of Marseille, Marseille,
France, the Engineer degree in microelectronics from
the Ecole Polytechnique Universitaire de Marseille,
Marseille, in 2006, and the Ph.D. degree in micro-
electronics from the University of Marseille, in 2009.
After her Ph.D. degree on the fabrication and
characterization of advanced dynamic random-
access memory (DRAM) units such as capacitorless
eDRAMs, she joined STMicroelectronics, Crolles,
France.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 4, APRIL 2010
Germain Bossu was born in Cambrai, France, in
1982. He received the Engineer degree in physics and
material science, the M.S. degree in microelectronics
from the Institut National des Sciences Appliquées
de Lyon, Villeurbanne, France, in 2005, and the
Ph.D. degree in microelectronics from the Université
de Provence, Marseille, France, in 2009.
After his Ph.D. degree on fabrication, character-
ization, and modeling of advanced thin-film non-
volatile memory solutions built on capacitorless
eDRAMs platforms, he joined Dolphin Integration,
Meylan, France, to design standard.
Pascal Masson was born in France in 1969. He
received the M.Sc.E.E. degree from the National
Polytechnic Institute of Grenoble (INPG), Grenoble,
France, in 1996 and the Ph.D. degree in micro-
electronics from the National Institute of Applied
Sciences (INSA) of Lyon, Villeurbanne, France,
in 1999.
From 2000 to 2001, he was an Assistant Profes-
sor with the INSA of Lyon, where he worked on
traps study in the gate dielectric of deep-sub-0.1-μm
MOS transistors. From 2001 to 2007, he was an
Assistant Professor and then a Full Professor with the Provence Materials
and Microelectronics Laboratory (L2MP), Marseille, France. In the “Memories
team,” he was heading the “New Memories on Silicon” (MISSi) Group. He is
currently with the Electronics Antennas and Telecommunications Laboratory
(LEAT), Université de Nice-Sophia Antipolis, Valbonne, France, w working
on modeling and characterization of advanced memories, such as 1TDRAM,
nanocrystal Flash, and single-poly Flash.
Pascale Mazoyer was born in Nîmes, France. She
received the B.S. and M.S. degrees in fundamentals
of physics and the Ph.D. degree from Joseph Fourier
University, Grenoble, France.
After her Ph.D. degree on nonvolatile memory
reliability within CEA LETI, she joined STMicro-
electronics, Crolles, France, in 1994. She has been
responsible for technological process developments
addressing successively bipolar integration, high-
density plasma etching, and eDRAM and HK dielec-
tric material evaluations. Her current position is on
the development of embedded volatile and nonvolatile memories that are com-
patible with the advanced CMOS technological platform. She is a cofounder of
the international memory workshop www.ewh.ieee.org/soc/eds/imw.
Rossella Ranica was born in Ivrea, Italy, in 1978.
She received the B.S. and M.S. degrees in material
engineering from Politecnico of Torino, Torino, Italy,
in 2002, and the B.S. and M.S. degrees in micro-
electronics from the Institut National Polytechnique
de Grenoble, France, in 2002, and the Ph.D. degree
in microelectronics from the University of Marseille,
Marseille, France, in 2004.
After her Ph.D. degree on fabrication and char-
acterization of advanced DRAM memories such as
capacitorless eDRAMs, she joined STMicroelec-
tronics, Crolles, France.
Alexandre Villaret was born in France in 1978.
He received the M.S. degree in physics engineering
from the Ecole Nationale Supérieure de Physique
de Grenoble (ENSPG), Grenoble, France, in 2000
and the Ph.D. degree in microelectronics from the
Institut National Polytechnique de Grenoble (INPG),
Grenoble, in 2004.
After his Ph D degree on integration, modeling,
and characterization of innovative memory devices
such as 1T-DRAMs and other alternative architec-
tures, he joined STMicrolectronics, Crolles, France.
PUGET et al.: MODELING THE IDG TRANSISTOR IN ACCUMULATION REGIME FOR 1TDRAM APPLICATION
Philippe Lorenzini was born in France in 1964.
He received the Ph.D. degree in physics and con-
densed matter from the University of Montpellier,
Montpellier, France, in 1992.
From 1993 to 2005, he was an Assistant
Professor with the Polytech’Nice Sophia Engi-
neer School, Université de Nice-Sophia Antipolis,
Valbonne, France, where his main research activ-
ities were electrical characterization and modeling
of III–V semiconductors and HEMT transistors with
the CRHEA-CNRS Laboratory. Since 2006, he has
been a Professor with the Antenna and Microelectronics Laboratory (LEAT),
Université de Nice-Sophia Antipolis, in the “Integrated Antenna and Microelec-
tronics Team.” He is currently working on the modeling and characterization
of advanced memories, such as 1TDRAMs on silicon and silicon-on-insulator
materials.
Jean-Michel Portal received the M.S. (Electrical
Engineering) degree in 1995 and the Ph.D. (Elec-
trical Engineering) degree in 1999, both from the
University of Montpellier, Montpellier, France.
He is currently a Professor with the Institute
of Materials, Microelectronics and Nanosciences
of Provence (IM2NP), Université de Marseille,
Marseille, France, where he is a member of the
Memory Team. His research interests include test-
chip design for process monitoring, DFM, memory
model, design and test.
Denis Rideau received the M.S. degree from the
École Supérieure d’Ingénieurs en Électronique et
Électrotechnique (ESIEE), Paris, France, in 1996
and the Ph.D. degree from the Université Paris-Sud,
Orsay, France, in 2001.
Since 2001, he has been with the Compact and
Technology Modelling Group, STMicroelectronics,
Crolles, France, studying RF devices, including
quantum effects, influence of mechanical strain, and
crystallographic orientation.
Gérard Ghibaudo was born in France in 1954. He
received the Engineer degree in Physics, the Ph.D.
degree in electronics, and the State Thesis degree in
physics from Grenoble Institute of Technology and
University of Grenoble, France, in 1979, 1981, and
1984, respectively.
In 1981, he became an Associate Researcher with
CNRS, where he is currently the Director of Re-
search, and the Director of the IMEP-LAHC Lab-
oratory, MINATEC–INPG, Grenoble. During the
academic year 1987–1988, he spent a sabbatical year
at the Naval Research Laboratory, Washington, DC, where he worked on the
characterization of MOSFETs. He is a member of the Editorial Board of
Solid State Electronics and an Associate Editor for Microelectronics Reliability
Journals. He has supervised more than 50 Ph.D. students in his career. He has
been involved in several European research projects (joint coordinator of BRA-
NOISE; participant to APBB, ADEQUAT 1-2-+, PROPHECY, ADAMANT,
NANOCMOS, PULLNANO, FOREMOST, HONEY, and MODERN; etc.)
or national programs (coordinator of RMNT-Ultimox, participant to RMNT-
CMOS-DALI or ANR multigate projects, etc.). During his career, he has
been the author or coauthor of more than 286 articles in international refer-
eed journals, 483 communications, 55 invited presentations in international
conferences, and 21 book chapters. His research interests include electronics
transport, oxidation of silicon, MOS device physics, fluctuations and low-
frequency noise, and dielectric reliability.
Dr. Ghibaudo has been a member of several technical/scientific commit-
tees of international conferences (ESSDERC, WOLTE, ICMTS 1996–2004,
MIEL, ESREF, SISC 1996–2000, MIGAS, ULIS, IEEE/IPFA, ICMTD, FaN
2006, ICNF 2005–present etc.). He was a cofounder of the First European
Workshop on Low Temperature Electronics (WOLTE 94) and an organizer of
14 workshops/summer schools during the last 15 years.
865
Rachid Bouchakour received the M.S. and Ph.D.
degrees in physics from the University of Paris, Paris,
France, in 1983 and 1987, respectively.
He became a Professor with the Université
de Provence Aix-Marseille I, Marseille, France,
in 1998, where he is currently the Director of
the Institute of Materials, Microelectronics and
Nanosciences of Provence (IM2NP). His research
interests include microelectronic and nanoelectronic
device modeling, reliability, and memory develop-
ment. During his career, he has been the author or
coauthor of more than 124 publications and two book chapters.
Gilles Jacquemod received the M.Sc. degree in
microelectronics engineering from the Institute of
Industrial Chemistry and Physical Science (ICPI)
Lyon, Lyon, France, the M.Sc. degree (DEA) from
the Ecole Centrale de Lyon, Ecully, France, in 1986,
and the Ph.D. degree from the Institut National des
Sciences Appliquées de Lyon, Villeurbanne, France,
in 1989.
From 1990 to 2000, he was an Associate Professor
with LEOM, Ecole Centrale de Lyon. In 2000, he
joined the Electronics Antennas and Telecommuni-
cations Laboratory (LEAT) and the Ecole Polytechnique, Université de Nice-
Sophia Antipolis, Valbonne, France, as a Full Professor. His research interests
include analog and integrated circuit design and behavioral modeling of mixed
domain systems, and RF design applied to wireless communications.
Thomas Skotnicki (M’91–SM’01) received the
M.S. and Engineer degrees from the Warsaw Tech-
nical University, Warsaw, Poland, in 1979, the Ph.D.
degree from the Institute of Electron Technology,
Warsaw, in 1985, and the Habilitated for Directing
Research diploma from the Institut National Poly-
technique de Grenoble, Grenoble, France, in 1993.
From 1985 to 1999, he was with France Telecom
R&D (CNET-National Center for Telecommunica-
tion Studies), Grenoble. Since 1999, he has been
with STMicroelectronics, Crolles, France, where he
is currently a Fellow and the Director of the Advanced Devices Program.
The current focus of his program at STMicroelectronics is on low power/low
variability for 32-nm and beyond CMOS, innovative device architectures, new
memory concepts and cells, and the integration of new materials for CMOS.
In 2006, he received the title of Professor (life title) from the President of
Poland. He is the Inventor or Coinventor of the voltage-doping transformation
technique and MASTAR models (MASTAR has been used to calculate the
ITRS 2003, 2005, and, currently, 2007 roadmaps), silicon devices showing
large dynamic negative resistance at room temperature, the silicon-on-nothing
(SON) technology (was given the Rappaport Award for the best IEEE EDS
publication of the year in 2000), capacitorless bulk DRAM cell, totally silicided
metallic gate technology (currently known under the name FUSI), double-gate
SON technology, dielectric pockets technology (awarded ESSDERC 2000 Best
Paper), etc. He is the holder of about 50 patents on new devices, circuits, and
technologies. He has presented more than 50 invited papers and short course
lectures and is the author or coauthor of about 250 scientific papers (review
based), one book, and several book chapters in the field of CMOS devices and
circuits.
Dr. Skotnicki is a Senior Member of SEE. From 2001 to 2007, he was Editor
for the IEEE T RANSACTIONS ON E LECTRON D EVICES. He has served on
numerous conference committees (IEDM, VLSI, ESSDERC, ECS, SNW, and
IWJT) and on several prestigious academic advisory boards.