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Abstract—PSP and the backward propagation of variance two different manufacturers. These results are verified using
(BPV) method are used to characterize the statistical variations Monte-Carlo simulations.
of metal-oxide-semiconductor field effect transistors (MOSFETs).
Compared to previous applications [7]–[9] of the BPV
BPV statistical modeling of NMOS and PMOS devices is, for the
first time, coupled by including self-consistent modeling of ring method, this paper introduces two new developments. First,
oscillator gate delays. Parasitic capacitances are included in the characterization of NMOS and PMOS devices is coupled.
analysis. The proposed technique is validated using Monte-Carlo Traditionally NMOS and PMOS transistors are statistically
simulations and by comparison to experimental data from two characterized separately. This does not guarantee accurate
technologies.
statistical modeling of circuit performances that depend on
Index Terms—Backward propagation of variance, PSP model, both NMOS and PMOS devices. In this paper, RO delay
statistical modeling. is included as a circuit level performance to be modeled,
which couples to, and is strongly correlated with, the char-
I. Introduction acteristics of both NMOS and PMOS devices [10]–[12].
Thus, in contrast to earlier work, our approach combines
TATISTICAL modeling is critical to the design of mod-
S ern integrated circuits (ICs) to ensure high product
yield [1]–[4]. The surface-potential based PSP metal-oxide-
electrical measurements both of individual device character-
istics and of circuit performance to develop a unified and
practical way to characterize the variations in circuit delays.
semiconductor field effect transistors (MOSFET) model [5],
We also found that it can be difficult to model statistical
[6] provides a unique and simple capability to physically
variations accurately over all biases by BPV fitting of electrical
link fluctuations in device electrical performances to vari-
performances at only one DC bias. The situation can be
ations in a small number of fundamental process parame-
improved by including electrical performances over bias as
ters. This is in contrast to MOSFET models that are based
statistical modeling targets. This can be easily achieved with
on a large number of empirical parameters, for which data
our proposed procedure. For instance, in our experiment the
driven numerical procedures are often required for statistical
variation of RO delay versus supply voltage was successfully
modeling.
fitted by targeting not just the variance of the saturated drain
This paper presents a unified and extendable method to
current at maximum gate bias but by (least squares) fitting
extract the statistics of PSP parameters directly from electrical
the additional drain current variances at several gate biases
test (ET) data. The procedure leverages the physical nature of
(with minimal loss in accuracy of modeling at the highest
the PSP model and uses backward propagation of variance
gate bias).
(BPV) method [7]–[9]. The BPV procedure is expanded to
The second new feature of the present investigation is that
characterize circuit performances as well as individual NMOS
the process parameters are selected directly from the parameter
and PMOS transistor performance.
list of the PSP model. Due to limited physical content in
We compare results of our procedure against ET data that
some older compact MOSFET models, mappings have to be
includes DC, capacitance, and ring oscillator (RO) gate delay
set up to link the process parameters and the actual compact
measurements from two 0.18 µm CMOS technologies from
model parameters. In PSP several of the model parameters
Manuscript received February 27, 2008; revised November 25, 2008 and (e.g., TOXO, VFBO, NSUBO) have direct relations to process
July 9, 2009. Current version published March 19, 2010. This work was variations and no external mappings need to be introduced for
supported in part by the Semiconductor Research Corporation, under Contract
no. 2006-VJ-1450. This paper was recommended by Associate Editor, M. statistical modeling.
Orshansky. We note that the method described in this paper is applied
X. Li is with Arizona State University, Tempe, AZ 85281 USA. He to characterize the global (geometry-independent) component
is now with GLOBALFOUNDRIES, Sunnyvale, CA 94085 USA (e-mail:
xin1.li@globalfoundries.com). of variation; the reason we present results from 0.18 µm
C. C. McAndrew is with Freescale Semiconductor, Tempe, AZ 85284 USA technologies is because for these technologies global varia-
(e-mail: rp3881@freescale.com). tion dominates the mismatch (or local, geometry-dependent)
W. Wu and G. Gildenblat are with Arizona State University, Tempe, AZ
85281 USA (e-mail: weimin.wu@asu.edu; gennady.gildenblat@asu.edu). component of variation. For more advanced technologies,
S. Chaudhry is with Jazz Semiconductor, Newport Beach, CA 92660 USA where mismatch becomes more important, one can extract
(e-mail: samir.chaudhry@jazzsemi.com). the mismatch and global variations in subsequent steps [8].
J. Victory is with Sentinel IC Technologies, Irvine, CA 92651 USA (e-mail:
james@sentinel-ic.com). First, mismatch variation is characterized based on mismatch
Digital Object Identifier 10.1109/TCAD.2010.2042892 measurements [9]. Then the global variation is obtained by
0278-0070/$26.00
c 2010 IEEE
600 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
subtracting the mismatch variation from the total observed For m electrical performances and n process parameters
fluctuations in each electrical performance (treated as model parameters), this results in an m × n linear
system
2
σei,global 2
= σei,total − σei,local
2
. (1)
σe2 = Sσp2 (5)
The extraction of global variation then proceeds as described
in the following sections. where
T
σe2 = σe21 , σe22 , . . . , σe2m (6)
II. Method
Much work has been devoted to investigate the nature of
T
process variations and their effects on the performances of σp2 = σp21 , σp22 , . . . , σp2n (7)
the individual MOS transistors [13]–[15]. For MOSFETs, the
process variations that impact circuit functionality the most and the sensitivity matrix is
are oxide thickness (Tox ), effective channel length (Leff ) and 2
width (Weff ), flatband voltage (Vfb ), and substrate doping ∂ei
(Nsub ). Variations in these process parameters affect electrical S= . (8)
∂pj
performances such as threshold voltage (Vth ), saturated drain i=1,2,...,m; j=1,2,...,n
current (Idsat ), gain factor (β = µ0 Cox W/L) and gate delay For m = n the variances of each process parameter can be
(td ). Although it is important to understand the physics and found by directly solving (5). A least squares fit is used when
mechanisms that cause variations in device characteristics, m > n. Note that for some process parameters and figures of
the ultimate goal of statistical modeling is to accurately merit the variations are normalized to percentage values; for
represent variations of circuit performances. Hence, extract- clarity and convenience of notation variations are expressed
ing the variations of the process parameters from wafer- here in absolute terms.
level data via a physical compact model (i.e., using the
BPV method) is a natural approach for statistical modeling
[7], [8]. III. Experiment
Let ei (i = 1, 2, . . . , m) be measures of electrical per- The method described in the previous section was applied
formance (i.e., Vth , Idsat , etc.) for a MOSFET and pj (j = to two 0.18 µm CMOS technologies. The ET data was taken
1, 2, . . . , n) be process parameters (e.g., Tox , Leff , etc.). Taylor from scribe grid process control (SGPC) monitors located
expansion of ei in the neighborhood of p̄ = (p̄1 , p̄2 , . . . , p̄n ) between dice throughout the wafers. Various test structures
gives were available, including several geometries of MOSFETs,
diodes, and capacitors, some mismatch structures, and some
n
ei ≈ ei (p̄) + si,j (pj − p̄j ) (2) ring oscillators. These enable monitoring and characterization
j=1
of the statistical variations of the process. The number of de-
vices measured from the sample wafers was: 448 MOSFETs,
and sensitivity analysis yields 112 oxide capacitance structures, 112 diodes, and 56 ring
oscillators. These sample sizes are sufficient to characterize
n
the statistical variations and correlations of the electrical
σe2i = 2 2
si,j σpj (3)
j
performances.
where The DC currents of the MOSFETs and the capacitances
of the junctions were measured on a standard probe station.
∂ei (p) Figures of merit that affect digital circuit performance were
si,j = |p=p̄ (4) selected as key quantities and were extracted from the raw
∂pj
data. For example, the saturated drain current of a short
and σe2i and σp2j are the variances for ei and pj , respectively. channel device is highly correlated with the switching speed
There are two assumptions that underlie (2): that the process of digital circuits. Hence, it is chosen as one of the ei in (2).
parameters are independent; and that the variations in the The selections of all ei for both types of devices are listed
parameters should be small so that the electrical performances in Table I. The PSP model parameters used for statistical
are well approximated as linear functions of process param- modeling are listed in Table II. Note that in our experiment,
eters. Parameter correlations can be handled by decomposing the body effect was not characterized and its dependence on
them into physical combinations of common and independent NSUB is weaker than on Tox , so we did not include NSUB
components, to provide a completely independent set of mod- as a process parameter. Rather, Vth at zero body bias was
eling parameters [16]. An extension to handle nonlinearities modeled through the flatband voltage VFBO. Note also that
in the ei (p) mappings is reviewed in Section V, but as our length dependent threshold voltage (VFBL) is an independent
results below show, this is not important for the devices we parameter to model the variation of VFB for short channel
analyze. devices, in addition to the effect of channel length variations
LI et al.: STATISTICAL MODELING WITH THE PSP MOSFET MODEL 601
⎡ 2 ⎤ ⎡ 2 2 ⎤
∂Vtr(N) ∂Vtr(N)
−
σV2tr(N)
∂Vtr(N) 2
σTOXO . . . ⎡ 2 ⎤
⎥ ⎢ ⎥ σVFBO(N)
∂VFBO(N) ∂LAP(N)
⎢ ∂TOXO
⎢ ⎥ ⎢ . . . . . . . . . . . . . . . . . . . . ........ 0 ⎥
⎢
. . .
2 ⎥ ⎢
⎢ ∂Ids(N) 2 2 ⎥⎢
⎥⎢ ... ⎥
⎥
⎢ 2 ⎥
⎥ ⎢ ⎥⎢ ⎥
∂Ids(N)
⎢σIds(N) − ∂TOXO σTOXO
∂Ids(N) 2 . . .
⎢ ⎥ ⎢ ∂VFBO(N) ∂LAP(N)
2 2 ⎥ ⎢ σ2 ⎥
⎢ 2 ⎥ ⎢
⎢
⎥
⎥
⎢
⎢
LAP(N) ⎥
⎥
⎢σ 2 − ∂V tr(P) 2
σTOXO ⎥=⎢ ∂Vtr(P)
...
∂Vtr(P)
⎥ ⎢σ 2 ⎥ (9)
⎢ Vtr(P) ∂TOXO ⎥ ⎢ ∂VFBO(P) ∂LAP(P)
⎥ ⎢ VFBO(P) ⎥
⎢ ⎥ ⎢ 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .⎥ ⎢ ⎥
⎢ ... ⎥ ⎢ 2 2 ⎥ ⎢ . . . ⎥
⎢ 2 ⎥ ⎢ ⎥ ⎣ ⎦
⎢ 2 ⎥ ∂Ids(P) ∂Ids(P)
⎦ ⎢ ⎥
∂Ids(P)
⎣σIds(P) − ∂TOXO σTOXO 2
⎣
... 2
2 ⎦ σLAP(P)
∂VFBO(P) ∂LAP(P)
2
2 2 2
σt2d − ∂TOXO
∂td 2
σTOXO ∂td
∂VFBO(N)
. . . ∂td
∂LAP(N)
∂td
∂VFBO(P)
... ∂td
∂LAP(P)
TABLE I TABLE II
Electrical Performance List PSP Model Parameters List
(LAP) (which also affects the gain factor). Vfb can in theory For example, LAP are key factors that are responsible for
vary with Tox through the effective interface charge; however, the variation of characteristics for short channel devices. They
this has been negligible in semiconductor processes for a long have a strong influence on both the saturation currents and the
time. The assumption of independence in the parameters is not gate delay of the ROs. Adding the RO delay into the equations
violated. ensures that the extracted statistics for Leff (and in fact for
The gate delays of ROs (fanout = 3) were also measured. all selected process parameters) are balanced for NMOS and
The inclusion of load capacitances implemented using MOS PMOS devices and, more importantly, the correct distribution
transistors with connected source and drain minimizes the for RO delay is reproduced because of the self-consistent way
relative contribution of the interconnect capacitance to the in which we solve the system. As suggested in [8] TOXO is
statistical variation of the propagation delay. The selection taken as a forward propagation of variance (FPV) parameter
of the process parameters for PSP is made in such way that since it is separately monitored and it affects all of the device
their perturbations are observable in the selected electrical and circuit performances. More important, it is assumed to be
performances. fully correlated between NMOS and PMOS, which is a good
A complete global PSP parameter set [5], [6] including approximation for the technologies we investigate. Also note
junction parameters [17] was extracted as a nominal parameter that in (9) the matrix does not have to be square. For exam-
set. Then, a system of linear equations was set up as shown ple, an over-determined system can be solved using a least
in (9) and solved. This system takes into account both types squares fit.
of devices and the RO circuits. The type of device (N or P) The sensitivity matrix S is calculated from numerical SPICE
for the parameters and electrical performances is indicated in simulations of the variations in ei caused by perturbations
accompanying parentheses in (9). The parameter with no type in pj around their nominal values. The magnitude of the
noted (i.e., TOXO in this case) is fully correlated between perturbations is ±3σpj , and as the σpj are not known before
NMOS and PMOS. Note that the sensitivities for the NMOS (9) is solved estimates of the σpj are used initially. Then σp2 are
and PMOS process parameters and electrical performances computed by solving the m linear equations in the n unknowns.
form a block diagonal matrix and the RO delay couples the Subsequently the sensitivity matrix is updated based on ±3σ
NMOS and PMOS parameters. The performances of NMOS perturbations using the new values for σp and the process is
and PMOS are correlated together via global variations such iterated until the σp2 values converge. Because the variations
as Tox . The correlation of individual device characteristics in in the electrical performances are close to linear functions of
turn affects the circuit performance. For example, positively the process parameters, the solution procedure converges in a
correlated saturation currents (Idsat ) of NMOS and PMOS few iterations. There are two reasons to evaluate sensitivities
cause the distribution of the RO delay to spread because they iteratively. The first is to make sure they are self-consistent,
cause variations in the delay to move in the same direction. as this was done in the original BPV for other models. The
The variances of selected process parameters are automatically second, and more important, is to make sure that the model
balanced by adding the coupling performance, i.e., RO delay. is evaluated over the whole ±3σ range. Sometimes a model
602 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
TABLE V
Standard Deviations Extracted for Junction Capacitances
NMOS PMOS
pj Nominal 1σ Nominal 1σ (Unit
CJORBOT 1.344 0.033 1.37 0.010 mF/m2
TABLE VI
Standard Deviations of the Monte-Carlo Simulation Results
for RO Delay Compared With Those of Measurements
TABLE VII
Device Contribution for the Gate Delay
NMOS PMOS
UO LAP UO LAP
Contributions 7% 16% 20% 51%
Fig. 5. Simulated standard deviations for the saturation currents for various
gate biases compared with the measurements.
TABLE VIII modeling presented here shows that accurate statistical mod-
Standard Deviations of the Monte-Carlo Simulation Results eling with a small number of statistical parameters is enabled
Using Additional Electrical Performances (cf. Table IV) by the strong physical basis of the PSP model. We also show
that overall statistical modeling accuracy can be improved, at
NMOS PMOS the expense of some loss in accuracy of ‘point’ modeling, by
ei Meas. Sim. Meas. Sim. Unit using an over-determined formulation, i.e., by including more
Large Vtr 3.9 4.0 3.5 3.4 mV electrical performances to fit than process parameters used for
Short Vts 14.5 16.4 12.7 17.8 mV
modeling.
Ids 2.13 2.33 3.37 3.33 %
Narrow Vtn 16.8 17.0 8.3 8.2 mV
Small Vtm 26.0 26.1 21.6 22.2 mV Acknowledgment
Idm 4.28 4.26 5.98 6.10 %
The authors are grateful to Y.-B. Park, I.-S. Lim,
V. Discussion on Modeling Nonlinearity A. Zlotnicka, D. Bush, C. MacKenzie, and W. Brown,
of Freescale Semiconductor, for their expertise, help with
One underlying assumption in our method is that the vari- lab measurements and characterization, and to I. To and
ations in the electrical performances can be approximated as D. Morgan, of Freescale Semiconductor, for their providing
linear functions of process parameters [see (3)]. A quadratic the sample wafers and technical documentations.
version of the BPV method [18] can be used when the
variations of the process parameters are large and it becomes
necessary to model the nonlinearity. Instead of (2), a second References
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606 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 4, APRIL 2010
[17] A. J. Scholten, G. D. J. Smit, M. Durand, R. van Langevelde, James Victory (M’90–SM’01) received the B.S.,
and D. B. M. Klaassen, “The physical background of JUNCAP2,” IEEE M.S., and Ph.D. degrees in electrical engineering
Trans. Electron Dev., vol. 53, no. 9, pp. 2098–2107, Sep. 2006. from Arizona State University, Tempe, in 1990,
[18] I. Stevanović and C. C. McAndrew, “Quadratic backward propagation of 1992, and 1994, respectively.
variance (QBPV) for nonlinear statistical circuit modeling,” IEEE Trans. From 1992 to 1997, he was the Principal Mem-
Comput.-Aided Design, vol. 28, no. 9, pp. 1428–1432, Sep. 2009, see ber of the Technical Staff, specializing in semi-
also Erratum, vol. 28, no. 12, p. 1896, Dec. 2009. conductor device modeling for circuit simulation
of radio frequency (RF) analog and power tech-
nologies. In 1997, he managed the ramp-up of an
Xin Li received the B.S. degree in electrical engi- RF-semiconductor characterization and modeling lab
neering from Huazhong University of Science and for Motorola’s European IC Design Center, Geneva,
Technology, Wuhan, China, in 2001, and the M.S. Switzerland. He held positions with the semiconductor product sector of
degree in electrical engineering from the Pennsyl- Motorola from 1992 to 2001. From 2001 to 2003, he was the Director
vania State University, University Park, in 2006. of Semiconductor Technology with ultrawide-band startup XtremeSpectrum,
He is currently working toward the Ph.D. degree and a key contributor to the industry first UWB chipsets. From 2003 to
in electrical engineering from the Arizona State 2008, he had been a Modeling Manager, and then Executive Director of IC
University, Tempe. Design Enablement with Jazz Semiconductor, Newport Beach, CA. In 2008,
Since 2009, he has been with GLOBAL- he cofounded Sentinel IC Technologies, Irvine, CA, to develop and deliver
FOUNDRIES, Sunnyvale, CA, where he works on innovative design enablement solutions to the greater semiconductor design
compact modeling for circuit simulation. His current and manufacturing industry. He has over 30 publications, including invited
research interests include device compact modeling and statistical modeling. papers and workshop tutorials on semiconductor device modeling and design
enablement for power and RF applications.