Department of Electrical and Electronics Engineering

Reg. No. :

MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL

(A Constituent Institute of Manipal University, Manipal)

FIFTH SEMESTER B.E. DEGREE MAKEUP EXAMINATION

(REVISED CREDIT SYSTEM)
31 July 2009
DIGITAL SYSTEM DESIGN (ELE 311)
Time: 3 hours Max. Marks: 50
Note : Answer any FIVE full questions. Missing data, if any, may be suitably assumed.

1A. Explain the steps involved in the fabrication of an integrated chip. (04)
1B. Explain the programming technologies used to make the FPGAs field programmable.
(06)
2A. Write a VHDL code for implementing 8:1 Mux using “with select” construct. (04)
2B. Define IEEE std-ulogic and std-logic data types (04)
2C. Write a VHDL function to determine the maximum of two input integer number. (02)

3A. Differentiate between function and procedure in VHDL with one example program. (04)
3B. Write a behavioral VHDL model for a 4-bit adder module and hence design a 16 bit adder
by instantiating 4- four bit adder modules and connecting them as a ripple carry adder
(structural Description). (06)

4A. A sequence recognizer has a single input X and a single output Z. The output variable Z
will be asserted if it detects a sequence of two 1’s followed by 3 bits in which only one bit
is 1. (i.e. we want to detect the sequences 11001, 11010, and 11100 in a continuous data
stream). Draw the minimal state diagram and write a VHDL code to implement it. (07)
4B. Write a VHDL code for detecting a prime number for a 4 bit data input. (03)

5A. Draw a block diagram and write a VHDL description of an 8-bit bidirectional shift
register that uses two 74194s as components. The parallel inputs and outputs to the
8-bit register should be X (7 downto 0) and Y (7 downto 0). The serial inputs should be
RSD and LSD. (04)
5B. Write a VHDL code to design a 2 to 4 decoder with active low enable and active high
output using behavioral modeling. (06)

6A. Sketch the basic block diagram of Xininx Spartan IIE FPGA and briefly explain the major
configurable elements. (06)
6B. Realize six bit prime number detector using Spartan IIE FPGA. How many CLBs are
required for the implementation? (04)