Module 1

Basic Structure of computers–functional unitsbasic operational concepts –bus structures –

software. Memory locations and addresses – memory operations – instructions and instruction
sequencing – addressing modes – ARM Example (programs not required). Basic I/O operations
– stacks subroutine calls.

Computer Architecture - is the design of computers, including their instruction sets,

hardware components, and system organization.

Most computers follow the Von Neumann Architecture, also known as Stored Program
Architecture or the Fetch-Decode-Execute Architecture. It simply means that programs
(together with data) are stored in main memory during execution.

Computer architecture refers to those attributes of a system visible to a programmer, or put

another way, those attributes that have a direct impact on the logical execution of a program.
Computer organization refers to the operational units and their interconnection that realize the
architecture specification.

Examples of architecture attributes include the instruction set, the number of bit to represent
various data types (e.g.., numbers, and characters), I/O mechanisms, and technique for
addressing memory.

Examples of organization attributes include those hardware details transparent to the

programmer, such as control signals, interfaces between the computer and peripherals, and
the memory technology used.

Basic Structure of a Computer

Figure 1 shows the general structure of the IAS computer. It consists of:

 A main memory, which stores both data and instructions.

 An arithmetic-logical unit (ALU) capable of operating on binary data.
 A control unit, which interprets the instructions in memory and causes them to be
executed.
 Input and output (I/O) equipment operated by the control unit.
 Fig.1 Basic structure of a computer.

Computer is an electronic machine that makes performing any task very easy. In computer,
the CPU executes each instruction provided to it, in a series of steps, this series of steps is
called Machine Cycle, and is repeated for each instruction. One machine cycle
involves fetching of instruction, decoding the instruction, transferring the data, executing the
instruction.
Computer system has five basic units that help the computer to perform operations, which are
given below:

1. Input Unit

Input unit connects the external environment with internal computer system. It provides
data and instructions to the computer system. Commonly used input devices
are keyboard, mouse, magnetic tape etc.
Input unit perform following tasks:

o Accept the data and instructions from the outside environment.

o Convert it into machine language.
o Supply the converted data to computer system.
2. Output Unit

It connects the internal system of a computer to the external environment. It provides the
results of any computation, or instructions to the outside world. Some output devices
are printers, monitoretc.

3. Storage Unit

This unit holds the data and instructions. It also stores the intermediate results before
these are sent to the output devices. It also stores the data for later use.
 The storage unit of a computer system can be divided into two categories:

o Primary Storage

This memory is used to store the data which is being currently executed. It is used for
temporary storage of data. The data is lost, when the computer is switched off. RAM
is used as primary storage memory.

o Secondary Storage

The secondary memory is slower and cheaper than primary memory. It is used for
permanent storage of data. Commonly used secondary memory devices are hard disk,
CD etc.

4. Arithmetic Logical Unit

All the calculations are performed in ALU of the computer system. The ALU can
perform basic operations such as addition, subtraction, division, multiplication etc.
Whenever calculations are required, the control unit transfers the data from storage unit to
ALU. When the operations are done, the result is transferred back to the storage unit.

5. Control Unit

It controls all other units of the computer. It controls the flow of data and instructions to
and from the storage unit to ALU. Thus it is also known as central nervous system of the
computer.

6. CPU

It is Central Processing Unit of the computer. The control unit and ALU are together
known as CPU. CPU is the brain of computer system. It performs following tasks:

o It performs all operations.

o It takes all decisions.
o It controls all the units of computer.

Registers
Register is a very fast computer memory, used to store data/instruction in-execution.
A Register is a group of flip-flops with each flip-flop capable of storing one bit of
information. An n-bitregister has a group of n flip-flops and is capable of storing binary
information of n-bits.
Following are some commonly used registers:

1. Accumulator: This is the most common register, used to store data taken out from the
memory.
2. General Purpose Registers: This is used to store data intermediate results during
program execution. It can be accessed via assembly programming.
3. Special Purpose Registers: Users do not access these registers. These registers are for
Computer system,
o MAR: Memory Address Register are those registers that holds the address for
memory unit.
o MBR: Memory Buffer Register stores instruction and data received from the memory
and sent from the memory.
o PC: Program Counter points to the next instruction to be executed.
o IR: Instruction Register holds the instruction to be executed.

Connection between processor and memory

The PC (Program Counter) contains the memory address of the instruction to be executed.
During execution, the contents of the PC are updated to point to the next instruction. Every
time that an instruction is to be executed, the program counter releases its contents to the
internal bus and sends it to the memory address register.
The MAR (Memory Address Register) holds the address of the location to or from which
data are to be transferred. As can be seen from the figure above, the connection of the MAR
to the main memory is one-way or unidirectional.

The MDR (Memory Data Register) contains the data to be written or read out of the
addressed location.

During the fetch operation, the MDR contains the instruction to be executed or data needed
during execution. In write operation, MDR the data to be written into the main memory.

The IR (Instruction Register) contains the instruction that is being executed. Before the IR
executes the instruction it needs to be decoded first. As soon as the content of the MDR is
transferred to the IR, the decoding process commences. After decoding, execution of the
instruction will take place.

Operating Steps

1. PC is set to point to the first instruction of the program (the operating system loads the
memory address of the first instruction).

2. The contents of the PC are transferred to the MAR (which is automatically transmitted to
the MM) and a Read signal is sent to the MM.

3. The addressed word is read out of MM and loaded into the MDR.

4. The contents of MDR are transferred to the IR. The instruction is ready to be decoded and
executed.

5. During execution, the contents of the PC are incremented or updated to point to the next
instruction.

Example

Enumerate the different steps needed to execute the machine instruction

ADD LOCA, R0

Assume that the instruction itself is stored in the main memory at location INSTR, and that
this address is initially in register PC. The first two steps might be expressed as:

1. Transfer the contents of register PC to register MAR.

2. Issue a READ command to the main memory, and then wait until it has transferred the
requested word into register MDR.

CPU Instruction Execution Steps

Instruction execution in a CPU can now be summarized by the following steps:

1. Fetching the instruction from the memory into the instruction register.

2. Incrementing the PC to point to the next instruction to be executed.

3. Determining the type of instruction fetched (instruction decoding).

4. Determining the location of data in the memory. If the instruction uses data.

5. Fetching the required data into internal CPU registers.

6. Executing the instruction.

7. Storing the results in the designated locations.

8. Return to Step 1.

This is commonly referred to as the fetch-decode-execute cycle.

Review of basic operational concepts

Now we focus on the processing unit, which executes machine instructions and coordinates
the activities of other units. This unit is often called the instruction Set Processor (ISP), or
simply the processor. We examine its internal structure and how it performs the tasks of
fetching, decoding, and executing instructions of a program. The processing unit used to be
called the central processing unit (CPU). The term “central” is less appropriate today because
many modern computer systems include several processing units.
The organization of processors has evolved over the years, driven by developments in
technology and the need to provide high performance. A common strategy in the
development of high-performance processors is to make various functional units operate in
parallel as much as possible. High-performance processors have a pipelined organization
where the execution of one instruction is started before the execution of the preceding
instruction is completed. In another approach, known as superscalar operation, several
instructions are fetched and executed at the same time. Pipelining and superscalar
architectures are discussed later.
A typical computing task consists of a series of steps specified by a sequence of machine
instructions that constitute a program. An instruction is executed by carrying out a sequence
of more rudimentary operations. These operations and the means by which they are
controlled are the main topic of this chapter.
1.3 CPU- single bus organization

To execute a program, the processor fetches one instruction at a time and performs the
operations specified. Instructions are fetched from successive memory locations until a
branch or a jump instruction is encountered. The processor keeps track of the address of the
memory location containing the next instruction to be fetched using the program counter, PC.
After fetching an instruction, the contents of the PC are updated to point to the next
instruction in the sequence. A branch instruction may load a different value into the PC.

Another key register in the processor is the instruction register, IR. Suppose that
each instruction comprises 4 bytes, and that it is stored in one memory word. To execute
an instruction, the processor has to perform the following three steps:

I. Fetch the contents of the memory location pointed to by the PC. The contents of this
location are interpreted as an instruction to be executed. Hence, they are loaded into the IR.
Symbolically, this can be written as

IR  [[PC]]
2. Assuming that the memory is byte addressable, increment the contents of the PC by 4, that
is,
PC  [PC] +4
3. Carry out the actions specified by the instruction in the IR.

In cases where an instruction occupies more than one word, steps I and 2 must be repeated as
many times as necessary to fetch the complete instruction. These two steps are usually
referred to as the fetch phase; step 3 constitutes the execution phase.

To study these operations in detail, we first need to examine the internal organization
of the processor. They can be organized and interconnected in a variety of ways. We will start
with a very simple organization. Later in this chapter and in Chapter 8 we will present more
complex structures that provide high performance. Figure 1.1 shows an organization in which
the arithmetic and logic unit (ALU) and all the registers are interconnected via a single
common bus. This bus is internal to the processor and should not be confused with the
external bus that connects the processor to the memory and 110 devices.

The data and address lines of the external memory bus are shown in Figure 1.1 connected to
the internal processor bus via the memory data register, MDR, and the memory address
register, MAR, respectively. Register MDR has two inputs and two outputs. Data may be
loaded into MDR either from the memory bus or from the internal processor bus. The data
stored in MDR may be placed on either bus. The input of MAR is connected to the internal
bus, and its output is connected to the external bus. The control lines of the memory bus are
connected to the instruction decoder and control logic block. This unit is responsible for
issuing the signals that control the operation of all the units inside the processor and for
interacting with the memory bus.

The number and use of the processor registers R0 through R(n - 1) vary considerably from
one processor to another. Registers may be provided for general-purpose use by the
programmer. Some may be dedicated as special-purpose registers, such as index registers or
stack pointers. Three registers, Y, Z, and TEMP in Figure 1.1, have not been mentioned
before. These registers are transparent to the programmer, that is, the programmer need not
be concerned with them because they are never referenced explicitly by any instruction. They
are used by the processor for temporary storage during execution of some instructions. These
registers are never used for storing data generated by one instruction for later use by another
instruction.

The multiplexer MUX selects either the output of register Y or a constant value 4 to be
provided as input A of the ALU. The constant 4 is used to increment the contents of the
program counter. We will refer to the two possible values of the MUX control input Select as
Select4 and SelectY for selecting the constant 4 or register Y, respectively.

As instruction execution progresses, data are transferred from one register to another, often
passing through the ALU to perform some arithmetic or logic operation. The instruction
decoder and control logic unit is responsible for implementing the actions specified by the
instruction loaded in the JR register. The decoder generates the control signals needed to
select the registers involved and direct the transfer of data. The registers, the ALU, and the
interconnecting bus are collectively referred to as the datapath.

With few exceptions, an instruction can be executed by performing one or more of

the following operations in some specified sequence:
• Transfer a word of data from one processor register to another or to the ALU
• Perform an arithmetic or a logic operation and store the result in a processor register
• Fetch the contents of a given memory location and load them into a processor register
• Store a word of data from a processor register into a given memory location
We now consider in detail how each of these operations is implemented, using the
simple processor model in Figure 1.1.
 Fig.1.1 Single bus organization of the data path inside a processor

REGISTER TRANSFERS
Instruction execution involves a sequence of steps in which data are transferred from one
register to another. For each register, two control signals are used to place the contents of that
register on the bus or to load the data on the bus into the register. This is represented
symbolically in Figure 1.2. The input and output of register Ri are connected to the bus via
switches controlled by the signals Riin and Riout, respectively. When Riin is set to 1, the data
on the bus are loaded into Ri. Similarly, when Riout is
set to 1, the contents of register Ri are placed on the bus. While Riout is equal to 0, the
bus can be used for transferring data from other registers.

Suppose that we wish to transfer the contents of register Rl to register R4. This can be
accomplished as follows:
  Enable the output of register Ri by setting Riout to 1. This places the contents of R 1 on
the processor bus.
 Enable the input of register R4 by setting R4in to 1. This loads data from the processor
bus into register R4.

All operations and data transfers within the processor take place within time periods
defined by the processor clock. The control signals that govern a particular transfer are
asserted at the start of the clock cycle. In our example, R1out and R4in are set to 1.
The registers consist of edge-triggered flip-flops. Hence, at the next active edge of the
clock, the flip-flops that constitute R4 will load the data present at their inputs. At the
same time, the control signals R1out and R4in will return to 0. We will use this simple
model of the timing of data transfers for the rest of this chapter. However, we should
point out that other schemes are possible. For example, data transfers may use both the
rising and falling edges of the clock. Also, when edge-triggered flip-flops are not used,
two or more clock signals may be needed to guarantee proper transfer of data. This is
known as multiphase clocking.

An implementation for one bit of register Ri is shown in Figure 1.3 as an example. A

two-input multiplexer is used to select the data applied to the input of an edge-triggered
D flip-flop. When the control input Ri1 is equal to 1, the multiplexer selects the data
on the bus. This data will be loaded into the flip-flop at the rising edge of the clock.
When Ri is equal to 0, the multiplexer feeds back the value currently stored in the
flip-flop.
Fig.1.2 Input and output gating for the registers in fig 1.1
 Fig. 1.3 Input and output gating for one register bit

The Q output of the flip-flop is connected to the bus via a tri-state gate. When Riout
is equal to 0, the gate’s output is in the high-impedance (electrically disconnected) state.
This corresponds to the open-circuit state of a switch. When Riout = 1, the gate drives
the bus to 0 or I, depending on the value of Q.

Bus Structure

A bus is a collection of wires that connect several devices within a computer system. When a
word of data is transferred between units, all its bits are transferred in parallel. A computer
must have some lines for addressing and control purposes.

Three main groupings of lines:

1. Address Bus.

 This specifies the location of data in MM.

Processor issues the address of the instruction byte or word to the memory
system through the address bus
 Processor execution unit, when required, issues the address of the data (byte
or word) to the memory system through the address bus
2. Data Bus
 When the Processor issues the address of the instruction, it gets back the
instruction through the data bus
 When it issues the address of the data, it loads the data through the data bus
 When it issues the address of the data, it stores the data in the memory through
the data bus
3. Control Bus.
  This indicates the direction of data transfer and coordinates the timing of
events during the transfer.
 Issues signals to control the timing of various actions during interconnection
 Bus signals synchronize the subsystems
 Control signals as per the processor design
 Control bus issues signals to control the timing of various actions during
interconnection
 Control bus signals from processor to Memory read, Memory write, IO read,
IO write
 Control bus signals synchronize the subsystems: memory and IO systems
 Control bus signals from processor to Address latch enable or data valid

Single Bus Structure

All units are connected to a single bus, so it provides the sole means of interconnection.
Single bus structure has advantages of simplicity and low cost.
Single bus structure has disadvantages of limited speed since usually only two units can
participate in a data transfer at any one time. This means that an arbitration system is required
and that units will be forced to wait.

Only two units can actively use the bus at any given time. Bus control lines are used to
arbitrate multiple requests for the use of the bus.

Buffer Registers are used to hold information during transfers.

Two Bus Structure

TWO-BUS STRUCTURE: The bus is said to perform two distinct functions by connecting
the I/O units with memory and processor unit with memory. The processor interacts with the
memory through a memory bus and handles input/output functions over I/O bus. The I/O
transfers are always under the direct control of the processor, which initiates transfer and
monitors their progress until completion. The main advantage of this structure is good
operating speed but on account of more cost.

The Figure 2.2 shows the two-bus structure and Figure 2.3 shows the alternate arrangement
of two-bus structure.

ALTERNATIVE TWO-BUS STRUCTURE:

 Here the positions of memory and processor are interchanged. I/O transfers are directly made
to or from the memory. So, special purpose processor called peripheral processor is used for
providing the necessary controls over the actual data transfer.

MEMORY LOCATIONS, ADDRESSES

INSTRUCTIONS AND INSTRUCTION SEQUENCING

A computer must have instructions capable of performing four types of operations
1. Data transfers between the main memory and the CPU registers
2. Arithmetic and logic operations on data
3. Program sequencing and control
4. I/O transfers
Notations used:

a) Register Transfer Notation (RTN):- Possible locations involved in transfer of information

are memory location, CPU registers or registers in the I/O subsystem. We identify the names
for the addresses of memory location as LOC, PLACE, A, VAR2 etc and the names for CPU
registers as R0, R5 etc. The contents of a location or a register are denoted by placing the
corresponding name between square brackets.

E.g. i) R1 _ [LOC] means that the contents of memory location LOC are transferred into
register R1. ii) R3 _ [R1] + [R2] adds the contents of registers R1 and R2 and then
places their sum into register R3.

b) Assembly Language Notation:- The same operations can be represented in assembly

language format as shown below.
E.g. i) Move LOC, R1 ii) Add R1,R2,R3
BASIC INSTRUCTION TYPES
There are five types of instruction formats in a computer that are commonly used, namely:
1. Three-address instruction format
2. Two-address instruction format
3. One-address instruction format
4. Zero-address instruction format
5. One-and-half address instruction format

Three-address instruction C = A + B is a high level instruction to add the values of the two
variables A and B and to assign the sum to a third variable C. When this statement is
compiled, each of these variables is assigned to a location in the memory. The contents of
these locations represent the values of the three variables.
Hence the above instruction requires the action:
C _ [A] + [B]

To carry out this instruction, the contents of the memory locations A and B are fetched from
the main memory and transferred into the processor – sum is computed – result is sent back
to memory and stored in location C. The same action is performed by a single machine
instruction (three address instruction)
Add A,B,C

Operands A and B are called the source operands, C is called the destination operand, and
Add is the operation to be performed on the operands.
The general format is Operation Source1,Source2, Destination

If k bits are needed to specify the memory address of each operand, the encoded form of the
above instruction must contain 3k bits for addressing purposes + the bits needed to denote the
Add operation.

Two-address instruction
An alternative method is to use two address instruction of the form
Operation Source,Destination
E.g. Add A,B which perform the operation B _ [A] + [B] Here the sum is calculated and the
result is stored in location B replacing the original contents of this location. i.e. operand B
acts as source as well as destination. In the former case (three address instruction) the
contents of A and B were not destroyed. But here the contents of B are destroyed. This
problem is solved by using another twoaddress instruction to copy the contents of one
memory location into another location.
Now C _ [A] + [B] is equivalent to Move B,C Add A,C
Note: In all the above instructions, the source operands are specified first, followed by the
destination. But there are many computers in which the order is reversed.

One-address instruction
Instead of mentioning the second operand, it is understood to be in a unique location. A
processor register usually called the Accumulator is used for this purpose.

E.g. i) Add A means that the contents of the memory location A is added to the contents of
accumulator and places the sum in the accumulator.
ii) Load A copies the contents of memory location A into accumulator

iii) Store A copies the contents of accumulator to the location A Depending on the
instruction, the operand may be source or destination.
Now the operation C _ [A] + [B] can be performed by executing the following instructions
Load A
Add B
Store C

The above mentioned instructions can also be handled by using general purpose registers. Let
Ri represent a general purpose register.
Move A,Ri
Move Ri,A
Add A,Ri

They are generalizations of Load, Store and Add instructions of the single accumulator case
in which register Ri performs the functions of accumulator. When a processor has several
general-purpose registers, then many instructions involve only operands that are in registers.
E.g., Add Ri, Rj
Add Ri, Rj, Rk

In the first instruction, Rj acts as both source and destination. In the second instruction, Ri
And Rj are source and Rk is the destination.

Advantages of using CPU registers:

i) Data access from these registers is faster than that of main memory locations; because
these registers are inside the processor.
ii) Only few bits are needed to specify the register; because the number of registers is
very less. For example, only 5 bits are needed to specify 32 registers.
iii) Instructions, where only register names are contained, will normally fit into one word
of memory
Zero-address instruction
Here locations of all operands are defined implicitly. Such instructions are found in machines
that store operands in a structure called a pushdown stack. A stack is a list of data elements,
usually words or bytes, in which these elements can be added or removed through the top of
the stack by following the LIFO (last-in-first-out) storage mechanism. A processor register
called stack pointer. (SP) is used to keep track of the address of the element at the top of the
stack at any given time. The terms push and pop are used to describe placing a new item on
the stack and removing the top item from the stack respectively.

Adressing Modes and Instruction Cycle

The operation field of an instruction specifies the operation to be performed. This operation
will be executed on some data which is stored in computer registers or the main memory. The
way any operand is selected during the program execution is dependent on the addressing
mode of the instruction. The purpose of using addressing modes is as follows:

1. To give the programming versatility to the user.

2. To reduce the number of bits in addressing field of instruction.

Types of Addressing Modes:

Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.

Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.
Advantages of this mode:

 Shorter instructions and faster instruction fetch.

 Faster memory access to the operand(s)

Disadvantages of this mode:

 Very limited address space

 Using multiple registers helps performance but it complicates the instructions.

Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of
operand which is in memory. Thus, the register contains the address of operand rather than
the operand itself.
Auto Increment/Decrement Mode
In this the register is incremented or decremented after or before its value is used.

Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.

 Single memory reference to access data.

 No additional calculations to find the effective address of the operand.
For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.

Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored
in memory. This slows down the execution, as this includes multiple memory lookups to find
the operand.

Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to
obtain the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and
R(that holds the displacement), or vice versa.
Relative Addressing Mode
It is a version of Displacement addressing mode.
In this the contents of PC(Program Counter) is added to address part of instruction to obtain
the effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell(the one pointed to by PC)

Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),
where A is displacement and R holds pointer to base address.

Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction
will POP top two items from the stack, add them, and will then PUSH the result to the top of
the stack.

Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the basic operational
process of a computer. This process is repeated continuously by CPU from boot up to shut
down of computer.
Following are the steps that occur during an instruction cycle:
Fetch the Instruction
The instruction is fetched from memory address that is stored in PC(Program Counter) and
stored in the instruction register IR. At the end of the fetch operation, PC is incremented by 1
and it then points to the next instruction to be executed.
Decode the Instruction
The instruction in the IR is executed by the decoder.
Read the Effective Address
If the instruction has an indirect address, the effective address is read from the memory.
Otherwise operands are directly read in case of immediate operand instruction.
Execute the Instruction
The Control Unit passes the information in the form of control signals to the functional unit
of CPU. The result generated is stored in main memory or sent to an output device.

The cycle is then repeated by fetching the next instruction. Thus in this way the instruction
cycle is repeated continuously.
ARM processor
An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set
computer) architecture developed by Advanced RISC Machines (ARM).

ARM makes 32-bit and 64-bit RISC multi-core processors. RISC processors are designed to
perform a smaller number of types of computer instructions so that they can operate at a
higher speed, performing more millions of instructions per second (MIPS). By stripping out
unneeded instructions and optimizing pathways, RISC processors provide outstanding
performance at a fraction of the power demand of CISC (complex instruction set computing)
devices.

ARM processors are extensively used in consumer electronic devices such

as smartphones, tablets, multimedia players and other mobile devices, such as wearables.
Because of their reduced instruction set, they require fewer transistors, which enables a
smaller die size for the integrated circuitry (IC). The ARM processor’s smaller size, reduced
complexity and lower power consumption makes them suitable for increasingly miniaturized
devices.

ARM processor features include:

 Load/store architecture.
 An orthogonal instruction set.
 Mostly single-cycle execution.
 Enhanced power-saving design.
 64 and 32-bit execution states for scalable high performance.
 Hardware virtualization support.

Input/Output Organisation
Input/Output Subsystem
The I/O subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input-output operations of the
computer system.

Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from
the CPU and are considered to be the part of computer system. These devices are also
called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:

1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well
as, output(from computer to the outside world). Example: Touch screen etc.

Interface
Interface is a shared boundary btween two separate components of the computer system
which can be used to attach two or more components to the system for communication
purposes.
There are two types of interface:

1. CPU Inteface
2. I/O Interface
Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with
CPU. In computer system, there are special hardware components between the CPU and
peripherals to control or manage the input-output transfers. These components are
called input-output interface units because they provide communication links between
processor bus and peripherals. They provide a method for transferring information between
internal system and input-output devices.

Modes of Transfer
Data transfer between the central unit and I/O devices can be handled in generally three types
of modes which are given below:

Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program.
Each data item transfer is initiated by the instruction in the program. Usually the program
controls data transfer to and from CPU and peripheral. Transferring data under programmed
I/O requires constant monitoring of the peripherals by the CPU.
Interrupt Initiated I/O
In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is time consuming process because it keeps the
processor busy needlessly. This problem can be overcome by using interrupt initiated I/O. In
this when the interface determines that the peripheral is ready for data transfer, it generates an
interrupt. After receiving the interrupt signal, the CPU stops the task which it is processing
and service the I/O transfer and then returns back to its previous processing task.
Direct Memory Access
Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA
controller manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network
cards and sound cards etc. It is also used for intra chip data transfer in multicore processors.
In DMA, CPU would initiate the transfer, do other operations while the transfer is in progress
and receive an interrupt from the DMA controller when the transfer has been completed.
Above figure shows block diagram of DMA