Design lab EC 881

S.D.E.T.-Brainware Group Of Institutions

398,Ramakrishnapur road, Kaji Para, Barasat, Kolkata-700124

Electronics and Communication Engineering (8th semester)

Design Lab [EC 881]

Prepared by…….

Name -Rusha Dutta

Class Roll-BSSE/UT/EC/14/035
MAKAUT Roll- 27000314042
Reg. No. – 142700110113

Teacher’s signature………………….

Electronics & Communication engineering Page 1

 Design lab EC 881

Content

Sl. no. Exp. name Page no. Date Signature

3
INVERTING AND NON-INVERTING
1 AMPLIFIERS

2 6
DESIGN A BCD TO 7 SEGMENT DECODER

3 9
TIMER IC 555

4 14
Multiplexer & De multiplexer

5 DC Regulated Voltage power supply 18

6 Design a mod 6 counter using JK flip flop 20

Electronics & Communication engineering Page 2

 Design lab EC 881

Exp 1 : INVERTING AND NON-INVERTING AMPLIFIERS

Objective:
To study the following linear applications op-amp

1. Inverting amplifier
2. Non-inverting amplifier

Apparatus required:
1. Op-Amp IC 741
2. Dual Power Supply 15V
3. Resistors
4. Function Generator
5. Cathode Ray Oscilloscope
6. Multimeter
7. Breadboard and Connecting wires

Theory:
Inverting Amplifier:

This is the most widely used of all the Op-Amp circuits. The output V0 is fed back to the inverting
input through the Rf – Rin network as shown in figure where Rf is the feedback resistor. The input signal
Vi is applied to the inverting input terminal through Rin and non-inverting input terminal of Op-amp is
grounded. The output V0 is given by

V0 = Vi (-Rf / Rin)

Where, the gain of amplifier is - Rf / Rin

The negative sign indicates a phase-shift of 180 degrees between Vi and V0. The effective input impedance is
Ri. An inverting amplifier uses negative feedback to invert and amplify a voltage. The Rin,Rf resistor network
allows some of the output signal to be returned to the input. Since the output is 180° out of phase, this amount is
effectively subtracted from the input, thereby reducing the input into the operational amplifier. This reduces the
overall gain of the amplifier and is dubbed negative feedback.

Circuit Diagram:

Tabulation:
Vi=___________ Rin=___________

Electronics & Communication engineering Page 3

 Design lab EC 881

Sl No. Rf Observed V0 Calculated V0=Vi(-

Rf/Rin)

Model Graph:

Non-inverting amplifier:
The circuit diagram of non-inverting amplifier is shown in figure. Here the signal is applied to the non-inverting
input terminal and feedback is given to inverting terminal. The circuit amplifiers the input signal without
inverting it. The output Vout is given by
𝐑𝟐
Vout=Vin (1+𝐑𝟏)

The voltage gain is given by

Compared to the inverting amplifier, the input resistance of the non-inverting is extremely large.

Circuit diagram :

Tabulation:
Vi=___________ Rin=___________

Electronics & Communication engineering Page 4

 Design lab EC 881

Sl No. Rf Observed V0 Calculated V0=Vi(-

Rf/Rin)

Model graph:

Result :
Thus the linear applications of 741 Op-Amp were studied experimentally.

Electronics & Communication engineering Page 5

 Design lab EC 881

Exp 2 :-DESIGN A BCD TO 7 SEGMENT DECODER

Objective-TO DESIGN A BCD TO 7 SEGMENT DECODER

Theory
The BCD to 7 Segment Decoder converts 4 bit binary to 7 bit control signal which can be displayed on 7
segment display. Seven display consist of 7 led segments to display 0 to 9 and A to F.

Truth Table

From the above truth table, the Boolean expressions of each output functions can be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

Electronics & Communication engineering Page 6

 Design lab EC 881

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

K-map Simplification:

From the above simplification, we get the output values as

Circuit Diagram:

Electronics & Communication engineering Page 7

 Design lab EC 881

Display Decoder Circuit Operation:

The circuit operation can be understood through the truth table itself. When all the inputs are
connected to low logic , the output of the combinational logic circuit would be so as to drive all the
output LEDs except ‘g’ to conduction. Thus the number 0 will be displayed. Similar operation would
take place for all other combinations of the input switches.

Practically BCD to 7 segment decoders are available in form of integrated circuits such as
74LS47. Apart from regular 4 input pins and 7 output pins, it consists of a lamping test pin used for
segment testing, ripple blanking input pin used to blank off zeros in multiple display systems, ripple
blanking output pin used for cascading purposes and a blanking input pin.

Electronics & Communication engineering Page 8

 Design lab EC 881

Exp 3 : TIMER IC 555

Objective : To design and study the following circuits using 555 timer.
1. MONOSTABLE MULTIVIBRATOR

2. ASTABLE MULTIVIBRATOR

3. SCHMITT TRIGGER

Apparatus required:
1. IC 555
2. Resistors
3. Capacitors
4. CRO
5. AFO
6. RPS

Theory :
555 is a very commonly used IC for generating accurate timing pulses. It is an 8-pin timer IC. The
555 has three operating modes.

1. Monostable mode
2. Astable – free running mode
3. Bistable mode or Schmitt trigger

The input/output relationship for the various multivibrators are shown in figure

Monostable multivibrators: Monostable multivibrator often called a one shot multivibrator, is a

pulse generating circuit in which the duration of this pulse is determined by the RC network
connected externally to the 555 timer. In a stable or standby state, the output of the circuit is
approximately zero or a logic-low level. When external trigger pulse is applied output is forced to go
high ( VCC). The time for which output remains high is determined by the external RC network
connected to the timer. At the end of the timing interval, the output automatically reverts back to its

Electronics & Communication engineering Page 9

 Design lab EC 881

logic-low stable state. The output stays low until trigger pulse is again applied. Then the cycle repeats.
The monostable circuit has only one stable state (output low) hence the name monostable.

Design of monostable multivibrator :

Time period of pulse= T=1.1

RC=10ms

Let C=100f

T=1.1 RC

10ms=1.1*R*100f

R=100K

Circuit Diagram :

Tabulation :
Input Output
Amplitude Time Period Amplitude Time Period

Model Graph :

Electronics & Communication engineering Page 10

 Design lab EC 881

Astable Multivibrator :
The astable multivibrator generates square waves, the period of which is determined by the circuit
external to IC 555. The astable multivibrator does not require any external trigger to change the state
of the output. Hence the name free running oscillator. The time during which the output is either high
or low is determined by the two resistors and a capacitor which are externally connected to the 555
time.

Circuit diagram :

Electronics & Communication engineering Page 11

 Design lab EC 881

Electronics & Communication engineering Page 12

 Design lab EC 881

Results :
Thus the monostable , astable multivibrator and Schmitt trigger circuits are designed and constructed
and the output waveforms are drawn.

Electronics & Communication engineering Page 13

 Design lab EC 881

Exp 4: Multiplexer & De multiplexer

Objectives:
1. Understanding how to implement functions using multiplexers.
2. To study de multiplexer.

Theory:
Multiplexers:

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines,
which are used to select which input line to send to the output.
A 2n-to-1 multiplexer sends one of 2n input lines to a single output line.
– A multiplexer has two sets of inputs:
• 2n data input lines
• n select lines, to pick one of the 2n data inputs
– The mux output is a single bit, which is one of the 2n data inputs.
2-to-1 Mux

The simplest multiplexer is a 2-to-1 mux

Q = S’ D0 + S D1
The select bit S controls which of the data bits D0-D1 is chosen:
– If S=0, then D0 is the output (Q=D0).
– If S=1, then D1 is the output (Q=D1).
Here is a full truth table for this 2-to-1 mux, based on the equation:
Q = S’ D0 + S D1

Electronics & Communication engineering Page 14

 Design lab EC 881

 4-to-1 Mux

Here is a block diagram and abbreviated truth table for a 4-to-1 mux.

•Be careful! In Logic Works the multiplexer has an active-low EN input signal. When EN’ = 1, the
mux always outputs 1.

Implementing functions with multiplexers:

Muxes can be used to implement arbitrary functions. For a function of n variables follow these steps:
1. Select the type of Mux [2n-1-to-1].
2. Select (n-1) as selection line.
3. The other input connects as input.

Implement following function with multiplexer:

Solution:
1. The type of Mux [23-to-1] == 8-to-1 mux
2. Select (3) as selection line. == For example (B, C, and D)
3. The other input connects as input. == (A)
Circuit diagram & truth table :

Electronics & Communication engineering Page 15

 Design lab EC 881

Demultiplexers:
The Demultiplexer is combinational logic circuit that performs the reverse operation of Multiplexer. It
has only one input, n selectors and 2n outputs. Depending on the combination of the select lines, one
of the outputs will be selected to take the state of the input.
The following figure shows the block diagram and the truth table for 1x4 Demultiplexer.
By applying logic '1' to the input, the circuit will do the same function of the typical 2-to-4 Decoder.

Circuit diagram & truth table :

Lab Work:
Part 1: 2-to-1 Mux
Construct 2-to-1 Mux using KL-33006 block e. (D1=A, D0=B, S=C). Connect inputs A, B to
SW0 and SW1. Connect input C to SW3.

Circuit diagram & truth table :

Electronics & Communication engineering Page 16

 Design lab EC 881

Part 2: 8-to-1 Mux

Using Mux KL-33006 block f connect inputs DO D7 to DIP Switch 1.0 1.7; inputs C,
B, A to DATA Switches SW2, SW1, SW0 respectively, strobe to 0, Y and W to L0, L1
respectively.

Circuit diagram & truth table :

Electronics & Communication engineering Page 17

 Design lab EC 881

Exp 5: DC Regulated Voltage power supply

Objective: To design a DC regulated voltage supply circuit.
Theory: The LM 317 series is adjustable to three terminal positive voltage regulators. The different
grades of regulators in the series are available with output voltage of 1.2 to 57 volts and output current
from 0.1 to 1.5 ampere.
The LM 317 series regulators are available in standard transmitter packages that are easily mounted
and handled. The three terminals Vin, Vout, adjustable.
The LM 317 develops a nominal 1.25 volt referred to as reference voltage between the output and the
adjustment terminal. The maximum value of adjustable pin current is 100μA.
It is highly efficient in protecting circuits that are complex and complicated. That is why LM 317
circuit is highly useful.

Components and apparatus required

BR1 = Bridge Rectifier, 100V - 3A C1 = 1000 μF, 63V
IC1 = LM317, adjustable regulator C2 = 0.1 μF
V = Meter, 30V, RI = 85 ohm C3 = 1μF
Plug = 3-wire plug & cord C4 = 10μF
TR1 = Transformer, 30V, 2A
R1 = 240 ohm, 5%
D1 = 1N4002
D2 = 1N4002
P1 = 5K, potentiometer
Fuse = 110V, 500mA, slow-blow, Fuse Holder, wire, solder, case, knob for P1 Red & Black Banana
Jacks

Circuit Diagram :

LM317 WITH CAPACITORS AND PROTECTIVE DIODES

Electronics & Communication engineering Page 18

 Design lab EC 881

Graph:

Result and Calculation :

V0= 0 to 30 V
I0 = 1.0 A
Iadj = 100μA max

If we use R1=240 ohm, then for V0 of 1.2 volt, the value of R2 from equation

V0=1.25(1+R2/R1)+(Iadj)(R2)
If V0=1.25V
1.2=1.25(1+R2/240)+(10-4)R2
R2=2.02 KΩ

If V0=30V
30=1.25(1+R2/240)+(10-4)R2
R2 =5.4 KΩ

Electronics & Communication engineering Page 19

 Design lab EC 881

Exp 6: Design a mod 6 counter using JK flip flop

Objectives: Design and implement a mod 6 counter using JK flip flop.
Components Required:

The required circuit should be implemented as per problem statements using TTL ICs. We can
use Quad/Dual JK Flip Flop (7473)/(74273) and NAND gates (also D flip flops)

Experimental Procedure:

 MOD 6 asynchronous counter will require 3 flip flops and will count from 000 to 101. Rest of
the states are invalid. To design the combinational circuit of valid states, following truth table
and K-map is drawn:

 From the above truth table, we draw the K-maps and get the expression for the MOD 6
asynchronous counter.

 Thus reset logic is OR of complemented forms of QC and QB. This will be given to the reset
inputs of the counter so that as soon as count 110 reaches, the counter will reset. Thus the
counter will count from 000 to 101. The implementation of the designed MOD 6
asynchronous counter is shown below:

Electronics & Communication engineering Page 20

 Design lab EC 881

Electronics & Communication engineering Page 21