Professional Documents
Culture Documents
2010-09-28
Carsten Wulff
Outline
• Who
am
I,
what
have
I
done,
and
what
do
I
do
• Nanoscale
effects
to
worry
about
• Reliability
effects
• Nanoscale
blocks
• Nanoscale
layout
If
there
is
Cme:
• CBSC
and
my
ADC
2
©
Carsten
Wulff
September
10
Who am I?
• Carsten
Wulff
• Born
Friday
13.
August
1976
• R
&
D
engineer
at
wireless
department
at
Nordic
Semiconductor
• Married
with
three
kids
• Graduated
from
NTNU
2002
(Programmable
analog
integrated
circuit
with
TOC,
0.6um
AMS)
• Ph.D
from
NTNU
in
2008
(Efficient
ADCs
in
nano-‐scale
CMOS
technology,
90nm
ST)
• Fortunate
to
spend
a
year
at
University
of
Toronto
(2006-‐2007)
with
David
Johns
and
Ken
MarCn
• h^p://www.scribd.com/carstenwulff
• h^p://www.wulff.no/carsten
3
©
Carsten
Wulff
September
10
ADC figure of merit
JSSC 1975-2005
ISSCC 2000-2008
10
0.1
0.01
0.001
0.0001
2 4 6 8 10 12 14 16 18 20
Norchip 2009
6
©
Carsten
Wulff
September
10
Headroom
7
©
Carsten
Wulff
September
10
Headroom, what works
8
©
Carsten
Wulff
September
10
Output resistance
9
©
Carsten
Wulff
September
10
Nanoscale transistor
102*3.4.-2536,+7/
• Threshold
voltage
increases
with
proximity
to
well
edge
• Place
switch
transistors
in
a
)*+,+-./0/,
)*+,+-./0/,
transmission
gate
far
from
well
edge
• Place
bias
transistors
(diode
!"# !"# !"#
11
©
Carsten
Wulff
September
10
Shallow trench isolation
! ! ! !
"#$ "#$ "#$
%&'()*++,&!-&.-+,/,0&!-12*-3&-34*)'5/-*6(5!+,&!-',+'5304-
7*38**!-+,/,0&!-1,&6,1*-5!1-+,/,0&!
12
©
Carsten
Wulff
September
10
Reliability effects
• -‐
Electrons
(in
NMOS)
see
a
high
verCcal
electric
field
and
if
this
field
exceeds
around
5MV/cm
electrons
will
go
into
the
gate
• -‐
Trapped
charges
in
the
dioxide
shios
the
threshold
voltage
• -‐
Can
cause
a
short
of
the
dioxide
• -‐
This
effect
sets
the
maximum
VGS
14
©
Carsten
Wulff
September
10
Hot carrier injection
• -‐
Electron
is
accelerated
due
to
the
high
horizontal
field
(high
Vds).
It
impacts
the
crystal
laqce
and
generates
a
electron
hole
pair.
• -‐
If
the
impact
is
high
enough
energy
the
electron
can
pass
through
the
gate
and
cause
damage
Can
occur
at
moderate
VGS
and
high
VDS
15
©
Carsten
Wulff
September
10
HCI effect: Channel initiated secondary electron
• -‐
An
fast
electron
impacts
the
laqce
and
creates
a
hole-‐electron
pair.
• -‐
Due
to
a
high
VSB
the
hole
is
accelerated
towards
the
substrate.
It
can
impact
the
laqce
again
and
make
a
new
hole-‐electron
pair.
• -‐
The
secondary
electron
sees
a
very
high
electric
field
and
will
accelerate
towards
the
gate
Sets
the
maximum
VSB.
VSB
~
2VDD
a
factor
10
reduced
lifeBme
16
©
Carsten
Wulff
September
10
Nanoscale blocks
F-based design
Typical differential OTA
Typical bias voltage generator
Typical comparator
Differential reference voltage
F based transistor design
• 1F
=
1
gate
length
• Why:
schemaCc
is
independent
of
technology
• Use
a
small
number
of
different
transistors
• Always
use
larger
than
1F25
length
for
analog
transistors
• Widths:
6F,
8F,
24F
Lengths
Purpose
1F
Digital
transistors,
posiCve
feedback
inverters
1F25
DifferenCal
pairs
2F
Cascodes
4F
Current
mirror
transistors
12F
Standalone
current
mirrors,
cascode
bias
transistors
18
©
Carsten
Wulff
September
10
Differential OTA – CM OTA with CT CMFB
!(%
,*+ -*.
!&% ,/0'0,)1 ,/0'0,)1 !&#
23'* 23'*
'**.
(56718591:;<918+1(=>1<?@A5
)**+
'**. )**+
$20"
19
©
Carsten
Wulff
September
10
Differential OTA – Bias voltages
!"#
)-./ !"#)
$%&$& $%&$& *&)$& $%&$&
'($ '($ '() '($
!+#
!+,
$%&$& *&)$&
'($ '()
!",
20
©
Carsten
Wulff
September
10
Differential pair dynamic comparator
$(&
21
©
Carsten
Wulff
September
10
Differential reference voltage
• If
you
don’t
care
about
gain
error,
use
three
unity
gain
amplifier
with
a
resisCve
divider
at
the
input.
Remember
to
low-‐pass
filter
the
input.
!"#
$%&%$%'(%#
)*+,-.%
!/3
1R
1R
23
3#8#2/?
"3<#8#/01"#9: 4/;"
/01"
43
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22
©
Carsten
Wulff
September
10
Nanoscale Layout
Rule
Why
Always
use
two
fingers
Transistor
parameters
change
with
current
direcCon
Always
run
all
gates
in
Stress
in
X
and
Y
same
direcCon
direcCon
affect
transistor
differently
Always
have
dummy
poly
Be^er
poly
control
" ! "
during
processing
Always
have
larger
than
Less
stress
from
shallow
minimum
length
of
trench
isolaCon
diffusion
Always
place
transistors
Reduce
mismatch
in
far
from
well
edge
threshold
voltage
Be
careful
with
metal
Metal
changes
the
stress
rouCng
across
transistors
in
the
channel
24
©
Carsten
Wulff
September
10
Layout from Lanny Lewyn
25
©
Carsten
Wulff
September
10
Things you should know about
Sooware:
SchemaCc
(Mentor
graphics,
Cadence,
Synopsys,
Tanner
tools)
Layout
(Mentor
graphics,
Cadence,
Synopsys,
Tanner
tools)
SimulaCon
(Eldo,
Spectre,
Hspice,
SMASH)
ScripCng
(Bash,
Perl,
TCL,
LISP)
Editors
(Emacs)
Math
sooware
(Matlab,
Maple,
Octave)
InformaCon
sources:
h^p://ieeexplore.ieee.org
h^p://webcast.berkeley.edu/
EE240
spring
2007
to
spring
2010
For
new
tricks,
scan
JSSC
(all
papers)
each
month
26
©
Carsten
Wulff
September
10
CBSC pipelined ADC with comparator preset, and
comparator delay compensation
12.4 Comparator-Based Switched-Capacitor Circuits is a constant offset in the output if the ramp rate a
delay are constant. The current source I2 turns o
For Scaled CMOS Technologies
after the switch opens, but this does not affect the
Todd Sepke1, John K. Fiorenza1, Charles G. Sodini1, Peter Holloway2, Preliminary analysis indicate CBSC circuits are m
Hae-Seung Lee1 cient than conventional opamp-based circuits, be
the virtual-ground condition is more energy efficie
MIT, Cambridge, MA
1 the virtual ground.
National Semiconductor, Salem, NH
2
Primary goals:
Increase Speed (target 100MHz)
Differential circuit
Secondary goals:
Keep resolution (target 8.5-bits)
High efficiency < 10mW
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36 © Carsten Wulff September 10
Results
1
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40 2
30
1
INL [LSB]
INL [LSB]
20
0
10
0 −1
−10 −2
0 50 100 150 200 250 0 50 100 150 200 250
Output Code
Output Code
50 2
40
1
DNL [LSB]
DNL [LSB]
30
20 0
10
−1
0
−10 −2
0 50 100 150 200 250 0 50 100 150 200 250
Output Code Output Code
0 70
−20 60
−40 50
Magnitude [dB]
Magnitude [dB]
−60 40
−80 30
−100 20
−120
10 SNDR
SNR
−140 SFDR
0 5 10 15 20 25 30 0
5 10 15 20 25 30 35 40
Frequency [MHz]
Input Frequency [MHz]