AMS2000 Code 0846B

AMS2000
MICROCODE VERSION 0846/B

RELEASED 10/13/2008
Newly supported features and functions for Version 0846/B
1 Support QE4/IF board on AMS2300

Contents Support QE4/IF board on AMS2300
2 Support 4GB cache DIMM
Contents Support 4GB cache DIMM
Improvements for Version 0846/B
1 Improved I/O response time in small-scale configurations

Contents Improved I/O response time in small-scale configurations
The change of contents for Version 0846/B
1 Data reliability improvement

Phenomena "Data transfer length inconsistency error" in a write operation to a SAS HDD, causing
possible data inconsistency.
Severity High
Conditions of Occurrence With all of the following conditions met, the phenomenon may occur.
1. The SAS HDD has some unstable behavior and “Data transfer length inconsistency
error” occurs in the SAS HDD
2. The SAS HDD responds normal end condition without the data transfer error. RSD
considers that the occurrence rate is very low, because RSD has never experienced
such a failure phenomenon ever before.
Cause Due to microcode bug in recovery process for Data transfer length inconsistency error
Affected Products/Version 0832/E or later
Fixed Product/Version Version: 0843/B or later
Category Common
Changed Part MICRO-Disk
2 The I/O error occurs by LU switch + I/O operation.

Phenomena The I/O error occurs by LU switch + I/O operation.
Severity High
Conditions of Occurrence 1. LU unit switch
2．SyncCache/ModeSelect command
Cause The exclusion of the processing between controllers became failure because the LU
unit switch and the SyncCache/ModeSelect command executed it at the same time, and
they became IO error.
Fixed Product/Version Version: 0843/B or later
Category Common
HDS Confidential 1 of 5
3 System Hang during non-stop code exchange from V4.3/C to V4.6/A
Phenomena System Hang during non-stop micro exchange executed from V4.3/C to V4.6/A.
Severity High
Conditions of Occurrence 1.DF800H
2.CTL reboot
Cause The kernel function was called when the system state flag was made READY when
CTL was rebooted, and the information of the special process was not reflected in local
memory. So CTL wait for long time until local memory is reflected.
Fixed Product/Version Version: 0843/C, 0846/A or later
Category Micro exchange
4 The CTL failure is generated by Micro program error [RCH].

Phenomena When SI re-sync was executed, the CTL failure was generated by Micro program error
[RCH] while executing RD/WR IO processes.
Severity High
Conditions of Occurrence １.Multi core
2. LU made in 1RG when LU are mapping in each core
Cause Logical contradiction is generated by the middle dirty check, When searching for the
cache segments by passing each other in the multi core.
Category Common
5 The controller failure occurred at PS ON.

Phenomena The controller failure occurred at PS ON.
The initialization of PCI Express failed because of the hardware error[DUAL](CTL-x)
Severity Medium
Conditions of Occurrence 1. CTL boot
Cause CPU detected internal bus failure.
Category Common
6 CTL failure occurred when cross path IO is issued

Phenomena CTL failure occurred if cross path I/O is issued between CTL or cores in high load I/O
"H06S00 [DCTL]The completer abort was detected in the completion status[E_IRQ6]
(CTL-0)"
Severity High
Conditions of Occurrence 1.DF800H
2.High load I/O
3.READ I/O operations of cross path IO of about 16KB in transfer length
Cause When the high load IO operation were executed, the buffer on PCI were full by I/F
controller and by the cross path register access, and detecting the time-out of PCI. CTL
failure occurred by PCI bus timeout.
Category CTL Failure
7 ENC failure and system down occurred with the IO operation
during ENC micro exchange, LU switch, or format
test
Phenomena ENC failure and system down occurred with the IO operation ENC micro exchange,
LU switch, and the format tests.
Severity High
Conditions of Occurrence 1.DF800S/M/H
2.LU switch (LU load balance) or cache Directory switch operation(controller
blockage and micro exchange)
3.Under the condition 2, initialization process and the another side's CSDS write
operation crossed each other
4. Under condition 3, the initialization of the flag in another CTL side core is executed
Cause When LU is switched, the flag in 0Y core is cleared by the micro program bug and the
response is not returned to demand origin core of LU switch. Therefore, 1X core keeps
waiting for the response in the demand origin of the LU switch. As a result, Kernel
Processing Error is generated.
Category MICRO-FC
8 The pin over occurred with host IO and ENC micro exchange.
Phenomena The pin over occurred with host IO and ENC micro exchange. "H06J00 [DCTL]The
unexpected completion was detected[E_IRQ6](CTL-0)"
Severity High
Conditions of Occurrence CHK1 occurred
Cause CHK1 generated, flag executing JOB of each PATH number had not been turned off
and HDD device discovery operation was not executed. Therefore, all device reset
piled up in concerned PATH, the PDEV time-out happened frequently with Pin over
Category Common
9 CTL failure generated while sequential WR I/O executed.

Phenomena The CTL failure was generated while sequential WR IO operation was executed.
"H06J00 [DCTL]The unexpected completion was detected[E_IRQ6](CTL-0)"
Severity High
Conditions of Occurrence 1. DF800H
2. Sequential WR IO
3. Heavy load IO operation
4. The data transfer length: about 16KB.
Cause The deadlock of PCI is generated by LSI ASIC of DF, and the CTL failure occurred.
Category Common
10 Watch-dog timeout error occurred with pair delete operation
Phenomena The hardware error occurs by a CTL, a kernel processing error and Watchdog time-out
occur by another CTL, and the subsystem is downed.
Severity High
Conditions of Occurrence １．CTL failure is occurred
２．DF800H
Cause The processing to match the synchronization between two cores causes the deadlock.
Affected Products/Version 0840/A or later
Fixed Product/Version Version: 0845/A or later
Category Common
Changed Part CTL Failure
11 System down is generated by failure of the power supply

Phenomena The system down is generated by failure of the power supply (3.3V) component.
Severity High
Conditions of Occurrence １．Failure of the power supply(3.3V) component
２．When condition 1 is generated; the micro program detects the time-out of the PCI
bridge in the controller.
Cause The micro program mistakes the judgment condition of the failure factor when the
micro program detects the time-out of the PCI bridge, and the system is down.
Category Common
12 With ENC replacement, subsystem down occurred

Phenomena When the ENC was pulled out and was inserted, the subsystem-down was generated
by both of controllers' failure. HH8W00 Backend has been down[All the routes have
been blockaded]
Severity High
Conditions of Occurrence 1.Seqential WR
2.High load IO
3.The data transfer length is about 16 KB
Cause The cross I/O between cores is waited for executing temporarily because of full of
internal IO queue. In this case, the change of the order of the queue is generated, and
the command sinks. As a result, the IO time-out was generated, and Pin over occurred.
Category Common
13 SGT SAS HDD code exchange while offline, LED warning on

Phenomena When SGT SAS HDD firmware exchange was executed with offline, the warning LED
Turn on.
Severity Low
Conditions of Occurrence A. The HDD firmware exchange is exchanged with offline
B. The HDD main program firmware and the HDD servo program firmware are the
same revisions
C. SAS HDD is made by Seagate corporation
Cause If the HDD main program firmware and the HDD servo program firmware are the
same revisions, HDD firmware exchange cannot be executed at all. The warning LED
turned on illegally
Category Common
14 A CTL failure is generated by Micro program error [POM]/ [SNR].
Phenomena A CTL failure is generated by Micro program error [POM]/ [SNR]. HJ2CQG Micro
program error[POM]
Severity High
Conditions of Occurrence 1. Pairs of Snapshot or True Copy Extended Distance exist
2. Hosts are executing I/O to the pairs or Snapshot restoring is executing
3. Single CTL failure has occurred
4. Ownership of a LU not belonging to the pairs defined by condition 1 and 2. Even if
the CTL failure has occurred, it is possible to change the LU ownership because
microcode manages which CTL owns the LU in each CTL.
Cause If pairs of Snapshot or True Copy Extended Distance exist, the data is copied to Data
Pool before new host I/O updates the data on P-VOL. When single CTL failure has
occurred, the table on memory is abnormally updated because of the conflict of the
process of data copy and changing ownership of a LU. As a result, “Micro program
error [POM]” occurs when the incorrect data on the table is found.
Category Common
15 LA error [DRR] occurred on CTL0 while CTL1 was recovered by

dummy replacement.
Phenomena LA error [DRR] occurred on CTL0 while CTL1 was recovered by dummy
replacement. "H20100 Parity generation LA error[DRR]"
Severity High
Conditions of Occurrence 1. Failure of controller's MPU
2. CTL dummy replacement
Cause The header of cache was broken by the failure of controller's MPU while gathering the
trace. The trace was gathered and referring to the broken header after the dummy is
replaced, the trace has been written in an illegal area.
Category Common
16 Error log of Event ID6 output on Windows OS at server reboot

Phenomena The error log of Event ID6 is output on Windows OS at the test of server rebooting.
Severity Medium
Conditions of Occurrence (1)Cross path IO
Cause There is a case for the threshold to improve unjustified counting when I/F controller's
Freeze is executed. Link initialize is executed at threshold over time. Because OS
detected the Linkup event unjustified, the log has been detected.
Category Host Interface

AMS2000 Code 0846B

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AMS2000

MICROCODE VERSION 0846/B

Newly supported features and functions for Version 0846/B

1 Support QE4/IF board on AMS2300

Improvements for Version 0846/B

1 Improved I/O response time in small-scale configurations

The change of contents for Version 0846/B

1 Data reliability improvement

2 The I/O error occurs by LU switch + I/O operation.

4 The CTL failure is generated by Micro program error [RCH].

5 The controller failure occurred at PS ON.

6 CTL failure occurred when cross path IO is issued

9 CTL failure generated while sequential WR I/O executed.

11 System down is generated by failure of the power supply

12 With ENC replacement, subsystem down occurred

13 SGT SAS HDD code exchange while offline, LED warning on

15 LA error [DRR] occurred on CTL0 while CTL1 was recovered by

16 Error log of Event ID6 output on Windows OS at server reboot

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