Automatic Register Transfer Level CAD Tool Design for
Advanced Clock Gating and Low Power Schemes
Yunlong Zhang, Qiang Tong, Li Li, Wei Wang
and Ken Choi
Electrical and Computer Engineering
Illinois Institute of Technology
3301 S Dearborn St., Chicago, IL 60616, USA
{yzhan167,qtong,kchoi12}@hawk.iit.edu
Abstract – Power reduction is nowadays becoming the first
consideration in VLSI design. Low power is one of major
concerns in deeply scaled CMOS technologies. There have been
many methods in very wide rang to achieve this objective. And
the Register-Transfer level (RTL) has become the most effective
stage in low power VLSI design, according to the significant
power optimization impact and accurate power estimation. In this
paper, some respective low power design techniques at RTL are
re-investigated at tsmc 45 nanometer CMOS technology. Clock
gating (CG) is one of the most widely used and effective technique
in RTL low power design. Without the enable signal, bus-specific
clock gating (BSC) and threshold-based clock gating (TCG) are
considered. Also an improved active-driven optimized bus-specific
clock gating (OBSC) is proposed in our laboratory. When the
enable signal is taken into account, this paper explains local-
explicit clock gating (LECG), enhanced clock gating (ECG),
waste-toggle-rate-based (WTR) clock gating and the single
comparator-based clock gating (SCCG) techniques. Operand
isolation is another useful design technique for reducing the
power consumption by blocking some redundant operations.
Memory splitting is an effective design solution for low power
design as well. These techniques have been experimented by using
tsmc 45nm technology library and the proposed low-power RTL
techniques are evaluated at gate level with logic synthesis results.
Keywords – Low power design, RTL, Clock gating, Operand
isolation, Memory splitting
I. INTRODUCTION
Considering Moore’s Law and the trend of industrial
technology, integrated circuit densities and operating speeds
have continued to go up during the past decades of years, and
this change will be unabated [5]. With this rapid progress of
technology, there will be larger chips, more complex design,
faster operation time and then result in tremendously increased
power consuming. Under this circumstance, power reduction
has become the first consideration in VLSI design. According
to infinite electricity resource, reducing power is highly
appreciated for tradeoff between more complex designs and
less power consumption in a proper operation time. There are
many techniques, such as multiple voltages design [9], pre-
computation, clock gating, operand isolation [7] and memory
splitting [8], have been come up with in a wide range from
system level to layout level to achieve power reduction.
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JongEun Jang, Hyobin Jung, and Si-Young Ahn
Epic Solution Inc.
1605 Sang-Am Dong, Ma-Po Gu
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{jhb, jjang}@epicsolution.co.kr
Register-transfer level (RTL) becomes the most proper
stage where power optimization has significant impact and
power estimation is accurate [1].
Fig. 1. Non-CG circuit: (a) Without enable (b) With enable [4]
This paper explains some representative low power techniques
at RTL, other techniques can be referred to any of excellent
references.
For Register-transfer level, digital circuits always contain
some computations which are redundant, in other words,
power reduction can be achieved by reducing these idle circuit
operations [5]. Clock gating (CG) is the most widely used and
effective technique at RTL. Two typical non-CG circuits are
mentioned in [4] as shown in Fig. 1. Fig. 1(a) is the circuit
without enable signal while the other one is with enable signal.
Without the enable signal, this paper explains bus-specific
clock gating (BSC) [2], threshold-based clock gating (TCG)
[3] and optimized bus-specific clock gating (OBSC) [1]
techniques. These techniques reduce the power consumption
by taking switching activity of signals into account. With the
enable signal as shown in Fig. 1(b), this paper includes local-
explicit clock gating (LECG) [4], enhanced clock gating
(ECG) [4], waste-toggle-rate-based (WTR) clock gating [4]
and the single comparator-based clock gating (SCCG) [6]
techniques. Not only all bits of data values at two consecutive
clk periods, but also the enable signal should be considered for
wasted clk toggles in this kind of circuit. Operand isolation
technique reduces power by blocking the propagation of
switching activity through the circuit [7]. Because of the much
less power consumption of operation to the half-size memory
than the full size memories, memory splitting technique can
save the power.
The low power techniques aforementioned are explained in
Section II. Section III shows experimental results followed by
conclusion in Section IV.
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Fig. 2. (a) Bus-specific clock gating (b) Local-explicit clock gating (c) Enhan-
ced clock gating [4]
II. RTL LOW POWER TECHNIQUES
A. Bus-specific clock gating (BSC)
This CG style as shown in Fig. 2(a) is proposed in [2] for
individual flip-flop (FF). The input and output bits are
compared by XOR gates, when the input data are equal to the
current output data, the XOR output is 0 and so does the
output of N-bit OR gate which is used for determine if any bit
changes. So the FF is gated, the power has been saved. On the
other hand, when the input data are different from current
output data, this circuit performs as normal. The AND gate
and the latch safely disable the clock without allowing any
glitch to reach the register clock [16]. However, power
consumption will increase if the output toggle rate of FF is
high which indicates the high switching activity of signal
because of the extra logics.
B. Local-explicit clock gating (LECG)
As shown in Fig. 2(b), this circuit constructed as follows: the
clock of FF is gated by using an AND gate and a latch.
Obviously, when en is low for a significant percentage of the
circuit operation, this technique saves a substantial amount of
power, however, if en is high for a significant percentage of
the circuit operation, the power consumption is increased
because the extra circuit power consumption is outweighs the
savings [4].
C. Enhanced clock gating (ECG)
In Fig. 2(c), ECG combines the gating circuits in BSC and
LECG so that the clock signal of the register is gated as long
as its toggle is wasted [4]. Besides the advantages incurred by
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Fig. 3. Single comparator-based clock gating [6]
the low en signal in a significant percentage of the clock
periods or the low signal switching activity, this gating circuit
which is more complex than LECG incurs more power
consumption when the situations aforementioned are not
emerged.
D. Threshold-based clock gating (TCG)
Comparing with BSC technique which gating all the FFs
without considering signal activities, in [3], Alberrto et al. has
proposed this data-driven clock gating technique to improve
BSC. In this technique, they claim a threshold which is 5% of
output switching activity, which means any FF whose output
toggle rate is less than 5% need to be clustered and gated using
one clock gating cell. The toggle rates of FFs of non-clock
gating circuit need to be tested at first time, and then according
to the list of toggle rate, those FFs are divided into two parts.
E. Optimized bus-specific clock gating (OBSC)
In [1], Li et al. proposes a fine-grained activity-driven CG
methodology which is to improve BSC as well. Unlike TCG,
this technique determines which FFs should be clustered and
gated by taking the relationship of each FF into account [1]. At
first all FFs are clustered and gated, and then the main point in
this fine-grained activity-driven OBSC scheme is as follows:
the larger the FF output toggle is, the less the clock cycles are
wasted, so the earlier that the FF should be excluded from
gating [1]. Apparently, this algorithm results in just N+1
possible CG solutions comparing with the 2N power estimation
results of N FFs. Meanwhile, the minimum power result is the
final OBSC circuit. However, according to the much complex
and densities of the VLSI circuit, its drawback is obvious, this
process takes too much time (e.g. for s15850, one sequential
circuit of ISCAS’89 benchmark, this time will be 28 hours).
F. Single comparator-based clock gating (SCCG)
In [6], Wei et al. proposes a novel single comparator-based
clock gating (SCCG) scheme to enhance the ECG for pipeline.
In the proposed SCCG, enable signal is moved from data path
to control logic, the data signal is analyzed, and only single
comparator is used to implement the clock-gating for all the
pipeline stages. For the proposed SCCG technique, there is an
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Fig. 4. Design with operand isolation
important constraint. If there is a constant input from outside
of the combination logic circuit, the pipeline can work
properly in this situation; however, if there is a variable input
from outside during an intact data transmitting procedure, then
the pipeline could not work properly, because such an input
may change the data consistency in the data path [6].
G. Waste-toggle-rate-based (WTR) clock gating
In [4], a RT level power reduction scheme is proposed. This
technique can be used for any applications that have power
problem when designers use traditional design flow. A novel
wasting-toggle-rate based clock power reduction technique is
introduced and verified along with traditional design flow. The
proposed technique can choose optimal clock-gating style
selectively to minimize the power based on proposed wasting
toggle-rate analysis at RT level, and the optimization is based
on proposed power equations without simulating the design at
gate level [4].
H. Operand isolation
Designs which do not fully utilize their arithmetic datapath
components typically exhibit a significant overhead in power
consumption. Whenever a module performs an operation
whose result is not used in the downstream circuit, power is
being consumed for an otherwise redundant computation.
Operand isolation is a technique to minimize the power
overhead incurred by redundant operations by selectively
blocking the propagation of switching activity through the
circuit [7].
In [7], it discusses how redundant operations can be
identified concurrently to normal circuit operation, and
presents a model to estimate the power savings that can be
obtained by isolation of selected modules at the register
transfer (RT) level as shown in Fig. 4. Based on this model, an
algorithm is presented to iteratively isolate modules while
minimizing the cost incurred by RTL operand isolation.
I. Memory splitting
Fig. 5 shows a memory with a large number of words split
into two smaller memories, each with half the number of
words.
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For most memory architectures, the power of a read or write
to the half-size memory is much less than the power of a read
Fig. 5. A memory with a large number of words split into two smaller
memories
or write to the full size memories. Even though the same
number of reads and writes are occurring in the new
architecture, the power is reduced because each read or write
is on only one of the smaller memories. To implement this
change, replace the single memory with two memories, each
having half the number of words. Select a bit of the address,
usually the MSB or LSB, to operate as a .bank select.. This bit
should be used as the chip enable to one memory, and inverted
to be used as the chip enable to the other memory. This bit
should also be used as the select input to a new multiplexor on
the memory outputs. This mux selects the appropriate memory
bank.
III. EXPERIMENTAL RESULTS
The BSC, TCG and OBSC techniques have been
experimented on all the ISCAS’89 benchcircuits by using tsmc
45nm technology library and Synopsys power complier. Also
the circuits are simulated for 10000 clock cycles (clock
frequency is 250 MHz) with random inputs. Table I reports the
area, delay and power of the non-CG circuit, the BSC circuit,
the OBSC circuit and the TCG circuit of each ISCAS’89
circuit. Table II gives the comparative results of the three CG
circuits versus the non-CG circuit.
As shown in Table II, the traditional BSC circuit will
increase power for many circuits, and the average power is
increased by 208.96%. On the other hand, compared to the
non-CG circuit, the OBSC circuit reduces 26.95% power on
average for all circuits, which is 16% more than the TCG
circuit. The area and delay of the OBSC circuit are increased
by 14.44% and 5.77% separately. Meanwhile, we should know
the impact of improvement of synthesis process.
For operand isolation, a simple benchmark is shown in Fig.
4, and we use tsmc 45nm technology library and Synopsys
power complier. Also the circuits are simulated for 10000
clock cycles (clock frequency is 250 MHz). As shown in Table
II, AND isolation style gives the maximum power reduction
which is 17.67% with only 3.17% delay increase, and isolated
candidate is a1.
For memory splitting, a simple benchmark is shown in Fig. 5
and we use tsmc 45nm technology library and Synopsys power
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 TABLE I
EXPERIMENTAL RESULTS FOR ISACS’89 CIRCUITS

Circuit non-CG BSC OBSC TCG

Area Delay Power Area Delay Power Area Delay Power Area Delay Power
[μm2] [ns] [μW] [μm2] [ns] [μW] [μm2] [ns] [μW] [μm2] [ns] [μW]
s27 60.54 0.37 29.50 87.29 0.43 33.43 73.21 0.41 28.09 60.54 0.37 29.50
s298 407.82 0.55 128.01 435.04 0.50 118.09 464.61 0.81 81.57 455.22 0.76 83.29
s344 448.65 0.68 174.49 538.76 0.78 204.30 491.83 0.78 157.45 464.61 0.65 172.62
s349 443.49 0.68 174.74 547.67 0.86 204.97 495.11 0.77 158.48 459.44 0.65 172.95
s382 518.58 0.58 163.29 581.46 0.46 154.78 637.78 0.88 85.46 618.07 0.69 86.00
s386 325.69 0.57 78.96 371.22 0.74 87.96 367.93 0.60 67.34 361.83 0.62 72.10
s400 518.58 0.57 161.94 590.85 0.46 155.49 626.05 0.75 84.20 618.54 0.81 84.74
s420 482.44 1.05 122.58 488.07 0.13 84.05 488.54 0.31 57.36 485.73 0.38 57.36
s444 515.76 0.59 163.49 600.70 0.46 156.19 630.27 0.87 87.20 635.43 0.78 89.40
s510 608.21 0.84 139.31 649.51 0.98 141.66 636.37 0.73 133.25 608.21 0.84 139.31
s526 618.07 0.67 167.10 657.49 0.58 154.64 710.05 0.87 87.43 718.97 0.79 88.41
s526n 620.41 0.67 165.83 654.67 0.58 153.72 711.93 0.87 87.69 719.44 0.82 87.76
s641 431.29 0.94 140.25 538.29 1.16 155.11 498.40 1.10 103.10 498.40 1.10 103.10
s713 431.29 0.94 140.68 535.94 1.16 156.42 498.40 1.10 103.59 498.40 1.10 103.59
s820 715.21 0.83 115.79 741.02 0.92 111.45 720.84 0.83 97.36 747.59 0.87 103.42
s832 703.95 0.83 112.63 744.31 1.01 106.35 726.48 0.90 94.56 726.48 0.90 94.56
s838 1002.42 1.97 223.21 1001.96 2.07 142.53 1005.24 0.38 67.35 1005.24 0.38 67.35
s953 1161.99 0.84 282.19 1467.97 1.10 296.56 1388.66 1.10 219.47 1256.79 1.02 238.60
s1196 1371.29 1.13 362.84 1512.08 1.14 410.50 1406.96 1.14 347.16 1387.72 1.05 352.35
s1238 1348.30 1.11 364.21 1502.23 1.20 408.73 1403.68 1.20 348.34 1386.78 1.01 358.00
s1243 2060.23 2.79 677.49 2277.51 2.87 751.12 2331.48 2.45 513.93 2321.63 2.51 514.88
s1488 1426.67 0.99 214.03 1429.49 1.04 194.72 1429.49 1.04 194.72 1445.91 1.04 206.45
s1494 1440.28 1.07 219.48 1451.54 1.08 199.61 1451.54 1.08 199.61 1462.81 1.09 212.54
s5378 4595.39 0.92 1770.87 5468.28 1.14 2080.89 4921.55 1.17 1257.17 4915.45 0.99 1260.99
s9234 3592.49 1.08 1069.87 6993.04 1.36 1916.52 6409.70 1.42 751.81 6456.63 1.48 820.70
s13207 11455.61 1.67 4468.86 11420.88 1.62 4467.97 14186.94 1.85 2641.32 14272.82 1.57 2978.21
s15850 10934.69 2.86 3482.67 10972.70 2.86 3523.70 12628.86 2.17 2244.16 13258.66 2.04 2880.70
s35932 31954.64 3.82 15429.47 45263.98 2.96 242558.76 37378.34 2.06 11823.30 34237.31 2.22 13844.43
s38417 31616.74 1.89 12763.25 44359.17 2.43 316289.90 44718.19 2.41 6680.10 41069.38 2.39 56389.14
s38584 29443.41 3.25 13201.90 46890.58 2.91 320556.78 30544.39 1.71 12540.20 31825.11 2.78 12911.38

TABLE II splitting are the applicable techniques for low power VLSI
POWER CONSUMPTION AND REDUCTION VS. AREA AND DELAY
design.
circuit Power Delay Area
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