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Technique used to
• Instructions are
fetched from the
enable one instruction cache
Prefetch/Fetch
instructionandtoaligned in
complete withprefetch
each buffers for
decoding.
clock cycle
• Instructions are
decoded into the
Pentium's internal
Decode 1 instruction format.
Branch prediction
also takes place at
this stage.
…is divided into five (5) stages:
• Same as Decode 1, and
microcode ROM kicks in
Decode 2 here, if necessary. Also,
address computations
take place at this stage.
• Integer hardware
Execute executes the
instruction