II\~RI

INTERNATIONAL RECTIFIER

HEXFET S
*

'lAIABOOK
POWER MOSFET
APPLICATION AND PRODUCT DATA

FIRST PRINTING
HDB-2

PUBLISHED BY
INTERNATIONAL RECTIFIER, 233 KANSAS ST., EL SEGUNDO, CALIFORNIA

The information presented in this DATABOOK is believed to be accurate and reliable. However, International Rectifier can assume no
responsibility for its use; nor any infringement of patents. or other rights ofthird parties which may result from its use. No license is granted
by implication or other use under any patent or patent rights of International Rectifier. No patent liability shall be incurred for use of the
circuits or devices described herein.

Copyright 1982, International Rectifier Corporation, Semiconductor Division. EI Segundo. California. All rights reserved.
Reproduction or use of editorial or pictorial content without express permission in writing is prohibited.
*HEXFET is the trademark for International Rectifier Power MOSFETs.

PRINTED IN U.S.A. 9182 M75

A-1
PREFACE
In mid-1979, International Rectifier
introduced a new series of power MOSFETs
to industry that opened vast, new
opportunities for designers of any
equipment, system or power supply that
had, until that time, been limited by the
performance characteristics of bipolar
transistors.
International Rectifier's "HEXFET" technology,
so named because of a structure based on
thousands of hexagonal cells in densities
up to 500,000 per square inch, brought
the first MOSFETs to the power range
capable of matching the on-resistance of
bipolar transistors. For the first time,
A-2
the advantages of power MOSFETs could be
utilized without a sacrifice in efficiency.
This technological feat has sparked a
revolution in design, capitalizing on the
advantages of voltage control, extremely..
high switching speeds, temperature stability
and the rugged physical characteristics of
power MOSFETs. The~e ar~ few circu!ts
previously designed with bipolar transistors
that cannot now be designed with MOSFETs
to perform far better, in less space, with
fewer components, and without the complexity
of protective circuits required by the
bipolar counterparts.
Along with thiS contribution to technology,
 INTERNATIONAL RECTIFIER I
I nternational Rectifier brought a commitment
to power MOSFETs that has made the
company today's leader in the field.
A commitment to quality. A commitment to
production that enabled the company to ship
more power MOSFETs in the 25-watt and
above range than all other power MOSFET
manufacturers in the world combined during
1980. A commitment to distribution that
has put yesterday's laboratory achievement
onto Distributors shelves around the world.
Perhaps the most convincing proof of the
total commitment International Rectifier
has made is pictured below. This new
structure houses today's largest state-
A-3
ICiR I
of-the-art, high technology facility
in the world devoted exclusively to power
MOSFET wafer fabrication. On stream now,
its initial production capacity is sufficient
to supply today's entire industry requirements
for power MOSFETs, and is expandable
to meet all demands to be experienced during
the evolution from bipolar transistors to
power MOSFETs in the equipment of tomorrow.
This DAT ABOOK lists todays broadest line
of readily available power MOSFETs. More
types and packages will follow to make your
design job easier and your products better.
We're committed to that.
TABLE OF CONTENTS

POWER MOSFET APPLICATION DATA Page

Qualtty, Reliability and the HEXFET ••..........••...........•.•.•..•.......... A-6
CHAPTER 1 Applying International Rectifier Power MOSFETs ............... A-8
CHAPTER 2 The Do's and Don'ts of Using Power HEXFETs .....•......... A-19
CHAPTER 3 Current Ratings, Safe Operating Area, and High Frequency
SWitching Performance of Power HEXFETs ........•......... A-25
CHAPTER 4 A New Gate Charge Factor Leads To Easy Drive
Design For Power MOSFET Circuits ........................ A-36
CHAPTER 5 Gate Drive Characteristics and Requirements
for Power HEXFETs ...................................... A-40
CHAPTER 6 The HEXFET's Integral Body Diode - Its Characteristics
and Limitations .......................................... A-48
CHAPTER 7 An Introduction to International Rectifier
P-Channel HEXFETs ...........................•......... A-60
CHAPTER 8 Understanding HEXFET Switching Performance .............. A-65
CHAPTER 9 Simplified HEXFET Power Dissipation and Junction
Temperature Calculation Speeds Heatsink Design ............ A-80
CHAPTER 10 A Universal 1 OOkHz Power Supply
Using a Single HEXFET ................................... A-87
CHAPTER 11 A Chopper for Motor Speed Control
Using Parallel Connected Power HEXFETs .........•......... A-99
CHAPTER 12 High Efficiency, High Voltage Switching
USing a Cascode Combination of HEXFET and
Bipolar Transistor ...•................................... A-111
CHAPTER 13 Linear Power Amplifier Using Complementary
HEXFETs ......... '.•..........................•........ A-123
CHAPTER 14 Transformer Isolated HEXFET Driver
Provides Very Large Duty Cycle Ratios ..................... A-128
CHAPTER 15 Custom Assembly of HEXFET Dice ........................ A-130

A-4
 INTERNATIONAL RECTIFIERIJ:\~RI

HEXFET PRODUCT DATA Page

HEXFET SELECTOR GUIDE
By Package, Voltage Range and "On" Resistance .•.......................•• A-139
INDEX BY VOLTAGE RATING
TO-3 Packaged HEXFETs ............................................•. A-140
TO-220AB Packaged HEXFETs .............•..........................•. A-141
NUMERICAL INDEX
TO-3 Packaged HEXFETs .............................................. A-142
TO-220AB Packaged HEXFETs .............•..........................•. A-143
"HEXDIP" Dual I n-Line Packaged HEXFETs ...•..........................•. A-144
TO-39 Packaged HEXFETs ....................................... .' ...•. A-144
Complementary Pairs (TO-220AB Package) ..•............................ A-144

MIL-SPEC HEXFETS
JAN, JANTX, JANTXV and C.E.C.C. Test Capabilities .......................... A-146
HEXFETs to JAN, JANTX, JANTXV and C.E.C.C. Specifications ................. A-149
Radiation Resistance of HEXFETs .......................................... A-150

INTERNATIONAL RECTIFIER TEST CAPABILITIES

Life Tests and Power-Age Capabilities ...................................... A-154
Environmental Test Capabilities ............................................ A-154
Military Test Standard Capabilities .......................................•. , A-155

HEXFET DEVICE CHARACTERISTICS AND RATINGS . ........ 0-1 thru

0-305

HEXFET DATA REGISTRATION FORM . ........................... 0-313

A-S
Quality, Reliability, and the HEXFET

It is International Rectifier's stated 100% Reliability Tests determine the ultimate process limits;
objective to make the HEXFET the Before any part is released for cus- this guarantees that the parts are
most reliable semiconductor device tomer shipment, each and every rugged and that there has been no
ever manufactured. In order to meet wafer and assembly lot goes through 'drift' in the process parameters (See
this goal IR budgets approximately an extensive series of tests designed table 2). Finally, 40 parts are kept
$1,000,000 a year to measure, record to indicate the ultimate reliability with all the lot travelers and test
and improve the reliability of our- that can be expected. This is caJled results so that if a future question
HEXFET. our Reliability Certification Pro- requires data we did not take we can
gram. always run a statistically valid test
HEXFET Quality Today and correlate our findings with those
All lots are screened at outgoing From each lot a sample of 80 pieces of our customer.
inspection to a 0.1% AQL. This cor- is taken. Forty pieces are put through
responds roughly to a 1000 part per a series of accelerated life tests (the If any lot does not meet any of our
million defect rate. The purpose of tests are listed in table 1). Another high standards during these tests it
screening HEXFETs to such tight 40 parts are destructively tested to will not be shipped.
levels is to provide our customers
with parts that will no longer require
an incoming inspection, hence re-
sulting in a significant savings and Table 1: Reliability Certification - Accalerated Teats
reduced inventory.
TEST SAMPLE SIZE REJECT ON PURPOSE
100% Visual Inspection
HTRB 40 Detect temperature dependent
All HEXFETs, commercial or Hi- TJ=150°C failure modes and any change in
Rei, plastic or hermetic, are 100% performance parameters with temp.
pre-cap or pre-encapsulation in-
spected. This inspection ensures GATE 40 Check the reliability of gate oxide
proper wire bond placement, no STRESS and oxide/silicon Interface.
damage to the semiconductor chip, TJ=150°C
as well as general appearance of the
die bond and die coat, where appli-
cable. International Rectifier's relia-
bility group has correlated these
inspection criteria to improved long Table 2: Reliability Certlflcatlo" - Destruction Tests
term reliability results on such tests
as HTRB (High Temp Reverse Bias) TEST SAMPLE SIZE REJECT ON PURPOSE
and gate stress. SOA 10 Check power handling
FAIL POINTS capability
Traceability
All parts are tested, marked and GATE 10 Check oxide integrity.
shipped so as to maintain wafer lot DIELECTRIC
and assembly lot traceability. Inter- STRENGTH
national Rectifier feels lot traceabil-
ity is an essential part of our reliabil- AVALANCHE 10 Check ability to handle
ity program so that, if, anytime in ENERGY inductive overloads.
the future, a customer has a problem THERMAL 10 Check Integrity of
or a question concerning HEXFETs RESISTANCE header/solder/die
they have received, IR can attempt
interface.
to correlate, the effect with the part's
process history.

A-6
- ---
 INTERNATIONAL RECTIFIER IIC~RI

Long Term Reliability Reports

Finally, International Rectifier pub- Table 3: Reliability Report
lishes quarterly HEXFET Reliability TEST CONDITIONS PURPOSE
Reports which summarize all the
reliability data we have taken during 85/85 .85 Vos Check ability of non-hermetic
that period. Once a year the results are (plastic packages) 85% relative packages to operate with
summarized. The reliability data TJ=85°C humidity bias in high relative humidity.
accumulated in this report is outlined 1000 hours
in Table 3. Reliability Reports are
available to all customers on request. Power Cycles Determine number of power
cycles the package/solder/die
Specifying a HEXFET power combination can withstand.
MOSFET for your design assures
the ultimate in reliability and HTRB Determine failures per
performance. 1000 hrs. for each failure
mode and temperature
dependent activation energy.

A-7
CHAPTER 1
APPLICATION NOTE 930
Applying International Rectifier's
Power MOSFETs
By BRIAN R. PELLY
International Rectifier's Power
MOSFETs open the door to the
design of advanced products by offer-
ing the superior characteristics of
Field Effect Transistors at true high
power levels. Power MOSFETs sim-
plify circuitry because they are
voltage-controlled devices and re-
quire only very small instantaneous
currents from the signal source. They
achieve switching times of less than
100 nanoseconds at high current lev-
DRAIN
"TRANSISTOR"
CURRENT
DIODE CURRENT
Figure 1. Basic HEXFET Structure
els. They have great ruggedness
because of the absence of the second
breakdown failure mechanism of
bipolar transistors. In parallel opera-
tion they inherently "current share"
rather than "current hog." The stabil-
ity of the gain and response time
characteristics over a wide tempera-
ture range is outstanding. The net
result is a radically advanced power
transistor of universal application
capability.
DRAIN
"TRANSISTOR"
CURRENT
A-8
HEXFET'M Tectmology
International Rectifier now offers
a truly advanced line of power
MOSFETs termed the HEXFETs'·.
The HEXFETs are IR's second gen-
eration power MOSFET design and
feature uniquely advanced technol-
ogy. The HEXFET technology
achieves both new high power
records in switching ratings for field
effect transistors and new economies
in MOSFET production costs. IR's
The HEXFET Structure
The HEXFET surface is character-
ized by a multiplicity of closed hex-
agonal source cells (over SOO,OOO
per square inch) from which the
name HEXFET is derived. In crqss
section, the HEXFET is based on a
doublEHliffused (DMOS) structure.
A channel is formed by double dif-
fusion at the periphery of each hex-
agonal source cell. An insulating
gate oxide layer covers the channel.
A silicon gate then overlays both the
insulating oxide and channel. The
silicon gate in turn is insulated from
the source by an additional oxide
layer. All of the hexagonal source
cells are then parallel connected by
a continuous sheet of metalization
which forms the source terminal.
Transistor action occurs by pene-
tration of an electric field into the
channel area which modulates the
conductivity between drain and
source. Conventional current flow is
from the drain substrate, across the
channel surface, and vertically out
the source terminal.
 COLLECTOR
ICURRENT
FLOW
~~
I jCURRENT
BASE
• GATE
EMITTER
(a) NPN BIPOLAR TRANSISTOR (b) N-CHANNEL MOSFET
Figure 2. Electrical Symbols for Bipolar and MOSFET
HEXFETs set the stage for large
scale usage in applications which
previously could be handled only by
the bipolar technology.
Until recently, large-area MOSFET
devices combining the low on-
resistance and the high-voltage char-
acteristics of a true power transistor
could not be fabricated. With IR's
HEXFET technology, however, on-
resistances as low as 0.05 ohms are
possible at the 100 volt level. Voltage
ratings as high as 500 volts are possi-
ble by making a tradeoff with higher
on-resistance. HEXFETswitching
ratings in excess of 4 kilowatts are
available in a single device.
The HEXFET Structure
As implied, the HEXFET struc-
ture involves a hexagonal device
geometry. At the core is a radically
new hexagonal cellular structure,
illustrated diagrammatically in Fig-
ure I. It is this hexagonal geometry,
along with advanced MOS process-
ing, that gives the HEXFET an on
state resistance, RDs(o.), one-third of
that possible with the best previous
MOSFET technology, in a given die
size. At a given current level, there-
fore, the HEXFET can achieve a
forward voltage drop quite compa-
rable to the collector-emitter satura-
tion voltage of high performance
bipolar transistors that have about
the same die size.
A planar, non V-groove structure,
the HEXFET conducts current verti-
cally. For high packing density, it
uses a silicon-gate structure. The
density of the hexagonal source cells
on the top surface of the silicon die is
over half a million cells per sq uare
inch. Electrons flow from a source
cell through the channel which is
DRAIN
-J-...
J
••• PRODUCES VOL lAGE PRODUCES
CURRENT AT GATE CURRENT
FLOW
1'7"<'~ [7"
1
VOLTAGE
SOURCE
(a) BIPOLAR TRANSISTOR (b) MOSFET
SOURCE
Figure 3. Bipolar Transistor is Current-Driven,
MOSFET is Voltage-Driven
around the periphery of that cell and produce a flow of current in the col-
then into the drain body. The bottom lector. The amount of drive required
surface of the drain body is in electri-
to produce a given output depends
cal and thermal contact with the upon the gain, but invariably a cur-
header. rent must be made to flow into the
base terminal to produce a flow of
The efficient hexagonal source pat- current in the collector.
tern, the silicon gate, and advanced
MOS processing techniques all com- The MOSFET is fundamentally
bine to produce the HEXFETs' different; it is a voltage-controlled
unique performance characteristics. device. A voltage must be applied
between the gate and source termi-
nals to produce a flow of current in
Some Basic Considerations the drain, as illustrated in Figure
As we have seen, the HEXFET is 3(b). The gate is isolated electrically
IR's advanced design of power from the source by a layer of silicon
MOSFET. Power MOSFET s are oxide. Theoretically no current flows
majority carrier semiconductor de- into the gate when a DC voltage is
vices, and their construction and applied to it - though in practice
principles of operation are funda- there will be an extremely small leak-
mentally different from those of tra- age current, in the order of nano-
ditional bipolar transistors, which amperes.
are minority carrier semiconductors.
These fundamental differences must With no voltage applied between
be understood if full advantage is to the gate and source electrodes, the
be taken of the MOSFETs' special impedance between the drain and
performance features. source terminals is very high, and
only a small leakage current flows in
the drain until the applied voltage
MOSFET Symbol and Terminology exceeds the drain-to-source ava-
lanche voltage. This is illustrated in
The collector, base and emitter
terminology for the terminals of a Figure 4.
bipolar transistor is replaced by
drain, gate, and source, respectively
for a MOSFET. Figure 2 shows tile
~ vGS" 0
circuit symbol for an N-channd a:
MOSFET, and makes a comparison a:
:::>
with a conventional bipolar tran- U LEAKAGE CURRENT
Z - MICROAMPS
sistor.
a:
"
o
Driving the Power MOSFET ORAIN -SOURCE VOL T AGE t
The conventional bipolar transis- AVALANCHE
VOLTAGE
tor is essentially a current-driven
device. As illustrated in Figure 3 (a),
a current must be applied between Figure 4. Drain-Source
the base and emitter terminals to Blocking CharacteristiC
A-9
 When a voltage is applied between
the gate and source terminals an
electric field is set up within' the
MOSFET. This field modulates the
resistance between the drain and
source terminals, and permits a cur-
rent to flow in the drain in response
to the applied drain circuit voltage.
The amount of current that flows
depe.nds upon the amount of voltage
~pphed to the gate, assuming that the
Impedance of the external drain cir-
cuit is not limiting.
.Because the gate draws only a
minute DC leakage current the DC
curre~t gain is extremely high, typi-
cally In the order of 109 • In fact, this is
a rather meaningless parameter for a
power MOSFET, and it is not nor-
mally used. Because a flow of current
in the drain is produced essentially by
a voltage applied to the gate, a more
useful parameter for the MOSFET is
the transconductance. This is the
change of drain current brought
about by a I volt change of gate
voltage.
The extremely low drive current
requirement ofthe power MOSFET
and the ~ssociated e~tremely high
power gain, are a major advantage
~ver the conyentional bipolar tran-
sistor or Darhngton. This feature will
often make it possible to drive the
power MOSFET directly from
CMOS or TTL integrated circuit
logic.
The Static Operating Characteristics
The fundamental drain-source
operating characteristics of the
power MOSFET are illustrated in
Figure 5(a). For comparison, Figure
5(b) shows the corresponding col-
"CONSTANT CURRENT"
>-.
~
a'"z
~c
DRAIN-SOURCE VOL TAGE
(8) POWER MOSFET
Figure 5. Comparison of Idealized Output Characteristics of Power MOSFET
and Bipolar Transistor
lector-emitter characteristics for a
conventional bipolar transistor.
F or any given value of gate voltage
there are essentially two clearly
separate regions on the drain current-
voltage characteristic (with an inter-
mediate zone that connects the two).
The first is a "constant resistance"
region. As the drain-to-source volt-
age is increased, the current in-
creases almost proportionately,
though in practice the resistance does
increase at higher currents. At a cer-
tain current level, however, a channel
pinchoff effect is reached within the
device, and the operating characteris-
tic moves into a constant current
region.
The bipolar transistor also exhibits
a generally similar type of collector
characteristic. It does not, however,
show a truly resistive effect in its sat-
uration region, nor does it exhibit
nearly such a well regulated constant
current characteristic.
For switching applications the
On-Resistance RoS(ON) of the p~wer
MOSFET is obviously an important
characteristic because it determines
the power loss for a given drain cur-
rent. The lower the On-Resistance
t~~ higher the current handling capa-
blhty of the device. On-Resistance is
thus an important "figure of merit" of
the power MOSFET.
Threshold Voltage and
Transconductance
Inspection of the static drain-
source operating characteristics of
Figure 5 reveals that as the gate-to-
source voltage is increased from zero
initially the drain current does not
I.
V GS
t
9V
•
1.2A
1.0A
.?
8V >-.
G8A
;l;
g;
7V
a G6A
6V
'"g O.4A
5V ~c
0.21'
4V " Cial reverse-biasing. All units have a
3V
COLLECTOR-EMITTER VOLTAGE, VeE
(bl BIPOLAR POWER TRANSISTOR
A-10
.. /
f--JJ06EcLLSE1sT
•
V~S:25V III 7
VI
, 7)7
711
, !.
V/
.~:.,,,,,c A
~~ 7
T = 25°C
J
TJ = ~!i!)OC
_ I ~V
6 • 1.
VGs • GATE TO SOURCE VOLTAGE IVOLTSt
Figure 6. Transfer Characteristics (IRF130)
increase significantly. Only once a
certain threshold gate voltage has
been reached, does the drain current
start to increase appreciably.
This i.s iIIustrat~d more clearly by
the typical relationships between
~rai~ current ~nd gate voltage shown
In.Flgure~. It IS seen that in the oper-
atmg region beyond the threshold
gate voltage, the relationship
between the drain current and- the
gate voltage is approximately linear.
Stated another way, the rate of
change of drain current with gate
voltage - the transconductance
referred to earlier - becomes rela-
tively constant at higher values of
drain current.
Features of IR Power MOSFETs
Basic Characteristics
Tabl~ I shows t.he ~vailable types
at the hme ofpubhcahon of this arti-
cl~, Sept~mber, 1979. Other types
Will contmue to be introduced, and
the reader should check with IR for
the latest product information.
All IR's MOSFETs will conduct
their rated continuous drain current
lo! with less than 10 volts, VGS, ap:
phed from gate-to-source. Conduc-
tion will begin before 3 volts VGse.h),
threshold voltage is applied to the
gate. The threshold voltage is always
greater than I volt, which allows
leakage currents from a previous
stage to be easily bypassed to ground.
(\ cutoff condition of the power stage
I~ thereby assured without any spe-
maximum junction operating
temperature of 150°C.
Rated at lOOV, 28A continuous
and 70A pulsed, the IRFI50 (Table
1) brings on-resistance down to the
lowest value to date of any power
~OSFET ~0.055~maximum. Typ-
Ical on-resistance, Just 0.040, pro-
duces a 1.0V saturation-voltage drop
 Oata Sheet Oata Sheet Oata Sheet Oata Sheet
PO 9.302 PO 9.304 9.303 PO 9.305
PARAMETER
IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF IRF
330 331 332 333 350 351 352 353 130 131 132 133 150 151 152 153
VOS Orain·Source
Voltage
(Max.) V 400 350 400 350 400 350 400 350 100 60 100 60 100 60 100 60
10 Continuous Orain
Current
(Max.) A 4 3.5 11 10 12 10 28 24
10M Pulsed Orain
Current
(Max.) A 8 7 25 20 30 25 70 60
ROS(on) On·State
Resistance
(Max.) Ohms 1 1.5 0.3 0.4 0.18 0.25 0.055 0.08
PD Power Dissipation
(Max.) W 75 150 75 150
9fs Forward
Transconduclance
(Typical) Mhos 3.5 9 5 10
td(on) Turn on Delay
Time
(Typical) ns 50 60 50 60
tr Rise Time
(Typical) ns 100 150 150 200
td(off) Turn off delay
time
(Typical) ns 100 400 100 300
If Fall time
(Typical) ns 100 150 150 200
Ciss Input Capacitance
(Max.) pF 1000 4000 1000 4000

Teble1. Ratings and Characteristics of IR's High Current HEXFETs. September 1979

at 25A, which is low enough to com-
pare with the VVE(SAT) of a bipolar
transistor of similar size, and lower
'than that of a Darlington transistor.
Such a small forward voltage drop
is particularly impressive in light of
the fact that the HEXFET requires
only nanoamperes of gate drive, not
the amperes of base drive a bipolar
needs. In addition, the MOSFET
does not suffer the loss of switching
speed the bipolar does when driven
hard into saturation.
The IRF350 (Table I) isa high vol-
tage version of the die size used for
the IRFI 50 transistor. Rated at 400V
and IIA continuous, 25A pulsed, the
IRF350 has a maximum on-
resistance of 0.30n. Moreover, an
ability to switch 4.4kW continuously
makes the IRF350 by far the highest-
power MOSFET available anywhere
in the world at the time of writing.
At a case temperature of 25°C,
both of these HEXFETs have a con-
tinuous dissipation rating of 150W.
Thermal impedance, from junr.tion
to case, is 0.S3°C/W. Both the
IRFI50 and IRF350 families are in
standard TO-3 metal cases, with
copper base and 0.06iu. diameter
pins for high electrical and thermal
conductivity.
The lower power IRF130 and
IRF330 families provide voltage rat-
ings and maximum on-resistance
values essentially equivalent to the
first generation IRFIOO and IRF300
MOSFET families (now obsolescent).
The HEXFETs accomplish the speci-
fications with a transistor die about
one-third the size of the original
MOSFET types.
Able to handle 12A continuous,
30A pulsed, the 100V IRFI30 holds
on-resistance to a maximum o.lsn.
And providing greater blocking volt-
age and lower current capability, the
IRF330 is rated at 400V and 4.0A
continuous, S.OA pulsed. Its maxi-
mum on-resistance is LOn.
At a case temperature of 25°C,
these lower power HEXFETs can
dissipate 75W of dc power. Their
internal thermal impedance is
1.6°CfW. Again, the package is the
industry-standard TO-3 case, with
0.04in diameter pins.

A-l1
 (8) SWITCHING TIME TEST CIRCUIT
PULSE
Vi
GENERATOR
r-----'
I
son I 0---+ TO SCOPE
I
I Vp
___ .J
I son IDl 0.01s}
HIGH FREQUENCY
L_ SHUNT
(b) THEORETICAL SWITCHING WAVEFORMS
- - - JI __________ I "INTERNAL"
""____ VOLTAGE,V
"'.........::==V::,i==~~,.-_ __
THRESHOLO
VOLTAGE ....,
=:!:·:...;;;~~:i========t.F~t"!!'''''";;VOLTAGE
Figure 7. Switching the MOSFET
Switching Times
MOSFET power transistors are
much faster than bipolar power tran-
sistors of comparable size, primarily
because they do not have minority
carrier delay times. The response
times of MOSFETs are determined
primarily by the device capacitances,
and secondarily by such factors as the
extremely short channel transit time
of the electrons.
The input capacitance, C", is the
primary factor which determines the
response time of a MOSFEt:
Although MOSFETs can be con-
trolled by extremely low currents (i.e.
high source impedances), the rela-
tively long charge and discharge time
of the input capacitance, C .., results
in a tradeoff of response time against
extreme sensitivity. A first order
approximation of the response time
of a MOSFET can be made by de-
termining the time constant which
results from the input capacitance
times the effective source impedance.
Figure 7 shows typical switching
waveforms of an IRF330 when
driven by a 500 nanosecond-wide
pulse. A good first order understand-
ing of the switching response times
leJlon" t r, tdlon.. and tr, can be made by
considering the power MOSFET an
ideal switch with a 3 volt "on" thresh-
old. The output current can be con-
sidered controlled, without delay, by
the instantaneous gate voltage which,
in turn, is controlled by the time con-
stant formed by Rinpul xC...
With these concepts in mind, the
switching waveshapes of Figure 7(b)
and the response times can be more
+2SV
....
z
w
-
",,,,
'"
IRF330 a~
z ~ 1.0
.~ ~
c
.P
.... 0
~2:.
ORIVE
zw
-'"
p
.;;~
GATE
DRAIN
CURRENT
easily understood. The turn-on
delay, tdlon" is primarily the time for
the transistor gate capacitance to be
charged by the control signal to the
threshold level of 3 volts maximum.
The rise time, t" is the gate charging
time required to drive from the thresh-
old voltage, through the linear con-
trol region, to the gate voltage (typi-
cally 5 to 8 volts) required for full
conduction of the drain current. In
turn-off the procedure is reversed,
and the turn-off delay time, tdlorr.. is
primarily the time required for the
gate capacitance to discharge from
the gate overdrive saturation voltage
(typically 10 volts) to the active gate
control region (typically 5 to 8 volts).
Finally, the fall time, tr, is primarily
the time delay required for the input
capacitance to discharge through the
active control region to the gate
threshold voltage.
Figure 8 shows typical relation-
ships for the IRF330 between the
3OOr----,--=-,...----,---.....,
10
AMPLITUDE Of INPUT GATE SIGNAL. VGS (VOL TSI
Figure 8. Typical relationships between
Switching Times and Applied
Gate Voltage (lRF330)
A-12
2.0 I- VD~
= 2JV
-
RL = l1f!
(-TJ =125 0 C
10
h
~
1\
1I \
r ", VI
~
SEE FIG. 13 \
...J
YSTclRCUIT
\
o
>
f'\.
200 400 600 800
t. TIME (NANOSECONDS)
(e) TYPICAL ACTUAL SWITCHING WAVEFORMS
amplitude of the applied gate voltage
signal, the turn off delay time, the fall
time, and the rise time of the drain
current, with the simple "resistive"
gate drive circuit shown in Figure 7.
Note that the turn off delay time
increases with increasing gate drive,
for the reasons already explained.
The rise time of the drain current, on
the other hand, decreases with
increasing gate drive; this is because
the higher the applied gate drive sig-
nal the faster the gate to source volt-
age reaches the level needed to sup-
port the drain current. The fall time
of the drain current remains practi-
cally constant with applied gate
drive; this is because the decay of the
gate-to-source voltage below the
point at which the drain current 10
can no longer be maintained, is prac-
tically independent of the amplitude
of the applied gate signal.
Typical relationships between
switching times and gate circuit re-
15
GATE RESISTANCE. FIG IOHMSI
Figure 9. Typical relationships between
Switching Times and Gate
Circuit Resistance (IRF330)
sistance are shown in Figure 9. Pre-
dictably, the higher the gate resist-
ance, the longer the switching times,
because of the longer time constant
Ro C ...
Simple Capacitive Speed-Up Circuit
The alert designer will realise that
circuit techniques for forcing the
charge on C"" give a means of con-
trolling the response time of the
MOSFET, or alternatively the input
impedance level at which a given
response time occurs.
~
NPUT
GATE
___ SIGNAL
",
Figure 10. Gate Speed-up Circuit
Figure 10 shows a simple gate
"speed-up" circuit. The circuit pro-
duces a significant reduction in the
switching times, at the expense of the
need for an increased amplitude of
input gate signal, and an increased,
(but still comparatively low) current
drain on the drive source. When
switching on, the capacitor C initially
provides a low impedance path for
the applied gate pulse, bypassing the
resistor R2, and thus the input capaci-
60
FALL!,U
~ 40
~\..p....
§ ,/'"
~ 30
~
~
;: 20
", I.
R2
C = 0Ol ... f
'0
'00
Figure " . Values in Gate Speed-up Circuit and Switching Times (IRF330)
tance C,,, of the MOSFET is rapidly
charged. When switching off, the
capacitor C is charged positively on
its left-hand terminal; the charged
capacitor forces a discharge current
through the input capacitance of the
MOSFET, thus making it switch off
rapidly.
A point to remember about this
gate speed-up circuit is that to be
effective it does require an increase in
the amplitUde of the source signal
voltage, because of the voltage divid-
ing effect of RJ with R, and R2.
Another point is that the resistor RJ
draws a continuous current from the
V· gate drive source. Clearly it is desir-
able that the value of RJ should be as
high as possible. Figure 11 shows typ-
ical switching times for different
values ofR" for a given values ofR"
R2 and C. It is seen that very fast
switching times - in the order of 50
nanoseconds - can be obtained with
the gate-to-source resistance R3 as
high as 10k Ohms. This represents a
continuous current drain on the gate
drive source of about I rnA. This is an
order of magnitude lower than the
drive current required for a compar-
ably rated bipolar Darlington, which
in any event exhibits switching times
more than an order of magnitude
longer.
Figure 12 shows typical relation-
ships between the switching speeds of
the IRF330 and the drain current,
with and without a gate speed-up cir-
cuit. Note the drastic reduction in the
turn off delay and fall times with the
speed-up circuit, at drain current lev-
-
II U,b.,\~
G,trl
J"
= RJ
1
I II
III 1000 10,000
Figure 12. Typical relationships between Switching
A-13
.
, J.H.
.\
\ "'--I-
.. .. ..
DRAIN SOURCE VOLTAGE IVOlTSI
Figure 13. Typical relationships between
Drain·Source Voltage and Drain-
Source Self 'Capacitance (IRF330)
els above 1A. The increase in the fall
time at low levels of drain current is
due to the drain-to-source capaci-
tance, CO". The lower the drain cur-
rent, the higher the load resistance R,
and the greater the time constant
RCo". A typical relationship between
Co," and drain to source voltage is
shown in Figure 13.
Simple external circuit techniques
such as this can be used to obtain the
fast switching speeds possible with
power MOSFETs, yet maintain
extremely high effective gain, thereby
keeping complexity to a minimum.
Power MOSFETs operating at many
amperes and kilowatt power levels
can commonly be driven directly
from linear and digital IC compo-
nents, whilst switching times still
much faster than those of bipolar
power transistors are easily achieved.
v+ = l00V
I
- NO SPEED UP CIRCUIT
"os" 15V.RG~SO!!
-I-- WITH SPEeD Uf' CIRCUIT
R,-50!I, R2 ~ R3 = lkt!
I C=O.Ol !JF, "GS~ lOV
DRA.IN CURRENT lAMPS)
Times and Drain Current with and without
Gate Speed·up Circuit (IRF330)
Switching Times with an Inductive
Load
So far we have considered the
switching of the power MOSFET
wilh a simple resistive load. In many
applications the load during the
switching interval will be essentially
inductive. and it is often of more
practical interest to the circuit
designer to know the switching times
with an inductive load. Figure 14
shows a simple circuit with a clamped
inductive load; corresponding ideal-
ized switching waveforms are shown
in Figure 15. Note that at switch-on
the current first rises, then the voltage
falls. At switch off the drain voltage
rises, then the current falls. Note that
this assumes that the load is suffi-
ciently inductive that current flows
continuously .in it; through the
MOSFETwhen it is switched on, and
through the clamping diode when the
MOSFET is switched off. It is also
assumed that stray circuit inductance
between the clamping diode and the
MOSFET is negligible. Thus at
switch on, load current that is already
flowing in the clamping diode com-
mutates into the MOSFET, and the
transfer of this current is unrestricted
by stray circuit inductance. In gen-
eral this assumption for the switch on
condition is somewhat pessimistic,
but it can be approximated in certain
circuits.
V>
Ili NPUT
GATE
___ SIGNAL
INDUCTIVE
LOAD
CLAMPING
DIODE
R,
'0 lAMPS)
'0 (AMPS)
'0 lAMPS)
~; : ::V,~~SC - ~O~O~JF ~
Figure 16. Typical relationships between
Switching Times and Drain
Current with Clamped Inductive
Load and Gate Speed-up
CircUit (IRF330)
Figure 16 shows typical relation-
ships between the switching times
and the drain current for a clamped
inductive load with a gate speed-up
circuit.
Maximum Operating Frequency
Because the switching times of the
power MOSFET are very fast - at
least an order of magnitude faster
than those of comparably rated bipo-
lar transistors - the energy dissi-
pated during switching is very much
lower, and the power MOSFET is
able to operate at switching frequen-
cies an order of magnitude or more
higher.
Relationships between operating
frequency and switching efficiency of
the IRF330 power MOSFET with a
resistive load, are shown in Figure 17.
This data is based upon actual mea-
sured values of switching energy at a
supply voltage of 300V, and a 50%
duty cycle. Figure 17 takes account of
the losses in the power MOSFET
itself, and not of other components in
the circuit; it does not therefore
represent the overall circuit effi-
ciency. Clearly, so far as the
MOSFET itself is concerned, switch-
ing frequencies up to 500kHz or
higher are quite feasible. The switch-
ing efficiency is defined as:
Switching Efficiency
Power Input - MOSFET losses
SO!!,
Power Input.
Safe Operating Area
One of the outstanding features of
IR's power MOSFETs is that they do
not display the second breakdown
phenomenon which is frequently the
Achilles heel of bipolar transistors. A
simple physical explanation accounts
for this superiority. If localized,
potentially destructive, heating
occurs within a MOSFET transistor,
the carrier mobility in that area
decreases. As a result the MOSFET
has a positive temperature coefficient
and acts in a self-protective manner
by forcing currents to be uniformly
distributed through the silicon die. In,
contrast a bipolar transistor, particu-
larly under conditions of high
collector-emitter voltage, displays

Figure 14. Simple circuit with Clamped In- 100

10= 1 AMP
ductive Load
99
r-. ~
l
~
z
~
98

97

96
10= 3 AMPS

10J 5A~Psl -
r---t -
I--- r--...
"
I'r-
I!
i " .......
"-
UJ
95
CONDITIONS,
'"
"",
94 50% DUTY CYCLE
TJ = 1oo·C
RQ= 5 OHMS
93 Vo = 300 VOLTS

I I
200
10 20 50 100 500 1000
Figure 15. Idealized Switching Waveforms FREQUENCY (kHz)
for Clamped Inductive Load

Figure 17. Switching Efficiency (IRF330)

A-14
"current croWding" in the base
region, which causes hot spots.
Because of the bipolar's negative
temperature coefficient, these hot
spots tend to further "hog" the cur-
rent and cause instantaneous, catas-
trophic destruction of the die.
As any power transistor circuit de-
signer will know, the rated maximum
power dissipation of the bipolar ac-
tually applies only over a very limited
range of collector voltage, typically
up to 10% of rated VeEO. At higher
voltages, the dc power dissipation is
severely limited by second break-
down. Typically, at rated voltage the
permissible power dissipation is only
5% of full rated power.
The Safe Operating Area of the
IRF330 series MOSFET is shown as
an example in Figure 18. Note that
the DC current is limited throughout
the voltage range only by the 75 watt
power dissipation slope. There are no
secondary slopes in the DC dissipa-
tion curve (or the pulse curve) that
indicate the second breakdown limit
commonly seen on bipolar Safe Op-
erating Area curves. Note also the
high values of pulse current and the
corresponding long time periods for
which the pulse power can be safely
tolerated.
The IRF330, for example, can
tolerate 0.375 amperes at 200 volts
on a DC basis. By contrast, the pop-
ular 2N6545, a bipolar transistor
with the same voltage rating, 'but
double the continuous current rating,
has only a 0.06 ampere DC second
breakdown limit at 200 volts. At one
10.0
IRF330.1
5.0
I RF332.3
I ..
~ ~~
IRF330.1'
::;
~ 2.0
!!
...
"-
ffi
0:: 1.0
"'
i:i
z on the input capacitance, C"" which
;)!
c
0.5
52
0.2 TJ ,I150 0 C MAX.
0.1
10
SINFLEtULSIE
20
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
Figure 18. Maximum Safe Operating Area. (IRF330/333)
millisecond pulse width and 300
volts, the IRF330 rates at 1.0
amperes versus only 0.45 amperes
for the 2N6545.
Thf' ahsence of second breakdown
means that the power MOSFET is
generally a much more rugged device
than the bipolar transistor. This is
extremely important, both for "lin-
ear" and "switching" applications.
The Vos absolute maximum rating
of MOSFETs should not be ex-
ceeded by allowing them to operate
in the avalanche region. However, it
is possible to reliably turn off high
level inductive currents, which can
generate high voltage inductive tran-
sients, by using a simple voltage
clamp circuit. All of IR's MOSFETs
have a clamped inductive rating such
that the maximum rated pulse cur-
rent can be turned off with a 100
micro henry inductor in series. Be-
cause MOSFETs are very fast de-
vices, caution must be taken that the
voltage clamp device has a suffi-
ciently fast response, and that it is
closely coupled to the drain-source
terminals. A zener diode connected
physically as close as possible to the
drain and source terminals generally
will provide acceptable voltage
clamping.
The transconductance, gr" of a
MOSFET is maximum at the highest
allowable drain currents. In contrast,
the DC gain, hFE, of a bipolar transis-
tor, decreases drastically at high col-
lector currents. The high transcon-
ductance of MOSFETs at high
currents, combined with the excellent
lOp.
., , bipolar transistors, for which the
r-...
!'
!\
", lOOp,
"- "- I
1m,
"1'-' J
IOn
"-
" 10~t
DC
50 100 200
Tt 331
500
IRn3~.21
A·15
SOA rating, result in MOSFETs be-
ing superb pulse amplifiers. All of
IR's power MOSFETs have a pulsed
current rating, 10M , that is at least
twice the continuous current rating.
10 . IR's power MOSFETs operate
excellently in the pulse region as long
as the allowable average power dissi-
pation, safe operating area. and ±20
volt maximum gate voltage ratings
are not exceeded.
Temperature Stability
MOSFETs have outstanding gain
and switching time stability with
temperature variations. relative to
the stability of typical bipolar transis-
tors. The transconductance of I R
Power MOSFETs typically varies
less than ±20% from the 25°C value.
over a -55°C to 125°C range. The
DC current gain of a power bipolar
commonly varies by a factor of 2 or 3
over this temperature range.
A rough comparison of the typical
DC gain stability for an IR power
MOSFET versus a power bipolar
would yield a transconductance, gr"
temperature coefficient of about
-0.2% per ° C versus a bipolar current
gain, hFE, temperature coefficient of
about +0.8% per °C - a four-fold
difference.
Reference to Figure 6 will show
that the threshold voltage (bias
point) and the transconductance (DC
gain) move with temperature in com-
pensating directions. Therefore, an
operating point on the DC transfer
characteristic maintains unusually
good open loop stability. Drift-free
operation becomes easy in a linear,
closed loop system.
The switching time of IR power
MOSFETs is essentially independent
of operating temperature. This is a
tremendous advantage relative to
25°C switching times and associated
power losses commonly increase by a
factor of 2 or 3 at the higher actual
operating temperatures. The ex-
traordinary switching time stability
of MOSFETs results because the re-
sponse times are primarily dependent
is essentially temperature invariant.
The on-resistance, RO(ON) of power
MOSFETs, has a positive tempera-
ture coefficient, of approximately
+0.7% perc C. This is an advantage in
paralleling MOSFETs, and as has
been seen it also accounts for their
excellent safe operating area. How-
ever, in determining the on-state
power losses in a switching mode, the
increased value of RO(ON) at the ac-
tual maximum junction operating
temperature must be used. Sufficient lars in many existing applications. In 19. This switching scheme by com-
heatsink must always be used so that order to take full advantage of their parison with the conventional line
a thermal runaway situation cannot unique operating features, and thus frequency power supply, offers
occur. to produce an optimum overall sys- smaller overall size, due to much
tem design, it will almost never be smaller transformer and smoothing
Paralleling sufficient merely to make a one-for- components, faster response, better
Power MOSFETs are easy to par- one replacement of a bipolar with a regulation, and higher efficiency.
allel. because the positive tempera- MOSFET in an otherwise unmodi-
ture coefficient forces current sharing Switching power supplies pres-
fied circuit. The much lower drive
among the paralleled devices. Cur- requirement of the MOSFET willently use bipolar transistors, and
rent sharing resistors, with their as- usually operate in the 20-35 kHz fre-
usually mean that very significant
sociated power losses, are not neces- quency range. Higher operating fre-
simplifications can be made in the
sary. Some resistance in series with quencies are not generally practical,
drive circuitry; the vastly superior
the gates (typically 100 ohms) and because bipolar switching times are
switching speed will offer the possi-
close paralleled lead connections too long. From the system viewpoint,
bility for lower losses, or higher op-
may be necessary to assure that the an increase in the switching fre-
erating frequency, or both; and the
good high frequency response of the quency to 200 kHz or higher would
superior safe operating area will offer
MOSFETs does not cause oscil- offer the possibility for further reduc-
greater loading and overloading ca-
lations. tions in size, weight, and response
pability, and minimization or elimi-
time. Such high operating frequen-
nation of protective snubber com-
MOS Caution cies now become a practical reality,
ponents. with the availability of IR's power
The ±20 volt absolute maximum
gate voltage rating of IR power Many potential applications of MOSFETs. Other potential advan-
MOSFETs should never be ex- Power MOSFETs are obvious, and tages would be elimination of electro-
ceeded, or permanent damage can are already being actively pursued by lytic capacitors, smaller EMI filters,
occur. circuit development engineers and simplified drive and snubber
throughout the world. A great circuits.
Zener diode protection should be number of as yet unexplored applica-
used if there is a danger of transient tions will surely emerge, as the The MOSFET also offers advan-
gate overvoltages. This caution ap- unique advantages of IR's power tages in the existing 20 to 30 kHz
plies also to the buildup of static MOSFETs become more widely un- range, in terms both of reduced over-
charge. IR power MOSFETs have derstood, and as power MOSFET all losses, because of reduced switch-
large gate capacitances and thick technology itself develops and ing losses, and reduced circuit com-
oxide layers relative to low level matures. plexity, because of the minimal gate
MOS devices, where static charge drive requirement.
damage can be particularly danger- In the following sections we will
()us. Though significantly more briefly review some of the most ob- Audio Amplifiers
rugged than such low level MOS vious application areas. This may The power MOSFEToffers a quite
devices, reasonable precautions help to stimulate the imagination of linear input to output transfer char-
which are normally taken in handling the reader to perceive new applica- acteristic. This means that with ap-
MOS devices should be observed tions for power MOSFETs in his propriate biasing it can be used as a
until the installation of MOSFETs own particular field of expertise. simple high quality audio amplifier,
in a circuit. illustrated in a simplified form in
Swite,hing Power Supplies
APPLICATIONS Figure 20.
Switching DC power supplies are
Power MOSFETs offer tremen- r~pidly replacing conventional 50 or The excellent Safe Operating Area
dous operating advantages over con- ' 60Hz transformer/rectifier supplies. of power MOSFETs make them par-
ventional bipolar transistors, and The basic principle of the switching ticularly well suited for class B ampli-
they will undoubtedly replace bipo- power supply is illustrated in Figure fiers, which require extreme low fre-

SO/60Hz
INPUT

Figure 19. Basic Principle of Switching Power Supply Figure 20. Basic Principle of Audio Amplification using Power MOSFET

A·16

Figure 21. Class D Audio Amplifier-
Basic Principle
quency response at high power levels.
The wide MOSFET bandwidth
makes good high frequency response
of the amplifier easy.
Another type of audio amplifier
uses the class D pulsewidth modula-
tion principle, illustrated diagram-
matically in Figure 21. Implementa-
tion of this type of amplifier with
bipolar transistors has not generally
been successful, because the carrier
frequency must be much higher than
the audio frequency to produce a
good quality output. The relatively
long switching times of the bipolar
are a fundamental limitation. With
the availability of IR's power
MOSFETs, these limitations are
eliminated. This type of approach
offers the possibility for an audio
amplifier of extremely high effi-
ciency, small size, and high fidelity.
Motor Speed Control
The use of bipolar transistors for
speed control of both DC and AC
motors is taking a firm hold in the
marketplace, for power ratings up to
several tens of horsepower. Basic
chopper and inverter schemes for
motor speed control using power
MOSFETs are shown in Figure 22.
The use of variable frequency DC to
AC inverters, for efficient control of
the speed of AC induction motors is
becoming particularly topical in view
of the present day emphasis on
energy saving techniques.
In these circuits the switching fre-
quency typically will be in the range
of a few hundred Hz, to a few kHz.
This, of course, is well within the
capability of bipolar transistors.
M OSFETs can however offer signifi-
cant advantages, because of their
substantially reduced drive power
requirements, and improved safe op-
erating area and ruggedness. These
features will result in simplification
of peripheral circuitry, improved re-
liability, and improved response
time.
The ease of paralleling power
MOSFETs for higher power output
is also an important advantage,
whilst the somewhat higher conduc-
tion voltage drop and hence higher
power loss of the MOSFET is but a
slight disadvantage - more theoreti-
cal than practical. The extra heats ink
required to accommodate the greater
power dissipation of the MOSFET is
minimal indeed, and is greatly out-
weighed by the advantages to be
gained.
AM Transmitters
Conventional AM broadcasting
transmitters operate in the 0.5 to
1.6 MHz range. They use vacuum
tubes, which are relatively bulky and
unreliable. Newer designs are using
parallel connected bipolar tran-
sistors.
Typically an AM transmitter using
bipolars requires about 60 devices,
for each kilowatt of output power.
The high operating frequency pushes
the limits of bipolar operation, paral-
leling is difficult, and the required
reliability is not easy to achieve.
Power MOSFETs are capable of
operation within the required fre-
q uency range, and are easily parallel-
able. The total number of devices
would be drastically reduced; for ex-
ample 8 IRF350's would be needed
for each kilowatt of output power, as
compared to 60 bipolar transistors.
Another advantage of the MOSFET
system would be that it is able to
handle mismatch and fault condi-
tions, and the driver stages would be
much simpler. A basic schematic of
an A M transmitter using power
MOSFETs is shown in Figure 23.
Figure 23. AM Transmitter - Basic Principle
Induction Heating
The heating of metal by energizing
an induction coil that couples mag-
netic flux and induces a flow of eddy
current into the work piece is an es-
tablished principle, that is widely
used throughout industry. It is an ef-
ficent, clean and cost effective means
of melting, heating, hardening, an-
nealing and welding of metals.

~
(a) CHOPPER FOR VARIABLE
VOLTAGE SPEED
CONTROL OF DC MOTOR

o J
DC SUPPLY

(b) PULSE WIDTH MODULATED INVERTER

FOR VARIABLE FREQUENCY SPEED
CONTROL OF A-C MOTOR

Figure 22. Basic schemes for Variable Speed Control of DC and AC Motors using Power MOSFETs

A-17
 Induction heating systems cover a
wide range of frequencies, starting at
line frequency and progressing up to
around 500kHz. The lower frequency
ranges. up to 20kHz or so, today are
generally covered by variable fre-
quency thyristor inverters, which
have now largely replaced the older
fixed frequency rotating generator
sets. '
Power levels of induction heating
equipment extend up to several mega-
watts at the lower end of the fre-
quency spectrum. As the required
frequency increases, generally the
power requirement decreases.
For frequencies in the 100 to
500kHz range vacuum tube o~cilla­
tors. with ratings from a few kilo-
watts upwards, are presently the
normal means of producing the re-
quired frequency. These are not too
efficient, typically about 60%, they
are quite large, and they require peri-
odic maintenance.
The availability of IR's power
MOSFETs offers the opportunity for
realising efficient, compact and reli-
able solid state RF induction heating
generators at the required power rat-
ings. at frequencies up to 500kHz.
Another use of induction heating
that has been proposed is in domestic
cooking. Heating currents are in-
duced from an induction coil directly
into the cooking utensil. This tech-
nique offers dramatic improvements
in efficiency and response time.
Commercial exploitation of this
principle has not so far generally
been successful, primarily because of
the complexity of the required high
frequency inverter circuitry. The
availability ofiR's power MOSFETs
,7 '\ ,:;"t\
' __ .L __'
Figure 24. HF Welding System - Basic Principle
makes possible a complete re-
appraisal of the induction cooker.
High Frequency Welding
Modern DC power supplies use
high frequency switching techniques
to obtain greater compactness, im-
proved efficiency and faster re-
sponse. This very same switching
technique is also applicable to DC
welding supplies. T.hese traditionally
use a bulky mains frequency trans-
former, often a ballast impedance to
obtain the required output regula-
tion, and an output rectifier to pro-
vide the required DC.
Figure 24 shows a basic schematic
of a possible high frequency welding
system using power MOSFETs. IR's
power MOSFETs can deliver several
kilowatts of power at frequencies
well above the audio range; this type
of scheme would provide a compact,
portable, silent, efficient welder, with
fast response and excellent control-
lability.
Fluorescent Lighting
Conventional mains frequency
fluorescent lighting requires bulky
inductive ballasting and power factor
capacitors, and is relatively ineffi-
cient. It is well known that by using
high frequency to supply the fluores-
cent tube, power consumption for a
given light output can be reduced by
30 to 35%, whilst tube life can be
substantially increased, and bulky
ballast components are eliminated.
• Fluorescent lighting schemes using
high frequency bipolar transistor in-
verters are presently used in applica-
tions such as transportation and
emergency lighting systems.
Application of high frequency
techniques to the general consumer
Figure 25. HF Lighting System - Basic Principle
A-18
market has so far been inhibited by
the relative complexity of the drive
circuitry required for the. bipolar
transistor. IR's power MOSFETs
with their extremely simple drive re-
quirements are potentially ideal for
this application.
A basic schematic of a high fre-
quency fluorescent . lighting scheme
using MOSFETs is shown in Figure
25.
Other Applications
'The applications discussed above
are just a few of the many potential
uses ofiR's power MOSFETs. Other
immediate application areas are high
frequency generators for diathermy,
drivers for high power bipolar tran-
sistors and thyristors, pulsewidth
modulated high current supplies for
spark erosion, beam control of video
displays for computer terminals, and
VLF and HF generators.
Summary
Power MOSFETs have numerous
operating characteristics which are
distinctly superior to those of power
bipolar transistors. These superiori-
ties occur because MOSFETs have
fundamentally different operating
principles. Understanding the oper-
ating principles and superiorities of
MOSFETs will allow the creative de-
signer to make fundamental im-
provements in many types of transis-
torized products, as well as to
innovate entirely new types of
product .
The introduction of IR HEXFETs
- the world's most advanced form of
power MOSFETs - further under-
scores the importance of MOSFET
technology for the circuit designs of
the future. 0
 CHAPTER 2
APPLICATION NOTE 936

The Do's and Don'ts of Using Power HEXFETs

By BRIAN R. PELLY

Summary nals; the applied gate voltage sets up The integral body-drain diode is a
In common with all power semi- a field in the channel region, which real circuit element, and its current
cond uctor devices, power M OSFETs modulates the resistance of the de- handling capability is typically as
have their own technical subtleties, vice. The gate is isolated electrically high as that of the transistor itself.
which must be properly understood from the body; as a result, the power Some circuits require an "inverse"
if the designer is to get the most out of HEXFET has a very high, almost rectifier to be connected across the
them. In this article, some ofthe most infinite, DC gain. switching device, and in these circuits
common "Do's and Don'ts" of using A feature of power MOSFETs is it will often be possible to utilize the
power HEXFETs are explained. that they inherently have built into body-drain diode of the HEXFET,
them an integral reverse body-drain provided the proper precautions are
Introduction diode. The existence of this diode is taken.
explained by reference to Figure I.
Power HEXFETs offer many ad- When the source terminal is made In this application note, some of the
vantages over conventional bipolar positive with respect to the drain, most common do's and don'ts of
transistors, in both linear and switch- current can flow through the middle using power HEXFETs are des-
ing applications. These advantages of the source cell, across a forward cribed. The objective is to help the
include very fast switching, absence biased P-N junction. In the "reverse" user get the most out of these remark-
of second breakdown, wide safe op- direction, the power HEXFET thus able devices, while reducing "on the
erating area, and extremely high gain. behaves like a P-N junction rectifier. job" learning time to a minimum.
Typical applications are high fre-
quency switching power supplies,
chopper and inverter systems for DC
and AC motor speed control, high
frequency generators for induction
heating, ultrasonic generators, audio
amplifiers, AM transmitters, compu-
ter peripherals, telecommunications
equipment, and a host of special mili-
tary and space needs.
There are several basic types of
power MOSFETsavailable. Original
designs used so-called V-groove or
V-groove structures, while the trend
today is towards vertical D-MOS
technology, with a closed cellular
source configuration. This technol-
ogy was first embodied in the HEX-
FET structure, shown in Figure I.
Current flows vertically through
the silicon from the drain, through
the body of the device, then horizon- DRAIN DRAIN
"TRANSISTOR" "TRANSISTOR"
tally through the channel region, and CURR~NT CURRENT
vertically out of the source, as illus-
DIODE CURRENT
trated. The flow of transistor current
is controlled by the voltage applied Figure 1. Basic HEXFET Structure
between the gate and source termi-

A-19
Be Careful When Handling & Testing
PowerHEXFETs
The user's first "contact" with the
power HEXFET could be a package
of parts arriving on his desk. Even at
this stage, it behooves one to be
knowledgeable about some elemen-
tary precautions.
Power HEXFETs, being MaS de-
vices, can potentially be damaged by
static charge when handling, testing
or installing into a circuit. The prob-
lem is rather slight by comparison
with that.experienced with low level
MaS devices. Power HEXFETs are,
after all, power devices; as such, they
have much greater input capacitance,
and are much more able to absorb
static charge without excessive build-
up of voltage. In order to avoid pos-
sible problems, however, the follow-
ing procedures should be followed as
a matter of good practice, wherever
possible:
• HEXFETs should be left in their
anti-static shipping bags, or con-
ductive foam, or they should be
placed in metal containers or con-
ductive tote bins, until required
for testing or connection into a
circuit. The person handling the
device should ideally be grounded
through a suitable wrist strap,
though in reality this added pre-
caution is seldom essential.
• HEXFETs should be handled by
the package, not by the leads.
When checking the electrical char-
acteristics of the power HEXFET on
a curve tracer, or in a test circuit, the
following precautions should be ob-
served:
• Test stations should use electric-
ally conductive floor and table
mats that are grounded. Suitable
mats are available commercially.
• When inserting HEXFETs into a
curve tracer or a test circuit, volt-
age should not be applied until all
terminals are solidly connected
into the circuit.
• When usinga curve tracer, a resis-
tor should be connected in series
with the gate to damp spurious
oscillations that can otherwise
occur on the trace. A suitable
value of resistance is 100 ohms.
• For repeated testing, it is conve-
nient to build this resistor into the
test fixture.
• When switching from one test
range to another, voltage and cur-
rent settings should be reduced to
zero, to avoid the generation of
potentially destructive voltage sur-
ges during switching.
The next step is to connect the
power HEXFET into an actual cir-
cuit. The following simple precau-
tions should be observed:
• Work stations should use electric-
ally grounded table and floor mats .
• Soldering irons should be groun-
ded.
Now that the power HEXFET has
been connected into its circuit, it is
ready for the power to be applied.
From here on, success in applying the
device becomes a matter of the integ-
rity of the circuit design, and of what
circuit precautions have been taken
to guard against unintentional abuse
of the HEXFET's ratings.
The following are the interrelated WITH •
device and circuit considerations th,at "'--
lead to reliable, trouble-free design.
Beware of Unexpected
Gate-to-Source Voltage Spikes
Excessive voltage will punch
through the gate-source oxide layer
and result in permanent damage. L_f+_- S
This seems obvious enough, but it is EXTeRNALLY CONNECTED
not so obvious that transient gate-to- CLAMPING ZENER DtODE
source overvoltages can be generated
that are quite unrelated to, and well Figure 2. A Rapidly Changing Applied
in excess of, the amplitude oftheapp- Drain-Source Voltage will
lied drive signal. The problem is illus- Produce Gate-Source
Voltage Transients
trated by reference to Figure 2.
If we assume that the impedance, Z,
of the drive source is high, then any
positive-going change of voltage app-
lied across the drain and source ter-
minals (caused, for example, by the _OYEAVOLTAGE
switching of another device in the TRANSIENT
DUETOL
circuit) will be reflected as a positive-
going voltage transient across the
source and the drain terminals, in the (_) UNCLAMPED
INDUC11YE
approximate ratio of: LOAD
I
I + ~s
Cdg
The above ratio is typically about I
to 6. This means that a change of
drain-to-source voltage of 300V, for Figure 3. Drain-Source Overvoltage
example, could produce a voltage Transient when Switching
transient approaching SOV between Off with Unclamped
the gate and source terminals. This Inductive Load
calculation is based upon the worst
case assumption that the transient
impedance of the drive circuit is high
by comparison with the gate-to-
source capacitance of the HEXFET.
. o-------f,~~lJ A =:Ls OVERVOLTAGE
T1WISENT
DUE TO L,
This situation can, in fact, be quite
easily approximated if the gate drive
circuit contains inductance - for (b) CLAMPED
INDUCTlVE
L
example, the leakage inductance of LOAD
an isolating drive transformer. This
~j:
inductance exhibits a high impedance
for short transients, and effectively o
decouples the gate from its drive cir-
cuit for the duration of the transient. La: STRAY CtRCUrT
The positive-going gate-to-source INDUCTANCE
voltage transient produced under the
above circumstances is undesirable Figure 4. Drain-Sou~ce Overvoltage
Transient Produced by Stray
because it may exceed the gate volt- Circuit Inductance When
age rating of the device, causing per- Switching Off with Clamped
manent damage; moreover, it tends Inductive Load
to turn the device ON "unintention-
A-20
ally", causing transient current over-
loading of this and other devices in
the circuit.
It is, of course, true that since the
applied drain transient results in a
voltage at the gate which tends to
turn the HEXFET device ON, the
overall effect is to an extent self-
limiting so far as the gate voltage
transient is concerned. Whether this
self-limiting action will prevent the
voltage transient at the gate from
exceeding the gate-source voltage rat-
ing of the device depends upon the
impedance of the external circuit.
Spurious turn-on is of itself undesir-
able, of course, though in practical
terms one may grudgingly be able to
accept this circuit operating imperfec-
tion, provided the safe operating area
of the device is not violated.
As a minimum solution to the prob-
lem, the gate-source terminals must
be provided with a voltage clamp (a
conventional zener diode is suitable
for this purpose) to prevent the gate-
source voltage rating from being ex-
ceeded. A more fundamental solu-
tion, of course, is to make the im-
pedance of the gate circuit low enough
that not only is the gate-source volt-
age rating not exceeded, but also the
voltage transient at the gate is con-
tained to a level at which spurious
turn-on does not occur.
It should be remembered that a col-
lapse of voltage across the HEXFET
(i.e., a negative-going dv/dt) will
produce a transient negative voltage
spike across the gate-source termi-
nals. In this case, of course, there will
be no tendency for the device to turn
ON, and hence no tendency for the
effect to be self-limiting. A zener
diode connected to clamp positive
transients will automatically clamp
negative-going transients, limiting
0
.0 ...._ _ ::"'1
L,
R::Ls
(e) ct.AMPED
~~~ l
Z£NERCLAMP
Vos
. .J}J-
CLAMPING
ZENER
Figure 5. Overvoltage Transient at SWltch-
Off Clamped by Local Drain-
Source Zener
them to the forward conduction volt-
age drop of the zener.
Beware of Drain-Source Voltage
Spikes Induced by Switching
The uninitiated designer is often
not aware that self-inflicted overvolt-
age transients can be produced when
the device is switched OFF, even
though the DC supply voltage for the
drain circuit is well below the VDS
rating of the HEXFET.
Figure 3 shows how a voltage spike
is prod uced when switching the de-
vice OFF, asa result of inductance in
the circuit. The faster the HEXFET
is switched, the higher the overvolt-
age will be. Inductance is always
present to some extent in a practical
circuit, and therefore, there is always
danger of inducing overvoltage tran-
sients when switching OFF. Usually,
of course, the main inductive com-
ponent of the load will be "clamped",
as shown in Figure 4. Stray circuit
inductance still exists, however, and
overvoltage transients will still be
produced as a result - to say nothing
of the fact that the clamping diode
may not provide an instantaneous
clamping action, due to its "forward
recovery" characteristic.
The first approach to this problem
is to minimize stray circuit induc-
tance, by means of careful attention
to circuit layout, to the point that
whatever residual inductance is left
in the circuit can be tolerated. If the
device has an inductive energy rating,
use can be made of this rating for this
situation. Generally, however, such
ratings do not yet exist for power
HEXFETs, and a clamping device
should be connected, physically as
close as possible to the drain and
. source terminals, as shown in Figure
'E
Eo
E L
;,l
:; 0
~ Eo R ~
Figure 6. Overvoltage Transient at Switch-
Off Limited by Local Diode-
Capacitor-Resistor Clamp
A-21
5. A conventional zener diode, or a
"transorb"clamping device, are satis-
factory for this purpose. An alterna-
tive clamping circuit is shown in Fig-
ure 6. The capacitor C is a reservoir
capacitor and charges to a substan-
tially constant voltage, while the re-
sistor R is sized to dissipate the
"clamping energy" while maintain-
ing the desired voltage across the
capacitor. The diode D must be cho-
sen so that its forward recovery char-
acteristic does not significantly spoil
the transient clamping action of the
circuit.
A simple RC snubber can also be
used, as shown in Figure 7. Note,
however, that an RC snubber not
only limits the peak voltage, it also
slows down the effective switching
speed. In so doing, it absorbs energy
during the whole of the switching
period, not just at the end of it, as
does a voltage clamp. A snubber is
therefore less efficient than a true
voltage clamping device.
Note that the highest voltage tran-
sient occurs when switching the high-
est level of current. The waveform of
the voltage across the HEXFET
should be checked with a high-speed
oscilloscope at the full load condition
to ensure that switching voltage tran-
sients are within safe limits.
Do Not Exceed the Peak
Current Rating
All HEXFETs have a specified max-
imum peak current rating. This is
conservatively set at a level that guar-
antees long-term reliability, and it
should not be exceeded.
It is often overlooked that peak
transient currents can be obtained in
a practical circuit that are well in
excess of the expected normal oper-
E
L,
~"'~UI;!L' OVERVOLTAGETRANSIENT
:.
REDUCOD BY SN,,":R
(eI) CLAMPED INDUCTIVE
~v ~..::..~
_ _ _----,I
Figure 7. Oyervoltage Transient at Switch-
Off Limited by Local Capacitor-
Resistor Snubber
ating current. unless proper precau-
tions are taken. Heating. lighting and
motor loads. fo~ example. consume
high in-rush currents if not properly
controlled. A technique that ensures
that the peak current does not exceed
the capability of the HEXFET is to
use a current sensing control that
switches OFF the HEXFET when-
ever the current instantaneously
reaches a preset limit.
Unexpectedly high transient current
can also be obtained as a result of
rectifier reverse recovery. when a
HEXFET is switched ON rapidly
into a conducting rectifier. This is
illustrated in Figure 8. The solution is
to use a faster rectifier. or to slow
down the switching of the HEXFET
to limit the peak reverse recovery
current of the rectifier.
Do Not Operate at an RMS Current In
Excess of the Rating
All HEXFETs have a maximum
continuous direct current rating. ID.
The internal bonding wires. bonding
pads. and source metallization of the
HEXFET are designed to carry this
rated current continuously. The total
continuous RMScurrent handled by
the HEXFET should not exceed the
ID rating. This means that ina ,witch-
ing application. for example. if the
peak current is IpK. and the duty
cycle is D. as illustrated in Figure 9.
then the maximum permissible value
vi
of I PK is I D/ D. so long as this
value is less than the ID(max) rating.
Stay Within the Thennal Umits
The power HEXFET. being a
power device. is thermally limited. It
must be mounted on a heatsink that
is adequate to keep the junction
1
1
Figure 8. Switching on the HEXFET into a Conducting Rectifier Can Result in High
Peak Current, due to Reverse Recovery of Rectifier.
temperature within the rated TJ(max)
( 150° C) under the "worst case" con-
dition of maximum power dissipa-
tion and maximum ambient temper-
ature.
It must be remembered that in a
switching application. the total power
is due to the conduction loss and the
switching loss. Switching time and
hence switching losses are essentially
independent of temperature. but the
conduction losses increase with in-
creasing temperature. because RD(on)
increases with temperature. This must
be taken into account when sizing the
heatsink. The required thermal resist-
ance of the heatsink can be calculated
as follows:
The'transistor conduction power.
PT. is given approximately by:
PT = 12T RD(oJ1) [I + 0.007
(.1TJA + TA - 25)]
where IT = RMS value of "tran-
sistor current"
=ON resistance at 25°C
= ambient temperature -
°C
.1 TJA = temperature rise. junc-
tion-to-ambient
The term within the brackets [ ]
accounts for the typical 0.7% increase
in RD(on) per degree C temperature
rise above 25° C. The data sheet can
be consulted for a more accurate
value of temperature coefficient for
any specific device.
The switching energy depends upon
the voltage and current being switched
and the type of load. The total switch-
ing loss. Ps, is the total switching
energy. fT. multiplied by the operat-
ing frequency. f. fT is the sum of the
energies due to the individual switch-
ings that take place in each funda-
mental operating cycle.
Ps =fT . f
Figure 9. To Slay Within 10 RMS Rating,
A-22
The total power dissipation is the
sum of the conduction power. PT.
and the switching power. Ps .
P = PT + Ps
= 12T RD(on) [I + 0.007
(.1TJA+TA-25)]+ Ps
Since:
.1TJA = PR JA
where:
RJA = junction-to-ambient therm-
al resistance
The required value of RJA for a
given value of .1 TJ A is given by:
RJA =
.1TJA
I"l RO(on)[1 +0.007 (.1TJ A+TA -25)]+ Ps
Thejunction-to-ambient thermal re-
sistance. RJA . is made up of the
internal junction-to-case thermal re-
sistance. RJC. plus the case-to-heat-
sink thermal resistance. Rcs. plus
the sink-to-ambient thermal resist-
ance. RSA . The first two terms are
fixed for the device. and the required
thermal resistance of the heatsink .
RS - A. for a given junction tempera-
ture rise .1 T J_A. can be calculated
from:
RS-A =RJ-A - (RJc + Rc-s)
Pay Attention to Circuit Layout
Stray inductance in the circuit can
cause overvoltage transients. slowing
down of the switching speed. unex-
pected unbalance of current between
parallel connected devices. and un-
wanted oscillations.
In order to minimize these effects.
stray circuit inductance must be min-
imized. This is done by keeping con-
duction paths as short as possible. by
minimizing the area of current loops.
by using twisted pairs of leads. and
DUn CVCLE D: T
Maximum Permissible Value of
IplI is 10/.JD, so long as IpK
.;;; lo(max)'
by using ground plane construction.
Local decoupling capacitors alleviate
the affects of any residual circuit
inductance, once these measures have
been taken.
Circuit layout should be kept as
symmetrical as possible in order to
maintain balanced currents in paral-
lel connected HEXFETs. The gates
of parallel connected devices should
be decoupled by small ferrite beads
placed over the gate connections, or
by individual resistors in series with
each gate. These measures prevent
parasitic oscillations.
Be careful When Using the Integral
Body-Drain Diode
The HEXFET's integral body-drain
diode exhibits minority carrier re-
verse recovery. Reverse recovery pre-
sents a potential problem when
switching any rectifier off; the slower
the rectifier, the greater the problem.
The HEXFET's rectifier is relatively
fast - not as fast as the fastest dis-
crete rectifiers available, but consid-
erably faster than comparably related
conventional general purpose rectifi-
ers. By comparison with the HEX-
FET itself. on the other hand, the
switching speed of the integral reverse
rectifier is quite slow. The switching
speed of a circuit which utilizes the
body-drain diode of the HEXFET
may therefore be limited by the recti-
fier. Whether this will be so depends
upon the circuit and the operating
conditions.
The most common applications of
the HEXFET in which the switching
speed, and hence frequency, will po-
tentially be limited by the rectifier,
are DC to DC choppers, and inver-
ters for regulated power supplies,
electric motor controllers, and so on,
in which "multiple" voltage pulses
~
I --~~~il
o---J "T~
__ J'IF:
INDIJCnVE LOAD
I CURRENT IS
- FREE·WHEELlNG
TO INDUCTIVE LOAD IN THE
BODY-DRAIN
DIODE OF
I J :::: DEVICE
o---J ~TAlCECAREWHEN
SWITCHING-ON
THIS DEVICE
Figure 10. Local Circuit Configuration
and Operating Condition
Requiring Special Care
When Using the HEXFET's
I ntegral Body-Drain Diode.
are used. Fortunately, these applica-
tions generally do not require ultra-
fast switching, and hence they can
tolerate the reverse recovery charac-
teristic of the rectifier.
Regardless of the overall circuit
configuration, or the particular appli-
cation, the "local" circuit operating
situation that is troublesome occurs
when the freewheeling current from
an inductive load is commutated from
the integral rectifier of one HEXFET
to the transistor of an "opposite"
HEXFET, the two devices forming a
tandem series connected pair across a
low impedance voltage source, as
shown in Figure 10. This "local" cir-
cuit configuration occurs in most
chopper and inverter schemes.
If the incoming HEXFET switches
ON too rapidly, the peak reverse rec-
overy current of the integral body-
drain diode of the opposite HEXFET
will rise too rapidly, the peak reverse
recovery current rating will be ex-
ceeded, and the device may possibly
be destroyed.
The peak reverse recovery current
of the rectifier can be reduced by
slowing down the rate of change of
current during the commutation pro-
cess. The rate of change of current
can be controlled by purposefully
slowing down the rate of rise of the
gate driving pulse. Using this tech-
nique, the peak current can be re-
d uced to almost any desired extent,
a t the expense of prolonging the high
dissipation switching period. The os-
cillograms in Figure II illustrate the
effect. By slowing the total switch-
ON time from 300ns to 1.8,us, the
peak current of the lRF330 has been
decreased from 20A to lOA. The
energy dissipation associated with
the "unrestrained" switch-ON in Fig-
ure II(a) is 0.9mJ, whereas it is 2.7mJ
= =
(8) I(max) 20A, di/dt SOA/ /ls.
Switching time = 300 nsec.
Figure 11. Oscillograms of IRF330 Switching into Reverse Rectifier of Another
IRF330 with Freewheeling Current of 4A.
Top Trace: Voltage 100V/div.
Bottom Trace: Current 4A/div.
Time Scale: 2/ls/div.
A-23
for the controlled switch-ON of Fig-
ure II(b). Note, however, that the
average switching losses at a switch-
ing frequency of, say Sk Hz, are quite
manageable - 4.SW and 13.SW for
Figures ll(a)and ll(b), respectively.
Note also that it is not necessary to
slow the switching-OFF of the HEX-
FET, hence the energy dissipation at
switch-OFF will be relatively small
by comparison with that at switch-
ON. For operation at frequencies up
to a few k Hz, where ultra-fast switch-
ing is not mandatory, slowing the
applied gate drive signal to reduce
the peak reverse recovery current of
the "opposite" rectifier offers a good
practical solution.
Be On Your Guard When Comparing
Current Ratings
The user can be forgiven if he
assumes that the continuous drain
current rating, ID , that appears on
the data sheet represents the current
at which the device can actually be
operated continuously in a practical
system. To be sure, that's what it
should represent; unfortunately it
often does not.
Most manufacturers assign a "con-
tinuous" current rating to the device
which in practical terms cannot be
used, because the resulting conduc-
tion power dissipation would be so
large as to require a heatsink with an
impractically low thermal resistance,
and/ or an impractically low ambient
operating temperature.
Table I is an illustration of the
present lack of standardization of
current ratings amongst different
MOSFET manufacturers. The devi-
ces with higher ON-resistance are
seen to have generally higher current
ratings assigned to them than the
lower ON-resistance parts - a tra-
(b) l(max)20A, dildt = SOA//ls.
Switching time 1.8/ls.
vesty of the "correct" situation that compare different types on the basis mal resistance (which, unfortunately,
would. and should. exist if all types of ON-resistance. and not of 10 rat- not all manufacturers specify), is a
of given chip size and junction-to- ing. Fortunately. all manufacturers much better indication of the HEX-
case thermal resistance were rated on specify RO(on) at 25°C. and this pro- FET's true current handling capabil-
the basis of a given power dissipa- vides a common basis for compari- ity.
tion. son. This parameter. taken in con-
The best advice to the user is to junction with the junction-case ther- Conclusions
Power HEXFETs have many ad-
Table 1. Comparison of Different Manufacturers' Practices for Assigning vantages. When properly applied they
Current Ratings (All Parts are Rated 400V) yield an overall system design that
Calculated frequently has fewer co-mponents, is
Device RO(on) 10 ROI"' T C(max) Applicable to 10 lighter and more compact, and has
Type Ohms Amps °CjW °C better performance than can be ob-
tained with other types of devices.
IRF330 1.0 4 1.67 90 In common with all power semi-
MTP565 1.5 5 1.67 25 conductors, power HEXFETs do
have their own little technical subtle-
HPWR6504 1.0 5 1.39 80 ties. If these subtleties are properly
VN400lA 1.5 8 'J <25 ? understood, the potential pitfalls can
be easily overcome. at minimal cost
VN0340BI 1.5 8 'J <25 ? - and potentially great reward. 0

A-24

Current Ratings, Safe Operating Area,
and High Frequency®
Switching Performance
of Power HEXFETs
By S. CLEMENTE, B.R. PELL Y, R. RUTTONSHA
Summary
This application note discusses the
current handling capability, safe op-
erating area, and power dissipation
of a HEXFET power MOSFET. It is
shown that the HEXFET's ability to
carry current is essentially limited
only by junction heating, both for the
"switched" and "linear" modes of
operation - unlike the bipolar tran-
sistor, which is limited by gain and
second breakdown. For this reason,
peak current ratings of HEXFETs
are phenomenally high by compari-
son with those of bipolar transistors.
Examples are given which show
how the HEXFET's current carrying
ability can be utilized, and how the
power dissipation of a HEXFET
compares with that of a fast switch-
ing bipolar transistor, as a function
of operating frequency.
Introduction
International Rectifier HEXFETs
are well established in a variety of
applications which previously have
been served by bipolar transistors,
and are continuing to find many new
applications. Designers who are fa-
miliar with the practical derating fac-
tors that need to be applied when
designing with bipolar transistors fre-
q uently do not realize that the criteria
for determining HEXFET ratings
are quite different, and as a result
often select a HEXFET which is
oversized for the job. This can have a
significant bearing on the cost effec-
tiveness of the design.
The purpose of this application
note is to explain the basis of the
current ratings and Safe Operating
Area (SOA) of power HEXFETs,
and thus enable the user to make a
properly informed choice of HEX-
FET for his particular application.
A practical comparison of the power
losses of a HEXFET and a bipolar
transistor is also given. Whereas the
conduction losses of a bipolar are
generally lower than those of the
HEXFET, the switching losses are
significantly higher. Base drive power
for the bipolar also reduces efficiency.
Test results are presented which
illustrate the difference in losses of
the HEXFET and the bipolar tran-
sistor as a function of frequency. The
HEXFET is shown to be generally
more efficient above frequencies in
the 20 to 40 kHz range.
Bipolar Transistor Current Ratings
It will help to set the stage by first
considering the basis of the current
ratings of a bipolar transistor. Where-
as the continuous and peak current
ratings of a bipolar that are "head-
lined" in the data sheet are theoretic-
ally valid, they are hardly ever usable
in practice. A basis for specifying the
current ratings of bipolar transistors
has been adopted in the industry
which unfortunately is not representa-
tive of usable current levels; it simply
provides a yardstick for making com-
parisons between different products
on a reasonably common basis.
The Achilles' heel of the bipolar's
current carrying capability is the crit-
ical question of the attendant gain,
saturation voltage and switching time
at elevated operating temperature.
A-25
CHAPTER 3
APPLICATION NOTE 949
These supporting parameters are usu-
ally specified at "rated" current at a
junction temperature of 25° C (where
they give the appearance of acceptabi-
lity), but the data sheet usually does
not specify their values at higher "op-
erating"junction temperature (where
they are usually not so acceptable).
In reality the bipolar is not intended
to be used at its headlined "rated"
continuous current. To do so would
require an inconveniently large
amount of drive current, and the sat-
uration voltage and switching times
would be hard to live with in a practi-
cal design, in which the normaljunc-
tion operating temperature WOUld, of
course, be well in excess of 25° C.
A good maximum design operating
level for a bipolar transistor is typical-
ly 60 to 70% of the headlined "con-
tinuous" collector current rating; ex-
perienced users know this and design
to it. Device manufacturers know it,
too; this is why the data sheet speci-
fies the minimum gain, maximum
saturation voltage and maximum
switching times at elevated junction
temperature (usually 100°C), at a
collector current which is 60 to 70%
of the headlined "rated" value, but
not at the "rated" current itself.
An example will illustrate this. The
industry-standard 2N6542j 3 bipolar
transistm has a "headlined" continu-
ous collector rating of5A. The maxi-
mum value of V CI;(SAl)' the corres-
ponding forced gain, and the maxi-
mum switching times at elevated
temperature (T C =100° C) are, how-
ever, specified at a collector current
of only 3A. If the designer really
wants to use this device at its head-
lined "rated" current, he will have to
refer to the manufacturer to deter-
mine the critical "worst case" sup-
porting data needed to design the cir-
cuit; this information will not be
found on the data sheet.
The rated peak collector current of
a bipolar is even more tenuous than
the rated continuous value. This is
usually specified without reference to
the required base drive current. Con-
sider the 2N6542/ 3. The peak collec-
tor current rating headlined on the
data sheet is lOA. Not specified is the
base current needed to produce this
collector current.
The DC gain curve, reproduced
from the data sheet in Figure I, ter-
minates at the "continuous" collector
current rating of 5A. Bearing in mind
that this is anyway a typical curve, it
is a matter of conjecture what the
minimum gain will be at a collector
current of lOA, at elevated operating
temperature - and hence what base
current will be needed to support the
lOA peak collector current rating.
In reality the gain will likely be less
than the unity. The 2N6542/ 3 device
would therefore have to be driven
with a base current of at least lOA in
order to utilize its peak collector cur-
rent rating of lOA - an untenable
situation for most practical designs.
Current Ratings of MOSFETs
Continuous Ratings
The MOSFET is quite a different
70
Z 50
:c
"w
I-
Z 30
II:
II:
:::I
(J
(J.
Q
...
iii
.c:
10
- - - VCE =10V
5.0~~~~ __ ~ __ __-L__
~ ~~~~-U~~~-L
0.05 0.07 0.1 0.2 0.3
IC COLLECTOR CURRENT (AMP)
Figure 1. Typical DC Current Gain, 2N6542/3 Bipolar Transistor
device to a bipolar,. and its continu-
ous 10 rating is based upon quite
different considerations. Whereas the
usable current of a bipolar is basically
limited by gain, this is not the case
with a power MOSFET. Figure 2
shows a typical relationship between
transcond uctance of a HEXFET and
a drain current. Transconductance
increases with increasing drain cur-
rent - just the opposite situation
than with a bipolar transistor. Ob-
viously the HEXFET - unlike the
bipolar - is not going to "run out of
gain" as the drain current increases.
Switching speed is generally much
faster than. that of a bipolar. With
proper drive circuit design, switching
speed of a HEXFET varies relatively
slightly as the current increases, and
is not a factor in determining the
rated current. This can be dedUCed
from Figure 3, which shows a typical
relationship between gate charge,
gate voltage, and 'drain current for a
HEXFET. For a given gate charging
current, switching speed is directly
proportional to gate charge. The gate
charge required for switching, and
hence switching speed. itself, is not
influenced greatly by the amplitude
of the drain current, and not at all by
junction operating temperature.
The major criterion on which the
continuous rating of a HEXFET is
based is heat removal. The HEXFET
will carry as much current as the
cooling system' will permit, while
keeping peak junction temperature
VCE=20V
__-L__ ~~
0.5 0.7 1.0 2.0 3.0 5.0
A-26
within the rated maximum value.
The more efficient the heat dissipator
to which the HEXFET is attached,
the lower the case temperature will
be, the greater the permitted case-to-
junction temperature rise, the greater
the permitted internal power dissipa-
tion, and the·greater permissible cur-
rent. These considerations are, of
course, exactly the same as those
which apply to other non-gain-
limited power semiconductor devices,
such as rectifiers and thyristors.
Usable current, 10 , for a HEXFET
is therefore:
_j TJmax -Tc
- ROS(on) Rth(JC)
where RO~on) is the limiting value of
the on-resistance at rated T(Jmax), at
the appropriate value of I D. R thJC is
the maximum value of internaljunc-
tion-to-case thermal resistance, and
T c is the case temperature.
Figure 4 shows the continuous cur-
rent rating of the IRF330 HEXFET
as a function of case temperature.
Note that below a case temperature
of 25° C, the continuous 10 rating is
limited by the current carrying capac-
ity of the internal source bonding
wire. But this is not a practicallimita-
tion.
Figure 4 also shows the relationship
between HEXFET internal power
dissipation and drain current. Power
is proportional to the square of the
current, so rises quite rapidly as cur-
TJ= -5S0C
--
~~ I TJ-25 U C
16
AV TJi1~5~C
l ,L .l.
o
f- I-- . vos=
1oov
....;. SO"••e PULSE TEST
o 2 4 6 8 10
10, ORAIN CURRENT (AMPERES)
Figure 2. Transconductance Vs.
Drain Current of the
IRF330.
rent increases. The required heatsink
DC thermal resistance decreases quite
rapidly with increasing continuous
drain current, for two reasons. First,
permissible case-to-ambient temper-
ature decreases; and second, power
dissipation increases.
For this reason the usable continu-
ous direct current of a power MOS-
FET for most practical purposes re-
lates to a case temperature around 90
to 100° C. This allows a sufficient dif-
ferential between case and ambient
temperature for the heat dissipator to
handle the heat transfer, maintaining
the case temperature at or below the
permitted maximum.
The "headlined" continuous current
rating shown on the data sheets of
most power MOSFETs is usually
greater than the above practically
usable level of continuous drain cur-
rent. This is because the case tempera-
ture adopted by the industry to which
the "headlined" continuous I 0 rating
applies is only 25° C.
Figure 5 shows typical heatsinks for
TO-3 and TO-220 packaged HEX-
FETs that allow them to operate in a
40° C ambient at a continuous direct
drain current that is 60 to 70% of the
rated continuous drain current at T c
= 25° C; the corresponding steady
case temperature is about 100°C.
Actually, the continuous current
rating of a MOSFET is often of little
direct use to the designer, other than
as a benchmark. This is because in
many switching applications the
*Thermal Impedance = Normalized Value x
o 4 6 7
GATE CHARGE (nC)
Figure 3. Typical Relationships for IRF330 HEXFET Between Gate
Charge. Gate Voltage and Amplitude of Drain Current
Being Switched.
MOSFET operates at a switching
duty cycle considerably less than
100%, and what is really of interest is
the current-carrying capability of the
device under the actual "switched"
operating conditions. This is dis-
cussed in the next section.
Switching "Duty Cycle" Ratings
As has been seen, the basic criterion
that determines the current-carrying
capability of a HEXFET is junction
heating. For most practical purposes,
the HEXFET can carry any wave-
form of current under any "duty
cycle", just so long as the peak junc-
tion temperature is kept within the
rated T(J.tDax) (150°C). (The RMS
content 01 the current wave must not
exceed the continuous 10 rating, in
order not to exceed the RMS current
carrying capability of the source
bonding wire. Compliance with this
will generally be a natural result of
compliance with the condition
above.)
Peak junction temperature for any
"duty cycle" application can be cal-
culated directly from the transient
thermal impedance characteristics for
the device, as given in the data sheet.
Transient thermal impedance curves
for the IRF330 HEXFET are shown
in Figure 6. Each of these curves is
normalized to the steady DC junc-
tion-to-case thermal resistance (1.67
deg. CjWatts for the IRF330).
The curve labelled "single pulse"
shows the rise of junction tempera-
DC Thermal Resistance
~
2~~4----+----~--+-~~
o 30
9 10 11 12
o 15
Figure 4. Case Temperature and Power as Function
of lofor IRF330 HEXFET.
A-27
ture per watt of power dissipation as
a function of pulse duration. As
expected, junction temperature rise
increases as pulse duration increases
- leveling off to a steady value for
pulse durations above I second or so.
The "single pulse" curve is useful
for determining transient junction
temperature rise for single or very
low duty cycle pulses of power; it is
not directly usable for repetitive
power pulses, such as are usually
encountered in switching applica-
tions. The remaining curves in Figure
6 show effective thermal impedance
for repetitive operation at different
duty cycles, and allow peak junction
temperature rise for repetitive opera-
tion to be calculated directly. These
curves are approximately related to
the single pulse curve, by the follow-
ing relationship:
Effective normalized thermal im-
pedance.
=D+( I - D) x (normalized transient
thermal impedance for single pulse
of duration t).
The effective thermal impedance,*
when multiplied by the power dissi-
pation during the conduction period t
(i.e., the power within the conduction
pulse itself, not the power averaged
over the whole cycle), gives the value
of the repetitive peak junction-to-
case temperature rise.
As seen from Figure 6, the effective
thermal impedance for any duty cycle
D increases as pulse duration in-
creases, showing that the peak junc-
80 90 120 150 - CASE TEMP. ·C
30 45 60 75 - POWER, WATfS
 (a) Type 621-A heatsink gives 4A
continuous rating for IRF331 with
5 CFM airflow in 40°C ambient.
Figure 5. Typical Heatsinks for HEXFETS. (Heatsinks by Wakefield)
0"05
~t0.1
f - - 01 .
f - - 0.05
f--O.02
F-0.01 SINGLE PULSE (TRANSIENT
.-!""""'I
mIRMA~ I~PEOtNrE\
1111 I I II
10-4
Figure 6. Normalized Transient Thermal Impedance Curves for IRF330 HEXFET. Curves are normalized to DC Thermal Resistance
(1.67°C/W for IRF330).
tion temperature rise increases as
frequency decreases. The reason for
this is illustrated by the waveforms in
Figure 7 (a) and (b). Both sets of
waveforms are for the same power
dissipation and duty cycle, but for
different operating frequencies. The
cycle-by-cycle fluctuations of junc-
tion temperature at 20Hz (Figure
7[a]) are clearly greater than at 200Hz
(Figure 7[b]), As frequency increases,
thermal inertia of the junction "irons
out"instantaneous temperature fluc-
tuations, and the junction responds
more to average, rather than peak,
power dissipation. At frequencies
above a few kHz, and duty cycles
above 20% or so, cycle-by-cycle tem-
perature fluctuations usually become
small, and peak junction tempera-
ture rise becomes equal to the aver-
(b) Type 641-A heatsink gives 3.5A
continuous rating for IRF331 with
natural convection cooling in 40° C
ambient.
'--
I I
10-3 .2 10-2
Ij,SQUARE WAVE PULSE DURATION (SECONDS)
age power dissipation multiplied by
the DC junction-to-case thermal re-
sistance, within one or two percent.
To determine the absolute value of
the peak junction temperature, it is,
of course, necessary to know the case
temperature T cunder steady operat-
ing conditions. Because of thermal
inertia, the heatsink responds only to
average power dissipation (except at
extremely low frequencies which gen-
erally will not be of practical inter-
est). T c is therefore given by:
Tc =TA + (R thC-S + R thS -A ) P AV
where:
TA = ambient temperature
R thC- S = case-to-sink thermal resist-
ance
R thS - A = sink-to-ambient thermal re-
sistance
A-28
(e) Type 689-756-4 heatsink gives lA
continuous rating for IRF71 0 with
natural convection cooling in 40°C
ambient.
NOTES:
3nJL.
~2~
1. DUTY FACTOR. 0 _ t1
t2
2. PER UNIT BASE 0 RthJC 01.67 OEG. CM.
3. TJM - T Co POM ZthJC(t).
10- 1 1.0 10
P AV = average power dissipation
= peak power x duty cycle,
for rectangular pulses of
power
Peak Current Ratings
The underlying limitation on cur-
rent handling capability of a HEX-
PET is junction heating, It is able to
carry peak current well in excess of
its continuous ID rating, provided
that the rated junction temperature is
not exceeded. There is, however, an
upper limit on the permissible cur-
rent, defined by the rated I DM . Most
HEXFETs have an I DM rating that is
about4X the continuous ID rating at
T C = 25° C. This is a very substantial
peak current carrying capability by
comparison with the ICM rating of a
bipolar - especially when it is rec-

~---,-100W
POWER
JUNCTION
TEMP
RISE
(a) t = 10 ms D = 0.2
POWER
JUNCTION
-H--t= 1 ms
TEMP
RISE
(b) t
Figure 7. Waveforms of Power and Junction Temperature for Repetitive Operation,
showing that Peak Junction Temperature is Function of Operating
Frequency. IRF330.
ognized that the IDM rating of a
HEXFET is usable, whereas the ICM
rating of a bipolar generally is not.
The IDM limit of a HEXFET is
determined by the fact that it is, after
all, fundamentally a "linear" device.
As drain current increases, the point
eventually is reached at which the
HEXFET goes into "linear" opera-
tion and starts to act, in effect, as a
current limiter. This point depends
upon the drive voltage applied to the
gate, the safe limit of which is deter-
mined by the thickness of the oxide
that insulates the gate from the body
of the device. 10M ratings of all
HEXFETs are achievable with an
20A/DIV 201ls/DIV
Figure 8. 52A, 7 !.tS Pulses Being Carried by the
IRF450 at Frequency of 1kHz.
=1ms D =0.2
applied gate voltage that is equal to
the maximum permissible gate-to-
source voltage of 20V.
Designers often do not know how
to interpret the IDM rating. Data
sheets typically give little or no sup-
porting information, and no direct
indication of whether this is a non-
repetitive or repetitive rating. The
fact is that the I DM rating of all
HEXFETs can be used both for
repetitive and non-repetitive opera-
tion, so long as the junction tempera-
ture is kept within the rated T Jm.x'
Peak junction temperature can be
calculated from the thermal impe-
dance data for the device (shown in
Figure 9. Single Shot 150A peak Exponentially
A-29
Figure 6). The IDM rating is simply a
"ceiling"; below this ceiling, the de-
signer is free to move, provided the
TJmax rating is not violated.
Use ofthe HEXFET's peak current
ratings is illustrated by the oscillo-
grams in Figures 8 through 10. Fig-
ure 8 shows operation of the 500V
rated IRF450 at a repetitive peak
current of 52A. The conduction time
of the rectangular current pulse is
7 IlS, and the operating frequency is
1kHz. The rated continuous ID (at
T C =25° C) of this device is 13A, and
its rated IDM is 52A.
Figure 9 illustrates the use of the
IDM rating ofthe 100V IRFI50 HEX-
FET for a "single shot" low duty
cycle application, such as capacitor
charging or motor starting. The peak
current is 150A, decaying to 50A in ap-
proximately 10 milliseconds. Figure
10 illustrates similar duty, but in this
case, the initial peak current is 100A,
decreasing to 30A in approximately
400 milliseconds. The rated continu-
ousID (at Tc = 25°C) of the IRFl50
is 40A, and its rated IDM is 160A.
It should be pointed out that the
on-resistance of any MOSFET does
increase as current increases. As
shown in Figure II, the on-resistance
of a 100V rated HEXFET at its rated
IDM with 20V applied to the gate is
tyically 1.4 x the value at the rated I D;
the corresponding multiplier for a
400V rated HEXFET is 2.9. This
increase of on-resistance must, of
course, be taken into account when
making thermal calculations and de-
signing for use of the IDM rating.
Safe Operating Area of MOSFET
It has been tacitly assumed so far
that the HEXFET is operated as a
"closed switch" in the "fully en-
50A/OIV 21ls/ 0lV
Decaying Pulse Applied to the IRF150.
Time Constant ~ 8msec
 can be calculated directly from the
single pulse transient thermal impe-
dance data. Nor are they particularly
useful from the circuit design view-
point, because they apply to single
pulses at a case temperature of 25° C
- conditions not generally encoun-
tered in practice.
Why, then, are the SOA curves
included in the MOSFET's data
sheet? The reason is that if they were
not, their absence would raise ques-
tions in designers' minds. Users who
are accustomed to bipolar transistors
have come to look upon the SOA
curves for these devices as being vital
- as indeed they are - because they
define the bipolar's second break-
down limits.
Figure 10. Single Shot l00A peak Exponentially Decaying Pulse Applied to SOA curves for HEXFETs, on the
IRF15o. Time Constant.;. 300msec . other hand, are in essence nothing
more than a graphical statement of
the absence of second breakdown-
vital information, to be sure, but
information which in reality need not
3~----~------~--'---~-----'------' be conveyed through a set of some-
100V
what arbitrary curves.
The oscillograms in Figure 13 (a)
HEXFET
and (b) are a verification of the
HEXFET's SOA data. Figure 13 (a)
shows a 10 microsecond 150A pulse
C 2~------~------~-4~--+---~~+-----~ of current being applied to the 100V
2 IRFI50 HEXFET, with an applied
:g
a::
!::
t
400V V GS =20V
drain-to-source voltage of 80V. Fig-
ure 13 (b) shows a 10 microsecond
50A pulse of current being applied to
z HEXFET the 500V rated IRF450 with an app-
:::l
lied drain-to-source voltage of 400V.
a::
w
CI.
Design Examples
The following examples illustrate
typical design procedures:
____ ____ ____-L______ ____-J Repetitive Operation -
O
~
~
.
-
~
~
o 20 t 40 60 80 100 30% Duty Cyele
A 400V rated HEXFET and a cor-
Rated 10@Tc = 25°C %IDM responding heatsink are required for
continuous operation with a rectan-
Figure 11. Typical Variation of On-Resistance with Drain Current. 100% 10M ,;, 4 x lo@ gular current waveform. Amplitude
Tc=25°C of the current is 3.5A, duty cycle is
30%, and ambient temperature is
45° C. Switching losses and cycle-by-
cycle fluctuations of junction tem-
perature can be ignored.
hanced" mode; the amount of cur- curve, for the IRF330, is shown in Candidate devices would be the
rent that the switch can handle has Figure 12. IRF332 and IRF320. Key ratings
been shown to be calculatable for any SOA curves for HEXFETs are and characteristics for these devices
specific design situation from a based upon a case temperature of are shown in Table I.
knowledge of the conduction losses, 25° C, and an internal power dissipa-
the effective transient thermal im- tion that increases the junction tem- Conduction losses for IRF332:
pedance, and the heatsink thermal perature to 150° C at the end of the =3.5 x 11.55 x 0.3
resistance. power pulse. Since HEXFETs, unlike = 12.IW
MOSFET data sheets generally bipolar transistors, do not exhibit Required R thJ _A = (150 - 45)
show a graph of Safe Operating second breakdown, SOA curves for 12.1
Area, for single pulses of power of each pulse duration invariably follow =8.7°C;W
varying duration, which for the most a line of constant power at all volt- Required R thS-A = 8.7 - 1.97
part cover areas of "linear" rather ages less than rated maximum Vos 6.7°C;W
than "fully enhanced" operation. and more than the "fully enhanced"
These curves embrace drain current VO!Xonl. =10 X Ros(gn)' Conduction losses for IRF320:
and voltage values up to rated 10M The SOA curves for HEXFETs in =3.5 x 13.9 x 0.3
and Vos, respectively. A typical SOA reality are redundant, because they =14.6W
A-30
 (150 - 45) Table 1. Design details for IRF332 and IRF320 HEXFErs
Required R thJ -A 14.6 IRF332 IRF320
= 7.2°CfW
Required R thS -A = 7.2 - 3.12 VDS Volts 400 400
=4°CfW I D @Tc =25°C Amps 4.5 3.0
These calculations show that either VDS(on) @ 5A, 150°C Volts 11.55 13.9
of the candidate HEXFETs could
serve the application. The smaller RthJ-C °CfW 1.67 3.12
IRF320 (almost half the chip size of °CfW 0.2 0.2
the IRF332) would require a rela- RthC-S
tively larger (though quite practical) Approximate die size miP 19,250 1l,700
heatsink, and would dissipate 14.6
instead of 1.21 W giving about a 1%
reduction in overall system efficiency.
The final choice of device will de-
pend upon trade-offs betweenecono-
mics, size, and performance. The 100
main purpose of this example has OPERATION IN THIS
been to demonstrate that there is a 50 AREA IS LIMITED
choice, and that either of two HEX- BY ROS(on)
FET types are viable candidates.
Repetitive Operation at High Peak 20
IRF330,1 1
Current, Low Duty Cycle ~mn II'
It is required to find the thermal
en
UJ
a:: 10
"-1 Jill ~ ~. "' 1', ~ '~
resistance of the heatsink needed to UJ
c..
operate the 400V, 5.5A (continuous) ::iE ='RF330,1
rated IRF330 HEXFETwith a repet- ~ lOps
5
itive rectangular current waveform t-
Z -'RF332,3 "- \ , 1
of amplitude 18A. On-time is IO UJ

'" "-
microseconds, and duty cycle is 0.1 %.
Ambient temperature is 40°C.
a::
a::
=>
u
2
/
~/ ~
"

-"
l1f
':No 11~s'-
z
-.
The limiting on-resistance of the
IRF330 at ID = 5.5A at 25°C is 1.0 <t
a:: 1.0 ~' I Ij I
ohm. Knowing that 100% IDM = 22A, Q

the limiting value of RDS(o!!l at ID = 6 f-T C = 25°C

18A can be estimated from Figure II "-

,
0.5
to be 2.3 ohms at 25° C. From the ~TJ = 150°C MAX. ~. 10 ms
relationship between RDS(on) and f- RthJC = 1,67 K!W !I lb6 ~s
rii IR~~31, 3
ln
temperature given in the data sheet, IIII
RDS(on) at TJ = 150°C and ID = 18A
0.2 I-f'~GLT PP1S IIII I

will be about 5.1 ohms. II I 'IRI ~~30,?- ~ ,C

0.1
Power per pulse = 182 x 5.1 1.0 2 5 10 20 50 100 200 500
= 1.652 x 103W
VOS ' ORAIN·TO·SOURCE VOLTAGE (VOLTS)
Junction-to-case transient thermal
impedance for IO IlS pulse (from Fig-
ure 6):
= 1.67 x 0.03 Figure 12. Safe Operating Area, IRF330 HEXFET.
=0.05°CfW

(s) IRF150, 50Aldiv, 2J'S/div (b) IRF450, 2OAldiv, 2J'S1div

Figure 13. Oscillograms Verifying SOA Curves of HEXFETs, Demonstrating the Absence of Second Breakdown

A-31
 lunction-to-case temperature rise
due to 18A pulse:
= 1.652 x 103 x 0.05
= 82.6°C.
Maximum permissible case tem-
perature:
= 150 - 82.6 = 67.4°C
Te-TA =67.4-40=27.4°C
Average power dissipation:
= 0.01 x 1.652 x 103
= 1.652W
:. RthC-A = 1~l5i = 16.6°CfW
High Peak Current, Single Pulse
Operation
The IRF330 HEXFET is to be
pulsed with a current having an initial
amplitude of 20A, and an exponen-
tial waveform with a time constant of
150 J.lsec. Case temperature is 30° C.
Verify that the peak junction tem-
perature does not exceed 150°C.
As an approximation, an equivalent
rectangular pulse of current will be
assumed, with an amplitude of 15A,
and a duration of 150 microseconds.
Ros(onJ for.the IRF330@ 10 = I~A,
T J = 25 C, IS 1.8 ohms. At 150 C,
ROS(on) is approximately 2.2 x this
value tsee above example), and is
about 4.0 ohms.
Equivalent "rectang'ular power";
= 152 x 4.0 = 900W
lunction-to-case transient thermal
impedance for 150 microsecond pulse
(from Figure 6):
= 0.065 x 1.67 = O.lloCfW
:. lunction-to-case temperature
rise
=O.ll x900=99°C
:. TJ = 30 + 99°C = 129°C
Hence, this operating condition is
within the capability of the IRF330.
Comparison of MOSFET and BI-
polar Losses
Conduction power in a bipolar tran-
sistor is generally lower than in a
MOSFET, but switching energy is
usually considerably higher. The bi-
polar, therefore, tends to be more
efficient at low frequency, while the
MOSFET is more efficient at high
frequency.
In an effort to close the gap between
bipolar and MOSFET performance
in high frequency switching applica-
tions, several new types of fast switch-
ing bipolar transistors have recently
been introduced, with switching times
in the order to 100 to 200 nanosec-
onds. It is pertinent to compare the
losses of these new bi polar types with
those of comparably rated MOS-
FETs.
Figure 14 shows measured power
8.0 r;::;=:;-;;::=;;-;---r----,r---,---"7--,.----,
en
5 6Dr------TL-~L-~--~--r---~~~~--_r----__1
3:
2'
o
~ 4.0 r------+-------f"o.,;....p---r----:7"'~------
~
Cii
ffi0 2.01-I _~~~~~~~~====~:::::j:::TIIR~F§3~3~01HliE~X~F~E1T~
3:
Il. EFFICIENCY CROSS-OVER POINT IRF330
AI':ID FAST SWITCHING BIPOLAR
EFFICIENCY CROSS-OVER POINT. IF\F330 AND 2N6542/3
FREQUENCY, kHz
Figure 14. Power Dissipation Versus Frequency for 2N6542/3, Fast Switching
Bipolar, and IRF330 HEXFET, Supply Voltage = 270V. Conduction Duty
Cycle = 0.33. Current Amplitude = 2.5A.
dissipation as a function offrequency device. Additional power is dissipated
for the IRF330 HEXFET, the in- in the external base drive circuit of
dustry-standard 2N6542/3 bipolar the bipolar. The "dashed" curve for
transistor, and a newly introduced the fast-switching bipolar includes an
fast switching bipolar. Power losses additionall.3W of external base drive
were obtained by measuring the case power. This corresponds to an 8V,
temperature rise of the device mount- 0.5A drive circuit, operating at 33%
ed on a calibrated heatsink. Thermal duty cycle.
resistance from case-to-ambient was Figure 15 shows collector current
approximately 4;5 deg. C/W. A and voltage oscillograms for the fast-
clamped inductive load was used. switching bipolar transistor operat-
Details of the three device types ing at 100kHz, and Figure 16 shows
listed are summarized in Table 2. drain current and voltage oscilla-
Note that the die area for the HEX- grams for the HEXFET at 100kHz.
FET is approximately 80% of that of Note the sharper HEXFET wave-
each of the bipolar transistors - forms, confirming its faster switching
thus, the comparison is weighted in speed.
favor of the larger-die bipolar devices. Oscillograms of base drive current
Figure 14 shows that the frequency for the bipolar and gate drive current
crossover point for the HEXFET
for the HEXFET are shown in Fig-
and the 2N6542/3 is approximately ure 17 (a) and (b), respectively. The
25kHz, while it is approximately bipolar requires a significant base
35kHz for the HEXFETand the fast- drive current both at turn-on -
switching bipolar transistor. Operat- about IA peak - and at turn-off-
ing conditions were: circuit supply 2.5A peak. The HEXFET, by com-
voltage = 270V, peak current = 2.5A, parison, consumes about 0.3A for a
duty cycle = 33%. few nanoseconds at turn-on, and
Note that the "full" curves repre- about 0.2A for a few nanoseconds at
sent only the dissipation within the turn-off. This current charges and
Table 2 Details of Devices Tested
IRF330 2N6S42/3 Fast-Switching
HEXFET Bipolar Bipolar
Vos Volts 400 400 450 VCEO(SUS)
IOcont A @ 6 5 5 Ie con! A @
Tc = 25°C Tc = 25°C
19,500 25,000 25,000 Die Area mii2
Die Area miP
A-32
(a) Collector Current. O.SA/Div, 1l's/Div (b) Collector Voltage. SOVIDiv, 1l's/Div

Figure 15. Collector Current and Voltage Waveforms for Fast-Switching Bipolar Operating at 100kHz.

(a) Drain Current. O.SA/Div, 1l's/Div (b) Collector Voltage. SOVIDiv, 1l's/Div

Figure 16. Drain Current and Voltage Waveforms for IRF330 HEXFET Operating at 100kHz.

(a) Bipolar. O.SA/Div 1l's/Div -2.5A (b) HEXFET. 0.1 A/Div 1l's/Div
Figure 17. (a) Base Drive Current for Fast Switching Bipolar (b) Gate Drive Current for IRF330 HEXFET Operating
Operating at 2.SA, 100kHz. Vee = 270V at 2.SA, 100kHz. Voo= 270V.

A-33
discharges the self-capacitance of the
device. Note the change of current
scale between Figure 17 (a) and (b).
Average gate drive power for the
HEXFET is negligible - about one-
fiftieth ofa watt at 100kHz. Although
the bipolar is driven with lA peak
base current, it nonetheless exhibits a
noticeable voltage "tailing" at tum-
on, as ,seen in Figure 15 (b).
The osci11ogra~s in Figure 18 com-
pare the instantaneous power and
energy dissipation for the fast-switch-
ing bipolar and the HEXFET. Figure
18 (a) shows instantaneous power,
while Figure 18 (b) shows the integral
of the power; in other words, the
accumulated energy dissipated dur-
ing the conduction period.
Clearly the energy expended in the
bipolar at turn-on and at turn-off is
greater than in the HEXFET, while
the energy expended in the HEXFET
during the conduction period is
greater than in the bipolar. These
oscillograms do not give precise
BIPOLAR 100W/DIV
25~J/DIV
Figure 18. Oscillographs of (a) Power and (b) Energy for Fast-Switching Bipolar Transistor and HEXFET from Turn-On to Turn-Off.
= =
Circuit Voltage 270V. Switched Current 2.5A. Duty Cycle 33%. Frequency 100 kHz.
quantitative data because of the lack
of resolution of the oscilloscope at
these fast-switching speeds; they do,
nonetheless, provide a good qualita-
tive picture of the different switching
and conduction losses in the two
types of devices.
Figure 19 shows a comparison of
power losses versus frequency for the
HEXFET and the fast-switching bi-
polar, for the same 2.5A current and
33% duty cycle, but at a circuit volt-
age of only 70V - instead of the
previous 270V. While the HEXFET
losses are about the same as in the
higher voltage circuit, the lower sup-
ply voltage greatly de-emphasizes the
switching losses ofthe bipolar, giving
a higher frequency crossover point
(almost 70kHz). These curves, how-
ever, are not representative of a typi-
cal operating situation, since the 70V
circuit voltage is unrealistically low
for 400 to 450V rated devices.
Finally, the curves in Figure 20
show power losses versus frequency
HEXFET 250W/DIV
= =
A-34
for the HEXFETandthefast-switch-
ing bipolar, operating at a peak cur-
rent of5A ina 270V circuit, at a duty
cycle of 33%. Although the conduc-
tion losses of the HEXFET are more
than 4x greater than with ID =2.5A,
the switching losses ofthe bipolar are
also significantly greater. Addition-
ally, the bipolar's base drive current
has to be increased significantly to
maintain acceptable switching per-
formance, as shown by the oscillo-
gram in Figure 21. Interestingly, the
frequency "crossover point" is not
greatly different from that obtained
at2.5A-about42kHzversus35kHz,
ignoring external base drive power,
and about 20kHz, taking this into
account.
Conclusions
The main purpose of this applica-
tion note has been to show that the
current-carrying capability of a
power MOSFET is determined essen-
tially by thermal considerations, un-
25~J/DIV
like that of the bipolar transistor,
which is limited by gain. With proper
thermal design, the HEXFET can be
operated at much higher peak cur-
rent than a comparable bipolar.
A practical comparison of power CONDUCTION 2N6542/3 BIPOLAR
losses of a HEXFET and a fast- CURRENT
switching bipolar transistor in a
switching application shows that the
HEXFET is generally more efficient
above frequencies in the 20 to 40 kHz
~
!.3.0 JTLIn
I

range. 0 S2 -J 1 1-2-1
~ 2.0~----~~-----+------~~~~~==
~
o
a:
w 1.0 r-----_+---7"~""I_------t--\---_+------+_----____I
~
Q..

O~ ____ ~______ ______ ____ ______ ____

~ ~ ~ ~ ~

Editors' Note: This Application Note AN-949

is a much expanded version of the subject o 20 40 60 80 100
discussed in Application Note AN-945, "Un-
derstanding HEXFET Current Ratings - A FREQUENCY, kHz
Necessity for the Cost-Conscious Designer,"
which this application note supersedes.
Figure 19. Power Dissipation Versus Frequency for 2N6S42/3, Fast-Switching Bipolar
and IRF330 HEXFET. Supply Voltage = 70V. Conduction Duty Cycle =
0.33. Current Amplitude = 2.SA.

FAST SWITCHING BIPOLAR

INCLUDING 4W BASE
DRIVE POWER CONDUCTION CURRENT

~
s
'\/
12r----t~~t-~_i~r-i=~~--~~
5A

z·
o
~ IRF330 HEXFET
I I

~ 81---::'---f-'r-+- EFFICIENCY CROSS-OVER POINT

EXCLUDING EXTERNAL
is BASE DRIVE POWER
a:
w
~
Q..

lA/DIV 2I's/DIV
60
FREQUENCY, kHz
Figure 20. Power Dissipation Versus Frequency for Fast- Figure 21. Base Drive Current for Fast-Switching Bipolar.
Switching Bipolar and IRF330. Supply Voltage = Circuit Voltage =270V. Collector Current =SA.
270V. Conduction Duty Cycle = 0.33. Current Operating Frequency = SOkHz.
Amplitude = SA.

A-35
CHAPTER 4
APPLICATION NOTE 944

A New Gate Charge Factor Leads to

Easy Drive Design for Power MOSFET Circuits
By B. R. PELL Y

Designers unfamiliar with
MOSFET characteristics begin drive
circuit design by determining compo-
nent values based on the gate-to-
source, or input, capacitance listed
on the data sheet. While RC values
derived in this manner do serve as a
starting point in design, they can only
be considered as a first-order bench-
mark.
If the designer wants to switch the
MOSFET in 100 nanoseconds, an
RC value based on the gate-to-source
capacitance is determined to provide
a suitable, theoretical time constant.
The RC value does not solve the
entire problem because the gate-to-
drain capacitance must also be
accounted for in charge time.
Although the gate-to-source cap-
acitance is an important value, the
gate-to-drain capacitance is actually
more significant - and more diffi-
cult to deal with - because it is a
non-linear capacitance affected as a
function of voltage; the gate-to-
static electrode capacitances. The
phenomenon of the effects of the
plate impedance and voltage gain on
the input admittance was first stu-
died in vacuum tube triode amplifier
circuits by John M. Miller.
Essentially, at high frequencies
where the grid-to-plate (gate-to-
drain) capacitance is not negligible,
the circuit is not open but involves a
capacitance that is a function of the
voltage gain.
Solving for the "Miller" effect is
not exactly a straightforward pro-
cess, even with vacuum tubes where
much is known, but is even more dif-
ficult in MOSFETs. In actuality, the
gate-to-drain capacitance though
smaller in static value than the gate-
to-source capacitance, goes through
a voltage excursion that is often more
than 20 times that of the gate-to-
source capacity. Therefore, the gate-
to-drain or "Miller" capacitance
typically requires more actual charge
than the input capacitance.
To account for both gate-to-
source and gate-to-drain capacitance
in a way readily usable by designers,
each HEXFET from International
Rectifier is tested to yield a specifica-
tion termed "gate charge," that can
be used to calculate drive circuit
requirements.
A typical test circuit that can be
used to measure the gate charge is
lOon
2W

source capacitance is also affected as

a voltag~ function, but to a much
lesser extent. This gate-to-drain cap-
acitance function is similar to that
found in vacuum tube amplifiers. 5V
5- 10 MSEC
The gate-to-drain capacitance 600 Hz
effect is akin to the "Miller" effect, a
phenomenon by which a feedback
path between the input and output of
an electronic device is provided by
the interelectrode capacitance. This
affects the total input admittance of
the device which results in the total Figure 1. HEXFET Gate Charge Circuit.
dynamic input capacitance generally
being greater than the sum of the

A-36
 Figure 2. Gate Charge Waveform for Different Values of Drain Voltage
(IRF130: IG" 1.5 rnA, 10" 1A, V DD ' 10,40 and 80 Volts).
shown in Figure l. In this circuit, an during the flat portion, the gate-to-
approximately constant current is sup- drain capacitance is charging. This
plied to the gate of the device-under- oscillogram therefore clearly differ-
test from the 0.1 JLF capacitor CI, entiates between the charge required
through the regulator diode D l. A for the gate-source and gate-to-drain
constant current in the drain circuit is ("Miller'') capacitances. At the
set by setting the voltage on the gate second voltage rise, both capacitan-
of HEXFET I, so the net measure- ces are charged to the extent needed
ment of the charge consumed by the to switch the given voltage and cur-
gate is relative to a given current and rent. A more detailed explanation of
voltage in the source-to-drain path. the interpretation of this data is given
An oscillogram of the gate-to- later.
source voltage during testing, shown The graph in Figure 3 represents
in Figure 2, relates the gate voltage to gate voltage versus gate charge in
time. Since a constant current is nanocoulombs for an IRFI30.
supplied to the gate, the horizontal Although the second voltage rise
time scale is directly proportional to indicates the point at which the
the charge supplied to the gate. With switching operation is completed,
a suitable scaling factor, therefore, normal design safety margins will
this oscillogram is a plot of gate vol- dictate that the level of drive voltage
tage versus charge. applied to the gate is greater than
The point on the oscillogram of the that which is just required to switch
second voltage rise indicates where the given drain current and voltage.
the device is fully switched on. Dur- The total charge consumed by the
ing the first voltage rise, the gate-to- gate will therefore in practice be
source capacitance is charging, and higher than the minimum required-
14
12
10
~o 8 achievable switching time. With gate
> charge known, the designer can
en
Cl
> the switching time required.
4 pie of a 100 kHz switcher, in which it
10 15 20 25 30
Q G NANOCOULOMBS
Figure 3. Gate Voltage Versus Gate Charge for the IRF130.
A-37
but not necessarily significantly so.
For example, the gate charge
required to switch 12 A at 80 V is 15
nanocoulombs (point A), and the
corresponding gate voltage is about 7
V. If the applied drive voltage has an
amplitude of 10 V (i.e. a 3 V margin),
then the total gate charge actually
consumed would be about 20 nano-
coulombs, (point B).
As shown on the graph, whether
switching 10 or 80 volts in the drain
circuit, there is a much less than pro-
portional difference in the charge
required. This is because the "Miller"
capacitance is a nonlinear function of
voltage, and decreases with increas-
ing voltage.
The importance of the gate charge
data to the designer is illustrated as
follows. Taking the previous exam-
ple, about 15 nanocoulombs of gate
charge are required to switch a drain
voltage of 80 V and a drain current of
12 A. Since the 15 nC gate charge is
the product of the gate input current
and the switching time, if 1.5 A is
supplied to the gate, the device will be
switched in 10 ns. It follows that if 15
rnA is supplied to the gate, then
switching occurs in 1 JLS, and so on.
These simple calculations imme-
diately tell the designer the trade-offs
between the amount of current avail-
able from the drive circuit and the
develop a drive circuit appropriate to
Consider a typical practical exam-
is required to achieve a switching
time of 100 nanoseconds. The
required gate drive current is derived
by simply dividing the gate charge, 15
X 10.9 , by the required switching
time, 100 X 10.9 , giving 150 rnA.
From this calculation, the designer
can further arrive at the drive circuit
impedance. If the drive circuit app-
lies 14 V to the gate, for instance, portionally. So long as the actual At time t2, the drain current
then a drive impedance of about 50 drain current is still building up reaches ID, and the freewheeling rec-
ohms would be required. 'Note that towards the available drain current, tifier shuts off; the potential of the
throughout the "flat" part of the ID, the freewheeling rectifier stays in drain now is no longer tied to the
switching period (Figure 3), the gate conduction, the voltage across it supply, voltage, VDD. The drain cur-
voltage is cO,nstant at about 7 V. The remains low, and the voltage across rent now stays constant at the value
difference between the applied 14 V the D UT continues to be virtually the' ID enforced by the circuit, whilst the
and 7 V is what is available to drive full circuit voltage, VDD-. The top end drain voltage starts to fall. Since the
the required current through the drive of the drain-to-gate capacitance eGD gate voltage is inextricably related to
circuit resistance .. therefore remains at a fixed poten-. the drain current by the intrinsic
The gate charge data also lets the tial, whilst the potential of the lower transfer characteristic of the DUT
designer quickly determine average end moves' with that of the gate. The (so long as operation remains in the
gate drive power. The average gate charging current taken by CaD dur- "active" region), the gate voltage now
drive power, PDRIVE, is QGVGf. ing this period is small, and for prac- stays constant because the
Taking the above 100 kHz switcher tical purposes it can be neglected, "enforced" drain current is constant:
as an example, and assuming a gate since eGD is numerically small by For the time being, therefore, no
drive voltage VG of 14 V, the approp- comparison with eGs. further charge is consumed by the
riate value of gate charge QG is 27
nanocoulombs (point e on Figure 3).
The average drive power is therefore
27 X 10-9 X 14 X 105 = 0.Q38 Watts.
Even though the 150 rnA drive cur-
rent which flows during the switching
interval may appear to be relatively
o
high, the average power is miniscule
(0.004%) in relation to the power
being switched in the drain current.
This' is because the drive current
flows for such a short period that the
average power is negligible.
Thus actual drive power for
MOSFETs is minute compared to
bipolar requirements, which must
sustain switching current during the
entire ON condition. Average drive
power, of course, increases at higher
frequencies, but even at 5 MHz it
would be only 1.9 W. Figure 4. Basic Gate Charge Test Circuit

The Gate Charge Curve

The oscillograms of the gate-to-
source voltage in Figure 2 neatly deli-
neate .between the charge required
for the gate-to-source capacitance,
and the charge required for the gate-
to-drain, or "Miller" capacitance.
[he accompanying simplified test GATE
circuit and waveform diagram VOLTAGE
(Figures 4 and 5 respectively) give the
explanation.
Before time to, the switch S is
closed; the device under test (DUT)
supports the full circuit voltage,
VDD, and the gate voltage and drain
current are zero. S is opened at time to;
the gate-to-source capacitance starts
to charge, and the gate-to-source vol-
tage increases. No current flows in
the drain until the gate reaches the
threshold voltage.
During period t1 to t2, the gate-to-
source capacitance continues to Figure 5. Basic Gate Charge Waveforms
charge; the gate voltage continues to
rise and the drain current rises pro-

A-38

I-----Qy
I---QOGy------,
I I
i I
Figure 6. Comparison of Gate Charge Characteristics of Different Device Types.
gate-to-source capacitance, because
the gate voltage remains constant.
Thus the drive current now diverts, in
its entirety, into the "Miller" capacit-
ance Coo, and the drive circuit
charge now contributes exclusively
to discharging the "Miller"
capacitance.
The drain voltage excursion dur-
ing the period t2 to t3 is relatively
large, and hence the total drive
charge is typically higher for the
"Miller" capacitance Coo than for
the gate-to-source capacitance CGs.
At t3 the drain voltage falls to a value
equal to ID X ROS(ON)' and the DUT
now comes out of the "active" region
of operation. (In bipolar transistor
terms, it has reached "saturation. ")
The gate voltage is now no longer
constrained by the transfer charac-
teristic of the device to relate to the
drain current, and is free to increase.
This it does, until time Lt, when the
gate voltage becomes equal to the
voltage "behind" the gate circuit cur-
rent source.
The time scale on the oscillogram
of the gate-to-source voltage is
directly proportional to the charge
delivered by the drive circuit, because
charge is equal to the product of cur-
rent and time, and the current
remains constant throughout the
whole sequence. Thus the length of
the period to to t\ represents the
"I
I ance than smaller ones - the more
charge QGS consumed by the gate-to-
source capacitance, whilst the length
of the period t2 to t3 represents the
charge QGD consumed by the gate-
to-drain or "Miller" capacitance. The
total charge at time t3 is the charge
required to switch the given voltage
Voo and current 10.
The additional charge consumed
after time t3 does not represent
"switching" charge; it is simply the
excess charge which will be delivered
by the drive circuit because the
amplitude of the applied gate drive
voltage normally will be higher (as a
matter of good design practice) than
the bare minimum required to
accomplish switching.
Beware When Comparing
Different Products
Manufacturers sometimes make
technical claims for their products
that appear to be plausible, but
which in actuality do not stand up to
scrutiny.
A case in point concerns the input
capacitance of a power MOSFET.
Statements such as "the input capac-
itance of device Y is less than that of
device X, ergo Y is a faster switch
than X", are frequently bandied
about, but are just as frequently
erroneous.
Apart from the obvious specious-
ness of many such statements -
A-39
"apples" are frequently not com-
pared with "apples", and obviously
larger chips have more self capacit-
basic fundamentals are generally
overlooked.
As this application note shows, of
"bottom line" importance is the total
gate charge required for switching.
The lower the charge, the lower is the
gate drive current needed to achieve a
given switching time.
A general comparison between
hypothetical MOSFETs brands "X"
and "Y" is illustrated in the Figure.
Device X has a higher input capacit-
ance; hence the initial slope of its gate
charge characteristic is less than that
of device Y. QGS of device X is, how-
ever, about the same as that of device
Y, because it has a higher transcon-
ductance and therefore requires less
voltage on its gate for the given
amount of drain current (V GX is less
than VGY). The "Miller" charge con-
sumed by device X is considerably
less than that consumed by device Y.
The overall result is that the total
charge required to switch device X,
Qx, is considerably less than that
required to switch device Y, Qy.
Had the comparison between devi-
ces X and Y been made on the more
superficial basis of input capacitan-
ces, it would have been concluded -
erroneously - that Y is "better" than
X.
Another consideration' is the
energy required for switching. Again,
device X scores handsomely over
device Y in this example. The energy
is the product of the gate charge and
the gate voltage, and is represented
by the area of the rectangle whose
corner lies at the "switching point".
(Point I for device X, and point 2 for
device Y.) It is ob:vious that X
requires significantly less gate energy
than Y.
To summarize: beware of superfi-
cial comparisons. Check the full facts
before deciding which MOSFET
really has the edge in switching
performance.D
CHAPTER 5
APPLICATION NOTE 937

Gate Drive Characteristics and

Requirements for Power HEXFETs
By STEVE CLEMENTE

Introduction Gate Voltage Limitations Since the perforation of this oxide

The conventional bipolar transistor
is essentially a current-driven device.
As illustrated in Figure l(a), a cur-
rent must be applied between the
base and emitter terminals to pro-
d uce a flow of current in the collec-
tor. The amount of a drive required
to produce a given output depends
upon the gain, but invariably a cur-
rent must be made to flow into the
base terminal to produce a flow of
current in the collector.
Figure 2 shows the basic HEXFET
structure. The silicon oxide layer
between the gate and the source
regions can be easily perforated ifthe
gate-to-source voltage exceeds 20V,
even if the current is limited to a very
low value.
l
••• PRODUCES
CURRENT
layer is one of the most common
causes of device failure, great care
should be exercised not to exceed the
gate-to-source maximum voltage rat-
ing. It should be kept in mind, also,
that even if the applied gate voltage is
kept below the maximum rated gate
.J-...
VOLTAGE PRODUCES
AT GATE CURRENT

~ l'o7~'"
iN COLLECTOR
The HEXFET is fundamentally dif-
ferent; it is a voltage-controlled power IC/
MOSFET device. A voltage must be
applied between the gate and source
terminals to produce a flow of cur- VOLTAGE
rent in the drain (see Figure Ib). SOURCE
The gate is isolated electrically from
the source by a layer of silicon oxide. (a) Bipolar Transistor (b) HEXFET
Theoretically, therefore, no current
flows into the gate when a DC volt- Figure 1. Bipolar Transistor is Current Driven, HEXFET is Voltage Driven
age is applied to it - though in prac-
tice there will be an extremely small
leakage current, in the order of nano-
amperes. With no voltage applied
between the gate and source elec-
trodes, the impedance between the
drain and source terminals is very
high, and only a small leakage cur-
rent flows in the drain until the app-
lied voltage exceeds the drain-to-
source avalanche voltage.
When a voltage is applied between
the gate and source terminals, an
electric field is set up within the
HEXFET. This field modulates the
resistance between the drain and
source terminals, and permits a cur-
rent to flow in the drain in response
to the applied drain circuit voltage.
Although it is common knowledge
that HEXFET transistors are more "TRANSISTDR"
DRAIN DRAIN
"TRANSISTOR"
easily driven than bipolars, a few CURRENT CURRENT
basic considerations have to be kept DIODE CURRENT
in mind in order to avoid a loss in
performance or outright device fail- Figure 2. Basic HEXFET Structure
ure.

A-40
voltage, the stray inductance of the
gate connection, coupled with the
gate capacitance, may generate ring-
ing voltages that could lead to the
destruction of the oxide layer. Over-
voltages can also be coupled through
the drain-gate self-capacitance due to
transients in the drain circuit. For
these reasons, it is advisable to con-
nect a zener diode between gate and
source to provide a reliable clamp on
the gate voltage. A small resistor or a
ferrite bead will normally be ade-
quate to swamp out undesired oscil-
lations.
The Impedance of the Gate Circuit
In comparing power HEXFETs to
bipolar transistors, the point is often
made that the former require hardly
any drive power. This is certainly
true, and is the main reason why the
drive circuit is normally an order of
magnitude simpler than for the bipo-
lar counterparts.
However, whenever more than me-
diocre performance is required, care-
ful thought should be given to the
design and layout of the drive stage,
particularly as far as its equivalent
internal impedance is concerned. For
this reason, a word is in order on the
bearing that this internal impedance
has on the device performance.
For a device to be turned ON, a
certain charge has to be supplied to
the gate to raise it to the desired vol-
tage, whether in the linear region, or
in the "saturation". Ideally, the best
way to achieve this is by means of a
voltage source, capable of supplying
any amount of current in the shortest
possible time. If the device is oper-
ated as a switch, a large transient cur-
rent capability of the drive circuit
reduces the time spent in the linear
region, thereby reducing the switch-
ing losses. On the other hand, if the
device is operated in the linear mode,
a relatively large current capability in
th:e gate drive circuit minimizes the
relevance of the Miller effect, im-
proving the bandwidth of the stage
and reducing the harmonic distor-
tion.
The above considerations can be
identified with a detailed analysis of
the basic switching waveforms at
turn-ON and turn-OFFfora clamped
inductive load, as shown in Figures 3
and 5. Figure 3 shows the waveforms
of the drain current, drain-to-source
voltage and gate voltage during the
turn-ON interval. For the sake of
simplicity, the equivalent impedance
of the drive circuit has been assumed

DfWN.SOIIRCE
VOLTAGE

9 ,_____

..l..

""""
G'
0AO
STRAY
INDUCTANCE

SOURCE
"OPEN CIRCUIT" INDUCTANCE
DRIVE
PULSE

DRIVE CIRCUIT

Figure 3. Waveforms at Turn-On

VOLTAGE DROP ACROSS

"IlIIS L MEANS TlIAT "IlIE +
DRAINVOil:u<t~~~~ _ _ DRAJN-SOURCE
VOLTAGE ____
DISCHARGE OF
"IlIIS CAPACITOR
RESULnNG IN ~
MORE CURRENT r - - --
"IlIROUGH "IlIIS J.. CURRENT
RESISTANCE 1""

---4. !

---"IlIIS INDUCED VOLTAGE

SUBTRACTS FROM "IlIE
- lis DRIVE VOLTAGE 1!-____ ~GAnVOLTAGE

~__________I'________~/+ RESULnNGIN '1 I GMHGI

1
~v'"

RESULnNG IN ___________
1 I).
t:z I,
SLOW RISE OF Is

Figure 4. Diagrammatic Representation of Effects When Switching-ON Figure 5. Waveforms at Turn-OFF

A-41
as purely resistive.
At time, to, the drive pulse starts to
rise. At t ( it reaches the threshold
voltage of the HEXFET, and the
drain current starts to increase. At
this point, two things happen which
make the gate-source voltage wave-
form deviate from its original "path".
First, inductance in series with the
source which is common to the gate
circuit develops an induced voltage,
as a result of the increasing source
current. This voltage counteracts the
applied gate drive voltage, and slows
down the rate of rise of voltage
appearing directly across the gate
and source terminals; this in turn
slows down the rate of rise of the
source current. This is a negative
feedback effect; increasing current in
the source produces a counteractive
voltage at the gate, which tends to
resist the change of current.
The second factor that influences
the gate-source voltage is the so-
called "Miller" effect. During the
period t( to t2 some voltage is dropped
across "unc1amped" stray circuit in-
ductance in series with the drain, and
the drain-source voltage starts to fall.
~----------~~--~--~I
A STEP OF VOLTAGE CAUSES
\ transients on the gate. With reference
A TRANSIENT
/ O N THE GATE
Figure 6. Transients of Voltage Induced on the Gate by Rapid Changes on the
Drain-Io-Source Voltage
The decreasing drain-source voltage
is reflected across the drain-gate cap-
acitance, pulling a discharge current
through it, and increasing the effec-
tive capacitive load on the drive cir-
cuit. This in turn increases the volt-
age drop across the source impedance
ofthe drive circuit, and decreases the
rate of rise of voltage appearing
between the gate and source termi-
nals. Obviously, the lower the impe-
dance of the gate drive circuit, the
less this effect will be. This also is a
negative feedback effect; increasing
current in the drain results in a fall of
drain-to-source voltage, which in turn
slows down the rise of gate-source
voltage, and tends to resist the in-
crease of drain current. These effects
are illustrated diagramatically in Fig-
ure 4.
This state of affairs continues
throughout the period t( to t2, whilst
the current in the HEXFET rises to
the level of the current, 1M, already
flowing in the freewheeling rectifier,
and it continues into the next period,
t2 to t3, whilst the current increases
further, due to the reverse recovery of
the freewheeling rectifier.
At time t 3 the freewheeling rectifier
,I
II
I starts to rise. The Miller effect gov-
.....
I
....-
!r,I ~ at a level corresponding to the con-
i I
L,J
I
I
I
I voltage. At t3 the rise of drain voltage
..,.
...L.
n~
I ,
I
I
I
I impedance.
YI
: if the performance is of no great con-
'""'.....-..,..
A-42
starts to support voltage, whilst the
drain current and the drain voltage
start to fall. The rate of fall of drain
voltage is now governed almost ex-
clusively by the Miller effect, and an
equilibrium condition is reached, un-
der which the drain voltage falls at
just the rate necessary for the voltage
between gate and source terminals to
satisfy the level of drain current es-
tablished by the load. This is why the
gate-to-source voltage falls as the
recovery current of the freewheeling
rectifier falls, then stays constant at a
level corresponding to the drain cur-
rent, whilst the drain voltage is faI-
ling. Obviously, the lower the impe-
dance of the gate-drive circuit, the
higher the discharge current through
the drain-gate self-capacitance, and
the faster will be the full time of the
drain voltage.
Finally, at time t4, the HEXFET is
switched fully ON, and the gate-to-
source voltage rises rapidly towards
the applied "open circuit" value.
Similar considerations apply to the
turn-OFF interval. Figure 5 shows
theoretical waveforms for the HEX-
FET in the circuit of Figure 4 during
the turn-OFF interval. At to the gate-
drive starts to fall. At t( the gate vol-
tage reaches a level that just sustains
the drain current, I, and the device
enters the linear mode of operation.
The drain-to-source voltage now
erns the rate-of-rise of drain voltage,
and holds the gate-to-source voltage
stant drain current. The lower the
impedance of the drive circuit, the
greater the charging current into the
drain-gate capacitance, and the fas-
ter will be the rise time of the drain
is complete, and the gate voltage and
drain current start to fall at a rate
determined by the gate-source circuit
In some circuit configurations, even
cern, it may be important to mini-
mize the impedance in the gate drive
circuit to minimize unwanted voltage
to Figure 6, when one HEXFET is
turned ON or OFF, a step of voltage
is applied between drain and source
of the other device on the same leg.
This step of voltage is coupled to the
gate through the gate-to-draincapac-
itance, and it can be large enough to
turn the device ON for a short instant.
To prevent this from occurring, the
gate circuit impedance and/or the
rate-of-rise of the step have to be
reduced to the extent that the voltage
coupled to the gate is below the thre-
shold voltage or some other suitably
chosen safe value.
Driving HEXFETs From TTL
Table I shows the guaranteed sourc-
ing and sinking currents for different
TTL families at their respective volt-
ages. From this table, taking as an
example the 74LS series, it is appar-
ent tha~, even with a sourcing current
as low as 0.4 rnA, the guaranteed
logic one voltage is 2.4V (2.7 for
74LS and 74S), and that is lower than
the possible threshold ofa HEXFET.
The use of a pull-up resistor on the
output (Figure 7) would take this vol-
tage up to SV, but it would still not be
sufficient to guarantee "saturated"
switching of the HEXFET, unless the
current to be switched is substan-
tially less than the rated value of the
HEXFET.
More specifically, with reference to
the output characteristics (Figure 3
of the data sheet), it can be seen that
for a low voltage device (e.g., I RF 130)
the drain current corresponding to a
gate voltage of SV is approximately
half its DC rated value, while for a
high voltage device (e.g., IRF330) it
is higher than the DC rated current.
It should be emphasized though, that
the curves show typical values and
that, with a VGS =SV, saturation is
not guaranteed for either DC or
pulse rated conditions for any device.
Figure 8 shows a typical application
of a TTL inverter driving a IRF320
with the waveforms that would nor-
mally be expected. The 74LSOS is an
open collector device, but waveforms
do not change significantly for a
totem pole device. With reference to
the drain voltage (bottom waveform)
it is apparent that the device turns on
much more slowly than it turns off.
This is because the gate-to-source
and gate-to-drain capacitances are
charged exponentially through the
pull-up resistor, while they are dis-
charged through a saturated bipolar

Table 1. Driving HEXFETs from TTL (Totem Pole Outputs)

Logic (S4L)/ (S4LS)/
Conditions S4/74 54H(74H 74L 74LS 74S
Logic Zero
Min. sink current l6mA 20mA (2)/3.6mA (4)/8 20mA
for VOL ";;;O.4V ";;;(O.4V)/ ";;;(0.3V)/ ";;;(O.4V)/
O.4V O.SV O.SV
Logic One
Max. source -O.4mA -O.5mA -O.2mA -O.4mA -l.OmA
current for VOH ~2.4V ~2.4V ~2.4V ~(2.S)/ ~2.7V
2.7V
Typical Gate IOns 7ns SOns 12ns 4ns
Figure 7. Direct Drive from TTL Output Propagation Delay

Top Trace: Gate Voltage 2V/div. TOp Trace: Gate Voltage 5V/div. Figure 10. Waveforms Associated with the
Middle Trace: Drain Current 1A/div. Middle Trace: Drain Current 2A/div. Circuit in Figure 9, at Different
Bottom Trace: Drain Voltage 100V/div. Bottom Trace: Drain Voltage 10V/div. Drain Voltage. Same Scales
Time Scale: 2I's/div. Time Scale: 500ns/div. except Bottom Trace: 100V/div.

200V VH

-p
12V
l.5Al +12V

68011

~,- 1 ~'RF320

1
Figure 8. Waveforms Associated with Figure 9. Waveforms Obtained with High Figure 11. Simple Interface to Drive
a HEXFET Driven by a TTL Gate Voltage TTL Driver HEXFETs from TTL

A-43
transistor. The waveforms show also,
that the device stays in the linear
region for 9 microseconds and that,
at the end of this time, the gate is
finally free to rise to 5V, after the
gate-to-drain capacitance has been
fully charged. The main reason for
such a poor performance is, of course,
the fact that the maximum voltage
available on the gate is 5V. The per-
formance improves substantially if
two or three gates are connected in
parallel to charge or discharge this
capacitance.
For guaranteed "saturation" and
fast switching, high voltage open col-
lector buffers can be used (7406, 7407,
etc.), possibly with several devices
connected in parallel.
Figure 9 shows the waveforms that
can be obtained with two parallel
high voltage drivers pulled up to 12V.
Whilst a dramatic improvement can
be seen with respect to Figure 8, the
performance is stilI well below what
can ultimately be obtained from a
HEXFET. The waveforms in Figures
9 and 10 are for the same device, with
the same drive circuit and the same
drain current, but with different drain
voltages. At higher voltages, CciD
takes a longer time to discharge, so
the device stays in the linear region
+12V
-12
Figure 12. High Performance Driver
COMPATIBLE) I
Ir----------
I
I
,..........----------
LOGtc INPUTS ,---,r----.
(TTl. I
--,
II
I
IL __________ _
'Figure 13. Buffer Stages Implemented with Special Purpose Drivers
for more than 0.5 microseconds be-
fore reaching saturation.
Whenever better switching perfor-
mance is required, interface circuits
should be added to provide fast cur-
rent sourcing and sinking to the gate
capacitances. One simple interface
circuit is the one shown in Figure II.
lt is a complementary emitter fol-
lower stage, capable of sinking or
sourcing approximately IA. The
choice of the output transistor is
important when switching times have
to be in the order of 40ns.
They should have good gain at high
currents to be capable of delivering
whatever current is required by the
Miller effect during the allowed
switching time. To gain a better in-
sight on the operation of these tran-
sistors, we can attempt a rough calcu-
lation of the current they have to
supply in a switching operation. Dis-
regarding for a moment the Miller
effect, if CGS is 700pF (IRF330) and
we want to charge it linearly to 12V in
40ns, a current pulse is required
equal to:
1= CGS X VGS
ts
= 0.7 X 10-9 X 12 = 0 21A
40.10-9 . I. C-MOS has a more balanced
In the simplistic assumption that
the gate-to-drain capacitance is dis-
charged in the same time, assuming a
drain voltage of 200V, we have:
1= COG X V DS
ts
= 40 X 0.10- 12 X (200-12)= 0 188A
40 10-9 . 3. Switching times are longer than
In the final assumption that the two
currents add up and that the switch-
ing frequency is ·IOOkHz, we can
obtain an approximate figure for the
power lost in one driver transistor:
P = VCE X Ic X ts X f = I X 0.398 X
40.10-9 X 100 103 =1.6mW
.12V
(TTl.COMPAnBLE)
A-44
The conclusion is that the driver
devices have to be capable of supply-
ing O.4A without significant voltage
drop, but that hardly any power is
dissipated in them. Core drivers
(2N3725, 2N3244), seem to be the
most suitable devices. Unfortunately,
the gain of these devices drops very
fast for currents over 0.5A. Audio
drivers (2N5320, 2N5322), have bet-
ter gain at high currents but are
slower. A double buffer stage may be
advisable in some applications with
fast switching bipolar devices (2N-
2369A and 2N4208 or MPS2369 and
MPS3640) driving two HEXFETs,
as shown in Figure 12.
Buffer stages can also be imple-
mented with special purpose inte-
grated circuits like the ones shown in
Figure 13. These buffers have gua-
ranteed switching times and high
current sourcing and sinking capabil-
ity. Furthermore, they are directly
compatible with 5V TTL.
Driving HEXFETs from C-MOS
While the same general considera-
tions presented above for TTL would
also apply to C-MOS, there are three
substantial differences that should be
kept in mind:
source/ sink characteristic that,
on a first approximation, can be
thought of as a 500 ohm resist-
ance for operation over 8V and a
Ik ohm for operation under 8V
(Table 2).
2. C-MOS can operate from higher
supply voltages than 5V so that
HEXFET saturation can be gua-
ranteed.
TTL (Table 2).
When C-MOS outputs are directly
coupled to the gate of a HEXFET,
the dominant limitation to perfor-
mance is not the switching time, but
the internal impedance (assuming
that C-MOS are operated from a IOV
YH
LOG~INPUT~~
.- 9
~
112 DSOO26
or higher voltage supply). It will cer- the C-MOS output itself. The circuit
tainly not be able to turn OFF the shown in Figure II (without the pull-
HEXFET as fast as the TTL, while up resistor which would not be need-
the turn-ON waveform will be slightly ed), and Figure 12 will improve the
better than what can be achieved drive capability, while the circuits in
with a 7407 with a 680 ohm pull-up Figure 13 will improve both drive
resistor. Of course, gates can be par- capability and switching times, but
alleled in any number to lower the require a TTL compatible drive sig-
impedance and this makes C-MOS a nal (SV). Another possibility, of
very simple and convenient means of course, is to interface C-MOS to
driving HEXFETs. Drivers can also TTL and then use the TTL drive cir-
be used, like the 4049 and 40S0 which cuits.
have a much higher current sinking
capability (Table 2), but they do not Driving HEXFETs From
yield any significant improvement in Linear Circuits
current sourcing. The complementary emitter follow-
For better switching speeds, buffer er configuration of Figure II can also
circuits should be considered, not be used in linear applications to
only to provide better current sourc- improve drive capability from an op-
ing and sinking capability, but also to amp or other analog source (Figure
improve over the switching times of 14).
Table 2. Driving HEXFETs from C-MOS (Buffered)
Standard Buffered
Outputs 4049/4050 Drivers
~y
Logic
Conditions
Voltage SV IOV ISV SV IOV ISV
Logic Zero:
Approximate sink current I.SmA 3.SmA 4mA 20mA 40mA 40mA
for VOL ~ I.SV
Logic One:
Minimum source ~.SlmA -1.3mA -3.4mA -1.2SmA 1.2SmA -3.7SmA
current for VOH ;;;..4.6V ;;;,9.5V ~13.SV ~2.5V ;;;,9.5V ~13.5V
Typical switching times
of logic drive signals:
RISE lOOns sOns 40ns lOOns sOns 40ns
FALL lOOns sOns 40ns 40ns 20ns ISns
INPUT
Figure 14. Current Booster for Analog Figure 15. Dual Supply Op-Amp Drive
Applications Circuit
A-45
If the driving signal is generated by
an operational amplifier, the use of
power operational amplifiers (e.g.,
j.LA791) that can supply as much as
IA can be considered. In practice,
their slew rate is so low (O.SV / j.Ls)
that their current capability would be
redundant and the usable bandwidth
would be less than 2SkHz. A larger
bandwidth can be obtained with bet-
ter operational amplifiers followed
by a current booster, like the ones
shown in Figures IS or 16. For a
system bandwidth of I MHz, the op-
amp bandwidth must be significantly
higher than I MHzand its slew rate at
least 30V / p.s. Presently, there are
several devices capable of this per-
formance, e.g., LFIS7, LMIIO,
p.A7IS, HA2620,etc. Ifa larger band-
width is needed, special purpose cur-
rent amplifiers can be used, like the
HA2630 (bandwidth 8 M Hz, slew rate
SOOV / j.LS; O.4A output current) or
very fast operational amplifiers like
the NESS39 (bandwidth 48MHz, slew
rate 600V / p.s) followed by a current
booster.
When analog signals determine the
switching frequency or duty cycle of
a HEXFET, as in PWM applica-
tions, a voltage comparator is nor-
mally used to command the switch-
ing. Here, too, the limiting factors
are the slew rate of the comparator
and its current drive capability. Re-
sponse times under 40ns can be ob-
tained at the price of low output vol-
tage swing (TTL compatible) and
this implies the use of output buffers
like the ones shown in Figures 9, II,
12 and 13. If better switching speeds
Figure 16. Single Supply Op-Amp Drive
Circuit (Voltage Follower)
are desired, a fast op-amp should be
used. Figure 17 shows a typical com-
parator connection. 1...I INPUT PULSE
In many applications, when the
HEXFEJ is turned on, current trans- /'....T"AC
fers from a freewheeling diode into
the HEXFET. If the switching speed
is high and the stray inductances in
the diode path are small, this transfer
can occur in such a short time as to
cause a reverse recovery current in
the diode high enough to destroy it.
For this reason, it may be necessary INPUT
to slow down the turn-on of the
HEXFET while leaving the turn-off li
as fast as practical. Pulse shaping cir-
cuits can be used for this purpose,
like the ones in Figures 18 and 19.

Figure 18. 555 as Schmitt Trigger in a Pulse Shaping Application

r--\ SLOPE OF IiAC

...J \.. YISEC

JL WITH DIODE
CONNECTED
AS INDICATED
r----t::+---l
I I
I I
I ,

Figure 17. Comparator Drive

In linear applications, the use of

special circuits like the LM391 audio
driver with an output booster can be
considered. The LM391 has separate
source and sink outputs.
Drive CircuHs Not Referer1ced
to Ground Figure 19. Pulse Shaper
To drive a HEXFET into satura-
tion, an appropriate voltage must be
applied between the.gate an,d source.
If the load is connected between
source and ground, and the drive vol-
tage is applied between gate and
ground, the effective voltage between
gate and source decreases as the
device turns on. An equilibrium point
is reached in which the amount of
current flowing in the load is such
that the voltage between gate and
source maintains that amount of drain
current and no more.
For this reason, it is often advan-
tageous to have the gate drive circuit
referenced to the source rather than
to the ground. There are basically
three ways of floating the gate drive
circuit with respect to ground:
I. By means of optically coupled
isolators.
2. By means of pulse transformers.
3. By means of DC to DC chopper Figure 20. Opto Coupler Drive Circuit
circuits with transformer isola-
tion.
A-46
 Opto couplers require a separate If the duty cycle is small, or the Obviously, this circuit will not work
supply grounded to the source on the frequency is low, the circuit in Figure if the HEXFET may be kept in the
receiving end of the optical link. 23 should be considered. The size of on-state for an undetermined period
Optically coupled gates (TTL com- Q, R, and C depend on the duty cycle of time and there is lower frequency
patible) are available with 50ns delay of the drain voltage waveform as well limit below which C becomes quite
times and 25ns rise and fall times. as its frequency and the amount of large and the circuit is not attractive
They can be used to a few M Hz, but gate capacitance that has to be driven. any longer. 0
they require a booster stage at the
output, as shown in Figure 20. c-
MOS level translators, like the 4504,
could be used in place of the 7406. If
speed is not a major factor, a simpli-
fied circuit can be used like the one
shown in Figure 21.
The Schmitt trigger function of the
74CI4 could be accomplished with a
555, which has fairly good switching
and driving capabilities (lOOns, 0.2A).
One of the major difficulties en-
countered in the use of opto couplers
is their susceptibility to noise. This is
of particular relevance in applica-
tions where high currents are being
switched rapidly. They do, however,
offer a simple means of transmitting Figure 21. Simplified Opto Coupler Drive. 555 can be substItuted for the 74C14
a signal that contains a DC compo-
nent. Pulse transformers, on the other
hand, can only transfer to the secon-
dary the AC component of the input
signal. Consequently, their output
voltage swings from negative to posi-
tive by an amount that changes with
the duty cycle. Furthermore, what-
ever leakage inductance the trans-
former has, reduces its effectiveness
as a gate drive circuit. To overcome
these difficulties, a signal condition-
ing stage may be necessary; this re-
quires a separate power supply. It LOAD
remains, however, a reliable approach
with high noise immunity, whenever
the duty cycle has a fixed known min- Figure 22. Supply for the Gate Drive Circuit Developed from the Drain Voltage
imum.
Chopper circuits are fairly com-
plex, expensive and limited in band-
width and performance. They do
have their advantages, though, like
the possibility of transferring a DC
component, noise immunity and the
fact that with some additional circui-
try, the separate supply can be avoided.
Considering the small amount of
power that is required to drive the
gate of a HEXFET, it may be possi-
ble in some applications to develop a LOAD
supply for the gate drive circuit di-
rectly from the drain voltage. Figure
Figure 23. Gate Drive Supply Developed from the Drain Voltage for Small Duty-
22 shows a possible way implement- Cycle or Low Frequency Operation
ing such a circuit. 0

A-47
CHAPTER 6
APPLICATION NOTE 934A

The HEXFET's Integral Body Diode

Its Characteristics and Limitations
By S. CLEMENTE, B.R. PELLY, and B. SMITH

Summary
All power HEXFETs have an inte-
gral reverse rectifier or "body diode"
built into them. The current rating of
the reverse rectifier is equal to that of
the transistor. This article details the
characteristics of the body diode, and
shows where and how to use it.
Introduction
Other circuits req uire the switching
device to support "negative" voltage
as well as "positive" voltage. In that
even t, a rectifier must be connected in
series with the HEXFET, because the
integral body diode does not allow it
to support "negative" voltage. This is
no different, of course, than with a
bipolar transistor, which also cannot
support significant reverse voltage
integral body diode plays no part in
the circuit operation, and it stays
unobtrusively in the background. The
same is true in the "forward" convert-
er circuit, shown in Figure 2b. There
are many circuits of this type.
OC INPUT

(but, unlike the HEXFET, nor can it

A not too well-known feature of
HEXFETs (actually in general, of all
power MOSFETs) is that they inher-
ently have built into them an integral
reverse p-n junction rectifier or "body
diode." This is illustrated in the equiva-
lent circuit diagram of Figure I. Far
from being an inconsequential "para-
sitic" component, the integral body
diode is a real circuit element with a
carry significant reverse current).
There are other circuits which actu-
ally require a "reverse" rectifier across
the switching device. In these circuits,
it will often be possible to utilize "free
of charge" the integral body diode
built into IR's HEXFET, thereby
obviating the need for additional dis-
/1
crete rectifiers in the circuit. This can .~ L - - //1~RRENT
~~~IN
be a significant added bonus of using

current handling capability as high as
that of the transistor itself, and, as it
normally happens with practical cir-
cuit components, its own set of char-
acteristics and limitations.
N-CHANNEL DEVICE P-CHANNEL DEVICE
D S
,dbfr,~,
the HEXFET, though, as will be seen,
certain precautions may be necessary.
The purpose of this application
note is to discuss some of the uses, as
well as the characteristics, ratings and
limitations of the integral body diode Figure 2a. Flyback Converter Circuit
in IR's HEXFETs. Solutions to the
potential circuit problems will be con-
DC INPUT
sidered, and design procedures given.
The intention is to give the circuit
designer the information he needs to
assess the importance and applicabil- I. I ·~
LLLTPUT

ity of this "hidden" component in IR's

HEXFETs.
S
Figure 1. Complete Symbols for the Some Basic Circuit Applications
HEXFET
The following discussion deals with
various circuit examples; this will give -1
n ~
II !?~AIN
~RRENT
The integral body diode mayor a basic understanding of where the

may not be important in a practical
circuit. In some applications it is
irrelevant, because the circuit opera-
tion is such that the voltage across the
transistor never reverses; hence, the
forward conduction characteristic of
the diode never comes into play.
,db1t~~,
reverse rectifier is important, and
where it can be utilized.
First, there are circuits in which the
reverse rectifier has no effect. The fly-
back converter shown in Figure 2a is
an example. Here. the voltage across Figure 2b. Forward Converter Circuit
the HEXFET is always positive; the
A-48
 UNCONTROLLED REGENERATIVE CURRENT
CAN FLOW IN REVERSE DIODE IF E>V HEXFET 1

r - --
I
-1-. I
I I
I
+
DC +
DC SUPPLY
SUPPLY V
V
E E

B
Figure 4a. HEXFET Circuit for Providing Speed Control and
Figure 3. DC Chopper Circuit for Motor Speed Control Regenerative Braking of DC Motor

The integral body diode has no

obvious effect upon the operation of --VOLTAGEA-B
the DC to DC chopper circuit shown
in Figure 3. If a situation could arise, - .- MOTOR emf E
however, where the motor is driven at
overspeed by an "overhauling" load, MOTORING REGENERATING

HJHJ
"uncontrolled" current would flow
through the integral body diode. If
this can occur, then a rectifier should
be connected in series with the
HEXFET, to prevent the flow of
energy back to the DC source, assum- -- t --- E I
.
U+UT t
---
ing that a regenerative braking facility
is not required.
If, on the other hand, it is required MOTORING
to provide a controlled regenerative CURRENT
braking facility, then this can be I MOTOR
neatly furnished by the circuit shown - - - - - - - - - CURRENT
in Figure 4a, which utilizes two I
REGENERATING
HEXFETs. For the motoring mode
of operation, HEXFET I is chopped CURRENT ----
on and off at some suitable repetition t
rate, typically a few hundred Hz to a
few kHz, to provide control of the
average level of voltage applied to the
motor. HEXFET 2 is off, but its inte- 4-
gral body diode acts as the conven-
tional free-wheeling rectifier, and car-
ries the motor current when HEXFET
lQ TRANSISTOR
CURrENT
I is instantaneously off.
For the regenerative braking mode I
rL-J
-IT -,HEXFET1
L-J CURRENT
of operation, HEXFET 2 is chopped RECTIFIER
on and off, to control the regenerative CURRENT
current fed back from the motor. t
HEXFET I is off, but its integral
body diode carries the motor current
when HEXFET 2 is instantaneously
off, thus carrying the motor current
back into the DC supply. Theoretical
operating waveforms are shown in
Figure 4b.
t
TRANSISTOR
CURRENT
Jl[J . HEXFET 2
Another example of the use of the , _ _ CURRENT
integral body diode is shown in Figure
5. Here, two HEXFETs connected in
-r-IT-l I
series opposition form a bi-directional L-J L-J RECTIFIER
AC switch. When control terminal 3 is CURRENT
driven positive with respect to control t
terminal 4, both HEXFETs are on.
and the switch is closed for current Figure 4b. Operating Waveforms for Circuit of Figure 4a.
flow in either direction. Current in one
A-49
direction flows via the transistor of
HEXFET I and the body diode of
HEXFET 2; in the other, it flows I
through the transistor of HEXFET 2 E + I HEXFET
and the body diode of HEXFET I. I
When control terminal 3 is driven to 2
the same potential, or negative, with I
L ____ .....J
respect to control terminal 4, the AC
switch is off, and it blocks voltage in
either direction. DC
Perhaps the most obvious use of the SUPPLY
integral body diode built into IR's VOLTAGE
HEXFETs is in voltage-fed DC to AC
inverter circuits of the types com-
E
E +
r- --,
I

JJ
monly used for switching power sup- I HEXFET 2
plies, motor speed controllers, and 2
general purpose AC power supplies. I
In these types of circuit, the basic I
principle is to switch the DC supply L_ ...J
voltage in alternating directions across (8) Voltage-Fed Inverter Circuit
the load, in accordance with a pre-
scribed switching pattern. The wave- VOLTAGE
form of the output current is deter- /" OUTPUT
mined by the characteristics of the VOLTAGE
load. AND
For all loads other than purely re- CURRENT
sistive, there are intervals during
which the polarity of the output cur-
rent is instantaneously opposite to
that of the impressed voltage. This
means that each switch within the
inverter must be capable of carrying
current in the "reverse" direction. In a (b) Simple Square Wave Operation - Pure Inductive Load RECTIFIER
conventional inverter circuit, this facil-
ity is provided by connecting a reverse
rectifier across each switching device. T~OLTAGE
~ CURRENT OUTPUT
These rectifiers are often known as VOLTAGE
- - - - - - - - AND
"reactive feedback" rectifiers.
The integral body diode in the CURRENT
HEXFET can automatically serve as
the reactive feedback rectifier. A sim- TRANSISTOR
ple "half bridge" DC to AC inverter
circuit operating from a "split" DC
supply is shown in Figure 6a. The cir-
L--_ _ _ _ _ _ tt___ HEXFET 1
CURRENT
cuit can be operated in a simple
square wave mode, in which case a
single voltage pulse is produced for RECTIFIER
(e) Pulse Width Modulated Operation - Filtered Load
Figure 6. Simple Voltage-Fed Inverter and Theoretical Operating Waveforms

HEXFET 1 HEXFET 2 each half cycle of the output, or it can

r-----, r---- -, be operated in a more complex "mul-
I I ti-pulse" mode, with many voltage
I pulses being produced for each fun-
damental output half cycle. This latter
I technique significantly reduces the
I harmonic distortion at the output.
MAIN I MAIN
I I TERMINAL
These two operating techniques are
TERMINAL! illustrated by the waveforms in Fig-
1 L L -1 2 ures 6b and 6c respectively. These
waveforms show that current flows
both in the "positive" direction,
through the transistor, and in the
CONTROL "negative" direction, through the inte-
TERMINALS gral body diode, during separate
intervals. The "reactive feedback" rec-
3 4 tifiers, therefore, play an essential and
Figure 5. Bidirectional AC Switch Using Two HEXFETs in Series Opposition important role in the operation of the
circuit.
A-50
 I
J.
102 f - - - I- TJ=25 C
0
102
13
0::
TJ = 25 0 C 13
0::
TJ - 150 0 C

...
W

~
...
w IDRM,IRF150
~ ~
~ ~
....
~
0:: /'
l/"
IDRM,IRF130
~TJ= 1500 C ....
~
0::
IR7'lOR, IRF150.l
0::
0::
:>
u .AI :>
u
-TJ=15~
rl
z
;{ 10
~DR,IRF130 z
;{
0::
10
0::
Cl Cl
w W
en
en 0::
0::
w TJ - 1500 C I w
~ TJ = 25 0 C
~
0:: "I 0:: I
Ii ci
E I E
I ' " TJ = 25 C 0

1.0 I I I 1.0
o 1 2 3 o I 2 3
VSO, SOURCE·TO·DRAIN VOLTAGE (VOLTS) VSD. SQURCE·TQ·ORAIN VOLTAGE (VOLTS)
Figure 78. Conduction Voltage Drop vs. Current in Integral Figure 7b. Conduction Voltage Drop vs. Current,in Integral
Reverse Rectifier (IRFI30, 530, Series HEXFET) Reverse Rectifier (IRF150 Series HEXFET)

Ratings and Characteristics of the

Reverse Rectifier
The integral body diode built into
the HEXFET consists basically of a
conventional p-n junction. Its electri-
cal characteristics, therefore, are basi-
cally those of a conventional silicon
rectifier.

Current Ratings
The peak current rating of the inte-
gral body diode I DRM, defines the max-
imum permissible peak "rectifier" cur-
rent, just as the peak current rating of
the transistor, I DM, defines the maxi-
mum permissible peak "transistor"
current. The "rectifier" and "transis-
tor" peak current ratings are the same
as one another, as also are the RMS
ratings. Figure 8. Typical Curves of forward conduction voltage vs. current through integral
reverse rectifier, with varying amounts of applied gate-source voltage.
Conduction Voltage IRFl30 VGS = 0, + 2, + 4, + 6, + 8, + 10V.
Relationships between the conduc-
tion voltage drop of the integral diode
and the instantaneous current through
it, at junction temperatures of 25° C
and 150°C, are shown in Figure 7.
The rated pulsed current level, I pK, is
indicated for reference on these dia-
grams. The voltage drop across the Equivalent
integral body diode is relatively low, Resistor
and ranges between I to 2V at normal
operating currents.
A point of interest is that the con-
duction voltage drop of the integral
body diode can be modified by apply-
ing positive drive voltage to the gate of
the HEXFET. Figure 8 shows what
happens as the gate to source voltage (a) ACTUAL (b) EQUIVALENT
is increased. At low current levels, the CIRCUIT CIRCUIT
conduction voltage drop across the Figure 9. Varying applied gate voltage results in varying equipment resistor
rectifier decreases as the drive voltage across reverse rectifier.
is increased.
A-51
 The physical explanation for this is
simple. As the gate voltage is in-
creased, the channel resistance of the
transistor reduces due to the applied
electric field, just as it does for the
normal "transistor" direction of cur-
rent flow. The reverse rectifier is thus
t .
RECTIFIER
FORWARD
shunted by the channel resistance, and CURRENT
the equivalent circuit is as shown in RECTIFIER 0
Figure 9. 25% REVERSE
I."",, RECOVERY
At low current levels, the voltage
drop across the channel resistance is ENT
lower than it would be across the rec- I." ,:Ur
tifier on its own, and most of the cur-
rent flows through the equivalent re-
sistor. As the current is increased, the
voltage drop across the rectifier is
lower than it would be across the re-
sistor in its own; most of the current
now flows through the rectifier. The Figure 10. Rectifier Reverse Recovery
resistor then has little effect, and the
influence of the applied gate drive volt- 10
age is minimal.
Reverse Recovery
An important practical considera-
tion is the reverse recovery character-
istic of the integral body diode. This
diode is a conventional p-n junction,
and therefore it exhibits a classical
reverse recovered charge; that is to
say, when the diode switches off, the I l..-
current through it reverses for a short
period, as illustrated in Figure 10. r---~MAX.
~
Values of t. and tb* for values of ~
initial conduction current and di/ dt "",,,,
other than those indicated in the data
sheet can be estimated from the t MAX."
approximate normalized relationships
shown in Figure II.
The reverse recovery of the integral
body diode must be carefully consid- 10-1
10-2 W1 I 10
ered in the design of a practical circuit, PER UNIT FORWARD CURRENT 1.0 PU =RATED IpK
and it may be necessary to make defi- Figure 118. Approximate correction factors for t. and tb as function of per unit initial
nite provisions to alleviate its effect. forward rectifier current
This is discussed in the next section.
"The minimum values of tb are important 10 1
because it defines the degree of "softness"
of recovery, and hence also the level of
~Ai'/MiN.
voltage transient induced in circuit induc-
tance during this period. I-- tb
~
......... ~
Rectifier Reverse Recovery I '~
-Circuit Conslderations- r--~
The HEXFET's integral body diode
exhibits minority carrier reverse re-
covery. Reverse recovery presents a I
t. MAX.
r---.. r-... ~ 100.
I"-

potential problem when switching any

rectifier off; the slower the rectifier,
the greater the problem. The HEX-
FET's rectifier is relativey fast - not
as fast as the fastest discrete rectifiers
a vailable, but considerably faster than
comparably related conventional gen-
eral purpose rectifiers. By comparison
with the HEXFET itself, on the other
hand, the switching speed of the inte- -1
10 I 10 102
gral reverse rectifier is quite slow. The dVdt (AI!'S)
switching speed of a circuit utilizing Figure 11b. Approximate Correction Factors for t. and tb as function of di/dt
the reverse rectifier of the HEXFET
A-52
may therefore be limited by the recti-
fier. Whether this will be so depends
upon the circuit and the operating
conditions, as discussed later.
The most common applications of
the HEXFET in which the switching
speed, and hence frequency, will
potentially be limited by the rectifier,
are DC to DC choppers and inverters
for regulated power supplies, electric
motor controllers, and so on, in which
"multiple" voltage pulses are used.
Effect of Reverse Recovery on
Circuit Operation
Regardless of the overall circuit
comparison with the overall funda-
mental operating cycle of the circuit, a
constant current 10 flows through an
external inductive load. During the
operating period to, the current 10
flows through the rectifier of HEXFET
2. At the start of the operating period
tl, HEXFET I is turned on, and the
load current starts to transfer to the
transistor of HEXFET I. The current
il in HEXFET I increases, whilst the
current i, flowing in the rectifier of
HEXFET 2 decreases. The sum of il
and i, is equal to 10 , At the end of
period t l, the current flowing in
HEXFET I is equal to the load cur-
rent 1 and the current flowing in the
0,
rectifier of HEXFET 2 is instantane-
ously zero.
possible voltage across H EXFET I
that takes account of the voltage drop
across circuit and inductance is repre-
sented by the dashed wave in Figure
13a.
If the rectifier was "perfect," with
no recovered charge, the commuta-
tion process would be complete at the
end of period tl. In practice, the recti-
fier current reverses during the recov-
ery period, before the rectifier begins
to support voltage. This happens dur-
ing periods to and tb (Figure 12c). Dur-
ing period to the reverse current i,
increases until it reaches its peak
value, IRM(REC} In the meantime, the
current idhrough HEXFET I, is now
the sum of the rectifier reverse current
i, and the output current 1 and its
0,

configuration, or the particular appli-
cation, the "local" circuit operating
situation that is troublesome occurs
when free-wheeling current from an
inductive load is com mutated from
the reverse rectifier of one HEXFET
to the transistor of an "opposite"
HEXFET, the two devices forming a
tandem series connected pair across a
low impedance voltage source. This
"local" circuit configuration occurs in
most chopped and inverter schemes.
The operating sequence is depicted in
Figure 12 and associated theoretical
operating waveforms are shown in
Figure 13.
Throughout the commutating se-
quence, which of course is short by
Note that during period tl (also dur-
ing the subsequent period tal the volt-
age across HEXFET I theoretically is
virtually the full source voltage. This
is because so long as the rectifier of
HEXFET 2 remains conducting, the
voltage across it can be only its con-
duction voltage; the difference between
this relatively small voltage and the
total source voltage is developed
across HEXFET l.
This ignores the effect of stray cir-
cuit impedance. In practice, some of
the source volt.age will be dropped
across the circuit impedance, and the
voltage across HEXFET I will be less
than the source voltage, by the voltage
drop across the circuit impedance. A
peak value, I MAX, is the sum of 10 and
IRM(REc). During period t", the voltage
across HEXFET I still theoretically
remains virtually equal to the source
voltage, because the voltage across the
rectifier of HEXFET 2 is still rela-
tively low.
During the final period tho the recti-
fier of HEXFET 2 begins to support
reverse voltage. The reverse rectifier
recovery current i, decreases, and the
voltage across HEXFET I falls to its
final conduction level. Note the effect
that circuit inductance has in produc-
ing an overvoltage transient across the
rectifier, as illustrated by the dashed
wave in Figure 13c.
Certain important points are evi-

(a) Period to (b) Period t,

+ +
WITH CIRCUIT
INDUCTANCE

: ,"-j -j (a) VOLTAGE

ACROSS
HEXFET 1
o- - - L _ - '=_=-=-=-=-==-
t I"" "'" I II (b) CURRENT
IN TRANSISTOR
TTl
1M " '------'-
OF HEXFET 1
HEXF,ET 2/ I"

:\~ INDUCTANCE
~ITH ~CIRCUIT
1

n
- -,
: '.
(e) Periods ta and tb i ' + (e) VOLTAGE
+ i
: E
j
ACROSS
HEXFET 2
O----~
RECTIFIER
REVERSE
RECOVERY
(d) CURRENT
IN RECTIFIER
OF HEXFET 2

.J too ---I t, t. t/,-t l -.....

Figure 12. Commutation of Freewheeling Current 10 from the Figure 13. Theoretical Voltage & Current Waveforms for
Rectifer of HEXFET 2 to the Transistor of HEXFET Com mutating Sequence Depicted in Figure 12.
,. HEXFET 1 and HEXFET 2 Form a Tandem Series
Connected Pair Across a DC Source.

A-53
dent. First, tl, t a, and, to a lesser
extent, tb, are high dissipation periods.
Second, the peak current in HEXFET
I is the sum of the load current and
the rectifier reverse recovery current,
and this peak current occurs at an
instant when the voltage across the
HEXFET is high. It is important that
this peak current does not violate the
HEXFET's IDM rating. In fact, if the
HEXFET is switched at a speed close
to its limiting capability, and no other
special precautions are taken, it may
well do. A marginal situation for the
IRF330 is illustrated by the voltage
and current oscillograms in Figure
14a. Here, the IRF330 HEXFET is
switched from a 300V source into a
freewheeling current of about 4A
(flowing in the integral rectifier of a
second IRF330) at a rate of change of (a) IMAX =20A. di/dt =50Aljls (t, + t a) =300 nanoseconds
current of about 50Aj /is. The peak
current, I MAx, in the HEXFET reaches
a, value that comes very close to the
pulsed current rating. If the peak cur-
rent was to substantially exceed the
rating, diode failure could result, as
explained in the last section. Funda-
mentally, the peak reverse recovery
current of the rectifier can be reduced
only by slowing down the rate of
change of current during the commu-
tation process. This is illcstrated in
Figure 15. Note that these waveforms
assume a linear rate of change of cur-
rent. The peak reverse current could
also be reduced by slowing down the
rate of change just in the reverse re-
covery region.
The rate of change of current can be
controlled either by inserting induc-
tance into the circuit, or by purpose- (b) IMAX =20A, di/dt =50A/jls (t, + t a) =300 1.8)Js
fully slowing down the rate of rise of Figure 14. Oscillograms of IRF330 Switching into Reverse Rectifier of Another
the gate driving pulse. Theoretical IRF330 with Freewheeling Current of 4A. Top Trace: Voltage 100V/div.
switching waveforms obtained with Bottom Trace: Current 4A/div. Time Scale! 2 jls/div.

t
FORWARD
RECTIFIER
CURRENT
0- - 0
I
REVERSE
RECTIFIER
CURRENT

TIME
,.
i
Figure 15. Reducing the Peak Rectifier Reverse Current by Reducing the Rate of Change of Current.

A-54
these alternative techniques are illus-
trated in Figure 16.
From the waveforms in Figure 16a,
it is seen that an inductor in series with
the HEXFET not only slows down '\ VOLTAGE ACROSS HEXFET 1
the rate of change of current, it also
supports the bulk of the source volt-
age, that would otherwise be deve-
loped across the HEXFET during the
turn-ON interval. The energy in the
HEXFET at switch-ON is therefore
"'-----
substantially reduced. There are, how-
ever, some disadvantageous side ef- ______c-_ _ _ _ _ _ _ _ _ _ _
t
fects. First, the energy stored in the
inductor inherently produces an over-
voltage transient when the rectifier
recovers, as shown. This voltage tran- VOLTAGE
sient must be limited by an RC ACROSS
snubber or a voltage clamp, which HEXFET 2
dissipates the stored energy. Second,
the inductance creates an overvoltage
transient across the HEXFET when it
is switched OFF (at a later point in the
cycle, not shown in Figure 16). This
overvoltage, again, must be clamped;
unfortunately, the energy dissipated in
-----------------'----
(a) Slowing the Rate of Change of Current by Inserting a Series
the clamp at turn-OFF is significantly Inductor
greater than the energy saved at
turn-ON.
The other solution mentioned,
which avoids the need for an addi-
tional power circuit inductor, is simply VOLTAGE ACROSS HEXFET 1

\-------
to slow down the switching-ON of the
HEXFET by appropriately slowing
down the rise of the applied gate drive
signal. The effect on the circuit opera-
tion is illustrated in Figure 16b. IRM(REC)
The peak current carried by the
HEXFET can be reduced to almost
any desired extent, at the expense of
prolonging the high dissipation period, ----==--.------ - - - - - -
and hence increasing the energy dissi-
pation at switch-ON. The practical
oscillograms in Figure 14b illustrate
this technique. By slowing the total VOLTAGE
switch-ON time (tl + t.) from 300ns to ACROSS
1.8ps, the peak current, I MAX has been HEXFET 2
decreased from 20A to lOA. The
energy dissipation associated with the
"unrestrained" switch-ON in Figure
14a is O.9mJ, whereas it is 2.7mJ for (b) Slowing the Rate of Change of Current by Slowing the
the controlled switch-ON of Figure Applied Drive Signal
14b.
Figure 16. Alternative Circuit Techniques for Controlling
Note that it is not necessary to slow the Peak Reverse Recovery Current
the switching-OFF of the HEXFET,
hence the energy dissipation at switch-
OFF will be relatively small by com-
parison with that at switch-ON. For for many applications where high connect an external fast recovery rec-
operation at frequencies up to a few switching frequency is required, the tifier, or Schottky rectifier, across the
kHz, where ultra fast switching is not reverse recovery characteristic of the HEXFET. So long as the conduction
mandatory, slowing of the applied integral body diode is not a factor, voltage drop of the external rectifier is
gate drive signal to reduce the peak even though this rectifier is used to appropriately lower than that of the
reverse recovery current of the recti- carry inductive load current. integral rectifier, the external rectifier
fier (ofthe opposite device) will offer a There will, however, be some high- will carry the bulk of the "freewheel-
good practical solution. frequency applications which require ing" current, and the reverse recovery
a reverse rectifier in which reverse re- characteristic seen in the circuit will be
covery will be critically important, that of the fast external rectifier. An
and in which the reverse recovery time example of the reduction in peak
Use of External Fast Recovery of the integral reverse rectifier will not reverse recovery current obtained by
Rectifier be fast enough. connecting an external fast rectifier
As will be seen in the next section, In this event, the frrst approach is to across the HEXFET is illustrated in
A-55
(a) IMAX = 25A, dildt =40AlJls (b) IMAX = 12A, di/dt = 40AlJls
Switching Energy ~ 500 JlJ Switchi ng Energy ~ 120 JlJ
Figure 17. Oscillograms of IRF130 Switching into a Current of 12A Freewheeling in (a) The Reverse Rectifier of Another IRF130 and (b)
an External Fast Rectifier Connected Directly Across the Reverse Rectifier of an IRF130.

Figure 17. With an external rectifier
across the IRF130, the peak current at
switch-ON is reduced from 25A to
16A, and the switching energy in the
HEXFET is reduced from 500 to
120pJ.
This solution will generally be
applicable for low voltage HEXFETs,
for which compatible low voltage
drop fast recovery rectifiers or
Schottky rectifiers are commercially
available. For high voltage HEXFETs,
however, fast recovery rectifiers are
not yet generally available with suffi-
ciently low conduction voltage. For
these applications, it may be necessary
to connect a rectifier or Schottky rec-
tifier in series with the HEXFET, and
a separate, high voltage, fast recovery
rectifier across the combination. The
series rectifier will block reverse cur-
rent from flowing through the integral
reverse rectifier of the HEXFET,
thereby alleviating the recovery prob-
lem by shifting it to the faster external
rectifier. (fig. 18)
Where Reverse Recovery Is Not
Critical
All ''full wave" voltage-fed inverter
circuits use at least one of the tandem-
switch circuit modules shown in Fig-
ure 12 (or an equivalent derivative
thereof). A half bridge circuit, for
example, uses one of these modules; a
full single-phase bridge circuit uses
two, and a three-phase bridge circuit
uses three.
As has been seen, reverse recovery
presents a difficulty when commutat-
ing current from a rectifier to a tran-
sistor. Whether or not this operating
condition occurs depends upon the
operating mode of the circuit. It does
not occur in an inverter in which each

DRAIN
VOLTAGE
DRAIN
CURRENT E

Figure 19. Voltage and Current Wave-forms When Switching Output

Figure 18. Cure for Reverse Conduction Current 10 from Transistor to Opposite Rectifier

A-56

+ .------~---------,
80V
J INDUCTIVE
J J
(a) DC to AC Inverter With Inductive Load
BOV 1'--_-,.---;;-,.,-1 --BA---..·-----
O ------l -. ... ~ ~LOAD VOLTAGE
-- Bovi
·BA
. , - - - - - , BA
o ' - - - - - - - HEXFET 1 CURRENT
BA
'------------v:;'T/;.~
REVERSE RECTIFIER
I T/B T/B I T/B I T/B I T/B I T/B
8A ",",,,"-u.£LL.£r'-REVERSE RECTIFIER
BA
.L--"R=Ecc..V.:::E;.c.RS=-E=-:R.:.:E:.:C:..;T-"IF,-,I-=E::.;R",")ILQl>~ ______ HEXFET 4 CURRENT
To TI T,
(b) Theoretical Operating Waveforms
Figure 20. Inverter Circuit and Waveforms
output half cycle comprises a single
voltage pulse, so long as the load is
resistive or inductive. With a resistive
load, the rectifiers do not come into
play. With an inductive load, current
is commutated from a transistor into
an opposite rectifier; but never from a
rectifier into an opposite transistor (it
simply reverses naturally from the rec-
tifier to the transistor of the same
device, at an instant determined by the
phase angle of the load, not by the
inverter switching). Inspection of the
waveforms in Figure 6c and Figure 20b
will verify this rule. This is an impor-
tant point, because it means that the
reverse rectifier of the HEXFET is not
frequency limiting conventional "sin-
gle voltage pulse" switching inverter
circuits (i.e., most common switching
mode power supply circuits), even
though these circuits can utilize the
rectifier to carry inductive current.
J Since operation under these condi-
LOAD
LOAD CURRENT
-"'L __
HEXFET 2 CURRENT
BA
T/B I T/B I
.....
BA HEXFET 3 CURRENT
T, T, T, T.
Where Reverse Recovery Is Crlcital
The situation is different with a
capacitive load, for which the current
leads the voltage. For a capacitive
load, the current is instantaneously
"negative" in a given switch at the
moment of commutation, and current
is now commutated from a rectifier to
the opposite transistor. But this is of
no great practical concern, since most
practical loads are not capacitive.
The critical commutation situation
will, however, be obtained in an inver-
ter in which multiple output voltage
pulses are produced during the course
of each fundamental output cycle. The
classical pulse width modulated invert-
er, commonly used for variable speed
control of AC machines, stand-by
power supplies, and so on, is an
example. Inspection of the waveforms
in Figure 6c will verify that the critical
A-57
commutation condition (i.e., commu-
tation of current from a rectifier to an
opposite transistor) does indeed occur
in this pulse width modulated (PWM)
circuit.
tions can sometimes lead to unex-
plained failures, if appropriate solu-
tions are not adopted, it may be
interesting to examine in more detail
the equivalent circuit of a power
MOSFET, taking into account its
parasitic elements. As shown in Fig-
ure 2 I, the integral reverse diode is
actually the base-collector junction of
a bipolar transistor that has a base-
emitter short.
If (for reasons that we shall exam-
ine later) this bipolar transistor goes
into conduction at a time when the
power MOSFET is supposed to block
forward voltage (i.e. VGS = 0) a poten-
tially hazardous circuit operation
would ensue that, depending on the
specific power circuit, could lead to
catastrophic failure. As we shall now
briefly examine, there are three con-
ceivable ways of causing unwanted
conduction of the bipolar transistor
shown in Figure 21.
The first is by avalanching the col-
lector-base junction. If the voltage rat-
ing of the device is exceeded by a sig-
nificant amount and if the supply has
a suitably low internal impedance, the
injection of minority carriers into the
base region will cause, at some point,
the bipolar transistor to go into con-
duction. This is knows as a "switch-
back" effect and is shown in Figure
22.
Some proprietary elements in the
geometry and in the process of
HEXFETs make them particularly
well suited to absorb energy in ava-
lanche without loss of blocking capa-
bility, as it appears from the wave-
forms for an un clamped inductive
energy test shown in Figures 23 and
24.
The second possible way of getting
the bipolar transistor into conduction
is by applying a very steep voltage
pulse on the drain. The collector-to-
base capacitance (Figure 21) would
couple such a pulse to the base of the
transistor which could, conceivably,
go into conduction. However, as
shown in Ref. I, for such a pheno-
menon to occur, the dv I dt of the volt-
age pulse would have to be well in
excess of 75V I ns and HEXFETs are
totally insensitive to practically achiev-
able levels of dv I dt.
Finally, the bipolar could go in
conduction if a relatively high dv I dt is
applied to the device when the diode is
recovering after forward conduction.
As explained in Ref. I, if the collector-
base junction is forward biased the
effective value of CI (Figure 21) can
 SOURCE GATE SOURCE

f}T}il I DRAIN
n+ T

Simplified Equivalent Circuit:

GATE-1
ffiS'DRAIN

RI

SOURCE

Figure 21. Parasitic Elements in the MOSFET Structure Figure 22. Undesirable switching during avalanche condition

TEST CIRCUIT

VARY Ip TO OBTAIN

=1R
REQUIRED PEAK I L

V GS

Figure 23. IRF330 Avalanche Energy Test

TEST CIRCUIT

VARY Ip TO OBTAIN

=1R
REQUIRED PEAK 'L

50 "sec / DIVISION . 1S()

.
VGS
' . i
"""":---r---
c±-L.
•100~
~
SO-l/)
o~
200y~ L=3D"Hy
150 .• -·
1 100 •...• \
~+
$Q 5 0 , , - - - - -
- 0

Figure 24. IRF150 Avalanche Energy Test

A-58

DRAIN CURRENT
(DIODE)
Figure 25. Current and Voltage Waveforms During Body Diode
Recovery
be many times greater. This, com-
bined with the fact that minority car-
riers are already present in the base
region, can cause spurious triggering
at much lower values of dv / dt.
It should be emphasized, however,
that this would only occur in those
circuits in which multiple output volt-
age pulses are produced during the
course of each fundamental output
cycle, as shown in Figure 6c. On the
other hand, in those circuits (like
power supplies) that only generate a
single voltage pulse for each half cycle
of the output, as shown in Figure 6b,
no dv/dt is applied to the diode dur-
ing reverse recovery because at that
time the diode itself is short circuited
by its own conducting MOSFET and
current transfers gradually from the
diode into the same MOSFET of
which the diode is a part. This would
not necessarily be true, however,
under abnormal operating conditions
caused, for example, by logic mal-
functions, misgatings due to noise or
double pulsing of the control inte-
grated circuit.
In those applications where a sub-
stantial dv / dt is likely to be applied
during the reverse recovery, means
should be provided to limit its value at
that specific time (Figure 25).
I" OF INTEGRAL RECTIFIER
__ D_R~I~ ~U~:E~T_____ j
(DIODE)
EXTERNAL DIODE CURRENT
Figure 26. Effect of an External Diode With Longer t"on the
dv/dt Applied to the Body Diode During Reverse
Recovery
In addition to the well known RC
techniques employed to limit the
dv / dt, a simple but often effective way
of achieving the same result is shown
in Figure 26. The connection 01 a
diode with longer reverse recovery in
parallel with the integral diode ensures
that it will have recovered completely
before any reverse voltage is applied
to it.
Conclusions
The HEXFET's integral body diode,
far from being a "parasitic" compo-
nent, can be utilized in its own right,
and indeed has a current rating equal
to that of the transistor. This applica-
tion note has shown where and how to
use this diode, what cautions should
be observed, and where it cannot be
used.
Generally, the HEXFET's integral
body diode will be applicable in the
following areas:
(a) DC to AC inverters, which oper-
ate with one voltage pulse per
output half cycle. In these circuits,
the use of the integral body diode
does not limit the switching fre-
quency, so long as the load is
inductive (as it normally is).
(b) Multi-pulse (PWM) DC to AC
A-59
Irr OF EXTERNAL DIODE
~
EXTERNAL DIODE
WITH LONGER In
5
inverters, such as those used for
variable frequency speed control
of AC machines, and geneari
purpose AC power supplies. Rec-
tifier switching speed will usually
restrict operating frequency to the
5-10 kHz range, but in many cases
this will not be practically limiting.
(c) DC to DC choppers, such as are
used in regenerative DC motor
controllers. Again, rectifier switch-
ing speed will usually limit switch-
ing frequency to the 5-1 Ok Hz
range.
(d) Bidirectional AC switching circuits.
The HEXFET's integral body diode
has so far been largely overlooked.
Circuit designers can now take serious
note of it; it represents yet another
potential application advantage of
IR's HEXFETs. 0
References
R. Severns: "dv / dt Effects in M OS-
FETs and Bipolar Junction Transistor
Switches," PESC-81 Record, IEEE
Power Electronics Specialists Confer-
ence, 1981
CHAPTER 7
APPLICATION NOTE 940
An Introduction to
Intemational Rectifier P-Channel HEXFETs
By S. CLEMENTE
With the introduction of Interna-
tional Rectifier's line of P-Channel
power HEXFETs, a new option is
available to the designer that can
simplify circuitry while optimizing
performance and parts count. This
application note discusses the basic
characteristics of P-Channel HEX-
FETs and gives a conceptual over-
view of typical circuit applications.
Basic Characteristics of P-Channel
HEXFETs
Like their N-Channel counterparts,
International Rectifier P-Channel
HEXFETs are all presently enhance-
ment mode devices; that is, applica-
tion of voltage between the gate and
the source terminals enhances the
conductivity and allows current to
flow, while no drain current flows
when the gate is shorted to the source.
For drain current to flow, the gate
voltage has to be increased (in abso-
lute value) towards the drain voltage.
In a P-Channel device, the conven-
tional flow of drain current is in the
"negative" direction - that is, cur-
rent flows out of the drain, with a
negative gate-to-source voltage app-
lied (Figure I).
While the basic physical principles
of operation for P- and N-Channel
HEXFETs are similar, the different
resistivity of the base silicon material
has a distinct bearing on their specific
characteristics, as well as upon cost.
Since the resistivity of P-type silicon
is much higher than that of N-type
silicon, the P-Channel device requires
a larger active area to achieve the
same on-resistance and current rat-
ing.
This difference in resistivity of the
basic silicon material is an obstacle to
the construction of a P-Channel de-
vice that is truly electrically comple-
mentary in all respects to an N-
Channel counterpart. Since for a
given drain-source voltage capability,
the on-resistance is the most basic
parameter, the P-Channel HEXFET
device will have the larger active area
needed to achieve the same on-resist-
ance as its complementary N-Channel
counterpart. Gate threshold voltage,
transconductance and self-capaci-
tances are equalized as nearly as pos-
sible by accurate device design. Table
I shows the parameters oftwo typical
complementary P- and N-Channel
HEXFETs (the IRF9130 and the
IRFI20) and shows to what extent
their major parameters match one an-
other. Voltage ratings, on-resistance,
threshold voltage and, of course,
Figure 1. P-Channel power HEXFET
package configuration, are exactly
the same. Input capacitance and
transcond uctance are also fairly der effect in most practical applica-
closely matched. However, those par- tions.
ameters that are closely related to the As shown in Figure I, the P-Chan-
die area, specifically thermal resist- nel HEXFET, like its N-Channel
ance, pulsed current rating, safe op- counterpart, has an integral reverse
erating area and, to some extent, rectifier, whose anode is connected to
continuous current rating, are differ- the drain. This diode is specified as a
ent, as would be expected. While real circuit element with a current
these last parameters do not affect handling capability as high as that of
circuit operation directly, they have a the transistor itself. It is a very valu-
bearing on circuit design and, when- able circuit component in some appli-
ever matched operation is required, cations.
the P-Channel device will operate
with a larger safety margin with Circuit Applications
respect to its current ratings and
thermal limits. In the following sections, we pre-
A close analysis of the data sheet sent a brief overview of the areas
would also show that the tempera- where a P-Channel can be used to
ture variations of the threshold volt- particular advantage.
age, on-resistance and transconduc-
tance for a P- and an N-Channel are Grounded Loads
slightly different. This difference can, One area where P-Channel HEX-
however, be considered a second or- FETs yield circuit simplification and
A-50
cost savings is where the load is con- Table 1.
nected to ground. This is mandated N-Channel P-Channel
in many automotive and aircraft
applications and, sometimes, in Device Type IRFI20 IRF9130
household appliances. In these appli- Drain-to-Source Voltage (Max.) 100V -lO~Y
cations, in addition to wide safe
operating area and excellent switch- Die Size 8.04mm2 13.25mm2
ing characteristics that are common On-Resistance (Maximum) 0.30 0.30
to all HEXFETs, the use of a P-
Channel device allows the load to be On-State Drain Current @ Tc = 90°C 6A -8A
tied to the drain so that the gate drive Pulsed Drain Current 15A -30A
can be referenced to one side of the
supply. If an N-Channel were used, a Gate Threshold Voltage 2to 4V -2 to -4V
separate supply would be required, (Minimum-Maximum)
referenced to the source, for the gate Forward Transconductance (Typical) 2.5 S 3.5 S
drive voltage.
Figure 2(a) shows how such a cIr- Input Capacitance (Typical) 450pF 500pF
cuit would operate when driven from Output Capacitance (Typical) 200pF 300pF
a C-MOS gate. However, if the load
is operated at voltages above 15V, Reverse Transfer Capacitance (Typical) 50pF IOOpF
the logic ground cannot be connected Maximum Thermal Resistance 3.l2deg. CjW 1.67 deg. CjW
to the load ground, and a separate TO-3
supply is needed for the logic circuits, Package TO-3

+15V 0 - - - - - -.....- - - - . , +vO--~~-----,------,

LOGIC 0; HEXFET ON

~'~o~~
P..cHANNEL P..cHANNEL
HEXFET HEXFET

GROUND GROUND
CONNECTED CONNECTED
LOAD LOAD

Figure 2(8). Switching Ground Connected Loads Operating Figure 2(b). Switching Ground Connected Load at Higher
from Low Voitages Voltages

+18V

LOAD

(VH -lllV

LOAD
Figure 3(a). Driving Grounded Load
in Linear Mode
(Low Voltage)

Figure 3(b). Driving Grounded Load in Linear Mode

(High Voltage)

A-61
as shown in Figure 2(b). An alterna-
tive approach is to drive the P-
Channel HEXFET through a level
shifter, as shown in Figure 5. Notice
that to achieve the same result with
an N-Channel HEXFET, a separate
supply referenced to the source would
be required.
A P-Channel device can also be
operated in linear mode as shown in
Figure 3. The device lends itself read-
ily to voltage or current regulation
which can be achieved through the
use of suitable feedback. In the appli-
cations shown in Figures 3(a) and
3(b), the device drops whatever excess
voltage is available from the unregu-
lated supply. For parallel connection
of devices, or :Where fast slew rate is
\ Whereas it is satisfactory in many
Figure 4. N-Channel Totem Pole and its Associated Drive Circuits
~------------------~---------.-------,
Figure 5. PIN-Channel Combination Totem Pole and Its Associated Drive
Circuits. Load is Connected to the Drains.
important, a current boosting stage
a.t the output of the operational amp-
lifier may be required.
Totem Pole Switching Circuits
One of the most common building
blocks for switching applications is
the "totem pole." It is used in a var-
iety of applications, such as switch-
ing power supplies, DC-to~AC con-
verters, AC motor speed controllers,
AM transmitters and Class D switch-
ing audio amplifiers.
Figure 4 shows one such circuit,
implemented with two N-Channel
HEXFETs, and its associated, gate
drive circuit. Since the drive circ;uits
have to be referenced to the respec-
P-CHANNEL
HEXFET
+1SV
A-62
tive sources, they are isolated from
each other. The most commonly used
techniques to develop an "isolated"
gate drive signal are optical isolators,
transformer coupling and "bootstrap-
ping." Optical isolators, shown in
Figure 4, require a separate supply
and are relatively slow ·and suscepti-
ble to noise. Pulse transformers, on
the other hand, can only transfer to
the secondary an AC signal (Figure
8), and hence have a limitation on the
maximum and minimum possible
switching duty cycle. They, also al-
ways have some unwanted amount of
leakage inductance. "Bootstrapping"
is a technique for deriving a local gate
drive voltage via a capacitor con-
nected in the main drain circuit.
applications, it again has limitations
regarding permissible duty cycle and
maximum operating frequency.
The totem pole shown in Figure 5,
using one N-Channel and one P-
Channel HEXFET, is a step\forward
in the simplification of the drive cir-
cuit, since the gate drive signals are
now referenced to separate ends of
the DC supply. As shown, the drive
signal referenced to the other rail can
be developed by means of a simple
level shifter. Furthermore, if the sup-
ply voltage is less than 20V, the two
gates can be connected together and
driven with respect to either end of
the supply (Figure 6).
When using this type of totem pole,
care should be exercised to have a
gate drive signal with fast rise time. If
the two gates are independent, as in
Figure 5, another possibility is to
have a dead band between the turn-
on gate command of the P-Channel
and that of the N-Channel equal to
the rise tiine of the gate drive signal.
Unless this is done, a short circuit
current will flow through the two
devices during the transition times,
+15V
INPUT -c:::r-
LOAD
Figure 8. PIN-Channel HEXFET
Totem Pole with Drive
Circuit for Operation at
Low Voltages
as shown in Figure 7. However, the
current regulating characteristic of
power MOSFETs tends to limit the
amount of this current and, while it
may significantly increase the switch-
ing losses, it would not necessarily
reach catastrophic values.
Should a common reference be de-
sired for both gate drive signals, the
circuit configuration shown in Fig-
ure 8 can be used. The positions of
the P- and N-Channel HEXFET de-
vices have been interchanged so that
both have the load connected to the
source. The gate drive signals are
now referenced to the same point;
however, this point is neither of the
two supply leads. This is probably
the circuit configuration that affords
the simplest and most noise-immune
gate drive circuit. An added advant-
age of this circuit is that it will not
draw a short circuit current (Figure
7), because it is inherently impossible
~ GATE-SOURCE DRIVE
VTMiff-=-====::":'-:::'::':F ~~~!~~:~R
VTMJLJtt7 -------r:t.= ~~liA~~U:g~
P-CHANNEL
"SHORT CIRCUIT'
CURRENT
Figure 7. Short Circuit Current Caused
GATE
CONTROL
O--~--VG PRIMARY
GATE VOLTAGE AT
DIFFERENT DUTY CYCLES
Figure 8. NIP-Channel Combination Totem Pole and its Associated Drive Circuits
to drive both devices ON simultan-
eously.
Application of the Switching Totem
Pole
The switching totem pole is used in
a number of different applications.
Some of the most common are the
following:
• DC-to-AC inverters for battery
operated supplies, stand-by and
uninterruptible power systems.
• Variable frequency inverter for
high efficiency speed control of
AC induction motors.
• Regenerative speed control of DC
motors.
Taking as an example this last
application, we show in Figure 9 a
way of implementing a DC motor
speed control with regenerative brak-
ing capability with a complementary
totem pole.
P-CHANNEL
DRIVE
N-CHANNEL
L -_ _...J-E
by Overlapping Gate Signals
A-63
In the "motoring" mode of opera-
tion, H EXFET I is switched ON and
OFF, at an appropriate repetition
rate, and provides control of the
average voltage applied to the motor.
HEXFET 2 is OFF, but its integral
reverse body-drain diode acts as the
conventional freewheeling rectifier,
and carries the freewheeling motor
current during the periods when
HEXFET I is OFF. When the motor
is required to act as a generator and
return energy to the DC source,
HEXFET2 is chopped ON and OFF,
and controls the current fed back
from the motor to the supply. In this
operating mode, HEXFET I is OFF,
but its integral reverse rectifier car-
ries motor current back to the DC
source during the intervals when
HEXFET 2 is OFF. The circuit shown
in Figure 10 could equally well be
used and would offer the advantage
of a common reference point for both
gate drive signals, as mentioned pre-
viously. For this application, since
only one device at a time is operated
within any given control cycle, there
is no danger of drawing a short cir-
cuit current.
J
Figure 9. Regenerative DC Motor
Controller
Figure 10. Alternative Configuration for
the Regenerative DC Motor
Controller
 Another consideration in choosing
between the circuit connections of
Figure 9 or Figure IO is the current
rating of the two devices. Normally,
the device that is being switched dur-
ing regeneration does not need to
have a current rating as high as the
motoring device. since friction and
windage in the motor contribute to
the braking torque. Therefore, the P-
Channel HEXFET, because of its
lower current rating for a given die
size, may be a better choice for the
regenerative operation;
Apart from being the basic building
block of a large variety of inverter ±1UV ±1UV
circuits, totem poles can be profit-
ably used to drive large transistors or
a parallel combination of them when-
ever high performance is required
(Figure II). This circuit can be used
either in linear or switching applica- -12
tions and provides a good low impe-
dance gate drive source. The integral
reverse rectifiers clamp possible volt- Figure 11. High Performance Drivers
age transients on the gate.
power MOSFETs require very little Summary
Unear Application of Complemen- drive power and are not subject to
tary PaIrs P-Channel HEXFETs are electrical
thermal runaway. complements to International Recti-
Because of the wide range of linear- Figure 12 shows the basic biasing fier N-Channel types. The availabil-
ity of l!r., immunity from secondary scheme for linear operation, but much ity of these devices offers new design
breakdown, high speed and intrinsic simpler versions can be developed for options to the circuit engineer, and
freedom from thermal runaway, specific applications, as shown in opens up the possibility for new
power HEXFETs are ideally suited Figure 13. The zener diodes should HEXFET applications that were not
for operation as linear amplifiers, be chosen to give the desired bias before feasible with N-Channel types
alone or in complementary pairs. current in relation to the available alone. 0
When used in linear mode, the gate supply voltage. The gain bandwidth
has to be biased to some level, de- product that can be obtained with
pending on the type of operation this stage driven by a simple differen- Acknowledgements
desired. Several circuit configura- tial amplifier is much larger than The amplifier circuit shown in Fig-
tions will achieve this end; they are what can be obtained by a more ure 13 was developed by H. Schar
inevitably simpler than would be complex bipolar configuration. The of International Rectifier GmbH,
required for bipolar transistors, since slew rate would also be much better. Frankfurt, West Germany.

+B

-B
Figure 12. Basic BiaSing Scheme for Linear Operation Figure 13. Simple Biasing Scheme for linear Operation

A-54
 CHAPTER 8
APPLICATION NOTE 947

Understanding HEXFET® Switching Performance

By S. Clemente, B.R. Pelly, A. Illdori

Abstract
A simple analytical technique for predicting the switching
performance of the HEXFET is presented.
Closed-form solutions for the gate voltage, drain current, and
drain voltage during the switching interval, in terms of each of
the relevant device and circuit parameters, are derived.
A specific design example is considered, in which the effects
are demonstrated of the drive circuit resistance, drain circuit
inductance, and drive voltage, on the switching time and switch-
ing energy.
I. Introduction
it and see" approach has generally held sway over more rigorous
analytical techniques.
One of the major "incidental" benefits of the HEXFET-in
addition to its very real operating advantages-is that it lends
itself rather well to analytical modeling; its operation can, there-
fore, be predicted rather easily at the design stage.
The primary objective of this application note is to show how,
starting with a simple model of the HEXFET and using logical
reasoning, the principles that govern the HEXFET's operation
in a switching circuit can be readily predicted, and approximate
mathematical relationships that describe these waveforms can
be readily derived. Emphasis will be placed upon an under-
standing of basic principles.

The HEXFET is an almost ideal switch, which is character-
ized by very high gain and extremely fast switching characteris-
tics. While users often ignore the intricacies of the switching
operation, on the assumption that this is not critical to the
overall design, the fact is that a clear understanding of the
factors that affect switching can have a profound effect upon
the system performance, particularly in high frequency circuits,
and is, therefore, of vital interest to the user who needs to
optimize his design.
Another reason why many users have a rather incomplete
understanding of the HEXFET's switching operation is that the
device is still relatively new, and HEXFET circuit design know-
how has not yet matured. Users also tend to relate to their
experience with bipolar transistors. The switching operation of
bipolars is very difficult to analyze, and hence an empirical "try
II. The HEXFET Model
The electrical model for the HEXFET is shown in Figure I.
The self-capacitances are actually nonlinear functions of the
applied voltage; also, to some extent, of the drain current. For
purposes of analysis, however, these capacitances will be
assumed to have fixed values; this does not detract from our
basic objective, which is to understand fundamental principles.
This simple model of the HEXFET is assumed to have a
linear transfer characteristic, with slope gfs and gate threshold
voltage VT' The external drain current is assumed
to be instantaneously responsive to the gate voltage, for
operation in the active region.
Under transient switching conditions, charging and dis-
charging currents flow through the various self-
capacitive elements.' The paths for components of these currents

d=i
is through the drain-to-source terminals. The presence of these
internal capacitive currents is assumed not to affect the transfer
RAIN OFF STATE 10 =0 characteristic between the gate voltage and the external drain
ACTIVESTATE 10 =,9,. (vGS-VTI current.
ho The presence of COS will also generally be ignored for

eGO t iO :;Oy operations in the active region. This is valid because the effect of
the gate-to-drain capacitance CGO-providing, as it does, a
coupling path from the drain circuit to the relatively sensitive

~ lj1VDI /'O>ID'~o~
gate circuit-generally "swamps" the effect of COS,
t
GATE v GS III. The Circuit Model
v CGS VT
IG '
The clamped load is assumed to have sufficient inductance
. Vo that the current flowing in it has a constant value 10 throughout
SOURCE FULLY ON STATE 10 = ROI(ONI the switching interval (Figure 2). The inductance Ltrepresents
"unclamped" stray circuit inductance.
Figure 1. Electrical Model for HEXFET The effect of the common source inductance LS' shown
dashed in Figure 2, will generally be neglected. This is not

A-55
 Instantaneous current flowing into drain terminal

!
Instantaneous current in CGS
D Instantaneous current in CGO
10 Steady current in clamped inductive load
(CONSTANT)
Initial value of current flowing into drain terminal at
L.e start of interval
'1 ..., ~VD
Gate drive circuit resistance

rit:~D ROS(ON) On-state resistance of HEXFET

.: " bJ.~
Rt Stray drain circuit resistance
G
Lt Stray drain circuit inductance
Inductance in series with source that is common to
gate circuit
Gate-source capacitance of HEXFET
Gate-drain capacitance of HEXFET
ell Ls
r' Orain-source capacitance of HEXFET
CGS + CGO
Figure 2. General Circuit Model
COS +CGO
because it is necessarily negligible, but because to include it in a gfs Transconductance of HEXFET
general analysis complicates the issue, making clarity of p Oifferential operator
presentation and a grasp of fundamental principles more
difficult. We prefer instead to consider the modifying effect of V. Analysis of Switching Operation
this inductance once the basic analysis is complete.
Each switching sequence, either from the OFF to the ON
A number of switching circuits can be resolved into the condition, or vice versa, is subdivided into a number of separate
equivalent circuit shown in Figure 2, or variants thereof, and in intervals, for which different constraints and conditions apply.
this sense the analysis is fairly general. The main point, Each interval will be considered in sequence. The end-conditions
however, is that the chosen circuit serves as a vehicle for for one interval become the starting conditions for the next. For
obtaining an understanding of basic principles; once this has simplicity we will take t = 0 at the start of each new interval.
been accomplished the designer will be well equipped to deal The approach will be to consider each time interval in a
with the switching operating of the HEXFET in any circuit. qualitative manner, and through aprocess of reasoning based
upon the known conditions and constraints, deduce as much as
IV. Nomenclature we can about the general shapes of the dynamic waveforms of
drain voltage, drain current and gate voltage.
Vo Instantaneous drain-source voltage For certain time intervals this qualitative reasoning leads
vGS Instantaneous gate-source voltage directly to the parametric analytic solution for that interval; for
Instantaneous gate-drain voltage other time intervals, however, the analytic solutions are not so
vGO quickly obtained, except for parametric extremes at each end of
Vo Steady applied drain circuit voltage the possible spectrum of external circuit conditions; a wide
VOR Applied positive gate drive voltage (turn-on) middle range of conditions remains for which derivation of the
VT Gate threshold voltage parametric solutions is rather too lengthy to be presented in its
entirety, and in these cases we will simply state the final
VF Positive gate drive "forcing" voltage (VOR - VT ) solutions.
-V2 Applied negative gate drive voltage (turn-oro
VO· Initial value of drain-source voltage at start of A. TURN-ON
interval Turn-On Delay Interval 1
VGS· Initial value of gate-source voltage at start of interval
The circuit model for this interval is shown in Figure 3, and
VCLAMP Orain-source clamping voltage operating waveforms are shown in Figure 4. The applied drive

GATE V
VOLTAGE __ T
~
I
__ _
-::::;l>"
1_-- vGS = VDR (1- e -
VT
G)

DRAIN
CURRENT ________ --
I I ID=O
I I .
DRAIN ---~~VD
VOLTAGE I I

Figure 3. Circuit Model for Turn-On Delay Interval Figure 4. Waveforms for Turn-On Delay Interval (t 1)

A-66
voltage is assumed to rise instantaneously to its full value;
however, the voltage actually appearing between the gate and
source terminals, which directly controls the external drain
current, rises at a finite rate determined by the gate-to-source
and drain-to-source self-capacitances. No drain current flows
so long as the gate voltage is less than the threshold voltage, YT .
The end of the turn-on delay period is defined as the point at
which the gate-to-source voltage becomes equal to the threshold
voltage.
The analytic solution for the turn-on delay is almost trivial.
Since no drain current flows, the drain voltage remains at YD'
Both the "drain" terminal of COD and the "source"terminal of
COS sensibly do not change their potentials. The drive source
voltage, YDR' 'sees' the parallel combination of COD + COS =
CO, through the series resistor RDR' The gate-to-source
voltage vas follows a classical exponential:
(1)
where
(2)
Turn-On Interval 2
The general circuit model for this interval is shown in Figure
5. The drain current now rises as the drain voltage falls. Which
of these events is completed first depends upon the external
circuit parameters. When one of these events is completed (or
both simultaneously) the interval ends.
VGS ::; VT+VF - lOR ROR
:: Vr at t::: 0
'0 ::.. 9f5 (VGS -Vr)
v l1 --;: lq~P
Figure 5, General Circuit Model for Switch-On Interval 2
VL,=ltdIO*'O
••
Figure 6. Circuit Model for Switch-On Interval 2
. SmaIiLt/ROR
A-6?
Since t~e drain current iD is less thah the current 10 through-
out this period, the difference between 10 and iD must continue
to circulate in the freewheeling rectifier D, forcing this diode to
stay in conduction. This keeps the potential at the "top" of Lt
virtually constant at YD'
As the gate-to-source voltage rises above the threshold level,
the drain current starts to increase since drain current is propor-
tional to gate voltage. The drain voltage also starts to fall
because the increasing drain current induces a voltage across
Lt. As the drain voltage falls, current iO D flows out of the
"Miller" capactance Co D; this current is drawn from the drive
source, and deprives the gate-source capacitance COS of a
portion of the charging current it would otherwise have
received. This, in turn, reduces the rate of change of gate volt-
age, and hence also of drain current.
A dynamically "intertwined" situation obviously exists, by
virtue of the "negative feedback" effect that couples the drain
circuit to the gate circuit via the "Miller" capacitance COD' The
"strength" of this feedback depends upon the ratio of the exter-
nal circuit parameters Ltto RDR' as we will now see.
Large Lt means large impedance to the rate of change of
drain current, while small RDR means fast gate circuit re-
sponse, and hence potentially fast rate of change of drain cur-
rent. With a high ratio of Ltto R DR the reactance of the drain
circuit will therefore be high, the voltage drop across Lt will be
high, the "Miller" effect will predominate, and the rate of
change of drain current will be unable to match the applied gate
circuit stimulus. High Ltl RDR' therefore, means that the
switching speed is severely limited by the constraints of the
drain circuit; the drive circuit is "too fast" for the drain circuit.
Small Lt/ RDR ratio means just the opposite; the potential
rate of change of drain current is now much faster than the drive
circuit actually allows. The voltage drop across Ltis small, the
"Miller" effect is small, and the gate circuit largely controls the
switching time, virtually unimpeded by the drain circuit. Both
of these extreme conditions are rather easy to analyze.
For intermediate Lt/ RDR' the drain circuit and gate circuit
responses can be envisioned as being reasonably "compatible"
with one another. From a purist's viewpoint, compatibility of
the gate and drain circuit responses might be considered to be
the "correct" design point, because the gate circuit is neither too
fast nor too slow for the drain circuit.
Small Lt/ROR
We will start the analysis by considering the situation when
Lt/ RDR is small. The circuit model is shown in Figure 6, and
switching waveforms are shown in Figure 7. Since there is very
little voltage developed across Lt, the drain voltage vD stays
virtually atthe circuit voltage, YD' until the drain current has
risen to its full load value 10'
 Because the rate of change of drain voltage is small (almost
zero), virtually no current flows through CGO, and the drive
circuit continues to see the simple parallel combination ofCGO
and CGS (as it did during the turn-on delay period). The
gate-to-source voltage, vGS' therefore, continues to rise
exponentially:
(3)
The drain current rises in sympathy with the gate voltage:
(4)
The drain voltage is equal to the circuit voltage V0, less the
small (almost negligible) voltage drop across Lt:
It remains to quantify how small the ratio Ltl ROR must be .
for equations (3) through (5) to remain valid. The essential
condition is that the rise of drain current must, for all practical
purposes, be exclusively under the influence of the applied drive
voltage. This means that whatever voltage change occurs across
Ltshould not be noticed in the gate circuit. The current through
CGO will, therefore, be small by comparison with the current
through CGS (CGS is typically about IO x CGO; however, a
sufficiently large voltage change at the drain would produce a
current through CGO which is comparable to or larger than
.that through CGS'
The essential condition therefore is that iao [='= CGO
(dvo/dt)] should be small by comparison with IGS [='= CGS
(dvGsl dT)].
By differentiation of equations (3) and (5), this yields:
(6)

(5) Table I puts the above criterion into perspective, and shows
typical value of Lt and the corresponding "minimum" values of
ROR' for various HEXFETs. Clearly the values of ROR
The period ends when iO = 10' needed to satisfy this condition are very high relative to most
Table 1: Limiting values of ROR that define which equations (turn-on Interval 2, and turn-off Interval 3) are
applicable, for various HEXFETs.

Small Le /RDR Intermediate L.e /RDR Large L.e /RDR

2 2
L,2
--<
CGS L£
GS
--<---
C 2 Le
-->---GS C 2 L.eGS
-->---
10C
RDR 10CCGgfs RDR 4CG~fs RDR 4C g GD fs RDR CGDg fs

Applicable Equations 3-5,37-39 8-10,4042 14-16,4345 24-26,4648

L,2 RDR-2.4kn min RDR -960.0. min RDR-960n max RDR-40n max
IRF510 100nH
(IOOV,2.5A) L.e RDR-24kn min RDR-9.6kn min R DR-9.6kn max RDR-400n max
1 llH
L,e RDR-1.3kn min RDR-S20n min RDR-S20.o. max RDR-20.o.max
lRFl30 lOOnH
(lOOV,9A) L,e RDR-13k.o. min RDR-S.2k.o. min RDR-S.2k.o. max RDR-200.o. max
1 llH
L,e RDR -410.0. min RDR-16Sn min RDR-16S.o. max RDR-6.o.max
lRFISO 100nH
(lOOV, 25A) L.e RDR-4.lk.o. min RDR-1.6Sk.o. min RDR-l.6Sk.o. max RDR-60nmax
I llH
L.e RDR-620.o. min RDR-32S.o. min RDR-325.o. max R DR-13.o. max
lRF710 IOOnH
(400V,IA) L,2 RDR-6.2kn min RDR-3.25k.o. min RDR-3.2Skn max RDR-130 max
I flH
L.e RDR-420n min RDR-170n min RDR-170n max RDR-7n max
IRF330 IOOnH
(400V,3.5A) L.e RDR-4.2kn min RDR-1.7kn min RDR-1.7kn max RDR-70.o.max
1 llH
L.e RDR-120n min RDR-SO.o.min RDR-SOnmax RDR-2nmax
IRF3S0 lOOnH
(400V,9A) L,2 RDR-1.2kn min RDR-SOO.o. min RDR-500n max RDR-20Q max
I llH

A-68
 GATE
VOLTAGE

DRAIN
CURRENT

DRAIN VD =VD- 9'0 VF Lr le'VT2 _ e'VT1 /

VOLTAGE (T1 -T2) I I

Figure 8(a). Waveforms for Turn-On Interval 2.

Intermediate Lt/ROR

I ...
~ ...
GATE ...... ~.------~~~VTI
VOLTAGE _ -!.
DRAIN
CURRENT
I 10* ~.--

DRAIN
VOLTAGE __

Figure 8(b). Waveforms for Turn-On Interval 2.

Intermediate Lt/ROR

normal application requirements. This condition will not, ROR that satisfy equation (7). This condition is certainly more
therefore, be frequently met in practice; its consideration here is likely to be encountered than condition (6), though once again it
useful, however, because it helps to introduce the overall is generally not representative of most typical practical situations.
problem. The gate voltage, vas, the drain current, iO' and the drain
voltage vo' are:
Intermediate Lt/RDR VF ~ -tiT 1 -t/T2 }
We will now consider the situation when the ratio of Lf) R DR vGS=V T +V F -(T I _T2) tTIe -T 2e (8)
is not small, but has some intermediate value; the voltage drop
across Lt due to the increasing drain current becomes signifi-
cant, and the current through CaD cannot be neglected. The
general circuit model of Figure 5 applies, and typical switching
iO=gfsVF tl-(T I ~T2) llTle-t/TI-T2e-t/T2} (9)
waves are illustrated in Figure 8(a) and (b).
The mathematical analysis is a little too lengthy to keep touch
_ gfsVFL.e J -t/T2 -tiT 1 }
with physical realities. We will, therefore, confine ourselves to a
simple statement of the results.
vO-VO- (T I -T 2) e -e t (10)
There are two possible sets of solutions, depending upon
whether or not the system is critically damped. If overdamped. where
then: 2L ECGORORgfs
T 1 = ---------r~~~========== (11)
yR20RC2GS - 4L£CGORORgfs
(7)
2LCGORORgfs
(12)
Note the similarity of condition (7) to (6). Table I also shows
typical values of Lt and corresponding' minimum values of

A-69
 The end of the time interval will generally be marked by the :. pLQiD = - pLQgfsRORiDR (21)
drain voltage having fallen all the way to iO x ROS(ON)' with
the drain current not having completed its rise. vD = V D - pLQiD
For an "underdamped" system. the converse of (7) applies:
Therefore from (21):
LQ CGS 2
- - >..,...".=- (13)
RDR 4C GDgfs VD = V D + pLQgfsRDRiDR (22)
The minimum values of ROR shown in Table I that satisfy
equation (7) now become the maximum values that satisfy iDR = - pCGDvD
equation (13). Generally. most practical situations will be
covered by equation (13). Therefore from (22):
The gate voltage vGS. the drain current iO. and the drain
:. (p2LQCGDgfsRDR + 1) iDR = 0 (23)
voltage vo. are:

vGS=(VT+VF)-VFe
-t/T 3 ~ sin w3 t
tOSw3t+ w3 T 3 \
l (14)
Equation (23) is a classical second order differential, with
purely "oscillatory" terms.
By imposing the appropriate boundary conditions [ vGS = VT
at t =0, and pLiO =0 at t =0 (since iGO "" 00)], the following
.
iD=gfsVF-gfsVF e
-t/T3 ~ sin w3 t
(OSW3 t + w3 T 3
lI (15) solutions are obtained:

(24)
(16)
(25)
where
(26)
(17)

(18)

The end of the time interval will be marked either by the drain
circuit in reaching 10' or the drain voltage Vo collapsing to iO x Yo
I IGO= CGD
d'l,
ROS(ON)' whichever occurs first. = IDA
S d'

Large Ll/ROR
Now consider the situation when Ltl ROR has a large
value-representing a "fast drive" circuit with a "slow" drain Figure 9. Circuil Model for Turn-On Interval 2.
circuit. The equivalent circuit model is shown in Figure 9. and High L/IROR
switching waves are illustrated in Figure 10. Note that' we are
ignoring the gate-to-source capacitance CGS' This is valid
bee. Ise with large Lt/ROR ratio the "Miller" effect predomi- I ... ~
natL and current through CGS is small by comparison with GATE ..~_ _.;-~ -
that through CGO' VOLTAGE .... ~VT VGS= VT - VF(I- cO""'l I)
The inductance Ltnow presents such a high impedance that -------
the increase of drain current "requested" by the drive circuit
cannot be satisfied; the drive circuit is largely impotent to bring
I
about the drain current that it asks for.
The drain voltage now collapses relatively quickly-generally
well before the current rise is completed. The end of the period is
marked by the HEXFET reaching the essential condition of a
DRAIN

;~;~~::~-N'lrc-~l- -
1 ... _ ...

'0= 9,. V.,tl- cos 1

"'1 )

"closed switch"-the voltage across it having collapsed completely.

The mathematics are rather simple; in order to gain insight. it Vo = Vo- grs VF 1r11l,sinw1 t
is useful to proceed through the analysis step by step: - - - - --
VGS = (VT + V F ) - iDRRDR (19) \-t2-l
Figure 10. Waveforms for Turn-On Interval 2 Large
iD = gfS<vGS - V T) Lt/ROR
LQ lOC GS 2
Therefore. from (19): --' >---
RDR CG~fs
(20)

A-70
 Lt = I /,H, and R OR = 2n, the voltage collapse will be com-
=V D - (27) pleted by the time the drain current has risen to O.2SA (i.e.,
about I% of rated current).
This result is to be expected; we have already reasoned that
where
for large Lt/ROR ratio, the HEXFET essentially acts as a
closed switch, the voltage across it collapsing quickly, with the
(28) current rising much more slowly, at a rate determined by the
external circuit inductance.
It remains now to establish how large Lt( ROR must be for
the above simple relationships to be valid. Turn-On Interval 3
The starting assumption was that the current through CGS is
The second time interval ends at the completion either of the
small by comparison with the "Miller" current iGO through
drain current rise or the drain voltage fall. The completion of
CGO' This implies: the remaining event-voltage fall, orcurrent rise-whichever it
is, takes place during the third time interval.
Fortunately, since only the drain voltage or the drain current
RDR < < w1C GS
are now still changing, the analysis is easy, and is independent of
the ratio of Lt/ R OR' lfthe drain current is no longer changing,
then Lt is irrelevant, since there is no voltage drop across it,
/gfsCGDRDR L Q whilst if the drain voltage is no longer changing, the HEXFET
RDR « CGS already acts as a closed switch, and ROR is irrelevant.
Consider first the situation when the voltage completes its fal~
2 during the third interval. The equivalent circuit model is shown
LQ GS C
--»--- (29) in Figure II. Atthe start ofthe period the drain voltage is V0*'
RDR CG~fs Since the drain current is constant, vGS must also be constant:

Table I shows maximum values of R OR for various HEX FET's (30)

for different values of Lt that satisfy the above condition. It is
clear that this condition, and hence expressions (24) through
Therefore iOR is also constant:
(26), will generally apply only to relatively low impedance drive
circuits. . 1 VDr (VT + Io/gFS )
Simple qualitative checks on the above relationships will IDR =RDR (VDR - VGS) = RDR (31)
prove their validity. From equation (28), "'I increases as ROR
or Lt decreases. The rate of rise of drain current, therefore, Since vGS' is constant, no current flows in CGS' and all of iOR
increases as either of these parameters decrease, which is to be flows in CGO' The rate of change of voltage across CGO is
expected. From equation (27), the voltage across Lt is propor- therefore:
tional to Lt( R OR. Thus increasing Lt or decreasing R OR
gives increasing voltage across Lt-again, to be expected. dVGD iDR VDR - (VT + Io/gfs )
(32)
The end of the interval occurs when either the drain current dt =CGD = RDRCGD
i 0 reaches la, or the drain voltage collapses to zero [more
precisely when it becomes equal to iO x ROS(ON)].lflO or VF' The rate of change of drain-source voltage is equal to the rate of
or both, are small, iO could reach 10 before the collapse of change of drain-gate voltage, since vGS is constant. Therefore,
drain voltage is complete. In practice, the voltage collapse will the drain voltage is:
generally occur well before the current has risen to 10' To take
an example, with the IRFI50 HEXFET (rated 25A at 100°C) v =V *- (
VDR - (VT + IO/gfS ») t (33)
operating in a 60V circuit, with a gate forcing voltage VF of7V, D D RDRC GD

GATE
VOLTAGE .... j I ..

10=10

Figures 11 al)d 12. Circuit Model and Waveforms for Turn-On Interval 3, iO is
Already Equal to 10 , vo Collapses.

A-71
 We will now consider the situation when the current com-
pletes its rise during the third time interval, the drain voltage
having already collapsed.
The equivalent circuit model is shown in Figure 13 and
switching waveforms are shown in Figure 14. The drain current 10 Vas = (VOR + VAl .·I/TO - V2

iDis: i 'D = 10
vD = ID ROS ION )
10
(34)
j
The gate voltage continues to increase exponentially during
the third interval, at time constant T G [equation (2)]. This,
however, has no influence over the drain current or voltage,
since the HEXFET is already "fully on."

Tum-On Interval 4 Figure 15. Circuit Model for Turn-Off Delay Interval
The gate voltage completes its exponential charge, at time
constant T G, to the level ofthe applied drive voltage VDR' This
has no influence over the drain current or voltage, since the
switching sequence in the drain circuit has already been
completed.

B. TURN-OFF
Turn-Off Delay Inlerval1
The equivalent circuit model is shown in Figure 15, and
operating waveforms are shown in Figure 16. The applied drive
voltage VDR is assumed to fall instantaneously to a negative

Yo

Lt Figure 18. Waveforms for Turn-Off Delay Interval (t 1)

iO= 'O'D! !=O

ROS(ON)
,
10
= 'O'+l:p

iO ROS ION )«
Vo!

Figure 13. Circuit Model for Turn-On Interval 3,
Already Collapsed. iO rises to 10'
VD
voltage -V2 (this COUld, of course, be zero, or even positive,
representing a small residual positive drive voltage). The volt-
age appearing between the gate and source terminals falls at a
rate determined by the time constant RDRCG, and nothing
happens in the drain circuit until the gate voltage falls to VT +
(10 1gfs)' which corresponds to the gate voltage needed to sus-
tain the drain current 10' This point marks the end of the
turn-off delay period. The gate voltage during the turn-off delay
Vo Has interval is given by:
(35)

Figure 14. Waveforms for Turn-On Interval 3, Vo Has
Already Collapsed. iO rises to 10 ,
Turn-Off Inlerval 2
The equivalent circuit model is shown in Figure 17, and
typical switching waveforms are shown in Figure 18. The drain
voltage rises to VD whilst the drain current remains cons/ant at
10, and the gate voltage remains cons/ant at (VT + 101 gfs)' At
first sight this may be surprising; a moment's thought shows it
has to be so. Until the drain voltage just exceeds the circuit
voltage, VD' the freewheeling rectifier D (Figure 2) remains
reverse biased; the whole ofiO must, therefore, continue to flow
into the drain of the HEXFET. So long as the drain current is
constant, the gate voltage will also be constant (since these two
parameters are inextricably tied to one another by the HEXFET's
transfer characteristic), and the current flowing "out of" the
resistor RDR is drawn exclusively from the gate-to-drain
capacitance.
Since the drain current is constant, the ratio of Lt/ RDR has
no bearing upon the operation during this period. By similar

A-72
reasoning used to analyze the voltage fall during the third
interval of switch-on. the following relationship is derived:

iGD = iDR - iGS

(36) vGS= -V2 + iOR ROR
=VT+g.'Q 8"=0
Is

Turn-Off Interval 3
iO = g,s (VGS - VT)
The general circuit model for this interval is shown in Figure VL r= Lr::O!
19. At the end of the second interval. the drain voltage is just
equal to the supply voltage VD. while the current is equal to the
full load value. 10' The freewheeling rectifier 0 (Figure 2) is
now poised at the point of conduction. ready to receive the load
iGO=-CGD d=~.1
current 10' and the potential at the "top" of Lt is now fixed Vo =Vo- VLr
essentially at VO' In order for the drain current to be commu-
tated into the freewheeling rectifier. it is axiomatic that the
drain voltage must increase above VO' This reflects the funda- Figure 19. General Circuit Model for Turn-Off Interval 3
mental property of inductance Lt; the voltage across it must
reverse in order for the current in it to reduce; a voltage-time
integral must be developed. equal to 10 x Lt. for the drain
current to be returned to zero. This fundamental consideration
relates directly to the inductance Lt. and is quite independent of
any other circuit considerations. The magnitude of the peak
overvoltage developed across the HEXFET will be propor-
tional to the size of the inductance Lt. the magnitude of the
current 10. and the speed of switching.
'D= 9f.IVGS - YT)
In most practical circuits. the voltage transient at the drain
can easily exceed the voltage rating of the HEXFET. In the vL t:;:: L,::D* 0
absence of an externally connected local voltage clamp. the vD=VD- "LlO
HEXFET will likely be driven into avalanche. acting. in effect.

VGS= VT + '0
10 ills
~
Figure 20. Circuit Model for Turn-Off Interval 3 Small
Lt/ROR

as its own voltage clamp, and preventing further substantial

increase of voltage. This mayor may not be permissible.
iOO= lOR
depending upon whether the HEXFET is rated to handle the
avalanche energy. If it cannot do so. then a local external
•,
Vo voltage clamp, such as a zener diode, connected physically close
to the drain and source terminals will be needed, and this will be
dV O 'GO functionally equivalent to the HEXFET itself avalanching, save
dt=CGo that the energy is absorbed by the clamp. rather than by the
HEXFET.
In this third time interval of turn-off. as during the second
time interval of turn-on, both the drain current and the drain
voltage change. Again. these two events are dynamically intert-
Figure 17. Circuit Model for Turn-Off Interval 2
wined. A change of drain current produces a change of voltage
across Lt; this produces a current flow through the "Miller"
capacitance eGO; this restrains the rate of decrease of gate
voltage. which in turn restrains the original rate of change of
drain current.
As we would expect, the form of the analytic solutions
depends upon the ratio of Lt/ROR' We will simply state the
results, since the derivation follows the same general procedures
covered for the second turn-on interval.

Small LtlROR
The equivalent circuit model is shown in Figure 20. and
operating waveforms are shown in Figure 21.

For small Lt/RoR, equation (6) must be satisfied:

Figure 18. Waveforms for Turn-Off Interval 2
(37)

A-73
 LtJ ROR that satisfy equation (7) are shown in Figure 22(a).
Expressions for the gate voltage vGS' the drain current i O ' and
the drain voltage Vo are as follows:

_(I0/gfs+ VT+ V2)! -t/T I -t/T2 1 .

vGS- (Tt- T2) ,Tie -T2c \-V 2 (40)

. (10 + gfs[V T + V2 J) \ -t/tt -t/T 2 1

10= ·(T I -T 2 ) ,Ttc -T2e \ ...

.. ·-gfs[V T +V 2 J (41)

_ (I0+gfs[V T +V 2 ))LR I -t/T2 -I/TII (42)

Figure 21. Waveforms for Turn-Off Interval 3 Small vO-V D + (T I -T 2 ) ( -e \
Lt/ROR

where T I and T2 are given by equations (II) and (12).

respectively.
Operating waveforms for Ltl R OR given by equation (13) are
shown in Figure 22 (b). Expressions for the gate voltage vGS'
the drain current iO' and the drain voltage Vo are as follows:

The interval ends when the drain current iO falls to zero.

Intermediate LlIRoR
The general circuit model shown in Figure 19 applies. Either
equation (7) or (13) must be satisfied. Operating waveforms for

-'~tl =(~~+ VT + V2)!Tl.I/TI-T2e'I/T21

GATE I ~_
VOLTAGE _ _ _ _ _ _ _
VGS

(Tl- T2)
-V2

I 10 DRAIN I
I
T----
" - -CURRE':'T (lo+alslvT+v211
'---~ 10= (Tl- T2) Tl.'I/TI-T2e·1/T2 -Gfs(V2 +VT)

--I~T ·1' .
DRAIN
_!~O~T~~
VD

1--'3 -----l
Figure 22(8). Waveforms for Turn-Off Interval 3
Intermediate Lt/ROR

GATE
VOLTAGE

DRAIN
CURRENT

DRAIN
VOLTAGE

Figure 22(b). Waveforms for Turn-Off Interval 3

Intermediate Lt/ROR

A-74
 Turn-Off Interval 3a (Clamping of the Drain Voltage)
The expressions just derived assume that the drain voltage
will increase to whatever extent the circuit operation dictates. In
IGO= lOR practice. as already stated. the instantaneous drain voltage is
YGS= -V2+ 10RROR likely to exceed the voltage rating of the HEXFET; this is
=VT+~ particularly true for high LtjROR ratio.
9,. 811=0
In this event. either the .HEXFET will be driven into
iO= 9,. (YGS-VT) avalanche-in effect acting as its own "voltage clamp" and
v Lt= L,d~~ limiting further increase of voltage-or. if the HEXFET is
unable to handle this, an external local voltage clamping device
iGO= -CGOdYLr= iOR would have to be connected.
CIt In either event. at the instant at which the drain voltage
YO =Vo- v L , becomes equal to the "clamp" voltage, interval 3, as given by the
previous equations. comes to an end. and interval 3a-the
clamping interval-starts.
Figure 23. Circuit Model for Turn-Off Interval 3 Large
Figure 25 shows the equivalent circuit for the "clamping"
Lt/ROR interval. with an external clamp, and operating waveforms are
shown in Figure 26. The drain voltage is assumed to stay
constant at the "clamp" level. VCLAMP. while the drain circuit
10
current decays linearly to zero:
I YT+-
GATE -:~Sl (VCLAMP - V0)
YOLTAGEi ___ "2:=-t iO=IO*- LQ t (49)

DRAIN --~O The period ends when iO = O. Note that if the HEXFET acts as
CURRENT I its own clamp and is driven into avalanche, then equation (49)
-------
YO" applies to the HEXFET's drain current; if an external clamp is
,
I
YOLTAGE'~
used. drain current can be assumed to stop flowing at the start
DRAIN of this interval. and equation (49) then applies to the current in
the external clamp.
, Iyo _L ____ _ Turn-Off Interval 4

1- t3---l At the end of interval 3 (or 3a) the drain current has fallen to
zero. but the drain voltage VO"' is greater than the circuit
Figure 24. Waveforms for Tu rn-Off Internal 3 Large
Lt/ROR
Yo =
10CGS 2
VCLAMP
LQ
-->---
ROR CGOg fs
'CLAMP::;; 10* at t::;; 0

-t/T 3 (VCLAMP -VoIl

vo =Vo + (10 + gfs[VT + V 2 ])w3LQe = 10'- -L-,--

{I +-h f~
w3 T3
sin w3 t (45)

where T3 and "'3 are given by equations (17) and (18).

respectively.
Figure 25. Circuit for Clamping Turn-Off Interval 3a
Large Li/ROR
Large Ltj ROR is defined by equation (29). The circuit model
is shown in Figure 23. and operating waveforms are shown in DRAIN
CURRENT
Figure 24. Expressions for the gate voltage vGS' the drain
current iO. and the drain voltage vo. are as follows: ID· ........ ~MP
--~RRENT
lo*'o
'CLAMP= ID·_IVCLA~t-vo)t
DRAIN "
VOLTAGE -;-'--T--
VCLAMP V
Ll __ f_
(48)
l- t 3a

Figure 26. Waveforms for Clamping Turn-Off Interval 3a

where", I is given by equation (28).

A-75
voltage VO' The drain capacitance Co then "rings" with the
stray circuit inductance Lt, the oscillation being damped by the
stray circuit resistance Rt. Figure 27 shows the equivalent cir- (a) ROR =5n
cuit for this interval, and Figure 28 shows a typical drain voltage
waveform.
L~ =200 nH
SWITCHING ENERGY = 0.12 I,J
(50)
where

2L£
T =- (51)
4 R£ t. ns

j4L£C o - C0 21\:2 Yo, V

(52)
w4 = 2L2Co 2 iO,A (b) ROR =SOn
P,WX 10
Ouring this interval the gate voltage discharges exponentially 50
with time constant T G towards a final value of -V2'
40
VI. A Worked Design Example 30
20
Figures 29 through 32 show switching waveforms for a spe-
10
cific design example, obtained from the analytic expressions
presented in this paper. Various combinations of Lt/ R OR ' and 0
amplitude of drive voltage, are considered in order to illustrate
the effects of these parameters on the switching performance.
The following data is used: YO,V
HEXFET type: IRFI50 j'O,A (e) ROR =SOn
p, W X 10 L~ =1,000 nH
CGS: 2650 pF
CGO: 350 pF 50
VT: 3 V 40 SWITCHING ENERGY = 1.8,uJ
gfs: 8 A/V 30 YO
VO: 50 V
20
10: 35A
10
°O~~~~~~~~-=~~~~~~~
t, ns
Figure 29. Turn-On Waveforms For Various
Circuit Conditions
(a) ROR + SOLS; 200 nH
(b) ROR +SOO, LS ; 200 nH
Vo = Vo· at t = 0 (c) ROR +SOO, LS; 1/LH
;- Vo + (VD·-vol e- t ,T4 cos ""4 t
IRF 150, V OR ; 10V
V2 ; 0

Figure 29 shows waveforms calculated for the turn-on inter-

Figure 27. Circuit Model for Turn-Off Interval 4
Figure 28. Drain Voltage for Turn-Off Interval 4
valfor: (a) ROR; 5 ohms, Lt= 200 nH;(b) RDR = 50 ohms, Lt
= 200 nH;and (c) ROR = 50 ohms, L{= I J'H. The drive voltage
VOR is 10 volts.
Condition (a) is representative of a fast drive circuit, and a
relatively high impedance of Lt. The drain voltage falls rapidly,
and most of the current /rise time occurs subsequent to the
collapse of drain voltage. The switching energy is almost neglig-
ible -a mere 0.12 J'J. In Figure 29(b), the inductance is the
same, but the drive resistance has increased to 50 ohms. The
gate drive circuit is now much slower, and the drain voltage
collapses much less rapidly; in fact, the drain current now
completes its rise before the drain voltage collapses completely.
The total switching time (current rise + voltage fall) increases
from 150 ns in Figure 29(a) to 360 ns in Figure 29(b). More
significantly, the switching energy increases from 0.12 J'J to 55
J'J.
In Figure 29(c), the drive circuit resistance is still 50 ohms,
while the drain inductance Lt has increased from 200 nH to I
J'H. The speed of the drive circuit is, therefore, the same as in
Figure 29(b), but the impedance ofL{increases by a factorof5.
The voltage drop in the drain circuit is, therefore, once again
very significant, and the drain voltage collapses much more

A-76
rapidly. Because of the increased inductance, however, the cur-
rent rise time is much longer. The switching energy decreases VO,V
from 55 IlJ in Figure 29(b) to 1.8 IlJ in Figure 29(c), because of iO' A
the much faster voltage collapse. It would be wrong to believe, p, W X 10
however, that the overall switching losses can be decreased by (a)
increasing Lt. The energy saved during turn-on by increasing Lt 50
is more than offset by increased energy at turn-off. Increasing VOR = 10V
40
Lt to reduce the turn-on losses is counterproductive; it simply
postpones the "day of reckoning" to the turn-off interval. 30
20 SWITCHING
Before studying the details of the turn-off waveforms in ENERGY = 55 IlJ
Figure 30, it will be instructive to make some basic comparisons 10
between the operation during the turn-on and turn-off intervals. 0
At turn-on the peak dissipation is drastically effected by the 0 t, ns
Lt/R OR ratio, and is very small if this ratio is large. At turn-off,
however, Lt/ ROR has no real influence on the peak dissipa- vo, V
tion, and this is always relatively high. This is because the drain iO' A
current cannot start to decrease until the drain voltage has risen p, W X 10 (b)
all the way to the circuit voltage. The peak dissipation during
the voltage rise interval (turn-off interval 2) will, therefore, 50 VOR= 15V
always be Vo x 10' While the value of drive resistance, ROR' 40
controls the duration of this period, Lt, has no effect upon it. 30 iO
The next turn-off interval (t3)' is also one of relatively high 20 SWITCHING
power dissipation. Even with no drain inductance, the drain
current must decay from 10 to zero with the drain voltage at the
10 =
ENERGY 6 p.J

full circuit value, VO' In practice Lt will never be zero, and the 00 100 200 300 400 500 600 700 t, ns
energy stored in this inductance (1/2 Ltl02) will also be dissi-
pated during this period. It is evident, therefore, that while the
turn-on energy depends strongly upon the Lt/ R OR ratio, and Figure 31. Tu rn-On Waveforms for:
can be very small ifLt/ROR is large, there is no way of avoiding (a) Orive Voltage VOR = 10V
a much more significant turn-off energy. Generally, the larger is (b) Orive Voltage VOR = 15V
Lt, the greater will be the 10101 energy dissipation, even though IRF 150 ROR = son
the turn-on dissipation may be very low. Ls = 200nH
VO' V
'D' A I
UNCLAMPED (a) ROR= 5" Figures 30(a) through (c) show waveforms at turn-off that
,
kw x 10": VOLTAGE = 235 VPK L, = 200 nH correspond to the same three sets of values ofROR and Ltas in
100 95V CLAMP "SWITCHING" ENERGY 451,J = Figure 29(a) through (c). The waveforms in Figure 30(a)arefor
"CLAMP"ENERGY 235 I,J = a fast drive circuit (ROR = 5 ohms). The drain voltage rises
80 TOTAL ENERGY = 280I,J rapidly to the clamping level of95V. Note that in the absence of
60 .\f\~ a clamp the drain voltage would rise to a hypothetical peak of
'oV
p
~ - 235V (assuming that this 100V rated HEXFET would take it!).
The energy dissipated in the HEXFET during the time the drain
t. ns voltage rises to the 95V clamp level is referred to in Figure 31 as
"switching" energy, and is 45 IlJ-more than two orders of
VO' V (b) ROR = 50!! magnitude greater than the energy at turn-on for the same
tiD,
A., L~ = 200 nH values of ROR and Lt[Figure 29(a)].
100 p, k W X 10 "SWITCHING" ENERGY = 450l'J Once the 95V clamp level is reached, the current decays
80 approximately linearly, and an additional 235 IlJ of energy is
60 dissipated during the clamping period. This energy would be
40f'--+--f. dissipated either in an external clamp, if this is used, or in the
20 ~r-_""'- HEXFET itself-assuming that it is capable of operating in its
O~~~L-~~~~~~~~--~--+ avalanche mode.
t, ns Note thatthe energy stored in Lt,I/2 Ltl02 = 122p.J, is about
(c) ROR = 50!! half the total energy dissipated during the clamping period.
L~ = 1000 nH Simple physical reasoning confirms the correctness ofthis; not
tUNCLAMPEO VOLTAGE = 150 VPK only must the energy stored in Lt be dissipated, but since the
100 supply voltage Vo continues to feed energy to the circuit (iO
80 continues to be dra wn from V0), this energy also must end up
60 being dissipated during this period.
Figure 30(b) shows waveforms for ROR = 50 ohms, with Lt
40r-->gJ~~;:
20~ the same as for Figure 30(a). The response of the gate drive
00 ns circuit is much slower, and hence the rate of rise of drain voltage
is also much slower -so slow, in fact, that the drain voltage
Figure 30. Turn-On Waveforms For Various Circuit never reaches the clamping level of 95V. In this case, all the
Conditions switching energy must be dissipated in the device itself, and
(a) ROR =5n,LS =200 nH there is no opportunity for shunting some of this into an exter-
(b) ROR = son. Ls = 200 nH nal clamp. The total switching time increases from 175 ns
(c) ROR =son. Ls = 1000 nH [Figure 30(a)] to 400 ns, and the total switching energy increases
IRF 150, VOR = 10V from 280 to 450 IlJ. Once again, the turn-off energy of 450 IlJ is
V2 = 0 much greater than the turn-on energy of 55 IlJ for the same
value of Ltand ROR [Figure 29(b)].

A-77

Vo v (a)
iO,A
P, kW X 10- 1
100
"SWITCHING"
ENERGY = 450 !-,J
80
60
40 F---::if--.l;~
20
\fV;;:-;-
O~~~~~~~~~~~--~-+
o 100 200 300 400 500 600 700 t. ns
Vo v (b)
iO,A "SWITCHING"
p. kW X 10- 1 =
ENERGY 110!-,J
95 V
I CLAMP
100 I A complete analysis of the switching operation that includes
80
700 t.ns
Figure 32. Turn-Off Waveforms for:
(al "Negative DriveVoltage" (-V 2l = 0
(bl "Negative Voltage" (-V 2l = 15V
IRF 150 RDR =500
LS =200nH
Figure 30(c) shows turn-off waveforms for ROR = 50 ohms.
but with Ltincreased to II'H. As would be expected. the initial
rate of change of drain voltage is the same as in Figure 30(b);
until the drain voltage becomes equal to the circuit voltage of
50V. the drain current remains constant at 10. and Lt has no
effect. Thereafter. however. the drain voltage moves much more
rapidly upwards, and has no difficulty in reaching the clamp
level of 95V. The total switching time increases to 950 ns,
because of the increased value of Lt, and the total switching
energy increases from 450 I'J in Figure 30(b) to 1435 I'J in
Figure 30( c).
It is interesting to compare the energy reduction at turn-on
when Ltis increased from 200 nH to II'H, Figures 29(b) and (c),
versus the energy increase at turn-off [Figures 30(b) and (c»).
The energy reduction at turn-on is (55 -1.8) =(53.2I'J, while the
energy increase at turn-off is (1435 - 450) = 985 I'J. The net
effect of increasing drain circuit inductance is a very
substantial increase in the total energy dissipation.
The waveforms in Figure 31 show the effect of increas-
ing the applied drive voltage from 10V to l5V, for ROR
50 ohms and Lt= 200 nH. The total switching time decreases
from 360 ns to 160 ns, and the switching energy decreases from
551'J to 61'J. '
Figure 32 shows the same comparison for the turn-off inter-
val. The waveforms in Figure 32(a) are for no applied drive
voltage during the turn-off interval, while those in Figure 32(b)
are for a negative drive voltage of -15V. The total switching time
decreases from 400 to 250 ns, and the switching energy from 450
to 305 I'J. The negative gate drive voltage not only reduces the
total switching energy, but also, because it forces the drain
voltage to reach the 95V clamping level, it offers the possibility
for "dumping" 195 I'J of energy which would otherwise be
dissipated in the HEXFET, into an external clamp.
A-78
VII. The Effect of Common Source Inductance
So far we have ignored the effect of the common source
inductance LS' shown dashed in Figure 2. This inductance will
always be present to some extent; even with careful circuit
layout, the user will have to accept, at a minimum, the internal
lead inductance within the package of the device. For a TO-3
package, this inductance is in the order of 10 to 15 nH. We will
now consider briefly the modifying effect of LS on the switching
operation.
Figure 33 shows the general equivalent circuit which includes
LS' As the drain current iO starts to increase at turn-on, a
voltage will be developed across LS due to the rate of change of
drain current. This voltage is common to the gate circuit, and its
polarity is such to reduce the net voltage appearing between the
gate and source terminals. Like the "Miller" effect, which pro-
vides a negative feedback from the drain to the gate, slowing
down the rate of change of current, so the common source
inductance also provides a negative feedback, from the source
circuit to the gate, also slowing down the change of drain
current.
the effect of the common source inductance can be accom-
plished by means of the procedures already presented. This is
beyond the scope of this paper. We will content ourselves
instead with an approximate analysis, the main benefit of which
is the extreme simplicity of the result.
Referring to the equvialent circuit in Figure 33, it is evident
that LS only has an effect when the drain current is changing,
and the HEXFET is in its active region. This restricts the
analysis to interval 2 during turn-on, and interval 3 during
turn-off.
The loop equation for the gate circuit is:
· RiGS 1._' L '. V
lOR OR + -c- + P-:sIGS + P SIO = OR (53)
p GS
By making the approximation (valid for practical operating
conditions) pLSiO ~ pLSiGS' equation (53) becomes:
· RiGS T_' V
lOR OR + -c- + P_;SIO = OR (54)
P GS
Now
· 8fsi GS (55)
IO=gt:VGS=--
s peGS
Vo
,----.0
10
Figure 33. Equivalent Circuit Including the Effect of
Common Source Inductance, LS
Substituting for iO into equation (54) gives:
ies gfsLsies
iDRRDR + pCes + Ces = VDR (56)
It is seen from equation (56) that the effect of LS' has been to
add a resistive voltage drop, equal to RiGS, into the loop
equation, where:
R' = gfsLs
(57)
Ces
Equation (57) quantifies the voltage which subtracts from the
gate-to-source voltage, and hence acts to restrict the switching
speed. Since iGS ~ lOR [ios iOR as Ltl RRO- 0] we could
conservatively represent thiS voltage drop as R'i OR ' To be sure
this will be "over representing" the modifying effect of LS' but
the result is too simple to resist. The loop equation then
becomes:
iCS
iOR(ROR + R') +-c- = V OR (58)
P CS
We conclude that we can conservatively represent the effect
of the source inductance LS by simply adding an equivalent
resistance R', given by equation (57) to the "real" drive circuit
resistance, R OR ' . switching times. and the lower the overall energy losses. It is
The only modification we then have to make to the analytic
expressions already obtained is to substitute (ROR + R') for
ROR' for turn-on interval 2 and turn-off interval 3. The ana-
lytic expressions for all other intervals remains unaltered.
It is interesting to see what a typical value of R' will be.
Taki".tgtheIRFI50, 100V28AHEXFET,andassumingLS= 10
nH, R' 30n.
According to this simple representation. the modifying effect
of LS will clearly be greatest when the "real" drive circ~it
resistance is low. This is to be expected. We should bear 10
mind, however. that this equivalent representation will tend to
become progressively more conservative as the real drive circuit
resistance becomes lower(assuming that this accompanied by a
corresponding increase in Lt/ R OR)' This is because as the
"Miller" effect becomes greater iGS becomes smaller relative to
iOR and hence the approximation iGSR' == iORR' becomes
more conservative.
VIII. Conclusions
Our major objective has been to convey an understanding of
the switching operation of the HEXFET. by giving a physical
A-79
insight into the switching mechanism. and into the interaction
of the H EXFET with the external circuit. and to provide analyt-
ical tools that enable the switching performance to be quanti-
fied at the design stage. The major conclusions are as follows:
I. The shapes of the switching waves during the intervals that
the drain current and drain voltage simultaneously change
are profoundly influenced by the external circuit parameters-
specifically the drain circuit inductance and the gate circuit
resistance. A given ratio of these parameters substantially
determines the geometry of the switching waves. but the
actual switching time depends upon specific values.
2. At turn-on. the current rises before the voltage fall is com-
pleted. if the ratio of Ltl R OR is small (assuming a clamped
inductive load). The converse is true. if the ratio of Ltl ROR
is large.
3. At turn-off. the drain voltage always rises to the circuit
voltage while the drain current remains constant (assuming
an inductive load). The rate of rise of drain voltage is con-
trolled by the drive circuit resistance. but it is independent of
drain circuit inductance. Once the drain voltage reaches the
circuit voltage. the waveshapes then depend upon the ratio
of Lt/RoR'
4. The turn-off energy is always greater than the turn-on
energy. Increasing the drain circuit inductance decreases
turn-on losses. but increases the turn-off losses by a far
greater amount. The smaller this inductance. the faster the
good design practice. therefore. to keep this inductance as
small as possible. by appropriate attention to circuit layout.
transformer design. etc.
5. Turn-on time and turn-on energy can be decreased by
increasing the applied drive voltage. Turn-off time and turn-
off energy can be decreased by applying an increasing nega-
tive drive voltage.
6. Common source inductance reduces the switching speed and
increases switching energy. It effects the operation during
those intervals in which the drain current changes. and the
HEXFET is in its active mode (turn-on interval 2, and
turn-off interval 3). For these intervals it can be conserva-
tively represented by an equivalent resistance added in series
with the drive circuit resistance. 0
References
I. "Paralleling of Power MOSFETs For Higher Power Out-
put." James B. Forsythe. 1981. lAS-IEEE.
2. "Analysis and Characterization of Power MOSFET Switch-
ing Interval Performance. "S.M. Clemente. B.R. Pelly. A.
Isidori. POWERCON 8, 1981.
CHAPTER 9
APPLICATION NOTE 942
Simplified HEXFETe . Power Dissipation
and Junction Temperature Calculation
Speeds Heatsink Design '.
by R. SEVERNS
The reliability and life expectancy
of HEXFETs, like that of any power
semiconductor, is directly related to
the maximum junction temperature
the device experiences. It is, there-
fore, vital for the designer to be able
to accurately determine the device
power dissipation and the maximum
junction temperature. The power dis-
sipation and maximum junction
temperature along with the ambient
temperature, determine the design of
the heatsink. . tion time, due to transient ringing of
The first step in this process is to
determine the total power dissipation
in the device. This is not trivial since
while the power dissipation deter-
mines the junction temperature, the
power dissipation is itself a function
of the junction temperature, because
the on-resistance increases with tem-
perature. Because of the nonlinear
nature of the on-resistance increase,
which varies from one device type to
another, strictly analytical solutions
can be time-consuming.
This application note presents a
simple graphical method for deter-
mining the total power dissipation
and junction temperature for any
given heatsink. Th\: method provides
a graphic illustration of the condi-
tions that provide a sound and stable
thermal design, as well as showing
the designer conditions that are to be
avoided because they lead to unneces-
sary thermal runaway.
The total power dissipation (PT ) is
the sum of the switching transition
loss (P s ), the conduction loss (Pd, a
fraction of the gate drive power (Po),
and the loss due to loss (P L ), during the sum of the turn-on and turn-off
the switch OFF time. transition losses.
If the load is resistive, then the
Switching Trenelion I.0Il switching transitions will be as shown
Because of the rapid transition times in Figure I(b) and the losses due to
which are possible, Psfora HEXFET each type of transition can be ex-
can, in theory; be almost arbitrarily pressed as:
small for switching rates up to several
P _ (V OS(lIIax) . ID(max» f
hundred kHz if a sufficiently low s- 6 T. , (2)
impedance gate driver is used. In a
practical circuit, however, there are If, because of load or drive circuit
often limitations on the switch transi- peculiarities, the straight line ap-
proximations of Figure I are not suf-
parasitic circuits or the capabilities of ficiently accurate, then the power
the rectifier diodes, so that Psis usu- dissipation can be found from:
ally not negligible. Even if the switch-
P s = f, j~' Vos(t)· lo(t) dt (3)
ing time were zero, any practical cir-
cuit will have stray capacity in the Usually a simple piecewise linear
drain circuit. The energy stored in approximation for Vos(t) and lo(t)is
this capacity while the device is OFF sufficient.
will be dissipated in the switch at
t.urn-on.
Unlike a bipolar switch, the losses ID-.,---,(-......_ _. VIIS .
during switching for a MOSFET are
(a) 8IPOLAII CURRENT
not increased by quasi-saturation or TAILING .
current tailing. As shown in Figure ~,..!
I(a), the switching waveforms for an '.
inductive load can usually be closely'
approximated by two straight lines.
The switching loss for each type of
transition (turn-on or turn-off) is
then:
P _ (VOS(max)' ID(max» f
s,. 2 T, • (I)
where f, is the switching frequency.
The values for VOS(lIIax) and T. will
probably differ for the turn-on and Figure 1. Inductive and Resistive
turn-off transitions due to stray in- Load Switching Transitions
ductance and capacitance. P s is then
A-80
 When the switching losses are cal-
culated from circuit oscillographs,
the foregoing equations are quite
accurate, but if the losses are being
estimated in advance of breadboard-
ing the circuit, a slightly different
procedure is needed.
It is not unusual for Cos + C stra to
be large enough to significantly alter
the transition time of Vos during
turn-off. Figure 2 shows an oscillo-
j!raph of typical switching wa veforms
m a power converter. Note that even
though the gate turn-on and turn-off
times are identical, the transition
time at turn-off is noticeably longer
than at turn-on. This is due to the
finite charging time for the capacit-
ance in the drain circuit by the drain
load current.
This capacitance, as shown in Fig-
ure 3, includes CO" which is integral
to the device, and the stray capacit-
ance in the drain circuit. A TO-3
case, using a thin mica or plastic film
insulating washer will add about
200pF to Cstray. A 0.062" beryllia
washer, on the other hand, will add
only about 2SpF to Cstray and as an
additional benefit will provide a lower
case-to-heatsink thermal impedance
(R 8CH)'
P s can be estimated by using equa-
tions (I) or (2) with the anticipated
transition times due to the gate drive
characteristics in the absence of the
output capacitance and then include
an additional loss (PsC> due to the
drain capacitance.
Figure 2. Effect of Drain-Source Capacity
This loss is:
P _ (Cos+ Cstray) V2osf,
sc- 2 (4)
where Vos is the value of Vos at
switch turn-on.
V+
r-r-
~9
Figure 3. Drain-to-Source
Capacitances
Drain-Source Leakage Current
Losses
During the switch OFF period, a
small temperature-dependent cur-
rent (loss) will flow through the
switch.
The loss due to this current is:
P L =loss' Vos (1 - D) (S)
where Vos is the drain-source volt-
age during the OFF time and D is the
ON time duty cycle of the switch.
Even for T j = ISO°C, this loss is
usually quite small, of the order of
Y.z W or less in a 400V device. There
are, however, circumstances where
P L is not insignificant. If due to the
drive circuit, VGS > 0 during the
OFF time, then loss can be an order
of magnitude larger, and in thilt case,
P L may well be important. This prob-
lem can arise when driving the HEX-
FET from IC logic.
Normally, with the logic driver in
the "0" state, the current into the
driver from the HEXFET is minute
(nanoamperes or less) and the gate-
source voltage is very low. However,
if an open collector driver is used
with a relatively low value of resist-
ance in the collector to improve the
switching speed, the "0" state gate-
source voltage may be high enough
to significantly increase loss.
Due to the considerable variation
in loss as a function of T j , VGS and
VGS(thj from one device to another, it
is difticult to quantify this effect in
advance of the actual design. The
designer will need to look at the
A-81
actual circuit to see if there is a prob-
lem when the device is bei ng operated
in a radiation environment or if VGS
is substantially greater than zero dur-
ing the OFF time.
In a radiation environment, VGS(th)
is progressively reduced as the dos-
age is increased. This can dramati-
cally increase loss, and it is recom-
mended that loss be reduced by
applying a negative VGS during the
OFF time.
Dissipation Due to Gate Drive
A portion of the gate drive power
(P Gi) will be dissi pa ted internally by
the device due to the internal gate
resistance. The portion of the total
gate drive power (P G) dissipated in
the device depends on the internal
gate resistance (Rd, and the external
drive source resistance (Rs) and may
be expressed as:
P Gi = p/~)
\Rs + RG
(6)
~GRG)
P Gi = VGS QG r, (Rs
RG is typically I to IOn. For switch-
ing rates below 100kHz, P Gi is very
small and may be ignored, but as the
switching rate is increased, Rs must
be reduced to obtain faster transition
times, and P G is increased due to the
faster switching rate. In addition, the
amount of VGS overdrive is often
increased to further reduce the tran-
sition times. The net result is that P Gi
may be significant especiaJly for
switching frequencies above SOOkHz.
Conduction Power Loss
The major power loss in a MOS-
FET is Pc. The conduction loss is:
Pc =PD(RMS) ROS(on) (7)
Equation (7) is deceptively simple.
In many applications, 10 will be a
duty cycle modulated triangular or
trapezoidal waveform, and the de-
signer must calculate the RMS value
of the drain current. R OS(onlis a func-
tion ofIo, T j and VGS, and T j is itself
a function of PT'
The data sheet provides graphs for
determining ROS(on)' Figure 4 shows
ROS(on) asa functIOn of VGS and loat
T j =2S o C, and Figure S shows the
normalized value of ROS(on) as a
function of T j .
The first step is to determme I D(RMS)
and VGS and then the value of ROS(on)
at 2SoC [ROS(on125od can be taken
from Figure 4. It T j is known, then
the appropriate multiplier for
ROS(on)250C can be found from Figure
Sand Pc calculated directly from
equation (7). Note that Figure S is for
a particular value OfID and Vas. The
curve does not change very much for
variations in I D, but it is strongly
affected by changes in Vas when Vas
is close to VaS(th)' The value of Vas
selected for the data sheet curve is
well above VaS(th) and as long as the
designer uses a value of Vas equal to
or greater than the curve value, then
little error will occur.
Instead of using Figure 6, an analyt-
ical expression for RDS(on) can be
used:
Tr25
R DS(on)!:R DS(on)25°C 1+
(
I~O )
The dashed line on Figure 5 is a plot
of equation (8) with or =0.7. The fit of
the equation is very good above
25 0 C, but below 25° C the fit becomes
quite poor. Figure 5 is for an IRF431
which is a 450V device. Figure 6
shows the normalized RDS(on) curve
for an IRFI51, a 100V device. Using
an or of 0.4, the fit is very good, and
the analytic expression for RDS(on) is
quite accurate. As the examples in
Figure 5 and 6 show, both the shape
of the RDS(on) curve and the value for
or, vary from one device type to
another and for each value of Vas. In
order to determine or, it is necessary
(8) to have the RD!Ron) versus tempera-
ture curve, but it one has the curve,
then there is no real need for an ana-
lytic solution since the graphical solu-
tion is simpler and will produce an-
swers of sufficient accuracy. For those
who wish an analytic solution using
equation (8), Table I is a tabulation
of solutions to that equation.
The solution for Pc is not so easy if
T J is not defined. In a typical applica-
tion, the properties of the heatsink
may be defined and the designer must
then calculate both Pc and T J for a
variety ofload and line conditions. In
this case, Pc is in part determined by
P s , P L and Po and the solution has
to include these losses. Fortunately,
there is a simple graphical solution
method.

2.2

I- .I
~
I/
2.2
1RF151

I
I 10
~
~~
V
V

j 3A~ t=
1.=0.7

bI'
~ 0=0.4

.......
V""

lA .1.
--
,. V'
'/ VGS
10 ~
~
1.5A
lOY
f--
... i,...oo'
Voa ~ lOY
ID= 14A I-

:- I. G.2
m
0 2
•• 10 12 1.
VGS-VOLTS
l' 211 ~ 0 ~
T,. JUNCTION TEMPERATURE ('C)
1211
~ 0 ~
TJ. JUNCTION TEMPERATURE ('C)
m 1211

Figure 4. RDS(ON) Dependence on I D Figure 5. Normalized On-Resistance Vs. Figure 6. Normalized On-Resistance Vs.,
Temperature (IRF431) Temperature (IRF151)

Table I
RDS(on) NORMALIZED
TJoC
TA = ATJ or= or= or= a= or= or= or= or= or= or= a= a= a= or= a=
25°C °C 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 .
-40 -65 0.82 0.80 0.77 0.75 0.72 0.70 0.68 0.66 0.64 0.62 0.60 0.58 0.56 0.54 0.52
-20 -45 0.87 0.85 0.84 0.82 0.80 0.78 0.76 0.75 0.73 0.71 0.70 0.68 0.67 0.65 0.64
0 -25 0.93 0.92 0.91 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 0.79 0.78
25 0 I I I I I I I I I I I I I I I
40 15 1.05 1.05 1.06 1.07 1.08 1.09 1.09 1.10 1.11 1.12 1.13 1.14 1.14 1.15 1.16
60 35 1.11 1.13 1.15 1.17 1.19 1.21 1.23 1.25 1.28 1.30 1.32 1.34 1.37 1.39 1.42
80 55 1.18 1.21 1.25 1.28 1.32 1.35 1.39 1.43 1.47 1.51 1.55 1.59 1.64 1.68 1.73
100 75 1.25 1.30 1.35 1.40 1.45 1.51 1.57 1.63 1.69 1.75 1.82 1.89 1.96 2.03 2.11
120 95 1.33 1.39 1.46 1.53 1.61 1.68 1.77 1.85 1.94 2.03 2.13 2.23 2.34 2.46 257
140 115 1.41 1.49 1.58 1.68 1.77 1.88 1.99 2.11 2.23 2.36 2.50 2.65 2.80 2.97 3.14
160 135 1.50 1.60 1.71 1.83 1.96 2.10 2.24 2.40 2.56 2.74 2.93 3.14 3.35 3.58 3.83
180 155 1.59 1.72 1.86 2.01 2.17 2.34 2.53 2.73 2.95 3.18 3.44 3.71 4.01 4.33 4.68
200 175 1.69 1.84 2.01 2.19 2.39 2.61 2.85 3.11 3.39 3.70 4.03 4.40 4.80 5.23 5.70

A-82
Graphical Solution for MOSFET
Thermal Design
From the earlier discussion:
PT=PS+PL+PO+PC (9)
For convenience, one can lump
together the fixed losses·:
PI = P s + P L + Po (10)
Substituting equations (7) and (10)
in equation (9):
P T = PI + I2D(RMs) ROS(on) (II)
From thermal considerations:
T J = TA + ROJA P T (12)
and
ROJA = ROHA + ROCH + ROJC (13)
• This example ignores the tempera-
ture dependent nature of P L on the
assumption that it is negligible or
that the worst case value is used.
To determine Pc and T J requires
the simultaneous solution of equa-
tions (II) and (12). This can be done
graphically as shown in Figure 7.
If PI and I DtRMS) are presumed
constant over the range of T J the
shape of the P T versus T J curve is
determined by ROS(on)' Except for a
scale factor and an offset, the curve
for P T is exactly the same as that
shown in Figures 5 and 6
The scale factor is:
KI = I2D(RMs) ROS(on) 25°C (14)
...~
il
; r
."..
2". Pn
~ ...
TJ
---+
JUNCTION TEMPERATURE
Figure 7. Graphical Representation of the Thermal Equations
The offset is: 4. If T J > Tj2 then P T is always
K2 = PI
greater than the heat removed.
P T and T J will then increase
Then the total power dissipation is: without limit until the device is
destroyed. This is a thermal run-
PT = KI ROS(on)normalized + K2 away condition.
As long as the initial temperature is
The curve for equation (12) is simply
a straight line with slope of 1/ ROJA less than T;; then T J will converge at
and which intersects the T J axis at T J T;;. If ROJA is further increased to
R OJA2 • there is no intersection of the
=T A • curves and this also represents a con-
=(TJ~\J
I dition of thermal runaway, since P T
(15)
is always greater than the heat re-
moved by the heatsink.
The intersection of the two curves is
the desired solution. Figure 7 clearly Design Example 1
demonstrates the effect of increasing Device = IRF431
R OJA ' As ROJA is increased, both P T R OJC = l.7 deg. Cf W
and T J increase. A point is reached ROCH = 0.4 deg. Cf W
where there may be two intersections ROHA =2 deg. CfW and
of the curves at TJ2 and T J2 · 4deg. e/w
TJ2 represents a point of stable ID(RMS) =2.IA
thermal equilibrium and T;2 repre- R OS(on)25° C = l.7n (max.
sents an unstable equilibrium point. ROS(on) at 10 =
That this is so can be seen by inspec- 3A)
tion of Figure 7 as follows: TA = 55°e
PI =0
I. Stable equilibrium can exist only
if the heat input (P T) from the Find T J and P T for each value of
R OHA '
switch equals the heat dissipated
by the sink. ROJA = RoJC + ROCH +
2. For T J < T;; P T exceeds the heat ROHA
removed by the sink. T J must = 4.1 deg. CfW
= 6.1 deg. CfW
therefore rise, increasing P T, un-
til T J = TI2 where P T equals the The graphical solution is shown in
heat removed. Figure 8. For ROHA = 2 deg. Cf W. P T
3. For TJ2 < T J < T;2 the heat =14.5Wand T J = 115°e. For ROHA =
removed by the sink is greater 4 deg. e/ w, there is no intersection
than P T and the device must cool and the device will experience ther-
down, reducing P T, until T J = T;;. mal runaway.
25
R//JA3
~
~
I
l-
Figure 8. Design Example 1
A-83
 Suppose one wishes to set P I to P T - PI TA = 55°C
some val ue other than zero or to vary , P N == = ROS(on)N (21) I D(RMS) " 2.1 and 1.2A
P T(250C) - PI
I g. The solution method used in Fig- PI "OWand4W
ure 8 would require the graphs to be P N = ROS(on)N Find T J and P T for each case.
redrawn for each new condition. It
would be preferable ifthe normalized The vertical scale of the R OS(on) Solution 1
ON-resistance versus temperature normalized scale is now numerically
graph could be used directly without equal to P N. Step I:
a change of scale for all solutions. Locate two points on the graph to
In a similar fashion. the second plot equation (26):
The P T and T J calc!llations could equation can be normalized:
then be done directly on the data Point I: For P N = O. T J = TA
sheet curves. adding only straight T J = TA + R9JA P T (23)
Point 2: For P N = I
lines. This can be done by normaliz-
ing the P T scale. Rearranging equation (21): T J = T A + R9JA J2D(RMS) R OS(on)250C
P T = PI + P N [PT(25°C) - Pil (24) T J = 55° + (4.1) (2.12) (1.7) = 86°C
At any temperature:
Equation (24) may be simplified to: Step 2:
P T = PI + PO(RMS) ROS(on) (16)
P T = PI + P N [PD(RMS)' Draw a straight line through:
At 25°C: R OS(on)250c1 (25) PN"O. T J = 55°Cand P N= I. T J = 86°C
PT(25oq= P I+ PD(RMS) ROS(on)25odI7) And then combine equations (23) Step 3:
and (25): Read T J directly off. T J = 115°C
Reordering equations (16) and (17):
TJ=TA+R9JA[PI+PN' P N= 1.9
P T - PI = PD(RMS) ROS(on) (18) (PO(RMS) ROS(on)250C)] (26)
Step 4:
PT(25oq-P I =PD(RMS) R OS(on)25od 19) Calculate P T
Once a graphical solution in terms
Dividing equation (18) by equation of P N is found. T J may be read out P T = PI + PO(RMS) R O(on)25°C P N
(19): directly and P T can be calculated
from equation (25). P T = 0 + (2.22) (1.7) (1.9)
P T - PI ROS(on) P T = 14.5W
PT(25~q - PI
= R OS(on)2SoC) Design Example 2
(20) Refer to Figure 9. Solution 2
" ROS(on)N = normalized value of Device = IRF431 10(RMs) is reduced to 1.2A and PI is
R9JC = 1.7 deg. CjW increased to 4W. TA remains at 55°C.
ROS(on) as given in the
data sheet graph. R 9CH = 0.4 deg. Cj W Step I:
R9HA = 2 deg. CjW Find two points for equation (26)
If we then define the normalized ROS(on)250C) = 1.7!1at2.IAand with P N = 0 and P N = I.
power P N: 1.5!1 at 1.2A Point I:
TJI = TA + R9JA PI
TJI = 55 + (4.1) (4)
TJI = 71°C

2.6 Point 2:
2.4 IRF431 T J2 = T A + R9JA P T(25oC)
2.2 T J2 " 55 + 4.1 [( 1.22) (1.5) + 4]
2.0 TJ2 = 80°C
Q
W 1.8 Step 2:
Draw a straight line through:
i
Q
Z
1.6
1.4
1.2
PN=O. T J = 71°Cand P N= I. T J " 64°C
I Step 3:
g 1.0 Read off T J = 85°C and P N " 1.6
~ 0.8
a:
0.& Step 4:
OA Calculate P T
0.2 P T = 4 + 1.6 [( 1.22) (1.5)]
-40 -20 o +20 +40 +60 +80 +100 -120 -140
PT =7..5W
JUNCTION TEMPERATURE, TJ - °c
Determination of the Peak Junction
Temperature for Pulsed Current
Figure 9. Design Example 2
Waveforms
The previous discussion and exam-
ples were for the average junction
temperature. For very long(> I sec.).
high duty cycle pulses or very short
A-84
« lOllS) pulses, the peak junction
temperature is very nearly equal to
the average junction temperature,
and the procedure is acceptable. For
other operating conditions, the pro-
cedure is identical, but the equation
(26) must be modified to use the tran-
sient thermal impedance, ZBJC' ZBJC
is related to R BJC by:
ZBJC = ret) R BJC (27)
where ret) is the normalizing factor
taken from the normalized transient
thermal impedance curves for the
particular device. The appropriate
values for the pulse width (t p ) and
duty cycle (D) must be used.
Equation (26) can now be modified
to:
T J = T A + (r(t) R8JC + R 8CA ) [PI + P N
(I2D(RMS) ROS(on)Wd] (28)
The procedure is exactly as shown
earlier except that equation (28) is
used instead of equation (26).
can be calculated from:
IRMS=
(2)
JFRMS(I)+ FRMS(2)+ .. ·+FRMS(N)
In some applications such as switch-
ing regulators, it is possible for the
designer to control the wave shape to
some extent. This can be very benefi-
cial in reducing the value for I RMS in
the switch for a given value of aver-
age current (IAVd.
Effect of Wavefonn Shape on RMS
Value
In a switch mode converter, the
current waveforms through the in-
ductors, transformer windings, recti-
fiers and switches will appear as
shown in Figure A-2, ranging from a
triangle to a rectangle depending on
the value of the averaging inductor
and the load. For the capacitors, the
waveforms will be similar, except
that there can be no DC component
as shown in Figure A-3. The RMS
values of the waveform are given in
the figures.
It can be shown that:
K = ~ =f (LI Lc) (3)
where: Ib
L = inductance of the averaging
choke.

"o-t---u
Summary
The power loss calculation for a
power MOSFET differs substantially
from the same calculation for a bipo-
lar power transistor primarily be-
cause of the FD(RMS) ROS(on) loss
characteristic. The calculation IS fur- I I PULSED T
ther complicated by the non-linear r- T --J SINUSOIDAL
behavior of ROS(on) versus T J . Be-
cause the RDS(on) characteristic must
be determined experimentally for I - I [0 sin
RMS- 12"+
T (1-0) cos 7r (1-0)
27r
ll12
_
each device type, a strictly algebraic
approach to the loss calculation is
very cumbersome. The graphical o ; 1-,.11
method shown here is much more
rapid and is just as accurate.
APPENDIX

Determining the RMS Value of 10

Waveforms
r-
T-[
11 ~ - - - ~ ---~

To accurately determine the con-

duction losses in a MOSFET, the o T
RMS value for ID must be known.
The current waveforms are rarely I---T- REctANGULAR
simple smusoids or rectangles. and
this can pose some problems in de-
termining the value for I RMS ' The
following equations and procedure
can be used to determine I RMS for
any waveform that can be broken up o =~
into segments for which the RMS T
value can be calculated individually.
The RMSvalue of any waveform is
defined as:
I RMS = [lIT s; [1(t)]2 dt]I/2
Figure A-I shows several simple
waveforms and the derivation for
I RMS using equation (I).
(I)
,,[ii-7T---J
I-- -l
T TRIANGLE
o
If the actual waveform can be ap-
proximated satisfactorily by combin-
ing the waveforms in Figure A-I, Figure A-1.
then the RMSvalue of the waveform
A-as
Lc =I is the critical inductance for a I.flb > 0.6, the additional losses A plot of equation (4) is given in
particular input voltage and load incurred by having L < a is only 2%, Figure A-5, where It• vg ) is constant
power. so from a practical point of view, L and I RMs is normahzed to D, I. =
As L is increased, K goes from 0 .need only be about twice Le. Increas- Obviously, triangular current wave-
(triangle) to I (rectangle). Substitut- ing the value of Ia lIb increases the forms with high peak currents and
ing K = I./Ib' for the continuous switch turn-on losses but decreases low duty cycles are to be avoided if
choke current casre_:_ _ __ the turn-off losses. Since the turn-off low losses are desired.
_~jK2+K+I losses frequently dominate, increas- For the case where: I. = Ib:
ing 1.1 Ib reduces the total switching
I RMs - v"1> 3 (K + 1)2 (4) loss also. I RMs - V 31)
-~
F~r constant Ilavg) and D, the ,:or- For the case of discontinuous in- the curve in Figure A-5 also applies.
mahzed(I RMs = for K =I) I RMS Isas ductorcurrent(L< 4), 1.1 Ib = Oand .t is important to realize that for a
shown in Figure A-4. This curve is no longer relevant, since the wave- given input voltage, current and
shows that, for triangular current forms are now triangles. For a given transformation ratio, there can be a
waveforms, the PR losses are 32% I(avg) the RMS current is: difference in duty cycle which allows
higher than for rectangular wave- one circuit to have lower losses due to
forms. It is also apparent that for I RMS -~
-3D the lower value of I RMS'

I 1.16

.((lfl
GENERAL CASE
III
!:!
:ii!
::I!
!
z
1.14

1.12

1.10

1.06
\
\
~ 1.06
'\.
_ {D [ I.' + I. Ib + Ib' 0
IRMS - 3 -"4 (I. + I bY]}''' .$ '\
1.1)4
T "-..
0 =
T 1.1l2 I'....
SPECIAL CASES
1) 0 =1
1
--- 1--1-

Ib-I.
00 0.1 G.2 G.3 G.4 o.s 0.6 0.7 o.a 0.9 1.0
IRMS = K =I.llb
v'12
2) I. = Ib
Figure A-4. Variation of I AMS with Squareness Ratio
IRMS = I• ..j 0 - 0'
3) I. =0

IRMS =Ib ~
3"-4 6 I
I
I
I
I I
I 1 I
I
I
IRMS(N) =y'l)

Figure A-2. RMS Current Through a Capacitor 5 IIIVII = CONSTANT -

Q 4
\
/
/11b
/ I
I SMALLL
~
~
I0 3
\
1\
/ I
/ I
/ I Z
/
/ I
I '"lI!
.$2
1.~'lb
"f'..-
---r---
/
/
/ t-- f--
/ 1
/
/ LARGEL
/
/
/
/
00 0.1 G.2 0.3 G.4o.s 0.& 0.7 o.a G.9 1.0
DUTY CYCLE

Figure A-3. Current Waveform Figure A-5. Variation of lAMS Value with Duty Cycle

A-S6

A Universal 100kHz Power Supply
Using a Single HEXFET
By S. CLEMENTE, B. PELLY, R. RUTTONSHA
Summary
Power MOSFETs are attractive
candidates for use in switching power
supplies. In order to take full advant-
age of their unique characteristics,
one cannot simply substitute a M OS-
FET for a bipolar transistor in an
existing circuit. More fundamentally,
it is necessary to rethink basic con-
cepts, and to shape the circuit around
the operating features of the device.
This application note describes a
100kHz, 100W off-line power supply
providing a regulated 5V DC output.
The circuit is "universal" in the sense
that it operates both from 115V and
240V line inputs, without any altera-
tion of circuitry or switching of com-
ponents. The circuit uses a single
500V-rated power HEXFET in a
modification of the classical "forward
converter" circuit.
Introduction
DC power supplies are employed
today wherever electrical or electronic
equipment is in use. Traditional de-
signs that operate from AC input
power are based upon the use of a
line frequency transformer, a sec-
ondary rectifier, an output filter and
a dissipative series regulating ele-
ment; typical overall efficiency is 40%
to 50%.
Newer designs are based upon fun-
damentally more efficient high fre-
quency switching techniques. The line
frequency is first rectified to DC,
then inverted to high frequency AC,
by a transistor switching circuit. The
high frequency voltage is fed through
an output transformer, rectified and
filtered to produce the required DC.
Regulation of the output is accom-
plished by controlling the pulse width
8
of the high frequency voltage wave.
This circuit technique gives much·
better efficiency - typically 75% to
85% - and a dramatic reduction in
size - typically 4 or 5 to I - because
of the much smaller magnetic and
filter components associated with the
use of high frequency.
Today, most switching power supp-
lies use power bipolar transistors.
Switching frequencies are in the range
of 20kHz to 40kHz. Although a few
designs operate at higher frequency,
this undoubtedly means "pushing"
the bipolar to the limits of its per-
formance.
Higher operating frequency than
the usual 20kHz to 40kHz range is in
principle advantageous, because it
offers the possibility for further re-
ductions in size of magnetic and filter
components, as well as faster re-
sponse. With the availability of power
MOSFETs, the switching component
is no longer the frequency limiting
element in the system. This new situa-
tion has generated considerable in-
terest in where the optimum switch-
ing frequency of a power supply now
lies, having due regard to the tech-
nology of the associated magnetic
and filter components. Presently,
there is no clear consensus. It is safe
to say, however, that the optimum
switching frequency is certainly
greater than the 20kHz to 40kHz
range of the bipolar transistor. Most
probably it is at least 100kHz, and
perhaps considerably higher.
It would be erroneous, however, to
assume that the potential advantage
of the power MOSFET is simply one
of faster switching speed and higher
frequency. In order to utilize all of
the characteristics of the power MOS-
FET to best advantage, the design
A-87
CHAPTER 10
APPLICATION NOTE 939
task is not simply one of pursuing
well trodden bipolar transistor cir-
cuit techniques, albeit with higher
operating frequency. Basic circuit
concepts should be rethought; only
then can all the potential advantages
of the MOSFET be realized.
By the same token, it can be quite
erroneous to labor under the notion
that because power MOSFETs still
are more expensive than bipolars,
therefore they are not yet economic-
ally competitive. This overlooks the
fact that performance advantages, or
cost reductions, or both, are achieve-
able at the system level with these
devices, that can more than compen-
sate for their higher costs.
In this application note, we present
a switching power supply using a
HEXFET that operates at 100kHz-
a considerably higher frequency than
normally used with bipolar transis-
tors. Attainment of this frequency
actually is no particular feat for a
power HEXFET, since frequencies
much higher are within easy reach. A
more vital objective of this applica-
tion note is to demonstrate that by
rethinking basic circuit concepts, re-
sults are achievable which, to many
circuit designers at first sight, might
seem to be unattainable. Specifically,
we will show that just a single 500V-
rated HEXFET can be used in a cir-
cuit that operates from a 265V line
input; this compares with the usual
800V minimum rating requirement
of a bipolar transistor in a single-
ended circuit. We will moreover
demonstrate a circuit which has the
surprising capability of maintaining
a constant DC output voltage over a
very wide range of line input voltage
-a "universal"powersupply-that
can operate both from the 115V line
common in the United States, and
from a 220V / 240V line common in
Europe, without any modification of
circuitry or switching of components.
Specific Design Goals
The discussion that follows is add-
ressed to the general circuit concepts
involved in using a single power
HEXFET in a wide input voltage
range switching power supply. A
specific implementation of the con-
cepts described is presented; this is a
circuit for a 100kHz, 100W, 5V DC
power supply that employs a single
500V / 3.5A-rated power HEXFETin
a TO-220 package.
The performance of this power sup-
ply is summarized in Table I. Varia-
tions from these specifications - dif-
ferent output power, different output
Table 1. Performance Characteristics of 100kHz "Universal" Power Supply
Minimum Input Voltage
Maximum Input Voltage
Output Voltage
Maximum Output Current
DC Output Voltage Regulation, For
All Conditions of Output Current &
Input Voltage
Maximum Output Ripple Voltage
Transient Response for a Step Change
of lOA Load Current
Full Load Efficiency
voltage, different operating fre-
quency, and so on - are obviously
possible, without departing from the
basic concepts.
Basic Concepts
The Conventional Forward Conver-
ter Circuit
The basic single-transistor forward
converter circuit is shown in Figure I.
Idealized voltage and current wave-
forms that describe the operation are
shown in Figure 2. During the con-
duction period of the transistor, cur-
rent is transferred from the primary
DC power source through the output
transformer to the output circuit.
During the OFF period of the tran-
sistor, the magnetizing current in the
transformer is returned via the clamp-
ing winding to the primary DC source,
85V RMS, 50-400 Hz
265V RMS, 50-400 Hz
5VDC
20ADC
±0.5%
50mV p-p
500mV, settling within
250/-,s
74%
resetting the flux in the transformer
core, prior to the next cycle of opera-
tion.
The clamping winding usually has
the same number of turns as the
primary, which means that the peak
voltage developed across the transis-
tor during the OFF period is twice
the primary DC supply voltage. For
a nominal line input voltage of say
240V, this peak voltage would be
about nov; this is why a transistor
voltage rating of. at least 800V is
required.
The maximum permissible conduc-
tion period of the transistor is 50% of
the total cycle time. It cannot be
longer than this, because there would
then be insufficient time for the trans-
former flux to be reset during the
transistor OFF period, and the trans-
former would be driven into satura-
tion. A 50% duty cycle is approached
for the condition oflow input voltage
and full load; the transistor conduc-
tion time automatically decreases
from this point as the line input volt-
age increases or as the output load
decreases, under the action of a
closed-loop regulator circuit, which
acts so as to maintain an essentially
constant output voltage.
Modified Circuit
There is no fundamental need to
clamp the peak transistor voltage to
twice the supply voltage. The device
voltage could be clamped to any level
that is higher than the DC supply

tUD
avoc
1o
-.L
I
::»':NQ
VOI.TAGE

¥DC TRANSISTOR
- - T

o
JLJ:l - -
CURRENT IN
SWITCHING
TRANSISTOR

'VLINE
INPUT
o~=:lGIN
WINOING

o
JLJJ __ _
CUMENTIN
TRANSFORMER
SECONDARY

------------------ ~~~
0-------------
Figure 1. Basic Single-Transistor Forward Converter Circuit Figure 2. Idealized Waveforms for the
Circuit of Figure 1

A-SS
voltage, so long as the voltage-time
integral developed across the trans-
former during the OFF period of the
transistor is equal and opposite to the
voltage-time integral during the con-
duction period, thereby fully resetting
the flux by the end of each cycle.
It is therefore possible, in principle,
to reduce the peak transistor voltage,
at the expense of reducing the con-
duction time of the transistor. The
penalty is that the peak device cur-
rent necessarily increases as the con-
duction time decreases, for a given
power output and input voltage level.
The idealized waveforms in Figure
3(a) illustrate operation with a 20%
duty cycle; for comparison, Figure
3(b) represents operation with a 50%
duty cycle, for the same power out-
put and input voltage. The peak tran-
sistor current is greater by a factor of
2.5 for the shorter conduction period;
the peak transistor voltage, on the
other hand, is lower, by a factor of
1.6. This means that for a 240V input,
the peak transistor voltage is reduced
from the usual720V to around 450V,
permitting a 500V-rated HEXFETto
be used.
With a bipolar transistor, opera-
tion with a duty cycle substantially
less than 50% is undesirable. The
gain of a bipolar decreases, and the
device becomes increasingly difficult
to use as the peak current increases.
The transconductance of the power
HEXFET, on the other hand, does
not decrease with increasing drain
(e) 20% Duty Cycle
EQUAL YOLT-8EC
....EAS
I~DEYIC.
2r
-1 _ _
(b) 50% Duty Cycle
I
~-.J ~
. - DEVICE
_ _...I _ _
t
Figure 3. Idealized Waveforms of
Device Voltage and Current
current, and it is quite practical to
operate a HEXFETwith a short duty
cycle at relatively high peak current.
Higher peak current will, of course,
produce greater conduction power
dissipation than would be obtained
in a circuit operating with a longer
conduction time at correspondingly
lower current. This is of little con-
cern, however, because the HEXFET
is well able to handle the "extra" dis-
sipation; in any event, the dissipation
in the switching device is substan-
tially less than that in the output rec-
tifiers. It is an unfortunate fact that
the conduction voltage drop in these
rectifiers is quite significant for a 5V
output, and the circuit losses tend to
be dominated by the rectifier losses.
Clamping the Drain Voltage
The drain voltage must be clamped
at a level that ensures the output
transformer is completely reset dur-
ing the OFF period of the HEXFET.
There are various ways of doing this.
A clamping· winding on the output
transformer - used in the conven-
tional forward converter with a 50%
duty cycle - can, in principle, still be
used. The ratio of clamping turns to
primary turns would, of course, no
longer be I to I. Taking the example
considered, for a conduction duty
cycle of 0.2, the peak transistor volt-
age must be at least 1.25X the prim-
ary DC source voltage. The clamping
winding should therefore have four
(a) Circuit
DEVICE
VOLTAGE
CURRENT
(b) Idealized Device Voltage
DEVICE:
VOLTAGE
CURRENT
Figure 4. Use of a Transformer
A-89
times the number of primary turns,
as shown in Figure 4(a).
This fixes the peak transistor volt-
age at 1.25X the primary DC source
voltage, as illustrated in Figure 4(b).
A duty cycle of 0.2 would be set to
occur when the line input voltage is
lowest, and the output load current is
highest. As the line input voltage
increases, or the load current de-
creases, the conduction time of the
transistor would decrease, under the
action of a closed-loop regulator, so
as to keep the DC output voltage at a
constant value. The transistor clamp-
ing voltage would always be 1.25X
the primary DC source voltage, re-
gardless of what that voltage might
be. The flux in the transformer is
therefore reset before the end of the
cycle, except at the condition of min-
imum line input voltage, and the
peak transistor voltage is therefore
generally higher than the level that is
just sufficient to reset the transformer
by the end of the cycle.
A transformer clamping winding,
though realizable, creates some prac-
tical problems. In the example consi-
dered, the peak voltage developed
between the primary and clamping
windings would be five times the DC
source voltage; the insulation be-
tween these windings must be suffi-
cient to withstand this voltage. The
clam pi ng rectifier also sees a total of
five times the DC source voltage and
must be rated accordingly. Perhaps
the biggest practical difficulty is that
CLAMPING DIODE - SEES 5X VDC
Clamping Winding
substantial leakage inductance and type have a maximum duty cycle of realized in a surprisingly simple man-
self-capacitance inevitably appears 0.5. At all events, if we design the ner. The circuit is illustrated in Fig-
between the primary and clamping circuit according to these principles, ure 6. The capacitor C is a "reservoir"
windings, and this gives rise to super- we will have a "universal" power capacitor which charges to an essen-
imposed high frequency oscillations supply, capable of delivering the same tially steady level of voltage - the
on the current and voltage waves, as regulated DC output voltage both necessary transformer resetting volt-
shown in Figure 4(c). These oscilla- from 115V and 220V /240V line in- age. The resistor R dissipates the
tions are difficult to eliminate. puts, with no modification of cir- energy delivered to the clamping cir-
cuitry, or switching of components. cuit from the transformer. Unlike the
transformer winding, which returns
A Different Approach the energy stored in the transformer
A much more satisfactory approach A C8pacit0r-Resistor-Diode Clamp to the primary DC source, this is a
arises from the basic fact that for The desired clamping circuit can be dissipative clamp.
minimum voltage stress on the HEX-
FET, the voltage that appears across
the transformer during the device
OFF period should have the right (e) Practical Oscillograms
amplitude to reset the fluxjust by the
end of this period, independent of the
conduction duty cycle. This principle CURRENT
Appro........, 4,\ P8IIk
is illustrated by the idealized wave-
forms in Figure 5. In this example, it
is assumed that the minimum duty
cycle, which occurs at maximum in-
put voltage, is 0.15. VOLTAGE
ApproaIrn8teIy 400V,...
If this principle is followed, the vol-
tage that appears across the trans-
former during the reset period by no
means bears a fixed relationship to
the primary DC source voltage; it Figure 4. Use of a Transformer Clamping Winding (continued)
increases as the DC source voltage
decreases and is inversely propor-
tional to (I-D), where D is the duty (8) Voc =VOClmax) D =0.15
cycle. Thus, a transformer clamping _~VCL"O"avDC(""')
winding, in principle, will not do the 1 -- --- - - - -- !
job.
VPK = 1.1IVDC(MAX) Voc = VDC(MAX)
If the required clamping circuit
could be devised, two benefits - in L__ _________ I
addition to the elimination of the (b) Voc = 0.5V DClmax) D = 0.3 VCLAMP " O""DC (MAX)
transformer clamping winding - L
would be realized. First, as already
mentioned, the voltage across the
HEXFET would be minimized. Sec-
VPK" O.72VDC(_~~~~~~t:DC" UVDC(MAX)

ond, there would not be a maximum (e) Voe =0.3VDClmax) D =0.5

permissible conduction period for
the transistor - as there is with a
transformer clamping winding -
above which the transistor OFF per-
iod becomes too short for the trans- YCLAMP = Yoitege Ac.... r,.,..tormer
During OFF Period
former flux to be reset. There would
therefore no longer be the same mini- Figure 5. Idealized Waveforms Illustrating Operation when Device Voltage
mum line voltage below which the During OFF Period Always has just Correct Amplitude to Reset
circuit cannot operate. Transformer by End of this Period.
This is very interesting; it means,
for example, that if the circuit is
designed so that it operates with a
rather short duty cycle, say 0.15 at a
line voltage around 265V, then the R
circuit could be made to stay in regu-
lation and to deliver the same DC
output voltage when the line input
voltage is as low as say 80V, at which
point the conduction duty cycle would
be about 0.5. This example is actually
represented by the idealized wave-
forms in Figure 5.
Even this would not theoretically
be the limiting range of operation; as
a practical matter, however, most Figure 6. Capacitor-Resistor-Diode Clamp
integrated circuits that are intended
for controlling power supplies of this
A-90
 From a practical point of view,
because of the possibility for operat-
ing at high frequency, the transformer
can be designed so that the power
dissipation in the clamp is kept to a
quite acceptable level. In the specific
circuit described, the power dissipa-
tion in the clamping circuit is quite
minimal, and ranges between 2% and
3% of the output power.
The inherent action of this simple
clamp can be arranged to be such as
to adjust the steady-state voltage
across the capacitor to the level re-
quired to reset the transformer just
by the end of the OFF period, regard-
less of the level of input voltage. This
can be seen by assuming for the
moment that the voltage across the
capacitor is insufficient to reset the
transformer. In this event, the mag-
netizing current, and the voltage
across the capacitor, "ratchet up"
during succeeding cycles, until the
voltage does become sufficient, at
which point an equilibrium condi-
tion is attained. This action is illus-
trated by the idealized waveforms in
Figure 7.
This clamp thus provides the re-
quired voltage to keep the trans-
former voltage-time integral within
balance, independent (within limits)
of the value of the capacitor C or the
resistor R. Care must be taken, how-
ever, to size the resistor so that mini-
mum energy is stored in the trans-
former ~ that is, so that the mag-
netizing current does not "ratchet up"
more than is necessary ~ otherwise,
the losses will be excessive. Assuming
that the magnetizing current will al-
ways be continuous, and thus that
the HEXFET voltage will always be
minimized, the "best" design will
result from sizing the resistor so that
the magnetizing current is just con-
tinuous at the highest input voltage
level.
CLAMP VOLTAGE
INCREASING
Figure 7. Idealized Waveforms Showing Transformer Magnetizing
Current "Ratcheting Up" to Create Sufficient Clamp
Voltage to Maintain Equilibrium
The general relationship between would then be 1.55' = 2.4X the losses
the voltage across the clamping resis- at maximum input voltage.
tor, VR, and the primary DC source The maximum power dissipation in
voltage, V DC, for a given conduction the clamp - obtained at the lowest
duty cycle, D, with continuous trans- input voltage ~ can be reduced, at
former magnetizing current is: the expense of a small increase in the
_ D VDC maximum voltage developed across
VR - (I-D) the HEXFET - obtained at the
highest input voltage ~ by sizing the
The required value of the resistor R resistor R so that the magnetizing
is therefore given by: current becomes discontinuous at
R= r D(min) VDC(max) ]2 some intermediate value of line input
voltage. As the input voltage increases
I-D(min) above this level, the peak magnetiz-
ing current stays constant, while the
[V2 L(mag) p(mag)PK + V2 Ls F LPK ] magnetizing current waveform be-
Where D(min) is the minimum full comes progressively more discontin-
load duty cycle, (obtained when V DC uous, and the voltage across the clamp
= V DC(max»' circuit stays constant, because (for a
L(mag) is the transformer magnet- given load current) the energy stored
IZing mductance. in the transformer is constant. Below
I(mag)PK is the peak magnetizing cur- the critical intermediate level of line
rent for just-continuous voltage, the transformer magnetizing
magnetizing current. current becomes continuous, and the
Ls is the leakage inductance clamping voltage rises as the input
of the transformer, referred voltage decreases.
to the primary. As an example of this design
I LPK is the peak full load current approach, assume that the clamp re-
in the transformer primary. sistor is sized to give just-continuous
is the frequency. conduction at 45% of maximum line
voltage. If the minimum duty cycle at
The ratio of the voltage V R across maximum input voltage is 0.15, then
R at any other lower value of primary at maximum input voltage, the peak
DC voltage V DC is: voltage developed across the transis-
~ = I-D(min) tor will be 1.23, instead of 1.18 times
VR(min) 1-[ VDC(max) . D(min)]
V DC
the primary DC source voltage. For a
total range of input voltage variation
of 3 to I, the maximum duty cycle
Considering a specific example, if would be 0.45, and the ratio of the
D . = 015 and VDC(max) maximum to minimum voltage across
(mm)' V DC = 0.3, the clamp resistor would be:
then: VR(max) = 1-(0.15/0.45) = 1.22
1-0.15 VR(min) I - 0.45
I - [(0.15)3] The range of maximum to mini-
mum power loss in the clamp resistor
1.55 at full output power would then be
The losses in the clamping resistor 1.222 = 1.49. Figure 8 illustrates this
at 1/3 of the maximum input voltage specific design example.
(a) 45% VDClmaxl 0 ~ 0.33 VCLAMP oO.225VOCCMAX)
VOLT ·SEes NOW SUFFICIENT =);r~~ voe O.45V OC (MAX)
9:~:::~",
1
-- ------
TRANSFORMER MAGNETIZING CURRENT
~
(b) 0 ~ 0.15 VPK 1.2"VOC (MAX)
___ 1 Voe ACROSS
SWITCH
DEVICE VOLTAGE _~~ (NOTE A)
~
T4
_____ ._ _ --'~~:~;E1~)8VDC(MAX)
Voe Voe (MAX)
TRANSFORMER
MAGNETIZING
CURRENT
"i:!
NOTE A: RSizedtorpnt
-- - - - - .. - - - - conbnuousmagnetJzing
TRANSFORMER MAGNETIZING CURRENT cun-ent al45% maximum
N~OTEA
__ NOTEB Input voltage.
__ -----J__ ~~B~:::~:-
__ _ __ __ _ ___ renl aI max. input voltage.
Figure 8. Idealized Waveforms Showing Opera-
tion when Clamp Resistor is Sized to
Give just Continuous Magnetizing Cur-
rent at 45% Maximum Input Voltage
A-91
Practical Circuit . 85Vinput. Figure I I(a) and (b) shows Figure 14(a) and (b) shows oscillo-
Figure 9 shows a complete diagram corresponding waveforms with 265V grams of HEXFET voltage and cur-
for a 100W, 100kHz, 5V DC output input. rent during turn-OFF for output cur-
circuit, which conforms with the per- Figure 12(a) and (b) shows oscillo- rents of 20A and SA, respectively,
formance specifications shown in grams of HEXFET voltage and cur- with 85V input. Transformer leakage
Table I. Component details are listed rent during turn-ON for output cur- inductance does not significantly ef-
in Table 2. rents of 20A and SA, respectively, fect the fall time of the current,
with 85V input. Note that although because the current in the leakage
Table 2. List of Components for the voltage across the HEXFET falls inductance when switching OFF is
Figure 9 in about 75ns, the rise time of the diverted into the clamping circuit,
HEXFET current with a 20A output and the slow fall time is not "seen" by
QI IRF830 HEXFET is over 300ns. This rather long rise the HEXFET. Figure 15(a) and (b)
IC Silicon General 3526 time is due to leakage inductance, shows corresponding oscillograms
primarily of the transformer, and during turn-OFF, with 265V input.
BI IR 3KCB80 does not reflect the switching speed In Figures II and IS, it can be seen
CI 500j.tF, 450V wkg. of the HEXFET. Figure 13(a) and (b) that with the maximum line input
C2 0.68j.tF, 100V shows corresponding oscillograms for voltage of 265V, the peak voltage
C3 4X 150j.tF, 6V the turn-on interval, with 265V in- developed across the HEXFET at
C4 22j.tF,16V put. The rise time of the current is full load, including the voltage "spike"
C5 O.Sj.tF, 25V wkg. faster, because the higher voltage when switching OFF, is about 440V.
C6 IOnF produces an increased rate-of-rise of This is comfortably within the 500V
C7 910pF current in the circuit inductance. rating of the device.
C8 0.0068 mfd.
C9 0.005j.tF
CIO O.Ij.tF
CII 22j.tF, 25V
RI I.5K (3X500n, 5W)
R2 12n 1/4W
R3 6.8kn 1/4W
R4 IOn
R5 12kn 1/4W
R6 lOon potentiometer
R7 33n 1/4W
R8 560n 1/4W
DI 20FQ030
02 60HQI00
03 IR 40SL6
ZI IN4112 zener diode
Z2 IN4112 zener diode
Z3 4X I N987B zener diodes in
series
LI Pan Magnetics International
E-248 I (Core Arnold
A-930157-2, 16 turns, 2 in
parallel # 14)
TI Pan Magnetics International
E-2478 (Core TOK 26/20.
+12
Primary: 20 turns, 3 in
parallel #32; Secondary: 3
turns, 0.3mm x 0.8cm copper
strip)
T2 Pan Magnetics International
E-2479 (Core TOK H5B2T10-
20-5. Primary: 6 turns #24;
Secondary: 6 turns #24)
T3 Pan Magnetics International
E-2480 (Core TOK H5B2T5-
10-2.5. Primary: I turn;
Secondary: 100 turns #32)

Per10nnance Measurements
Oscillograms for various operating
conditions are shown in Figures 10
through 20. Figure lO(a) and (b)
shows oscillograms of drain voltage Figure 9. Circuit Diagram of 100kHz, 100W Wide Range Power Supply
and drain current for output currents
of 20A and SA, respectively, with a

A-92
 Upper Trace: Drain Current: 5A/division (a) Upper Trace: Drain Current: 1A/division (b)
21's/division 21's/division
Lower Trace: Drain Voltage: 100Vldivision Lower Trace: Drain Voltage: 100V/division
Output Current: 20A OUtput Current: 5A
Figure 10. Oscillograms of Drain Voltage and Current, 85V Line Input

Upper Trace: Drain Current: 5A/division (a) Upper Trace: Drain Current: 1A/division (b)
21's/division 21's/division
Lower Trace: Drain Voltage: 100V/division Lower Trace: Drain Voltage: 100V/division
Output Current: 20A Output Current: 5A
Figure 11. Oscillograms of Drain Voltage and Current, 265V Line Input

Upper Trace: Drain Current: 5Ndivision (a) Upper Trace: Drain Current: 1Ndivision (b)
SOns/division SOns/division
Lower Trace: Drain Voltage: 1OOVId ivision Lower Trace: Drain Voltage: 100V/division
Output Current: 20A Output Current: SA

Figure 12. Oscillograms of Drain Voltage and Current During Turn-On, 8SV Line Input

A-93
 Upper Trace: Drain Current: SA/division Upper Trace: Drain Current: 1A/division (b)
(a)
100ns/division 100ns/division
Lower Trace: Drain Voltage: 100V/division Lower Trace: Drain Voltage: 100V/division
Output Current: 20A Output Current: SA
Figure 13. Oscillograms of Drain Voltage and Current During Turn-On, 26SV Line Input

Upper Trace: Drain Current: SA/division (a) Upper Trace: Drain Current: 1A/division (b)
SOns/division SOns/division
Lower Trace: Drain Voltage: 100V/division Lower Trace: Drain Voltage: 100V/division
Output Current: 20A Output Current: SA
Figure 14. Oscillograms of Drain Current and Voltage During Turn-Off, BSV Line Input

Upper Trace: Drain Current: SA/division Upper Trace: Drain Current: 1A/division
(a) (b)
100ns/division 100ns/division
Lower Trace: Drain Voltage: 100V/division Lower Trace: Drain Voltage: 100V/division
Output Current: 20A Output Current: SA

Figure 15. Oscillograms of Drain Current and Voltage During Turn-Off, 26SV Line Input

A-94
 Figure 16(a) and (b) shows oscillo-
grams of the gate-to-source and
drain-to-source voltages at line input
voltages of 85V and 265V, respec-
tively, with the full load output cur-
rent of 20A, while Figure 17 shows
oscillograms of voltage across the
output rectifiers, D( and D2, with 5A
output current, for input voltages of
85V and 265V. Note that with 265V
input, the voltage across the output
freewheeling rectifier, D2, including
the transient commutation spike, is
about 75V. An experimental 20A,
100V Schottky rectifier was used in
this position. At the time of writing,
this particular device is not yet com-
mercially available; the 60A, 100V-
rated 60HQIOO Schottky rectifier,
though really oversized, is listed in
Table 2, since it is commercially avail-
able. Alternatively, of course, an ap-
propriate 100V fast recovery recti-
fier, such as the 40HFLlOOS02, could
be employed. Note that the peak volt-
age across rectifier D(, including the
commutation "spike", is less than
20V, which means that a 30V-rated
Schottky is adequate.
Figure 18(a) and (b) shows the tran-
sient response of the output voltage
to a step change in output current
from lOA to 20A, and vice versa,
with 85V input, while Figure 19(a)
and (b) shows corresponding oscillo-
grams for 265V input.
Figure 20(a) and (b) shows oscillo-
grams of drain current and drain volt-
age with a short circuit applied at the
output, at input voltages of 85V and
265V, respectively. With 85V input,
the peak HEXFET current is regu-
lated to about 3A, by the automatic
current limiting facility built into the
control circuit, and the correspond-
ing DC output current is just over
20A. With 265V input, however, the
peak HEXFET current is about 7 A,
the short circuit DC output current is
about 55A, and the peak HEXFET
voltage is almost 500V. The lack of
effective current limiting under this
condition is due to the fact that the
control circuit has a minimum ON
conduction time of about 0.8 micro-
seconds, and this is not short enough
to keep the current under control
under short circuit conditions.

Upper Trace: Gate-Source 10Vldivision (a) Upper Trace: Gate-Source 10V/division (b)
Voltage: 21's/division Voltage: 2!is/division
Lower Trace: Drain Voltage: l00V/division Lower Trace: Drain Voltage: 1OOV /division
Line Input: 85V Line Input: 265V
Figure 16. Oscillograms of Gate-Source Voltage and Drain Voltage, 20A Output

I ------
20Y
Voltage across 01: 10Vldivision (a) Voltage across 02:20V/division (b)
21's/division 21's/division
Input: 85V Input: 85V

.......
-
~

r-----
,

-
- - ~ ..-
tOY SOY
Voltage across 01: 10V/division (c) Voltage across 02:50V/division (d)
21's/division 21's/division
Input: 265V Input: 265V

Figure 17. Oscillograms of Voltage Across Output Rectifiers 01 and 02, 5A Output Current

A-95
 Output Voltage: 100mV/division (a) Output Voltage: 100mV/division (b)
50llS/division 50IlS/division
Step Load Step Load
Change: 10Ato 20A Change: 20A to 10A

Figure 18. Oscillograms of DC Output Voltage During Step Change of Output Load Current, 85V Line Input

Output Voltage: 100mVldivision (a) Output Voltage: 100mV/division (b)

50IlS/division 50lls/division
Step Load Step Load
Change: 10A t020A Change: 20A to 10A

Figure 19. Oscillograms of DC Output Voltage During Step Change of Output Load Current, 265V Line Input

Upper Trace:' Drain Current: 5A/division (a) Upper Trace: Drain Current: 5A/division (b)
2lls/division 2lls/division
Lower Trace: Drain Voltage: 100V/division Lower Trace: Drain Voltage: 100V/division
Line Input: 85V Line Input: 265V

Figure 20. Oscillograms of Drain Voltage and Current with Short Circuit at Output

A-96
 Attention should be paid to this
point in a production design. A solu-
tion could be to add a circuit that
clam ps the "soft start" terminal of the
control circuit to ground when the
output current exceeds a predeter-
mined level, thereby switching OFF
the power supply. Resetting would
be done manually once the fault con-
dition has cleared. While this design
aspect certainly needs consideration,
it is of interest to see that the circuit
continues to operate satisfactorily,
albeit under high stress, with a short
circuit output current close to 3X the
ra ted val ue.
Generally, our objective has been to
demonstrate the feasibility of the
basic circuit concepts described, and
we have not paid particular attention
to design details that can be handled
in a rather routine manner, accord-
ing to the particular requirements of
the designer. In this vein, we have
taken for granted that l5V DC is
available to supply the control cir-
cuit. This auxiliary DC supply could
be derived from a small line fre-
quency transformer with a rectifier
and a relatively coarse voltage regu-
lator. A 12V to 16V range ofregula-
tion would be quite satisfactory.
Current consumption of the control
circuit is 50mA maximum, which
eq uates to a total power dissipation
in this auxiliary power supply circuit
of a little over 2W at maximum input
voltage, and less than I W at mini-
mum input voltage.
Power Losses and Overall Efficiency
Table 3 shows the power dissipa-
tion in the various individual com-
ponents of the circuit, as well as the
overall efficiency, for various levels
of output power, at input voltages of
90V and 260V. This data has been
obtained through a combination of
measurement and estimation.
The DC power delivered from the
input bridge rectifier, and the DC
output power, are measured directly,
and the overall loss in the intervening
circuitry is derived from the differ-
ence of these two measurements. The
loss in the input rectifier, the HEX-
FET, the output rectifier, and an
assumed auxiliary DC control power
supply, fed from the input line
through a transformer (as discussed
above), are estimated individually
from a knowledge of the operating
voltage and currents for these com-
ponents. The loss in the clamp circuit
is calculated from the measured volt-
age across the clam p resistor; and the
power loss in the output transformer
and filter choke is taken as the differ-
ence between the total power dissipa-
tion, and the sum of the losses in the
other components.
The overall full load efficiency ar-
rived at in this way is 76% at 265V
input, and 74% at 85V input. It should
be added that an EMI filter, required
in a practical system, but not included
here, would reduce the overall effi-
ciency slightly from the values shown
here.
'Wide Range" Versus "Dual Range"
A point of contention may have
arisen in the mind of the astute
reader. This is that it is a usual design
requirement to maintain rated DC
output voltage during loss of the
input line voltage for one cycle. In
order to do this, the input reservoir
capacitor, C, in Figure 9, must be
sized to supply the required energy to
the output, while its voltage must not
deplete below a level at which control
of the output voltage can be main-
tained. If this capacitor is sized to
supply the required energy when op-
erating from a 115V input, as it should
be, it will then be grossly oversized
for operation from a 240V input, and
most likely will be larger and more
expensive than the capacitance re-
quired by a conventional power
supply.
A conventional "dual voltage"
power supply can operate either from
115V or 240V input, by means of
switching from a voltage doubler cir-
cuit when operating at 115V, toa full
rectifier bridge circuit when operat-
ing at 240V, with the two "doubler"
capacitors then connected directly in
series across the output of the bridge.
Substantially the same primary DC
source voltage is thereby maintained
for both AC input voltage levels.
Taking the specific case of a lOOW
supply, the choice would then typi-
cally be between the single 500MF
450V capacitor, shown in Figure
21(a), for the wide range power sup-
ply, versus two 600MF 200V capaci-
tors, shown in Figure 21(b), for the
"dual voltage" supply. The single
capacitor in Figure 21(a) has approx-
imately 30% more volume than the
combined volume of the two capaci-
tors shown in Figure 20(b); the cost
differential is about II %, or $0.60
extra for the capacitor for the wide
range power supply. This could be
more than compensated for by the
fact that the additional complication
of switching from a doubler to a
bridge configuration is eliminated, to
say nothing of the functional conven-
ience of not having to make any
adjustments when operating from
115V or 240V input.
A quite different aspect is that if the
wide regulation capability of the cir-
cuit is utilized only under the short-
term condition of loss of input line
voltage for one cycle, then a drastic
reduction in the size of the input
reservoir capacitance can be made.
This is because the voltage across this
capacitor can then be allowed to
"drift" all the way from, say, 3lOV
down to 120V, during the one-cycle
"outage" period.

Table 3. Power Losses and Overall Efficiency Under Various Operating Conditions
Estimated
Estimated Power Estimated Estimated
Power Estimated Power Loss in Power Power
Line DC Total Loss in Power Loss in Transformer Loss in Loss in
Input Output Power Power Input Loss in Clamp and Filter Output Control Overall
Voltage Voltage Output Loss Rectifier HEXFET Circuit Choke Rectifier Circuit Efficiency
V V W W W W W W W w %
90 5.0 97.26 34.09 4 8.0 2.99 2.7 15.5 0.9 74
5.0 73.11 24.4 3 4.6 2.60 2.4 10.9 0.9 75
5.0 48.81 15.94 2 2.3 2.24 1.5 7.0 0.9 75
5.0 24.40 9.3 I 0.8 2.02 1.28 3.3 0.9 72
260 5.0 96.96 30.22 1.3 5.4 2.02 3.3 15.5 2.7 76
5.0 72.81 22.74 1.0 3.7 1.54 2.9 10.9 2.7 76
5.0 48.66 16.69 0.7 2.3 1.29 2.7 7.0 2.7 74
5.0 24.35 10.98 0.4 1.1 1.18 2.3 3.3 2.7 69

A-97
 Capacitor required for wide range
power supply when designed to
operate from 115V and 240V inputs
without modification.
Capacitor Required: 1 X 500jlF, 450V
Total Volume: 14.72 cubic inch
Typical Cost: $6.50
Figure 21. Input Reservoir Capacitors Required for Various Alternative Designs
With this design approach, it would
be necessary to switch from a voltage
doubler circuit to a bridge circuit
when operating from 115V and 240V
inputs, respectively, but the size of
the required input capacitors would
be reduced as shown in Figure 21(c).
The volume ofthese capacitors isjust
under 50% of the volume of the
capacitors required for a conven-
Capacitors required for power supply
with facility for switching from
"voltage doubler" to bridge con-
figurationsfor115V and 240V inputs,
respectively.
Capacitor Required: 2 X 600jlF, 200V
Total Volume: 11.49 cubic inch
Typical Cost: $5.88
tional "dual voltage" power supply,
and the cost is approximately 45%-
an absolute saving in the region of
$3.00.
Conclusions
In order to get the most out of a
power HEXFET, it is necessary to
rethink basic concepts, and to design
A-98
Capacitors required for wide range
power supply when used with facility
for switching from "voltage doubler"
to bridge configurations for 115V
and 240V inputs, respectively.
Capacitor Required: 2 X 200jlF, 200V
Total Volume: 5.23 cubic inch
Typical Cost: $2.64
the circuitry to take maximum ad-
vantage of the special operating fea-
tures of the device. An illustration of
this basic precept is the 100kHz,
100W "universal" switching power
supply described in this article. The
circuit uses a single 500V-rated HEX-
FET to provide a regulated 5V DC
output, over the entire range of line
input voltage from 85V to 265V. 0
 CHAPTER 11
APPLICATION NOTE 941A

A Chopper for Motor Speed Control

Using Parallel Connected Power HEXFETs
By S. CLEMENTE, B. PELL Y

Summary
Today's MOSFETs are rated at
currents as high as 28A continuous
and 70A peak, at I OOV. They are eas-
ily parallelable for higher current
operation, and are attractive candi-
dates for controlling the speed of
electric motors at currents up to sev-
eral hundred amperes.
This application note demonstrates
an experimental DC to DC chopper
circuit using parallel connected power
MOSFETs, for speed control of a
separately excited DC motor. The
circuit operates from a 48V battery,
and provides "two-quadrant" opera-
tion, with maximum motoring and
regenerating currents of 200A and
140A, respectively.
In this application note, we demon-
strate the technical feasibility of a
chopper circuit using parallel con-
nected HEXFETs to provide a 200A,
48V output for motor speed control.
A particular feature of the circuit is
its facility for providing electrical
braking of the motor by feeding elec-
trical energy back to the DC source.
This is accomplished through the use
of the integral body-drain diode of
the HEXFET, which acts as a circuit
component in its own right, and pro-
vides the "freewheeling" and "fly-
back" functions for the "motoring"
and "regenerating" modes.
The Power HEXFET
The basic structure of a HEXFET
is illustrated in Figure I, and the elec-
trical symbol is shown in Figure 2.
Current flows from the drain region
vertically through the silicon, then
horizontally through the channel,
then vertically out through the source.
The HEXFET design is based upon
vertical D-MOS technology. The
closed hexagonal cellular structure
with the buried silicon gate allow for
optimum utilization of silicon, and
yield a rugged, highly reliable device.
A feature of the HEXFET (actu-
ally, of all power MOSFETs) is that
it inherently has built into it an inte-
gral reverse "body-drain" diode. The
full electrical symbol for the power
MOSFETinciudes the reverse paral-
lel rectifier shown dashed in Figure 2.

Introduction
Efficient speed control of DC mo-
tors operating from DC supplies is
today accomplished with switching
chopper circuits using forced com-
mutated thyristors or bipolar transis-
tors. Battery operated systems rated
at hundreds of amperes are in com-
mon use in forklift truck and electri-
cal vehicle controllers. Larger thyris-
tor choppers rated at thousands of
amperes, at DC voltages up to 1500V,
are in use in high power railway trac-
tion applications.
In this type of application power
MOSFETs would offer some advant-
ages, like very high gain, very rugged
performance, and very fast switching
speed. The power MOSFET lends it- DRAIN DRAIN
"TRANSISTOR" "TRANSISTOR"
self readily to paralleling (providing CURRENT CURRENT
the proper precautions are observed), DIODE CURRENT
and a power MOSFET chopper op-
erating at currents of several hundred Figure 1. Basic HEXFET Structure
amperes is technically within grasp.

A-99
 tion is such that the voltage across I V change of voltage on the gate. The
the switching device never changes transconductance of the IRFI50
DRAIN polarity, and the forward conduction HEXFET is typically 10 amps per
characteristic of the body-drain diode volt.

J
never comes into play. This is the Another important advantage is

Ii ,~';.
GATE~
_____ ....l
SOURCE
Figure 2. Electrical Symbol for
PowerHEXFET (MOSFET)
including the Body-Drain
Diode
The existence of this integral reverse
rectifier is explained by reference to
Figure I. Current is free to flow
through the middle of each source
cell across a forward-biased P-N junc-
tion, and out of the drain. The path.
for this "reverse" current flow is at
least comparable in cross-section to
that of the "forward" current "tran-
sistor" channel. Far from being an
inconsequential "parasitic" compon-
ent, the integral reverse body-drain
diode is therefore a real circuit ele-
ment, with a current handling capa-
bility as high as that of the transistor.
The integral reverse body-drain di-
ode mayor may not be important in a
practical circuit. In some circuits, it is
irrelevant, because the circuit opera-
case, for example, in a simple DC to
DC chopper circuit for motor con-
trol which is not configured for re-
generative energy flow, and in which
the motor voltage never exceeds the
i
source voltage.
A DC to DC chopper circuit for
motor speed control that provides
a regenerative braking capability
would, however, require rectifiers to
be connected across the switching
devices, and in this case, the reverse
body-drain diode of the HEXFET
can be used for this purpose, and, in
fact, eliminates the need for addi-
tional discrete rectifiers.
Potential Advantages of Power HEX-
FETs for Motor Drives
The power HEXFET has several
unique features which make it a
potentially attractive switching com-
ponent for a chopper drive. These
features are briefly discussed below:
High Gain
The HEXFET is a voltage driven
device. The gate is isolated electri-
cally from the source by a layer of
silicon oxide. The gate draws only
minute leakage current, in the order
of nanoam peres, and the DC gain -
in the conventional sense used for a
bipolar transistor is rather meaning-
less. A more useful parameter is the
transconductance. This is the change
of drain current brought about by a
that, unlike the bipolar transistor,
the gain of the HEXFET does not
decrease with increasing current. This
means that the HEXFET is able to
handle high peak current, without
showing the bi polar transistor's ten-
dency to "pull out of saturation."
Typical relationships between gate-
to-source voltage and drain current
are shown in Figure 3.
Because the gain of the HEXFET is
very high, the drive circuitry required
is relatively simple. It should be clear-
ly recognized, however, that although
the gate consumes virtually no cur-
rent under "steady" conditions, this
is not so under transitional switching
conditions. The gate-to-source and
gate-to-drain self-capacitances must
be charged and discharged approp-
riately to obtain the desired switch-
ing speed, and the drive circuit must
have a sufficiently low output impe-
dance to supply the required charg-
ing and discharging current. Even
once these requirements have been
catered for, the fact remains that the
drive circuitry required for a HEX-
FET is considerably simpler than
that required for a bipolar transistor.
Ruggedness
One of the outstanding features of
the HEXFET is that it does not dis-
play the second breakdown pheno-
menon of the bipolar transistor, and
as a result, it has an extremely rugged
switching performance.

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A-100
 A simple physical explanation ac-
counts for this superiority. If local-
ized, potentially destructive heating
occurs within a HEXFET, the carrier
mobility in that area decreases. As a
result, the device has a positive tem-
perature coefficient and acts in a self-
protective manner by forcing cur-
rents to be uniformly distributed
throughout the silicon. The safe oper-
ating area of the IRFl50 HEXFET is
shown as an example in Figure 4.
Note that the safe operating area for
IOJts is fully rectangular; this means,
in principle, that it is possible to
switch 70A at IOOV in this device. As
a matter of good design practice, of
course, one would not operate at this
limit.
The absence of second breakdown
is, of course, important for this type
of application.
Ease of Paralleling
Power HEXFETs are, in principle,
easy to parallel, because the positive
temperature coefficient forces current
sharing among parallel devices. They
therefore lend themselves well to the
construction of a chopper rated at
several hundred amperes, and the
problems of paralleling will be much
less than those associated with bipo-
lar transistors.
A Basic HEXFET Two-Quadrant
Chopper Circuit
Figure 5 shows the basic circuit of a
DC to DC chopper that provides con-
tinuous speed control in the "motor-
ing" mode of operation (i.e., with the
motor receiving power from the DC
source), and also provides the facility
for the motor to return regenerative
energy to the DC source, over the
whole speed range. Idealized wave-
forms that describe the o!1tration are
shown in Figure 6, while Figure 7
defines the two operating quadrants
of the circuit developed.
VOLTAGE

....
I
-----,
HEXFETI

I REGENERATING MOTORING

~--~_rl.,
I I
I
A Figure 7. Motoring and Regenerat-
ing Operating Quadrants
I I for the Circuit of Figure 5
I -
==+ I

L----1Jj
HEXFET2
I I r-----.,
DC •
SUPPLy.....L
i In the "motoring" mode of opera-
tion, HEXFET I is switched ON and
V OFF, at an appropriate repetition
IL _ _ _ _ ....JI E rate, and provides control of the
average voltage applied to the motor.
HEXFET 2 is OFF, but its integral
reverse body-drain diode acts as the
B conventional freewheeling rectifier
and carries the freewheeling motor
Figure 5. Basic Two Quadrant Chopper Circuit USing HEXFETs current during the periods when
HEXFET I is OFF. When the motor
is required to act as a generator and
return energy to the DC source,
HEXFET 2 is chopped ON and OFF,
--VOLTAGEA-B
_ _ _ MOTOR emf E and controls the current fed back

nTrnT. ROO~
from the motor to the supply. In this
operating mode, HEXFET I is OFF,
but its integral reverse rectifier car-

1 -- i --
• - v
-- i --
LJ!Ill ries the motor current back to the DC
source during the intervals when
HEXFET 2 is OFF.
~--- MOTORING In order for the motor to "regener-
CURRENT MOTOR ate," it is necessary for it to have
- - - - - - - - - REGEN~RATING - - - - - - - - - CURRENT either a shunt or a separately excited
CURrNT -~ field. A series-connected field is not
feasible, unless the connections to it
are reversed for the regenerative mode
TRANSISTOR
CURRENT
of operation, which is not practically
REctiFIER 1-- n-- r- ~~~N~ convenient.
The major objectives of this appli-
CURRENT L.-J L--J
cation note are to demonstrate the
I
TRANSISTOR ,...., r-1
feasibility of operating a group of
parallel connected HEXFETs at cur-
CUR~ENT -L _L-L _I EX
HCU RFRETENT2 rents in the order of hundreds of
RECTIFIER amperes, and of using the reverse
CURRENT
body-drain diode of the HEXFETas
•
Figure 6. Idealized Operating Waveforms for Figure 5
a circuit element in its own right, in
the basic two quadrant chopper cir-
cuits shown in Figure 5.
To achieve these objectives, it is

A-101
necessary to consider certain detailed
aspects of the operation of the HEX-
FETs. We do this in the following
section.
Use of the HEXFETs Body-Drain
Diode
An important consideration when
using the HEXFET's integral body-
drain diode is its reverse recovery
characteristic. This rectifier is a con-
ventional P-N junction device, and
therefore it exhibits a classical reverse
recovery charge. That is to say, when
the rectifier switches 0 FF, the cur-
rent through it reverses for a short
period, as illustrated in Figure 8.
25%
I......
I, ••:ur
Figure 8. Rectifier Reverse Recovery
'1 he reverse recovery time depends
upon the operating conditions. For
(a) PERIOD"
+ +
HEXFETj
HEXFETj
'"
(e) PERIODS t" AND 10
+
I,
J ~
J '"
Figure 9. Commutation of Freewheeling Current 1M from the
Rectifier of HEXFET 2 to the Transistor Of HEXFET
1. HEXFET 1 and HEXFET 2 form a Tandem Series
Connected Pair across a DC source.
the IRFl50 HEXFET, rated 28A
continuous at 100V (the type used
here), the reverse recovery time is
about 400ns at maximum operating
temperature, and about 260ns at
25° C, for an initial peak forward cur-
rent of 70A, and a di/dt of looA/ J.Ls.
Reverse recovery presents a poten-
tial problem when switching any rec-
tifier OFF. The slower the rectifier,
the greater the problem. Although
the HEXFET's body-drain diode is
relatively fast - not as fast as the
fastest discrete rectifiers available,
but considerably faster than com-
parably rated general purpose recti-
fiers - by comparison with the HEX-
FET itself, it is rather slow. This
presents a potential problem in a
chopper circuit, as we will now see.
!
RECTIFIER
FORWARD
To illustrate the problem, we will
consider the motoring mode of oper-
ation. The operating condition that is
troublesome is when freewheeling
~~~~'~~R
REVERSE
0
current is commutated from the
RECOVERY
body-drain diode of HEXFET 2 to
ENT the transistor of HEXFET 1. The
operating sequence is depicted in
Figure 9; the theoretical operating
waveforms are shown in Figure 10.
Throughout the commutating se-
quence which, of course, is short by
comparison with the overall funda-
mental operating cycle of the circuit,
a constant current, 1M , is assumed to
flow through the motor. During the
operating period, to, the current, 1M ,
(b) PERIOD I,
HEXFET~ : ri"1
0---*--- -----.
t
I...
~I
I•••
~
I I
HEXF~ --!_--J_
'"
(d)PERIODI:z
+
II '
o ----~ - - RecTiFIER
~
~
0'" - - - -P"""----
~ -.~J
Figure 10. Theoretical Voltage and Current Waveforms
for CommutatinR SeQuence Depicted in
Figure 9.
A-102
is freewheeling through the rectifier
of HEXFET 2. At the start of the
operating period, t l, HEXFET 1 is
turned ON, and the load current
starts to transfer to the transistor of
HEXFET I. The current, i" in HEX-
FET I increases, while the current, i2,
flowing in the rectifier of HEXFET 2
decreases. The sum of i l and i2 is
equal to 1M , At the end of period t l,
the current flowing in HEXFET I is
equal to the motor current, 1M , and
the current flowing in the rectifier of
HEXFET 2 is instantaneously zero.
Note that during period tl (also
during the subsequent period tal, the
voltage across HEXFET I theoreti-
cally is virtually the full source volt-
age. This is because, as long as the
rectifier of HEXFET 2 remains con-
ducting, the voltage across it can be
only its conduction voltage; the dif-
ference between this relatively small
voltage and the total source voltage is
developed across HEXFET 1.
This ignores the effect of circuit
inductance. In practice, some of the
source voltage will be dropped across
circuit inductance, and the voltage
across HEXFET I will be less than
the source voltage, by the voltage
drop across this inductance. A typi-
cal voltage across HEXFET I that
takes account of the voltage drop
across circuit inductance is repres-
ented by the dashed wave in Figure
10.
WITH CIRCUIT
INDUCTANCE
(8) VOLTAGE
ACROSS
HEXFET·l
II ~ (b) CURRENT
IN TRANSISTOR
OF HEXFET 1
I.
-I ~ 1,- - ~IT~
';;IRCUIT
: • INDUCTANCE
~
i • (e) VOLTAGE
:
: E
l ACROSS
HEXFET 2
REVERSE
RECOVERY
(d) CURRENT
IN RECTIFIER
OF HEXFET 2
 If the rectifier was "perfect," with
no recovered charge, the commuta-
tion process would be complete at the
end of period t l . In practice, the recti-
fier current reverses during the re-
covery periods ta and tb' During the
period t a , the reverse current i2 in-
creases until it reaches its peak value,
IRMJrill.:. The current, ii' through
HEXFET I is now the sum of the
rectifier reverse current, i2, and the
motor current, 1M, and its peak value,
IMAX, is the sum of 1M and IRM(recl'
The voltage across HEXFET I sti I
theoretically remains high, because
the voltage across the rectifier of
HEXFET 2 is still relatively low.
During the second part of the re-
covery period t b, the rectifier of
HEXFET 2 begins to support reverse
voltage. The rectifier recovery cur-
rent i2 decreases, and the voltage
across HEXFET I falls to its final
conduction level. Note the effect that
circuit inductance has in producing
an overvoltage transient across the
rectifier, as illustrated by the dashed
wave in Figure 10.
Certain important points are evi-
dent. First, t" ta, and to a lesser
extent, t b, are high dissipation peri-
ods. Second, the peak current in
HEXFET I is the sum of the motor
current and the rectifier reverse re-
covery current, and this peak current
occurs at an instant when the voltage
across the HEXFET is high. It is
important that this peak current does
not violate the HEXFET's 10M rat-
ing. In fact, if the HEXFET is
switched at a speed close to its limit-
ing capability, and no other special
precautions are taken, it certainly
will do. If the peak current was to
substantially exceed this rating, diode
failure could occur, as explained in
Ref. I.
Fundamentally, the peak reverse re-
covery current of the rectifier can be
reduced only by slowing down the
rate of change of current during the
FORWARD
RECTIFIER
CURRENT
~"""""'::::::~7"'-:::;<:=:::z==:j:b- - 0
REVERSE
RECTIFIER
CURRENT
t switching transitions, the current in a
Figure 11. Reducing the Peak Recti-
fier Reverse Current by
Reducing the Rate of
Change of Current
commutation process. This is illus-
trated in Figure II. The rate of
change of current can be controlled
either by inserting inductance into
the circuit, or by purposefully slow-
ing down the rate-of-rise of the gate
pulse that drives HEXFET I. A lin-
ear inductor inserted in the circuit for
the purpose of slowing down the rate
of change of current when the HEX-
FET is switched ON is not attractive,
because it produces a transient volt-
age spike when switching OFF, to
say nothing of the fact that it is an
added "power circuit" component.
The better practical solution is sim-
ply to slow down the switching-ON of
the HEXFET by slowing down the
drive signal. The peak current carried
by the HEXFET can be reduced to
almost any desired extent, at the
expense of prolonging the high dissi-
pation period. This is a necessary
compromise in order to keep the peak
current within safe limits, and as a
practical matter, the switching losses,
when averaged over the full operat-
ing cycle, are relatively small, for the
operating frequencies that will be of
interest in this application (normally
a few hundred to a few thousand Hz).
Note that it is not necessary (nor
desirable) to slow the switching-OFF;
hence, the energy dissipation at
switch-OFF will be relatively small
by comparison with that at switch-
ON. As explained in detail in Ref. I,
in this application a substantial dv / dt
is likely to be applied across the
HEXFET that acts as a diode during
its reverse recovery. Since the device
is sensitive to dv/ dt at that time, a
snubber should be added between
drain and source, as shown in Figure
21.
Paralleling of HEXFETs
A key question that is fundamental
to the successful demonstration of a
chopper operating at hundreds of
amperes, is the feasibility of multiple
paralleling of HEXFETs.
Two questions must be considered:
(I) "steady-state" sharing of current,
and (2) dynamic sharing of current
under the transitional switching con-
ditions.
Steady-state Sharing of Current
During the periods outside of the
parallel group of HEXFETs will dis-
tribute itself in the individual devices
in inverse proportion to their ON res-
istance. The device with the lowest
ON resistance will carry the highest
current. This will, to an extent, be
self-compensating, because the power
loss in this device will be the highest.
A-103
It will run hottest, and the increase in
ON resistance due to heating will be
more than that of the other devices,
which will tend to equalize the cur-
rent.
An analysis of the "worst case"
device current in a group of "N"
parallel connected devices can be
based on the simplifying assumption
that (N - I) devices have the highest
limiting value of ON resistance, while
just one lone device has the lowest
[N-1] HEXFETS
I IN PARALLEL,
• ~OT ALL WITH Rma.
...-------, I
lA
Figure 12. Simplified Equivalent
Circuit for Estimating
Worst Case Steady-State
Current Unbalance
limiting value of ON resistance. The
analysis can then be concentrated on
the current in this one device.
The equivalent electrical circuit
shown in Figure 12 simplifies the
analysis further by assuming the num-
ber of devices is sufficiently large that
the current that flows through each
of the high resistance devices is ap-
proximately hOT/IN. I)' On this as-
sumption, the vo tage drop across
the lone low resistance device, and
hence the current in it, can be calcu-
lated.
The ON resistance of each of the
"high resistance" devices, at operat-
ing temperature, T, is given by:
R(max)T =R(max)25 (I + [(T A - 25)
+ I~OT ]
(N _ 1)2 R(max)T RJA K)
where ~max)25 is the limiting max-
imum value of ON resistance at 25° C,
RJA is the total junction-to-ambient
thermal resistance in deg. C/ W, and
K is the per unit change of ON resist-
ance per °C.
:. R(max)T =
R(maxl25 (I + [TA - 25] K)
(I)
I - R(max)25 14roT RJA K
(N-I)2
The voltage drop, V, across the
parallel group is:
V l TOT • R
= (N - I) (max)T (2)
 The resistance of the one low resist- Using the relationships (I), (2), and ent events that occur during a switch-
ance device at its operating tempera- (3) above, it can be calculated that ing transition.
ture is: the "worst case" maximum value of The problem will be introduced by
R(min)T = Rlmin)25 (I + [TA - 25 + device current is 27 A for the hypo- considering the switching waveforms
VI(ID.X) R JA ] K) thetical situation where all devices for the basic chopper circuit, shown
but one have high limiting ON resist- in Figure 5, which contains a single
where R(min)25 is the limiting min- ance, of 0.0450., and carry 20A each, HEXFET in each of the "motoring"
imum value of ON resistance at 25° C, whereas the remaining one has low and "regenerating" positions. We will
and I(m.x) is the current in this device. limiting ON resistance of 0.030.. consider the motoring mode of oper-
V ation, under which HEXFET I is
But, ~min)T = -1-- switched ON and OFF, while the
(m.x) r-:-:-:---:--=:::- Dynamic Sharing of Current Under motor current (assumed to be smooth,
:. I
(max)
= -b + V(b2 + 4aV) (3)
2a
Switching Conditions due to the motor inductance) alter-
Tum-On nates between this HEXFET and the
where: It is necessary to take positive steps body-drain diode of HEXFET 2,
b = ~min)25 (l + [TA - 25] K) to ensure that the current is distrib- which acts as a freewheeling rectifier.
a = ~min)25 V RJA K uted properly between a group of Figure 13 shows waveforms of drain
parallel connected devices during the current, drain-to-source voltage, and
The following example shows the gate voltage during the turn-ON in-
"worst case" degree of current shar- switching transition. Since the HEX-
FETs will not all have identical terval. We have already seen that in
ing that can be expected, by applying order to limit the peak recovery cur-
the above relationships to the IRFI50 threshold and gain characteristics,
some will tend to switch sooner than rent of the body diode of HEXFET 2,
HEXFET, and making the following the gate drive voltage for HEXFET I
assumptions: others, and attempt to take more
than their share of the current. Add- must be applied at a controlled rate.
~m.x)25 = 0.0450. ing to the problem is the fact that This is the reason that the applied
R(min)25 = 0.030. circuit inductance associated with drive pulse is shown increasing at a
each device may be different, and this relatively slow rate.
RJA =3 deg. C/W will also contribute to unbalancing At time, to, the drive pulse starts its
lTOT =20A the current under switching condi- rise. At t" it reaches the threshold
(N - I) tions. A detailed analysis of these voltage of the HEXFET, and the
waveforms can be found in Ref. 2. drain current starts to increase. At
K = 0.006 per degree C Here we will limit ourselves to a brief this point, two things happen which
TA = 35°C qualitative description of the differ- make the gate-source voltage wave-

DRAIN-SOUACE
VOlTAGE

VOLTAGE DROP ACROSS

DRAIN CURRENT ~ THIS L MEANS THAT THE +
DRAIN v~~-r:.~-riN~ ~
DISCHARGE OF
THIS CAPACITOR
RESULTlNG IN ~
MORE CURRENT r - - --
THROUGH THIS J.
RESISTANCE .,..

--4. !

< I I I
to " " ---THIS INDUCED VOLTAGE
SUBTRACTS FROM THE
MOPEN CIRCUIr DRIVE CIRCUIT - lis DRIVE VOLTAGE
DRIVE PULSE RESISTANCE
J - - - -.... / . RESULTlNG IN

RESULTlNG IN ________

SLOW RISE OF Is

DRIVE CIRCUIT

Figure 14. Diagrammatic Representation of Effects When

Figure 13. Waveforms at Turn-ON - Single HEXFET Switching-ON

A-104
 form deviate from its original "path."
First, inductance in series with the
source which is common to the gate
circuit develops an induced voltage,
as a result of the increasing source
current. This voltage counteracts the
applied gate drive voltage and slows
down the rate-of-rise of voltage ap-
pearing directly across the gate and
source terminals; this, in turn, slows
down the rate-of-rise of the source
current. This is a negative feedback
effect; increasing current in the source
produces a counteractive voltage at
the gate, which tends to resist the
change of current.
The second factor that influences
the gate-source voltage is the so-
called "Miller" effect. During the
period tl to t 2 , some voltage is
dropped across circuit inductance in
series with the drain, and the drain-
source voltage starts to fall. The
decreasing drain-source voltage is
reflected across the drain-gate capac-
itance, pulling a discharge current
through it, and increasing the effec-
tive capacitance load on the drive cir-
cuit. This, in turn, increases the volt-
age drop across the im pedance of the
drive circuit and decreases the rate-
of-rise of voltage appearing between
the gate and source terminals. This
also is a negative feedback effect;
increasing current in the drain results
in a fall of drain-to-source voltage,
which, in turn, slows down the rise of
gate-source voltage and tends to re-
sist the increase of drain current.
These effects are illustrated diagram-
matically in Figure 14.
This state of affairs continues
throughout the period tl to t 2 , while
the current in the HEXFET rises to
the level of the current, 1M , already
flowing in the freewheeling rectifier,
and it continues into the next period,
~ to t3 , while the current increases
further, due to the reverse recovery of
the freewheeling rectifier.
At time t3 , the freewheeling rectifier
starts to support voltage, while the
drain current and the drain voltage
start to fall. The rate-of-fall of drain
voltage is now governed by the Miller
effect, and an equilibrium condition
is reached, under which the drain
voltage falls at just the rate necessary
for the voltage between gate and
source terminals to satisfy the level of
drain current established by the load.
This is why the gate-to-source volt-
age falls as the recovery current of the
freewheeling rectifier falls, then stays
constant at a level corresponding to
the motor current, while the drain
voltage is falling.
Finally, at time t4 , the HEXFET is
switched fully ON, and the gate-to-
source voltage rises rapidly towards
DRAIN-SOURCE
VOLTAGE _ _
G-SVOlTAGE
,",__-""""III\JTI
I
1
"OPEN CIRCUIT
DRIVE PULSE \
__ - \_.----.:--'1""""""_
II
to 11
Figure 15. Waveforms at TURN-OFF -
the applied "open circuit" value.
The gate-to-source voltage wave-
form for the circuit shown in Figure
5, with just a single device in each
position, provides the clue to the dif-
ficulties that can be expected with
parallel connected devices. The first
potential difficulty is that if we apply
a common drive signal to all gates in
a parallel group, then the first device
to turn ON - the one with the lowest
threshold voltage - will tend to slow
the rise of voltage on the gates of the
others, and further delay the turn-
ON of these devices. This will be due
to the Miller effect. The inductive
feedback effect, on the other hand,
only influences the gate voltage of its
own device (assuming that each source
has its own separate inductance).
The second potential difficulty is
that if the individual source induc-
tances are unequal, then this will
result in dynamic unbalance of cur-
rent, even if the devices themselves
are perfectly matched. Obviously,
the solution to this is to ensure that
inductances associated with the indi-
vidual devices are as nearly equal as
possible. This can be done by proper
attention to the circuit layout.
As examined in detail in Ref. 3,
there are several other circuit and
device parameters that will contri-
bute to dynamic unbalance. The con-
clusions presented in the above men-
tioned paper indicate, however, that
the problem is not severe, as long as
attention is paid to the following
points, in order to ensure satisfactory
sharing of current between parallel
A-105
I
GATE VOlTAGE
:--r-
GMNG I
VTh
I Il
12 13
Single HEXFET
HEXFETs at turn-ON:
• Threshold voltages should be
within determined limits.
• Stray inductances throughout the
circuit should be equalized by
careful layout.
• Gates should be decoupled with
individ ual resistors, but not more
than strictly required, as it will be
explained later.
Tum-Off
Similar considerations apply to the
dynamic sharing of current during
the turn-OFF interval. Figure 15
shows theoretical waveforms for
HEXFET I in the circuit of Figure 3
during the turn-OFF interval. At to,
the gate drive starts to fall. At t l , the
gate voltage reaches a level that just
sustains the drain current, I. The
drain-to-source voltage now starts to
rise. The Miller effect governs the
rate-of-rise of drain voltage and holds
the gate-to-source voltage at a level
corresponding to the constant drain
current. At t3 , the rise of drain vol-
tage is complete, and the gate voltage
starts to fall at a rate determined by
the gate-source circuit impedance,
while the drain current falls to zero.
Figure 16 shows theoretical wave-
forms for two parallel connected
HEXFETs with their gates connected
directly together. For purposes of
discussion, the source inductance is
assumed to be zero. At t l , the gate
voltage reaches the point at which
HEXFET B can no longer sustain its
drain current. The load current now
 pares the motor voltage with a refer-
ence voltage and processes the result-
DRAlN-SOURCE
ing "error" signal to keep the motor
VOLTAGE -. voltage essentially equal to the refer-
ence value. In a practical system, the
voltage control loop could be com-
plemented with a signal proportional
___ CURRENT IN
to the armature voltage drop, to give
HElIFET .. a closer regulation of actual motor
_. ____ CURRENT .. speed. Alternatively, the voltage feed-
HEXFETB back signal could be substituted with
a signal from a tachogenerator, to
give a more precise speed regulation.
.I IiI: An inner control loop regulates the
current to the level required to satisfy
~ _ GATE VOLTAGE FOR
". the load on the motor. The current
I

I 1'1 HElCFET B GIVING 112

"OPEN CIRCUIT
I~.t--~I"-r_I_HE_XFET_v:"
k~
D~~~ +~_.I _.
I .
DANE CIRCUIT
Figure 16. Waveforms at Turn-OFF - Two HEXFETs with Common Gates and
Common Sources
redistributes; current in HEXFET B
decreases, while that in HEXFET A
increases. At t2 , HEXFET B can no
longer sustain its current; both HEX-
FETs now operate in their "linear"
region, and the drain voltage starts to
rise. The gate-to-source voltage is
kept practically constant by the Mil-
ler effect, while the currents in the
two HEXFETs remain at their sep-
arate levels. Clearly, the unbalance of
current in this example is significant.
While a turn-off unbalance is poten-
tially a more serious problem, the
analysis in Ref. 3 shows that this is
not so in practice as long as the devi-
ces are turned off with a "hard"(very
low impedance) gate drive. This by
itself wiJI almost guarantee limited
dynamic unbalance at turn-off.
In summary, to achieve good shar-
ing at turn-off the same precautions
should be used as for turn-on, with
the addition of a "hard" drive.
Figure 17 shows that when using
paralleled devices, a low impedance
path is generated that may be prone
to parasitic self oscillations. For this
reason some degree of gate decoup-
ling is needed as necessary to prevent
osciJIations.
.-GATE VOLTAGE FOR
GIVING 1/2 ....
'II ;___ V_
I i
i I~
" .
LOW IMPEDANCE
PATH
'D2
Figure 17. Low Impedance Path for Para-
sitic Oscillation for Unbal-
anced Parallel Branches
A Complete Functional Control
Scheme fora Two-Quadrant Chopper
A simplified functional diagram of
the control and drive circuitry for a
two-quadrant HEXFET chopper is
shown in Figure 18; this is intended
to demonstrate the basic operating
principle of the overall chopper sys-
tem, and differs in some minor details
from the actual practical. circuitry
presented later (Figure 22).
The control system has an outer
voltage feedback loop, which com-
control loop also determines the
chopper switching frequency by reg-
ulating the peak-to-peak ripple cur-
rent between preset upper and lower
limits. This it does by switching the
HEXFET ON whenever the current
falls a given amount below the refer-
ence value, and switching the HEX-
FET OFF whenever the current rises
a given amount above it.
The current control loop also pro-
vides instantaneous limiting of the
peak HEXFET and motor current.
This is accomp~ished simply by set-
ting a maximum limit on the current
reference signal and clamping it to
this level. Whenever the instantane-
ous motor current attempts to exceed
the maximum current reference by
more than the preset peak ripple cur-
rent, the HEXFET is immediately
switched OFF. Thus, the system is
completely self-protecting against
overcurrent.
Referring to the functional diagram
in Figure 18, the voltage reference is
compared with the voltage across the
motor;and the error signal is ampli-
fied through the voltage error ampli-
fier. The output of the voltage error
amplifier is the current reference sig-
nal. The voltage error signal is also
fed into the motor-regenerate logic
comparator. When the voltage error
is positive, the current reference is
also positive, and the control circuit
is demanding "motoring" current.
The output of the motor-regenerate
logic comparator is high, the motor
signal has a logic "I" value, while the
regen signal has a logic "0" value.
Switches A and D are closed, while
switches Band C are open.
When the current reference is nega-
tive, the control circuit is demanding
"regenerating" current. The output
of the mOlor-regenerate logic com-
parator is negative, the regen signal
has a logic "I" value, while the motor
signal has a logic "0" value. Switches
Band C are closed, while A and Dare
open.
The motor-regenerate logic com-
parator has a built-in hysteresis to

A-106
 v*
MOTOR!
REGENERATE
COMPARATOR
Figure 18. Simplified Control System
prevent unwanted "bouncing" back
and forth between the "regeneration"
and "motoring" modes of operation,
at low current levels.
Consider the "motoring" mode of
operation. The positive current ref-
erence signal is compared with a sig-
nal representing the actual motor
current; the difference is amplified
through the current error amplifier.
The output of this amplifier is fed
through switch A, which is closed, to
the motor comparator. This com-
parator produces a "0" output signal
in response to a positive input signal
above a preset threshold level, and a
"I" output signal in response to a
negative input signal below a certain
preset level.
The output signal of the motor
comparator is isolated and shaped to
become the gate drive signal for the
"motoring" HEXFET. The "motor-
ing" HEXFET is thereby switched
ON when the motor current falls a
predetermined amount below the ref-
erence and OFF whenever the motor
current rises a predetermined amount
above the reference value, while the
switching frequency automatically
adjusts itself to keep the peak-to-
peak ripple current constant. The
peak-to-peak ripple current and oper-
ating frequency can be adjusted by
m_OUTPUT
~
ISOLATION
OUTPUT~
liE INPUT
CURRENT FEEDBACK
VOLTAGE FEEDBACK
adjusting the hysteresis of the motor
comparator.
Note that in the motoring mode,
switch D is closed, applying a steady
negative input to the regen compara-
tor, and shutting OFF the gate drive
signal to the "regenerating" HEX-
FET. Theoretical waveforms which
illustrate the operation of this scheme
in the motoring mode are illustrated
in Figure 19.
In the regenerating mode of opera-
tion, switches Band C are closed. A
continuous positive signal is applied
to the input of the motor compara-
tor, shutting OFF the drive to the
"motoring" HEXFET. The current
reference is negative, and the current
error signal is fed to the input of the
regen comparator. This comparator
produces a "I" output signal in re-
sponse to a positive input signal
above a certain preset level, and a "0"
output signal in response to a nega-
tive input signal below a given preset
level. The "regenerating" HEXFET
is now switched ON whenever the
regenerative current from the motor
falls a preset amount below the refer-
ence value, and OFF whenever the
motor current rises a preset amount
above the reference' value. Theoreti-
cal waveforms which illustrate the
operation in the regenerating mode
A-107
AND
DRIVE
SULJ l
isI
.J
CIRCUIT "MOTORING"
HEXFET
DRIVE
CIRCUIT
"REGENERATING"
HEXFET
are shown in Figure 20.
A 48V, 200A Experimental Chopper
Power Circuit
A schematic diagram of the power
circuit of an experimental laboratory
chopper is shown in Figure 21. This
employs a total of ten IRFI50 HEX-
FETs connected in parallel for the
"motoring" switch, and five IRFl50
HEXFETs connected in parallel for
the "regenerating" switch.
All HEXFETs are mounted on a
22-inch length of aluminum heatsink
extrusion, with outer dimensions of 5
inches by 3 inches, with the regener-
ating HEXFETs being isolated elec-
trically from the heatsink.
The assembly is capable of deliver-
ing 200A forward "motoring" cur-
rent and I40A of "regenerating" cur-
rent. The "motoring" HEXFETs by
themselves actually are capable of
carrying about 300A of output cur-
rent; the 200A limit is set by the cur-
rent carrying capacity of the five
freewheeling body-drain diodes of
the "regenerating" HEXFETs.
Control and Drive Circuitry
Figure 22 shows a diagram of the
control and drive circuitry. This is
based upon the functional circuit Test Results circuit keeps the peak motor current
shown in Figure 18 and requires no to just over 200A. The chopping fre-
additional explanation other than to Practical test results are shown in quency is about 2 kHz.
point out that for practical reasons, Figures 23 through 27. Figure 24 shows motor current and
some of the signal polarities are op- Figure 23 shows the current when voltage waveforms when accelerat-
posite to those assumed for the sim- the motor accelerates from standstill ing from half speed to almost full
plified functional circuit of Figure 18. to about half speed. The current limit speed, then decelerating back to half
speed. The current limit holds the
peak motoring current to about 205A,
and the peak regenerating current to
about 140A.
0- -- - - - - - - - - - - - - - - - - - - - - -- -- - - - ---- -- Figure 25 shows the output voltage
and current of the chopper with a
" A. A. ~
CURRENT REFERENCE I passive inductive load. Note the clas-
ANDACTUA~~~~ ~ A A. sicallinear rise and fall of the current
I VV associated with an inductive load.
Figures 26 and 27 show turn-ON
and turn-OFF oscillograms respec-
tively for one HEXFET, with the
OUTPUT OF REGEN_ chopper operating with a passive
COMPARATOR inductive load of 120A. These wave-
o forms generally agree with the fore-
going theoretical discussion. Note,
Figure 19. Theoretical Waveforms for the Motoring Mode of Operation however, in Figure 27, that the gate
voltage reverses at a switch-OFF;
this is due to resonance between the
gate capacitance and circuit induc-
tance.

I'~AA. Conclusions
CURRENT REFERENCE I' A A / ~V'
ANDACTU~~~~~~ 7VV This application note has demon-
strated the technical feasibility of a
0 - - - - - - - - - -- - ---- ------ DC-to-DC chopper using parallel
connected HEXFETs for motor speed
OUTPUT OF CURRENT 0 _
ERROR AMPLIFIER control, operating at the 200A level,
and the use of HEXFET's body-
OUTPUT OF MOTOR drain diode to provide the freewheel-
COMPARATOR ing and flyback functions needed for
two quadrant operation. The poten-
Figure 20. Theoretical Waveforms for the Regenerating Mode of Operation tial attractions of using HEXFETs
are simplicity of drive circuitry, rug-
gedness, speed of response, ease of
paralleling and overall compactness.
Power HEXFETs also offer an in-
teresting system advantage in this
M~'~W~~-------------------4~----------------------- type of application. Due to the ease
~1~W~~~________________~~_______________________ of operating at high frequency, a
separately excited field winding, with
the added motor controlability and
superior system performance that this
provides, becomes a practical reality.
TOTAL OF
'IDI SIMII.AR
Present-day choppers using bipolar
UNITS transistors or thyristors generally
operate at relatively low frequency
(in order to keep them simple), and
require a series-connected field wind-
ing to keep the motor ripple current
to an acceptable level. With the higher
TOTAL OF
FlVESlMH.AR chopper frequency made possible by
all UNITS power HEXFETs, on the other hand,
1W
the inductance of the motor arma-
ture is by itself sufficient to smooth
the current, thus allowing the field
~~~~~-------------------~~----------------------- winding to be disassociated from the
armature circuit, and to be independ-
ently controlled, offering better sys-
tem performance and superior con-
Figure 21. Power Circuit Schematic trol flexibility.
As improvements in circuit design,
MOSFET technology, packaging,

A-108
 TO GATEOF'
GENERAnNG
HEXFETS

A.B,C
D:
E:
F:
TL0B2 OR EQUIVALENT
SlUCONIX DG2Q1
LM311
555
01:
03,05:
02:
04,06<
2N3725
2M532O
2M3244
2N5322
z TO GATE OF
MOTORING
HEXFETS

G: GE -H11A5100 07: 2N2219

Figure 22. Control and Drive Ci rcuit Schematic

Figure 23. Motor Current under Acceler-
ation. Peak Motor Current =
220A. 40A per division. 10ns
per division.
Figure 24. Motor Voltage & Current when
Accelerating & Decelerating.
Peak Motoring Current = 205A.
Peak Regenerating Current =
140A. Top Trace: Voltage 25V
per division. Bottom Trace:
Current 115A per division.
Figure 25. Output Voltage & Current of
Chopper into Passive Inductive
Load - 2201's per division.
Lower Trace: Voltage 10V per
division.

A-109
and device costs all take place, the
type of system described in this appli-
cation note will become economically
as well as technically superior to
today's chopper systems using bipo-
lar transistors or thyristors. 0

References:
I. International Rectifier Applica-
tion Note AN934A: "The HEX-
FET Integral Body Diode".
2. International Rectifier Applica-
tion Note AN947: "Understanding
HEXFET Switching Perform-
ance".
3. J.B. Forsythe: "Paralleling of
Power MOSFETs," IEEE-lAS Figure 26. Turn-On Oscillograms for one Figure 27. Turn-Off Osciliograms for one
Conference Record, October 1981. HEXFET. Total Output Current HEXFET. Total Output Current
=120A.SOOnsperdivision. Top = 120A. 200ns per division. Top
Trace: Gate-Source Voltage SV Trace: Gate-Source Voltage SV
per div. Middle Trace: Drain- per div. Middle Trace: Drain-
Source Voltage 20V per div. Source Voltage SA per div.
Acknowledgements Lower Trace: Drain Current LowerTrace: Drain Current SA
10A per div. per div.
The assistance of H. Murphy and T. Gilmore
of Allis Chalmers, and of F. Stich of Siemens
Allis, in reviewing and commenting upon this
application note, and in providing the motor, .
is gratefully acknowledged.

A-110

High Voltage, High Frequency Switching Using a
Cascode Connection of HEXFET® and Bipolar
Transistor
(HEXFET is the trademark for International Rectifier Power MOSFETs)
By S. CLEMENTE, B. PELLY, R. RUTTONSHA, B. TAYLOR
Summary
A cascode connection of high volt-
age bipolar transistor and low voltage
HEXFET is described. A specific
example is considered that is capable
of switching lOA at 750V in 200-300
nanoseconds. The use of this combi-
national "BIMOS" switch is demon-
strated in a lOA inverter bridge circuit
operating at 25kHz from a dc input
voltage up to 750V.
Introduction
Power HEXFETs are now firmly
established at voltage ratings up to
500V. Their main attributes are very
fast switching speed, permitting switch-
ing frequencies of hundreds of kilo-
hertz ~ very high input impedance,
permitting very simple drive circuitry
- and absence of second breakdown,
permitting reduction or elimination of
protection circuitry, and enhanced
reliability.
The power HEXFET is a majority
carrier device, and its on-state voltage
drop is a strong function of voltage
rating. A 100V rated HEXFET, for
example. has a voltage drop at rated
usable current, at rated maximum
junction temperature, of about 2.5V,
while a 500V rated device has a volt-
age drop of about 9V, at rated maxi-
mum junction temperature.
MOSFETs with voltage ratings
above 500V are technically feasible,
but voltage drop increases rapidly, as
illustrated in Figure I. An 850V rated
MOSFET, for example, would have a
voltage drop of about 18V, and a
IOOOV rated MOSFET would have
about a 23V drop. This relationship
between voltage drop and voltage rat-
ing is presently a barrier to general
commercial usage of power MOSFETs
at voltage ratings much above 500V.
CHAPTER 12
APPLICATION NOTE 946
Circuit designers would nonetheless in a so-called cascade connection -to
welcome an 800 to IOOOV rated device, yield a combined high voltage, high
with the switching performance and speed switch is not new, and has been
Safe Operating Area of a power employed in the past using pairs of
HEXFET, but with a voltage drop - bipolar transistors.
and price - that are lower than those With the availability of power
of a comparably rated high voltage HEXFETs, this cascode technique
MOSFET. can be looked at with renewed inter-
This device, if it existed, would est, because a high voltage device with
open up a range of application possi- HEXFET-like switching performance
bilities, such as direct off-line (240V) and relatively low conduction voltage
high frequency (20-250kHz) single- drop can be implemented by combin-
ended switching power supplies, and ing a high voltage bipolar with a low
direct off-line (440/ 480V, 3-phase) voltage HEXFET. The best features
high frequency bridge inverter circuits of each device can be combined to
for motor drives, uninterruptable provide operating characteristics that
power supplies, and high power (class cannot be achieved with either one
D) switching amplifiers. on its own. This cascode combination
The concept of using a low voltage, of BIpolar transistor and power
fast switching transistor in the emitter MOSFET is referred to in this appli-
of a second high voltage transistor ~ cation note as a BIMOS switch.
20
~
~ 15
w
"~
o
>
z 10
o
;::
U
:l
o
Z
o
u
200 400 600 800 1000
VOLTAGE RATING (VOLTS)
Figure 1. Conduction voltage versus voltage rating of power MOSFET. TJ 0 150·C
A-111
Basic Principle of BIMOS Switch
The basic BIMOS switch is shown
___
in Figure 2. It is switched ON and HIGH VOLTAGE
OFF by control of the gate of the BIPOLAR
HEXFET. When the HEXFET is
ON, the bipolar is ON, since it receives
base drive current from the bias
supply voltage VB' When the HEX-
FET is OFF, the bipolar is also OFF, D

19'---
LOW VOLTAGE
since its emitter is open-circuited. HEXFET
The voltage developed across the
HEXFET when it is OFF is essen-
tially only the bias voltage supply VB
(typically 10 to ISV). The collector-
source blocking voltage capability of
the combined BIMOS switch is the Figure 2. Cascade connection of HEXFET and bipolar
relatively high VCBO rating ofthe bipo-
lar, because of the "common base" IC
configuration. In addition, the switch- COMMON BASE
ing speed of the bipolar is much faster 15~----------~1------------'
than is achievable in the usual com-
mon emitter connection. In essence, 1
1 -------- I

;
this is because the "forcible" opening 10 --------1
of the emitter at switch-OFF diverts
-::M~::-r--l----T--
8
the collector current in its entirety out
of the base.
Since the ON or OFF condition of
the BIMOS switch is controlled at the
EMITTER /!
300
:
450
::
650 750 850
gate of the HEXFET, the input impe-
dance is that of the HEXFET; the Figure 3. Comparison of common emitter and common base switching SOA of
2N6547 Bipolar
externally applied drive current is only
that needed to charge and discharge
the self capacitance of the HEXFET.
Consideration of a specific example
- the 2N6547 bipolar transistor in
! 10A
combination with the IRFI31 HEX-
FET - will illustrate typical perfor-
mance characteristics. Figure 3 shows
the Switching Safe Operating Area of
the 2N6S47 transistor in common base
-
2A

2N6547
t
I
VCE (SAT) = 2.5V MAX.
(TJ = 100°C)
configuration. Also shown is the Safe
Operating Area for the common emit-
ter configuration. Note the substan-
E
l 12A
tially wider Safe Operating Area for
common base, reflecting the 8S0V
VCBO rating versus the 400V VCEO rat-
D
t
ing of this device. VDS (ON) = 4.3V MAX.
Table I shows typical switching (T J = 150°C)
times of the 2N6S47 in the common
base connection, for different conduc-
tion times, when switching lOA in a
IRF131
I
6S0V circuit. The storage times (180ns
to 1000ns) are considerably shorter vC-S = 6.SV MAX.
than for the common emitter connec- Figure 4. Maximum conduction voltage of BIMOS switch using 2N6547 and IRF131
tion (typically 2 to 4J.!s), as are the
switching times (40ns to 230ns versus
I to I.SJ.!s). Test Conditions Circuit Implementation
Table 1. Turn-Off Switching Times- for Table I are: Ic =IOAmps In practice it will generally be more
2N6547 (Common Base). IBI =2Amps convenient to replace the fixed voltage
Clamped Inductive Load. Vcollecto, =6S0V DC supply VB in Figure 2 with a propor-
Storage Switching Switching time is the sum of collector tional base drive, derived from a cur-
On Time Time Time voltage rise time and collector current rent transformer in the collector cir-
fall time, measured from 10% collec- cuit. A practical circuit is shown in
lJ.!s l80ns 40ns tor voltage to 10% collector current.
2J.!s 200ns SOns Figure 5.
As illustrated in Figure 4, the con-
4J.!s 400ns 8Sns duction voltage drop across the The capacitor CI is charged to the
6J.!s S20ns 120ns BIMOS switch at a load current of voltage of the zener diode DZI when
8J.!s 620ns 160ns lOA (the maximum usable current of the BIMOS switch is OFF. When the
lOJ.!s 700ns 170ns the 2N6S47) is about 6.8 V. This com- HEXFET is switched ON, base drive
ISJ.!s 900ns 2 IOns pares with about 18V for an equiva- for the bipolar is initially derived from
20J.!s lOOOns 230ns lent lOA, 8S0V rated HEXFET. C I. Once the collector current is estab-
A-112
 Base
Current
Switch
Voltage

DZ1
Switch Voltage
Current
Gate
Voltage

(a) Upper: 200Vldiv 5"s/div (b) Upper: 5A/div 5"s/div

Lower: 5A/div Middle: 10V/div Lower: 20Vldiv

Figure 6. Oscillograms for BIMOS switch of Figure S when switching 6S0V, 10A into resistive/inductive load (GS!1, 50"H) with parallel
clamping diode

lished, CTI supplies steady base drive

current to the bipolar.
C With this particular transformer the
maximum ON time of the switch
when carrying lOA is about 251ls, and
the minimum OFF time - required
CT1 to reset the current transformer - is
about 1.51ls. The peak "reset" voltage
across the secondary of the current
transformer is approximately 135V;
02
this is determined largely by circuit
01 capacitance. Typical operating oscil-
lograms for this basic BIMOS switch
are shown in Figures 6 through 10. A
R1
brief description of these waveforms
folJows:
Figure 6(a) shows waveforms of
voltage and current when switching
650V, lOA. The load has approxi-
mately 650 resistance and 50llH series
inductance, with a clamping (free-
oZ 1 C1 wheeling) diode connected across it.
The relatively slow rate of rise of cur-
rent at switch ON is due to the load
02 inductance. Note the rapid fall time of
the voltage during turn ON and the
rapid rise and fall times of the voltage
G and current during turn OFF.
Figure 6(b) shows the base current
in the bipolar transistor, the voltage
across OZI, and the drive voltage at
the gate of the HEXFET. Note the
initial "spike" of base current supplied
by the capacitor CI. Note also the
reverse base current of lOA during the
storage period, equal to the lOA col-
Figure 5. Practical implementation of BIMOS switch lector current, due to the open emitter.
(For component detail see Table 2, page 6.) The storage time for this lOA collector

A-113
 (a) (b)

o o
Current Current

o
o Voltage
Voltage

Voltage: 100v/div 100ns/div

Current: 5A/div
Figure 7. Voltage and current waveforms for BIMOS switch of Figure 5 (a) at turn-ON. and (b) at turn-OFF, when switching 650V, lOA,
into resistive/inductive load (650, 50jLH) with parallel clamping diode

(8) (b)

CTl CT1
Secondary Secondary
Current Current

CTl CT1
Secondary Secondary
Voltage Voltage

DZl DZl
Voltage Voltage

Upper: 5A/div 5jLs/div Upper: 5A/div 1jLs/div

Middle: 50V/div Lower: 10V/div Middle: 50V/div Lower: 10V/div

Figure 8. Base drive circuit waveforms for BIMOS switch of Figure 5 when switching lOA (a) 5jLs/div (b) expanded to ljLs/div to show
details of. turn-OFF

current level and 18JLs conduction

time is approximately IJLs.
Figure 7 shows expanded voltage
and current waveforms for the BIMOS
switch at turn-ON and turn-OFF. The
voltage fall time at turn-ON is less
Collector than lOOns, and the combined voltage
Current rise time and current fall time at turn-
OFF for this 18JLs conduction time is
CT1 about 200 nanoseconds.
Secondary
Current Figure 8 shows base drive wave-
forms for the bipolar. The reset volt-
CTl
age spike across the secondary of CTI
Secondary has a peak value of approximately
Voltage 135V. The reset time is approximately
1.5JLs.
Figure 9 shows base drive wave-
forms for a "forbidden" operating
mode when the conduction time is
extended beyond the 25JLs maximum
Upper: 5A/div 5jLs/div
Middle: 5A/div Lower: 50V/div permitted by this particular current
transformer. The transformer starts to
Figure 9. Base drive circuit waveforms for BIMOS switch of Figure 5 with conduction saturate after about 28JLs, collapsing
time greater than the 25jLs maximum limit permitted by CT1 the base drive to the transistor. Since

A-114
the HEXFET is still switched ON, the
emitter of the bipolar is still "grounded."
The collector current continues to
flow for the relatively long "grounded
emitter" storage time of the bipolar -
about 12~s. (To add insult to injury,
negative base current is zero; this
would normally be applied to the
grounded emitter configuration to
shorten storage time.) The "grounded
base" storage time, by contrast, (Fig-
ure 6(b» is about I~s.
Figure 10 shows the effect on the
switching waveforms of changing the
TURN-ON
100ns/div
Figure 10. Voltage and current waveforms at turn-ON and turn-OFF for the BIMOS switch of Figure 5 when switching 10A at 650V with
DZ1 voltage (a)·5V and (b) 18V
voltage of zener diode DZ I (Figure 5).
With a zener voltage of 5V (Figure
lO(a», the fall time of the voltage at
turn-ON is relatively slow (lOOns),
since the capacitor C I is charged to
only 5V, and supplies only a mediocre
"spike" of base current at turn-ON.
During the storage time at turn-OFF
the collector-drain voltage becomes
the zener voltage of DZI plus the col-
lector-base voltage; this voltage is rela-
tively low, because the zener voltage is
relatively low. Dissipation during this
period is therefore relatively small.
With a zener voltage of 18V (Figure
(a)
o Current 0
Voltage 0
(b)
o Current o
o Voltage o
Voltage: 100Vldiv
Current: 5A/div
A-115
lO(b» the fall time of the voltage at
turn-ON is reduced to about 50ns,
because of the increased charge in CI.
The collector-drain voltage at turn-
OFF during the storage time is,
however, relatively high, because the
zener voltage is relatively high, and
dissipation during this period is
increased.
Judicious selection of the zener volt-
age will minimize the total switching
losses. The 10V zener used in Figure 5
and II was judged to be near-
optimum.
TURN-OFF'
200ns/div
 650-750VOC

CTt

02
~ 0 04
CT2

06
~
07
0 08
03
01
• A1
05

A3
03
01 V
A2
A4

'.l~
C1
C2
~ t:: ....
C3 ...
a ~
- C4
OZ1
.. OZ2
I<

I~
0 G2
G1
lte-
,. 02
>
iE
04

51
LLOAO
.
Q
0
,S 2

I
CT3
~ 0) COUTPUT CT4
~ 0
09 010 011 012
r 013 014 015 016 ,.
, R7
A5
07
05
V
R6 R8

C5
- C7 -~
r," ~
C6
'.l~ :: CB
OZ3 OZ4
G3
,.
lte- 08 G4
lte-
,. 08

53 54

Figure 11. BIMOS bridge circuit

Table 2. Components Listing for Figure 5 and 11.

LIST OF COMPONENTS FOR BIMOS BRIDGE CIRCUIT

A BIMOS Bridge Inverter
Operating at 650-750V DC, 10A,
25kHz

A major circuit application area for

Q" Ql, Qs, Q7
Q2, Q., Q6, Qs
C" C l , C s, C7
C 2 • C•• C6• C s
R,. R3> Rs. R7
R 2 , R •• R 6• Rg
D" Ds. D 9 • DIl
D 2, D6, D IO , DI'
D l , D7, D", DIS
D., Dg. D 12, DI6
DZ, DZ 2 , DZ 3 , DZ.
CT I• CT 2 , CT3 • CT.
IR2N6547 a BIMOS switch is in high frequency
IRFI3I bridge inverters operating from 440/
O.I~F 480V, I or 3-phase lines, for large
0.068~F, IOOOV switching power supplies, motor
drives, welding, induction heating,
lOOk ~W uninterruptible power supplies, high
lOOk 2W power switching amplifiers, and so on.
UESI305
IR IN4007
The feasibility of a BIMOS switch
Two IR 40SL6 connected in series for this type of application has been
with sharing resistors demonstrated in an experimental
12FLlOOS05 single phase BIMOS bridge circuit
IOV zener diode, 1.5W operating from 650 to 750V DC at
Primary 2 turns #16 lOA, 25kHz. A diagram of the power
Secondary 10 turns #24 circuit is shown in Figure II. The test
Core TDK H5B2TIO-20-5 results reported in this article are for
an inductive load, with a blocking
capacitor, COUTPUT, used to prevent
DC load saturation. The experimental
control and drive circuitry is shown in
Figure 12.

A-116
 18V

Rt

R?

TO G3

r---------------.-------------~----._------------_.--_ol.V

18V

Q?

Rt?

TO G4

~~------------o

Figure 12. Control and drive circuit for BIMOS bridge

Table 3. Components Listing for Figure 12.

LIST OF COMPONENTS FOR CONTROL AND DRIVE CIRCUIT FOR BIMOS BRIDGE

IRFD9121 5kO. ten turn potentiometer !4 W

IRFDIII 1500.2W
Texas Instrument TlA94 220. !4W
MCI45288 4.7kO. !4W
MCI40938 500kO. !4 W ten turn potentiometer
O.OI/LF 50kO. !4 W ten turn potentiometer
68pF Primary: 40 turns #24
.0068/LF Secondary: 40 turns #24
5kO. ten turn potentiometer Core TDK H s8 2TIO-20-5
2.2K !4W

A-117
 Idealized gating waveforms for the
BIMOS switches are shown in Figure
13. Each leg or "pole" of the inverter
circuit is gated to deliver a 180" square
wave of output voltage (with respect
to DC midpoint potential), with a
short deadtime when switching from
an upper to a lower device, and vice
versa, to allow for the storage time of
the BIMOS switch. Pulse width con-
trol of the output voltage of the bridge
is obtained by phase-shifting the gat-
ing waveforms applied to the two legs
of the bridge. With this gating regime
two of the four switches are always
gated ON (except during the short
crossover dead-time), and the output
voltage waveform is always defined by
the gating pattern, independent of the
load characteristics.
A "simpler" gating regime under
which diagonally opposite pairs of
switches were simultaneously gated
ON for a controllable time, with all
gating signals being removed during
the intervening periods, was unsatis-
factory. This is because substantial
oscillation took place between the self
capacitance of the switch and the
inductance of the load, once inductive
current feedback from the load to the
DC source was completed, and the
BIMOS switches were then left tem-
porarily "floating" with no gating sig-
nals applied to them. Operation with
this "incorrect" gating regime is illus-
trated by the oscillograms in Figure
14.
Figures 15 through 24 show wave-
forms which illustrate the operation of
this experimental BIMOS bridge cir-
cuit. The de input voltage for Figures
15 through 23 is 650V, and for Figure
24 it is 750V. A description of these
oscillograms follows:
Figure 15(a) shows output voltage
and current waveforms with partial-
width output voltage pulses, and Fig-
ure 15(b) shows corresponding wave-
forms with almost "full" width output
voltage. The peak current for this lat-
ter case is approximately lOA.

- / - DEAD TIME

J J,-_ _L GATE

I
Output
-'I....-____...lf GATE 3 Current

=-:J ± _1,-__ GATE 2

-±.--~
-II-- DEAD
_-- -,_
'---------.J± TIM E
_ GATE 4
Output
Voltage

OUTPUT
VOLTAGE

Figura 14. Output current and voltage waveforms with "incor-

Figure 13. Gating regime for experimental SIMOS bridge rect" gating regime. Inductive load

(a) (b)

Output Output
Voltage Voltage

Output Output
Current Current

Upper: 500V/div Upper: 500V/div 10/oLs/div

Lower: 2A/div Lower: 5Ndiv
Figure 15. Output voltage and current of SIMOS bridge circuit with 650V DC input
(a) "Partial" output voltage
(b) "Full" output voltage

A-118
 Figures 16(a) and (b) show the out-
put voltage and gating pulses for
BIMOS switches No's 3 and 4 at par-
tial and full ouput voltage respectively.
Figure 17 shows voltage and cur-
rent waveforms for the No. I BIMOS
switch/feedback diode combination,
at partial and full output voltage.
Note the relatively long period of
"negative" freewheeling current in the
feedback diode at partial output
because of the relatively short period
of the "active" output voltage pulse.
Figure 18 shows an expanded trace
of voltage and current for the No. I
BIMOS switch/feedback diode com-
bination, during the time that the No.
3 switch turns off, forcing inductive
load current into the No. I feedback
diode.

(b)

Output
Voltage

Gate
Voltage #3

Gate
Voltage #4

Upper: 500Vldiv 1Ol's/div

Middle: 20Vldiv Lower: 20V/div
Figure 16. Output voltage and gate drive voltages for BIMOS bridge. 650V DC input. (a) "Partial" output voltage (b) "Full" output voltage

(b)

o Current

o Voltage

Voltage: 100V/div 500ns/div Voltage: l00Vldiv 500ns/div

Current: 2A/div Current: 5A1div
Figure 17. Voltage and current for BIMOS switch/feetback diode combination. 6S0V DC input.
(a) "Partial" output voltage (3A peak at switch-off) (b) "Full" output voltage (10A peak at switch-off)

(b)

o Current

o Voltage

Voltage: 100Vldiv 5l's/div Voltage: 100V/div 5l's/div

Current: 2A1div Current: SA/div
Figure 18. Voltage and current for No.1 BI MOS switch/feedback diode combination when NO.3 turns-off and current com mutates into
No.1 feedback diode. 650V DC input.
(a) "Partial" output voltage (3.5A peak at commutation) (b) "Full" output voltage (lOA peak at commutation)

A-119
 (b)

o Current

o Voltage

Voltage: l00Vldiv Current: 2A/div

Figure 19. Voltage and current for BIMOS switch at partial output voltage when switching off 3A.
(a) Il's/div (b) l00ns/div 650V DC input.

(b)

o Current

o Voltage

Figure 20. Voltage and current for BIMOS switch at full output voltage when switching off lOA.
(a) Il's/div (b) 100ns/div 650V DC input.

(b)

Voltage
across
switch

Current-
BIMOS
switchl
Feedback
diode

Current-
Feedback
diode

Figure 21. Voltage and current waveforms for BIMOS switch and feedback diode (No. 1.) 650V DC input.
(a) "Partial" output voltage (b) "Full" output voltage

Figure 19 shows voltage and cur-
rent waveforms for the BIMOS switch
at partial output voltage, when turn-
ing off 3A. The storage time is approxi-
mately 600ns, and the sum of the volt-
age rise and current fall times is about
500ns.
Figure 20 shows similar waveforms
at full output voltage, when turning
off lOA. The storage time is about
500ns, and the sum of the voltage rise
and current fall times is about 300ns.
Note that the current waveforms in
Figures 19 and 20 include the current
in the clamping circuit D3, C2, R3
(Figure II). The current fall-times
seen in these oscillograms are there-
fore greater than for the BIMOS
switch itself.
Figure 21 shows waveforms of volt-
age and current for the No. I BIMOS
switch/feedback diode combination,
and the waveform of current for the
feedback diode by itself. Note the
"notch" of current "missing" from the
feedback diode current waveform.
The "missing" current flows through
the base-collector junction of the bi-
polar transistor, as explained below.

A-120
 (a) (b)

Output Output
Voltage Voltage

Collector Collector
Current Current

Gate Gate
Voltage Voltage

Upper: 100V/div 10l's/div Upper: 500V/div 10l's/div

Middle: 2A/div Lower: 20V/div Middle: 10Ndiv Lower: 20V/div
Figure 22. Output voltage, collector current, and gate voltage waveforms. (Switch No.1) 650V DC input.
(a) "Partial" output voltage (3A peak) (b) "Full" output voltage (10A peak)

(b)

Base
Current

Voltage
ZD1

Gate
Voltage

Upper: 2A/div Middle: 10V/div Lower: 20V/div 10l's/div Upper: 5A/div Middle: 10V/div Lower: 20V/div 10l's/div
Figure 23. Base current, zener voltage, and gate voltage waveforms for BIMOS switch. 650V DC input.
(a) "Partial" output voltage (b) "Full" output voltage

(b)

o Switch
Current

o Switch
Voltage: 500Vldiv Current: 5A/div Voltage: 100Vldiv Current: 10A/div Voltage
Figure 24. Waveforms of (a) Output voltage and current and (b) Switch voltage and current at turn-off. 750V DC input

Figure 22 shows waveforms of out-
put voltage, collector current, and
gate voltage for BIMOS switch No. I.
Note the negative collector current
notches - the "missing" feedback
diode current notches referred to
above - which occur just after the
opposite device in the same inverter
leg has turned OFF, but before the
No. I HEXFET is gated ON. During
this period, the inductive load current
flows through the bipolar transistor's
collector base junction, which is for-
ward biased by the voltage on the
capacitor CI. By the time the HEX-
FET is gated ON, whatever charge
still remains on capacitor C I is rapidly
discharged through the HEXFET,
and the load current transfers into the
feedback diode (D4).
A-121
Figure 23 shows waveforms of base
current, zener voltage, and gate volt-
age for BIMOS switch No. I. The
"notch" of base-collector current
referred to above can be seen on the
base current waveform. This notch of
current substantially discharges capac-
itor CI by the time the HEXFET is
gated ON.
Figure 24 shows waveforms of out-
Table 4. Comparisons Between Alternative Devices

BIMOS SWITCH HIGH VOLTAGE HEXFET GTO

Maximum voltage capability IOOOV IOOOV 1800V
Switching speed Fast Very Fast Moderate
40ns to 250ns fall time 50 to lOOns fall time I t02p.s fall time
180ns to Ills storage No storage IlLs storage
Voltage drop Moderate High Low
Snubber energy Low Low High
Relative efficiency Good at intermediate to high Good at high frequency. Good at low frequency.
frequency Moderate at low frequency. Poor at high frequency.
Overload caQability Poor Good Good
Drive Circuitry Simple Simple Complex
Relative cost Low / moderate High Low
Table 5. Approximate Cost Comparison

850V lOA BIMOS 850V lOA HEXFET 850-l500V lOA GTO

2N6547 I
Basic Device Cost
IRFI3I* I
Other circuit components
Drive circuitry (isolated)
Total $
*EstImated 10K piece pnce, 1984
put voltage, output current, and volt-
age and current for the No. I BIMOS
switch at turn-OFF, with a DC input
voltage of 750V. The peak load cur- .
rent is about lOA. These waveforms
are included to demonstrate the solid
capability of the BIMOS switch to
operate at a voltage close to the VCBO
rating of the bipolar - and actmilly
represent a slight excursion ,beyond
the limits of the common base Safe
Operating Area shown in Figure 3 for
the 2N6547.
Comparison With Alternatives
Alternative candidate devices to the
BIMOS switCIl are (a) a single 'high'
voltage HEXFET (or two HEXFETs
connected in series, which, would have
approximately similar characteristics)
and (b) a gate turn-off thyristor
(GTO).
Each of the three alternatives has its
own particular features, and each will
find use in the applications in which it
best fits. A comparison between the
most salient features of a BIMOS
switch, a high voltage HEXFET, and
a GTO is given in Table 4. Table 5
gives an approximate comparison of
component costs; this 'provides an
indication of relative costs, and is not
exact. It does not include circuit
assembly costs, which will have a
modifying effect, but will not greatly
'alter the relative comparison.
$2.90
$20.00*
2.00
3.60 0.50
0.50 0.50
9.00 21.00
The following general summary can
be made:
(a) A high voltage HEXFET (or two
HEXFETs connected in series)
offers the fastest switching speed,
and therefore has the greatest
advantage at high frequency (say
200kHz and above). For lower
frequency it will generally not be
the best choice for applications
requiring 850-l000V rating, be-
cause voltage drop and cost are
relatively high.
(b) The GTO offers the highest volt-
age capability - up to 1800V -
and will generally be the best
choice for applications that require
clevice voltage ratings substan-
tially in excess of 1000V, provided
that the o,perating frequency is not
too high - say 10 to 15kHz maxi-
murn. (It is to be noted, however,
that the GTO can be operated at
higher frequency, perhaps up to
50kHz, by operating at reduced
current and/ or voltage. But cost
per switching volt-ampere then
increases significantly.)
Switching speed of the GTO at
normal "rated" conditions is rela-
tively slow, and snubber energy is
relatively high, Snubber losses per
device could typically be 50W for
a GTO switching lOA at 700V, at
10kHz - unless a complex "loss-_ kilohertz, and power levels up to tens
less" snubber circuit is used. Drive
$4.00*
0.70
3.00
7.70
circuitry for the GTO is also rela-
tively complex. ,
(c) The BIMOS switch offers higher
frequency than the GTO, up 100
or 200kHz, with relatively good
efficiency. Its cost is significantly
lower than for a high voltage
HEXFET, but higher than for a
GTO. Several discrete compo-
nents are needed to make a BIMOS
switch, which is a disadvantage,
but external drive circuitry is
simple.
AilOther possibility, not included in
the above cornparison, would be a
cascode connection of GTO and low
voltage HEXFET. This would offer
higher voltage capabiliW than the
BIMOS switch, but would havesiower
switching speed, higher losses, and
probably somewhat higher cost. It
would have the advantage over the
GTO on its own of much simpler
external drive circuitry, and improved
switching speed.
Conclusion
The BIMOS switch should be con-
sidered as a serious candidate for
applications requiring device voltage
ratings up to 1000V, operating fre-
quency up to one or two hundred
of kilowatts. 0

CopynghllEEE. ThiS matenal was prepared for presentation at the 1982 IEEE
Industry Applications Society Conference, and IS reproduced by permiSSion
of the IEEE.
A-122
 CHAPTER 13
APPLICATION NOTE 948

Linear Power Amplifier

Using Complimentary HEXFETs
By Peter Willon

Introduction the driver transistor, Q4, t!> operate tion in HEXFET threshold voltage.
The class AB amplifier described at near constant current\ which A degree of temperature compensa-
in this application note uses a com- improves the linearity of tne driver tion is built into the circuit as both
plementary pair of HEXFET devices stage. The diode 01 acts as a clamp the bipolar transistor, Q3, emitter
as the output stage. This feature for the bootstrap circuit, restricting base voltage and the combined thre-
offers performance improvements the positive voltage at the gate of Q5 shold voltages of the HEXFETs, Q5,
over the equivalent bipolar output to +VDD. This allows symmetry to be Q6 have a temperature coefficient of
stage and allows a reduction in the maintained under overload -O.3%jOC.
complexity of the driver circuit, the conditions. The class A driver transistor, Q4,
output devices being driven by a sin- Transistor Q3 and resistors Rll, operates at a bias current determined
gle class A driver. R12, R13 provide gate-source offset by resistors Rs, R9, nominally 5mA.
The design described will deliver voltage for the output devices. RI2 is Q4 is driven by a PNP differential
60W rms into a 4 ohm load when variable, allowing adjustment of the input pair, QI, Q2. The bias current
working from ±30V supplies. The output quiescent current for varia- in the input stage is set to 2mA by
bandwidth is in excess of 100kHz,
but may be tailored to the user r--_--G!D--_--~--<r_~-<>.VDD
requirements by making component
value changes.
Circuit Description
The amplifier circuit diagram is
shown in Figure I, and the com-
ponents listing in Table I. Split power
supply rails (±VOO) are used, giving
improved rejection of power supply
ripple and allowing the load, R load, to
be direct coupled. The output devices
Qs. Q6> operate in source follower
configuration. This offers a twofold
advantage; a) the possibility of oscill-
ation in the power output stage is -Voe
reduced as the voltage gain is less
Figure 1. Class AS Amplifier Circuit Diagram
than unity and b) signal feedback
through the heatsink on which the
devices are assembled is eliminated Table 1. Components List
as the drain terminal, which is elec- RI 4.7KO R9 2.7KO CI 220pF QI,Q2, 2N4356,2N5086
trically connected to the tab on the R2 47KO RIO 6800 C2 100,..F IOV or equivalent
T0220 package, is at dc voltage. R3 15KO RII IOKO C3 47,..F 40V Q3,Q4, 2N441O,2N5088
Symmetrical output is achieved by R4 1.2KO RI2 IKO Pot. C4 47,..F 40V or equivalent
providing "bootstrapped" drive to Rs 5600 R13 8200 Cs 2200,..F 40V Qs IRF532
R6 47KO RI4 4.7KO C6 2200,..F 40V Q6 IRF9532
the gate of the n-channel device, Q5,
R7 4700 Rls 100lW C7 68nF DI IN4002
from the output. The use of the boot- 2.7KO
Rs Rload 8/40 LI 3,..H aircored
strap circuit, C4, Rs, R9 also allows

A-123
resistor R3. Negative feedback from
the output of the amplifier is fed to OO,------,------,-----,---r------,------,-----,---,
the base of Q2 by resistor R6. Com- // /
ponents R7, C2 set the closed loop
gain of the amplifier (R6/R7) and
provide low frequency gain boosting.
The additional components RIS, C7
/'11
4~--~ro-WE-"-DIS-SIP~~E-D--~41--~~r-~~~7~
/~--~~
:2U /
__
connected between the output node
and ground suppress the high fre- ",=40HM I
quency response of the output stage,
allowing the h.f. performance of the 21-----t----t-----~~::::~/~1/- t - - - - r - - 1
amplifier to be determined by the
input circuit. Components RI, R2,
DlsslPATEI
CI at the input of the amplifier define o~-----+----~~--_4~~~ __/~+-----_t----i_--
the input impedance (47Kohm) and ~L "'8HM/
suppress noise.
The amplifier input stage requires
additional power supply ripple sup-
pression which is provided by com-
4/
;fV
ponents R4, C3.
Additional circuit components
have been added to ensure high fre-
quency stability of the complete
i 2~----4------+~--~--~----i_----_t----i_~

amplifier. Placement of the compo-
nents and component values will
depend to some extent on the printed
circuit board layout. The following
rules should be followed when
designing the printed circuit board:
(a) A 'common ground' princi-
ple should be adopted, i.e., power
supply decoupling capacitors, load
and input stage biasing components
should all be taken to ground in close
proximity, eliminating the effects of
Copper Side
Figure 2. Amplifier Printed Circuit
Board Layout
_:L------L/L-v~ --'--~-----!-----;-7--;:'
I 'oL--" /_:_,
OUTPUT CURRENT (AMPS RMS)
Figure 3. Power Curves for the Amplifier with 4 and 8 Ohm Loads and ±30V
Power Supplies
common node ground current. Sim-
ilarly, a "common output node"
should be used, the load, feedback
resistor and h.f. suppression compo-
nents being taken from a common
point on the pcb.
(b) The length of connecting lead to
the gate terminals of HEXFETs Qs,
Q6 should be an absolute minimum
to avoid oscillation of the power out-
put stage. A series gate resistor, RIO,
may be used to suppress oscillation,
but too high a resistor value will limit
the slew rate. Oscillation of the
amplifier caused by capacitive cou-
pling to the base of the driver transis-
tor, Q4, is suppressed by the addition
of a series resistor, R14.
(c) Phase shift in the amplifier when
driving a reactive load can lead to
high frequency instability. With a
capacitive load, the addition of a
small, air-cored choke (3",H with an
8 ohm, 2",F load) will restore stabil-
ity. The final value of the choke is
defined by experiment.
Figure 2 shows a printed circuit
layout which can be used for the cir-
cuit shown in Figure I. The preced-
ing design rules have been followed.
Amplifier Performance
(a) Output Power: To achieve 60W
rms into a 4 ohm load, the current in
the load is 3.9A rms or 5.5A pk. This
information is derived from equa-
tions (I) and (2):
PO= I2rmsRIoad
2
V rms
(I)
= Rload
_ Ipk
Irms - -ff (2)
Vrms =~ (3)
.J2
Also from equation (I), the voltage
developed across the load at 60W
output is 15.5V rms or 22V pk. To
sustain a source current of 5.5A, the
n-channel HEXFET, IRF532,
requires a gate source voltage of 5V.
One can conclude that the gate bias
voltage to achieve peak power in the
positive sense is Vpk + Vgs = 27V. A
similar calculation for the negative
peak, using the P channel HEXFET,
IRF9532, shows that a negative gate
bias supply of -28V is required.
Consequently, a ±30V supply will
be adequate for a 60W output, pro-
vided that the supply voltage does
not fall below ±28V when loaded,
i.e., the power supply impedance
should be better than I ohm. The

A-124
 (c) Total Harmonic Distortion: The
40
fidelity of the amplifier is shown in
the distortion curves, Figure 5, and is
limited by the loop gain. Reduction
of the closed loop gain from 100 to 20
30
OPENLOOP produces a significant improvement
............ in distortion figure. The output stage
~ quiescent current was adjusted to
R7 ", 100
~ 100mA and can influence the distor-
-
...
20
- R7 == 100
r-
tion measurement significantly if
allowed to fall below 50mA.
(d) Quiescent Operating Condi-
A; tions: The dependence of the quies-
10
.... r-.. cent current in the output stage and
Voc=::b3QV of the output offset voltage on power
supply voltage are illustrated in
AL=80HM Table 2. The quiescent current is set
by first adjusting the potentiometer,
103 1004
R12. for minimum offset voltage -
FREQUENCY (Hz) turned fully anticlockwise if the pcb
layout in Figure 2 is used - and apply-
Figure 4. Amplifier Open and Closed Loop Frequency Response Curves ing the power supply voltage, the
positive supply passing through an
ammeter with IA f.s.d. R12 is then
relationship between the power deli- connections to the HEXFETs
adjusted until the meter reading is
vered to the load and the power broken,ls.-30db, -3db points occur-
100mA with ±30V supplies. The
absorbed from the supply is shown in ring at 15 Hz and 60kHz. Closed loop
meter should be removed from cir-
Figure 3, assuming a sinusoidal curves are shown for amplifier gains
cuit before applying an input signal
waveform and a ±30V supply. The of 100 (R7 = 470 ohm) and 20 (R7 = to the amplifier.
curve representing the power deli- 2.2K ohm). In both instances the
vered to the load can be easily plotted curves remain flat to within +Idb Power Supply Requirement
with the help of equation (I) for between 15 Hz and 100kHz with an 8 A simple line derived power supply
different values of load current. ohm load. The slew rate ofthe ampli- suitable for the class AB amplifier is
The power absorbed from the supply fier, measured with a 2V pk-pk illustrated in Figure 6. The ±30V
has been plotted with the help of the square wave input is I3V / ",s positive supplies are taken from the center-
following relationship: going and 16V / ",s negative going. tapped secondary of the line
The discrepancy could be balanced transformer.
out by addition of a series gate resis- The 2200",F supply decoupling
PS = (Vavg)(Iavg) tor for Q6. capacitors, Cs, C6, (Figure I) which

= (2VDC )('7 Irms) (4)

10'
Voo ± 30V

F= 1KHz
----
The difference between the two is
the power dissipated in the
HEXFETs and as it can be seen from
Figure 3, it has a peak of approxi- f I)
10'
mately 46W. Assuming a maximum GAIN = 100 AL=40HM
I ~
ambient temperature of 55°C, the ,..--
--
total thermal resistance between the
t'
z
0
I I
~ I
junction of the two HEXFETs and GAIN = 100 AL80HM
the ambient will have to be less than
2°C/W. Considering that the
IRF532 and IRF9532 have a thermal
C
\?
z
0
I ./
~
a: 10·' II GAIN
-
20 AL ~ 4
?~
resistance between junction and case <
of 1.67°CfW each, the maximum
x
g ,,- GAIN == 20 RL '" 8 OHM

case temperature will have to be less I-

than 110°C and the thermal resist-

ance of the heatsink will have to be
less than 1.16°CfW to ambient.
(b) Frequency Response: Open
loop and closed loop frequency 10 20 30 40 50 60
response curves for the amplifier are OUTPUT POWER (WATTS)

shown in Figure 4. The open loop Figure 5. Amplifier Total Harmonic Distortion Curves
gain, measured with gate and source

A-125
should be mounted as close as possi-
ble to the amplifier output stage,
reduce the supply frequency ripple to
S.SV pk-pk at full load.
Setting up Procedure
and Faultfinding
It is unlikely that any experienced
experimenter will have difficulty in
achieving satisfactory results when
building an amplifier to this design.
The printed circuit board shown in
Figure 2 is intended to assist in this
respect. The major problems antici-
pated are those associated with the
faulty assembly of components and
damage to the HEXFETs through
handling or circuit oscillation.
The following troubleshooting
checklist is offered as a guide to the
experimenter:
1. When assembling the printed
circuit board, mount the passive
components first, ensuring the cor-
rect polarity of electrolytic capaci-
tors. Then solder in the transistors
Q1 - Q4 checking for correct pin iden-
tification. Finally, mount the
HEXFETs, avoiding static discharge
by shorting the pins together to
ground and using a grounded solder-
ing iron. Check the assembled board
for correct component placement. A
component side overlay as shown in
Figure 2 is useful for this purpose.
Check the copper side of the board
for solder bridges between tracks,
and remove them. Check for dry
solder joints visually and electrically
using a resistance meter and rework,
if necessary.
2. Power can now be applied to the
amplifier and the output stage quies-
cent current set to between 50 and
100mA. The potentiometer, R12 is
first adjusted for minimum offset
(fully anticlockwise on the pcb layout
in Figure 2). An ammeter is con-
nected in series with the positive
supply and selected to read IA f.s.d
R12 is adjusted until the ammeter
reads between SOmA and 100mA.
Quiescent current setting can be per-
Table 2. Variation in Output offset voltage and Output Quiescent current with
supply voltage
Supply Voltage Output Offset
±VDD V Vas mV
35 -40
30 -20
25 +4
20 +30
SECONDARY:
45VRMS
INPUT
LINE
3KCB20
Figure 6. Simple Line-derived Power Supply
formed without the load connected.
If, however, a loudspeaker load is
connected in circuit, it can be pro-
tected by a fuse from dc overload.
With the quiescent current set, the
output offset voltage can be con-
firmed to be less than 100mV. Exces-
sive and erratic variation in quiescent
current as R12 is adjusted are indica-
tive of circuit oscillation or faulty
wiring. The solutions described in
"Circuit Description" (series gate res-
istors, minimized gate wiring and
common earthing) should be
adopted. Also, supply decoupling
capacitors should be mounted in
close proximity to the amplifier out-
put stage and load ground point.
Quiescent current setting should be
performed with the HEXFETs
mounted on their heatsink to avoid
overdissipation.
3. With the quiescent current set,
the ammeter should be removed from
the positive supply and a signal can
be applied to the amplifier input. Sig-
nal requirements for full rated output
are:
gain = 100:
RL = 4 n, Yin = l50mV rms
RL = 8 n, Yin = l60mV rms
Output Quiescent Current
lq rnA
135
100
75
54
A-126
+30V
+
OV
+
-30V
2A FUSE
gain = 20:
RL = 4 n, Yin = 770mV rms
RL = 8 n, Yin = 800mV rms
"Clipping" of the output wave-
form when operating at rated power
indicates poor supply reguilltion and
can be remedied by reducing the
input signal amplitude and derating
the amplifier. Alternatively, a lower
impedance supply should be used.
The frequency response of the ampli-
fier can be checked over the fre-
quency range 15 Hz - 100kHz with
the aid of an audio test set or signal
generator and oscilloscope. Distor-
tion of the output waveform at high
frequency is indicative of a reactive
load and adjustment of the output
choke will be required to restore the
waveform. The high frequency
response may be tailored with a com-
pensation capacitor in parallel with
R6. The low frequency response is
controlled by components R7,C2.
4. Hum pickup will be more likely
to occur in a high gain circuit. Pickup
at the high impedance input is min-
imized by use of a shielded cable,
grounded at the signal source.
Supply frequency ripple injected
through the supply to the input stage
of the amplifier can be detected
across capacitor, C3. This is attenu-
ated by the common mode rejection
ratio of Q1, Q2 before being ampli-
fied. However, if this is the source of
hum, adjustment to the values OfC3,
Rs can be made to suppress the signal
amplitude.
5. In the event of the output stage
being destroyed, either through short
circuit load or h.f. oscillation, both
HEXFETs should be replaced. It is
 (a) SINEWAVE FREQUENCY RESPONSE
1 KHz 100l.Hz

INPUT

OUTPUT

(b) SQUARE WAVE RESPONSE

1KHz 25 KHz

INPUT

OUTPUT

Figure 7. Amplifier Waveforms illustrating Frequency Response

unlikely, howeyer, that other circuit
components will have been affected.
The setup procedure should, of
course, be repeated with the new
devices in circuit.
Performance Summary
Using a complementary pair of
HEXFETs, IRF532 and IRF9532
and with a ±30V supply, the follow-
ing performance can be achieved:
Maximum rms output power:
60W into 4fi
32W into 8fi
Bandwidth:
15 Hz to 100kHz ±Idb
Total harmonic distortion (1kHz):
0.15% at 60W into 4fi
0.08% at 32W into 8fi
Voltage gain:
Adjustable, XlOO to X20
Input impedance: 47Kfi
Figure 7 illustrates the amplifier
response to 1kHz and 100kHz sine-
wave input signals and also the
square wave response at 1kHz and
25kHz.o

A-127
CHAPTER 14
APPLICATION NOTE 950

Transformer-Isolated HEXFET® Driver

Provides very large duty cycle ratios
(HEXFET is the trademark for International Rectifier Power MOSFETs)

ByP.WOOD

Transformer coupling of low level
signals to power switches offers sev-
eral advantages such as impedance
matching, DC isolation and either
step up or step down capability.
Unfortunately, transformers can
deliver only AC signals since the core
flux must be reset each half cycle.
This "constant volt seconds" prop-
erty of transformers results in large
voltage swings if a narrow reset pulse,
i.e., a large duty cycle is required
(Figure I).
E T-1
power MOSFET does not require
drive current in the ON or OFF
states. Switching speed, however, is
seriously comprised by Ciss if a high
impedance driver is used.
The circuit in Figure 2 provides a
low impedance answer during the
switching intervals, and a duty cycle
ratio of 1-99%; furthermore, it can
have any desired voltage ratio, and
provides electrical isolation!
In Figure 2, Q2 is a power HEXFET
providing the switching function for
a switching power supply, motor
drive or other application requiring
isolation between the low level logic
and high power output. Q I is a low
power HEXFET such as the
IRFDIZl, which is used to control
the drive signals to Q2, and T I is a
small I: I driver transformer provid-
ing electrical isolation from, and cou-
pling to, the low level circuitry.
The waveforms in Figure 3 explain
the circuit operation. Waveform A is
the desired logic signal to be switched
by Q2. When this voltage is applied
to the primary ofTl the waveform is
supported by changing core flux until
saturation occurs as shown in wave-
form B. At this time the winding volt-
ages fall to zero and remain so until

I~XFET
01

R1
~~1
r -....----I POWER SWITCH

T/3
NOTE: VOLT-SECONDS PRODUCT IN
SHADED AREAS MUST BE EQUAL.
=tFtfJII
THIS CAUSES RESET VOLTAGE TO BE 1:1
3 TIMES APPLIED VOLTAGE E.
Figure 2. Wide Duty Cycle HEXFET Driver Circuit
Figure 1. Constant-Volt-Seconds
Characteristics of Transformers

For this reason, transformers in +12V

semiconductor drive circuits are lim- A 0 --LOW LEVEL LOGIC SIGNAL
ited to 50% duty cycle or roughly -12V
equal pulse widths positive and nega-
tive because of drive voltag"e limita- +12V
tions of the semiconductors them- B 0 T1 WINDING VOLTAGE
selves.
-12V
For large duty cycle ratios design-
ers must choose an alternative to the +12V
transformer, such as an optical cou- C 0 VGS POWER HEXFET 02
pler to provide the necessary drive -12V
isolation.
These devices have poor noise im- VDS POWER HEXFET 02
munity, high impedance output and
require additional floating power
sources which add complexity.
Whenapower HEXFETis used for D 0 ----------------
the power switch, the high output
impedance of optical couplers is less Figure 3. Waveform Characteristics of HEXFET Driver Circuit
of a problem because the HEXFET
A-128
the core flux is reversed by the nega-
tive-going portion of waveform A.
."
Saturation will again occur if the
negative-applied pulse exceeds the
volt-seconds capability of the core.
V1NO
Hr.
IRFD1Z1C
~-. - VO

i3f •
During the positive portion of the
secondary waveform, which, of
.-L
course, has the same form as the
primary, the intrinsic diode of QI is fI
T!
in forward conduction and Q2 re- _J
ceives a positive gate drive voltage
with a source impedance of RI plus
the intrinsic diode forward imped- ----_ .. _--.! ----- .... --0

ance. In a practical circuit this can be Figure 4. Single Switch Regulators

less than 10 Ohms total, with a conse-
quent turn-on time of around 75nsec.

~rVo
When TI saturates, the intrinsic
diode of QI isolates the collapse of
voltage at the winding from the gate
of the power HEXFETand the input
capacitance Ciss of the power switch
holds the gate bias at the fully en-
~ Tf' _Inqr-- IRF840

--11-
hanced condition for a time limited ----<)

IRFD1Z1

I~I-
only by the gate leakage current of
Q2 as indicated in Figure 3c. HEXFET
When waveform A goes 12 volts - AVALANCHE
negative Q I will become fully en- II --, ___ PROTECTION

hanced; and the main switch Q2 will ~I IRF840

IRFD1~~
now be turned off at approximately
-12V at a source impedance RI + 0---'3 I
R DS(ON) of Q2. This will again be less imt I~
than 10 Ohms and will yield a turn-
off time less than lOOn sec.
When TI again saturates, during iILI---:
'il1l~=ir--0
the negative half cycle, its winding
voltages fall to zero and Q I turns off.
As TI voltage collapses, the gate of
Q2 also follows this voltage and
remains at zero bias. The drain volt-
age of the power HEXFET Q2 ap-

tr
Figure 5. High Voltage, High Power HEXFET Switch (SOOV, SA per Section)
pears in Figure 3d, showing that it is
indeed a mirror image of waveform
A, the desired low level logic signal. ,-----0
Note that because TI need only sup- IRF840 IRFD1Z1 IRFD1Z1 ,0

-mfI?r1~
port a 12V signal, for I J.Lsec or less, it
1fT
IRFD1Z1
\
~
is very small - and inexpensive.

)([; ii(TJ~L
ON <r
There are many circuits where pow-
er HEXFETs are replacing bipolar
~ II _1. /
..
INTRINSIC

transistors, and this one illustrates an

important feature of HEXFETs not
shared by bipolars, namely the insig-
nificant gate currents required to
achieve full conduction - so small,
in fact, that the ON or OFF bias lev-
els can be stored in the gate-to-source
capacitance!
A few examples of possible circuit
applications are shown in Figures 4,
5, and 6.
It should be noted with reference to
Figure 3b that the gate-source volt-
age of Q2 in the OFF state returns to
zero when TI saturates. For most
applications, the noise immunity pro-
vided by the threshold voltage of Q2
is sufficient (2V<VTH<4V). In some
applications it may be desirable to
provide more noise immunity. This
can be achieved merely by adding
another small N-Channel HEXFET
ADDITIONAL
CAPACITANCE FOR
LONG SWITCH PERIODS
Y~ :f/
IRF840~
Figure 6. Bi-directional AC Switch using HEXFETs
(typically an IRFDIZI) as shown in
Figure 7.
The circuit now provides -12V to
the power MOSFET after the trans-
former saturates, and this reverse
bias remains until the next positive
half cycle of drive. Thus, a minimum
of 14V noise immunity is provided which
should be adequate for all applica-
tions. Cost of the HEXFETs used in
Figure 7 is minimal, and these are
available in 4-pin HEXDIP pack-
A-129
,_- _____ J
Figure 7.
HEXFET Driver Circuit with
additional Noise Immunity
ages, which can be stacked side by
side in standard DIP sockets.
Conclusion
As described in this application
note, the circuit in Figure 7 offers a
simple and inexpensive way to drive
HEXFETs. It is especially useful
where isolated drives with variable
ON-OFF ratios are needed, and which
are difficult to accomplish with con-
ventional transformers or optical iso-
lators.D
CHAPTER 14
APPLICATION NOTE 931 B

Custom Assembly of HEXFET® Dice

Introduction Ole Characteristics operating area, SOA, thermal resist-

This application note describes the
HEXFET transistors available from
International Rectifier in die form.
These power MOS field effect tran-
sistor dice feature the same high reli-
ability planar technology used for the
IRF series of TO-3, TO-220, TO-39
and HEX-Dip packaged HEXFETs.
The same advanced MOS processing
techniques, silicon gate structure, and
efficient hexagonal source pattern
are available in die form for hybrid
assembly. As the name implies, the
HEXFET consists of an hexagonal
cell structure which results in a pack-
ing density of over 500,000 cells per
square inch. Use of a silicon-gate
design and state-of-the-art MOS pro-
cessing techniques result in an ex-
tremely reliable device which is highly
reproducible in various die sizes. Hy-
brid packaging of such die results in
substantial savings in weight and
volume compared to standard pack-
aging.
Six HEXFET die sizes presently
available from International Recti-
fier are summarized in Table I. These
are termed HEX-Z (43 mil x 35 mil),
HEX-I (91 milx69 mil), HEX-2(137
mil x 87 mil), HEX-3 (175 mil x 115
mil), HEX-4 (227 mil x 170 mil), and
HEX-5 (257 mil x 257 mil). The
majority of die sizes are available in
eight voltage ranges, with the excep-
tion of the P-Channel devices (see
Table 2), at corresponding on-re-
sistances. All die sizes have one gate
and one source bonding pad as shown
in Figures I through 6. Each HEX-
FET die is individually probed at
room ambient temperature to the
electrical specifications shown in
Tables 2 and 3.
Because of limitations when electri-
cally probing in wafer form, some of
the generic specifications of the equi-
valent packaged device cannot be
tested and guaranteed in die form.
These are power dissipation, Po, safe
ance, R 1hJc , on-resistance at rated
current, R OS(on), and inductive cur-
rent, I LM . (On-resistance at 10 = lA
is tested and guaranteed according to
Tables 2 and 3. These parameters are
dependent upon the user's assembly
technique. However, the following
characteristics are guaranteed by de-
sign to meet the specifications of the
equivalent part: gr" Ciss' Coss' C rss '
tdlon)' t" td(ort)' tr, and T J(max)' Con-
sult the appropriate data sheet from
each table.
Following electrical probing, the
dice are inked for identification and
scribed. The dice are mechanically
separated, 100% visually inspected,
and packed for shipment.
Dimensional Tolerances (Table 1.)
Bonding Pad l or W:
< 0.025 in., Tolerance =±O.OOO5 in.
;;. 0.025 in., Tolerance =±O.OOl in_
Overall Ole l or W:
< 0.050 in., Tolerance = ±O.004 in.
;;. 0.050 in., Tolerance = ±O.OO8 in.

Table 1. HEXFET Ole Dimension Summary with Photo

Showing Size Relationship (HEX-4 circled)
HEXFET DIE
DIMENSIONS HEX-Z HEX-l HEX-2 HEX-3 HEX-4 HEX-5
inch 0.043 0.091 0.137 0.175 0.227 0.257
L
mm 1Ji9 2.31 3.48 4.45 5.77 6.53
inch 0.035 0.069 0.087 0.115 0.170 0.257
W
mm 0.89 TI5 TIl 2.92 4.32 6.53
inch 0.006 0.012 0.024 0.029 0.040 0.050
LGate mm iiT5 (f.3(J 0Ji1 0.74 T.02 TIl
inch 0.006 0.014 0.031 0.038 0.060 0.070
WGate
mm iiT5 D.36 iU9 Q]7 1:52 T.78
inch 0.006 0.012 0.023 0.029 0.040 0.050
LSource mm iiT5 (f.3(J D.58 0.74 TIi2 127
inch 0.006 0.014 0.029 0_040 0.060 0.070
WSource mm iiT5 D.36 D.74 112 T.52 T70
inch 0.016 0.016 0.016 0.016 0.016 0.016
Thickness mm 0.41 liA1 D.41 D.41 D.41 D.41
Number of 1 1 2 2 4 6
Gate Fingers

A·130
Table 2. Electrical Probe Specifications for N-Channel HEXFET Power MOSFET Ole
R~S(On) @ VGS(TH)@
0= lA 10= lmA,
HEXFET MAXIMUM VGS= 10V 10SS@ IGSS@ VOS = VGS DATA SHEET FOR
DIE PART RATED RATED VOS VGS = 20V CORRESPONDING
SIZE NUMBER VOS TYP MAX MAXIMUM MAXIMUM MIN MAX PACKAGED DEVICE
IRFC1Z0 l00V 2.2 0 2.4 0 0.5mA lOOnA 2.0V 4.0V PD-9.380
HEX-Z IRFC1Zl 60V 2.2 0 2.4 0 O.5mA l00nA 2.0V 4.0V PO-9.380
N IRFC1Z2 l00V 2.8 0 3.2 0 0.5mA l00nA 2.0V 4.0V PD-9.380
IRFC1Z3 60V 2.8 0 3.2 0 0.5mA 100nA 2.0V 4.0V PD-9.380
IRFCll0 l00V 0.5 0 0.6 0 0.5mA lOOnA 2.0V 4.0V PO-9.325
IRFClll 60V 0.5 0 0.6 0 0.5mA l00nA 2.0V 4.0V PD-9.325
IRFCl12 l00V 0.6 0 0.8 0 0.5mA l00nA 2.0V 4.0V PD-9.325
IRFCl13 60V 0.6 0 0.8 0 0.5mA l00nA 2.0V 4.0V PO-9.325
IRFC210 200V 1.0 0 1.5 0 0.5mA l00nA 2.0V 4.0V PD-9.326
HEX-I IRFC211 150V 1.0 0 1.5 0 0.5mA l00nA 2.0V 4.0V PD-9.326
N IRFC212 200V 1.5 0 2.4 0 0.5mA 100nA 2.0V 4.0V PD-9.326
IRFC213 150V 1.5 0 2.4 0 0.5mA l00nA 2.0V 4.0V PO-9.326
IRFC310 400V 3.3 0 3.6 0 0.5mA l00nA 2.0V 4.0V PO-9.327
IRFC311 350V 3.3 0 3.6 0 0.5mA lOOn A 2.0V 4.0V PO-9.327
IRFC312 400V 3.6 0 5.0 0 0.5mA l00nA 2.0V 4.0V PD-9.327
IRFC313 350V 3.6 0 5.0 0 0.5mA l00nA 2.0V 4.0V PO-9.327
IRFC120 l00V 0.250 0.3 0 1.0mA l00nA 2.0V 4.0V PO-9.312
IRFC121 60V 0.250 0.3 0 1.0mA l00nA 2.0V 4.0V PO-9.312
IRFC122 l00V 0.3 0 0.4 0 1.0mA l00nA 2.0V 4.0V PO-9.312
IRFC123 60V 0.3 0 0.4 0 1.0mA 100nA 2.0V 4.0V PO-9.312
IRFC220 200V 0.5 0 0.8 0 tOm A lOOn A 2.0V 4.0V PO-9.316
IRFC221 150V 0.5 0 0.8 0 1.0mA l00nA 2.0V 4.0V PD-9.316
IRFC222 200V 0.8 0 1.2 0 1.0mA l00nA 2.0V 4.0V PO-9.316
HEX-2 IRFC223 150V 0.8 0 1.2 0 1.0mA l00nA 2.0V 4.0V PO-9.316
N IRFC320 400V 1.5 0 1.8 0 1.0mA l00nA 2.0V 4.0V PO-9.134
IRFC321 350V 1.5 0 1.8 0 tOm A l00nA 2.0V 4.0V PO-9.134
IRFC322 400V 1.8 0 2.5 0 tOm A lOOn A 2.0V 4.0V PD-9.134
IRFC323 350V 1.8 0 2.5 0 tOm A l00nA 2.0V 4.0V PO-9.134
IRFC420 500V 2.5 0 3.0 0 1.0mA l00nA 2.0V 4.0V PD-9.323
IRFC421 450V 2.5 0 3.0 0 1.0mA l00nA 2.0V 4.0V PD-9.323
IRFC422 500V 3.0 0 4.0 0 1.0mA l00nA 2.0V 4.0V PD-9.323
IRFC423 450V 3.0 0 4.0 0 1.0mA l00nA 2.0V 4.0V PD-9.323
IRFCl30 l00V 0.140 0.180 tOm A l00nA 2.0V 4.0V PD-9.303
IRFC131 60V 0.140 0.180 1.0mA l00nA 2.0V 4.0V PD-9.303
IRFC132 l00V 0.2 0 0.250 1.0mA l00nA 2.0V 4.0V PD-9.303
IRFCl33 60V 0.2 0 0.250 1.0mA l00nA 2.0V 4.0V PD-9.303
IRFC230 200V 0.250 0.4 0 1.0mA lOOn A 2.0V 4.0V PD-9.306
IRFC231 150V 0.250 0.4 0 1.0mA l00nA 2.0V 4.0V PD-9.306
IRFC232 200V 0.4 0 0.6 n tOm A l00nA 2.0V 4.0V PD-9.306
HEX-3 IRFC233 150V 0.4 0 0.6 n 1.0mA l00nA 2.0V 4.0V PD-9.J06
N IRFC330 400V 0.8 n 1.0 n 1.0mA l00nA 2.0V 4.0V PD-9.302
IRFC331 350V 0.8 0 1.0 0 1.0mA 100nA 2.0V 4.0V PD-9.302
IRFC332 400V 1.0 0 1.5 0 tOm A l00nA 2.0V 4.0V PD-9.302
IRFC333 350V 1.0 0 1.5 0 1.0mA l00nA 2.0V 4.0V PD-9.302
IRFC430 500V 1.3 0 1.5 0 1.0mA l00nA 2.0V 4.0V PD-9.310
IRFC431 450V 1.3 0 1.5 0 1.0mA l00nA 2.0V 4.0V PD-9.310
IRFC432 500V 1.5 0 2.0 0 1.0mA l00nA 2.0V 4.0V PD-9.310
IRFC433 450V 1.5 0 2.0 0 1.0mA l00nA 2.0V 4.0V PD-9.310
IRFC140 l00V 0.070 0.0850 1.0mA 100nA 2.0V 4.0V PO-9.369
IRFC141 60V 0.070 0.0850 1.0mA 100nA 2.0V 4.0V PD-9.369
IRFC142 l00V 0.09 0 0.110 1.0mA 100nA 2.0V 4.0V PD-9.369
IRFCl43 60V 0.09 0 0.110 1.0mA l00nA 2.0V 4.0V PD-9.369
IRFC240 200V 0.140 0.180 tOm A 100nA 2.0V 4.0V PD-9.370
IRFC241 150V 0.140 0.i80 tOm A 100nA 2.0V 4.0V PD-9.370
IRFC242 200V 0.200 0.220 1.0mA lOOn A 2.0V 4.0V PD-9.370
HEX-4 IRFC243 150V 0.200 0.220 1.0mA l00nA 2.0V 4.0V PD-9.370
N IRFC340 400V 0.470 0.550 1.0mA l00nA 2.0V 4.0V PD-9.371
IRFC341 350V 0.470 0.550 tOm A l00nA 2.0V 4.0V PD-9.371
IRFC342 400V 0.68 0 0.80 0 tOm A l00nA 2.0V 4.0V PD-9.371
IRFC343 350V 0.68 0 0.80 0 1.0mA 100nA 2.0V 4.0V PD-9.371
IRFC440 500V 0.8 0 0.850 1.0mA l00nA 2.0V 4.0V PD-9.372
IRFC441 450V 0.8 0 0.850 tOm A l00nA 2.0V 4.0V PD-9.372
IRFC442 500V 1.0 0 1.1 0 tOm A 100nA 2.0V 4.0V PD-9.372
IRFC443 450V 1.0 0 1.1 0 1.0mA l00nA 2.0V 4.0V PD-9.372
IRFC150 l00V 0.0450 0.0550 1.0mA 100nA 2.0V 4.0V PD-9.305
IRFC151 60V 0.0450 0.0550 1.0mA 100nA 2.0V 4.0V PD-9.305
IRFCl52 l00V 0.06 0 0.080 1.0mA l00nA 2.0V 4.0V PD-9.305
IRFC153 60V 0.06 0 0.08 0 tOm A 100nA 2.0V 4.0V PD-9.305
IRFC250 200V 0.070 0.0850 1.0mA l00nA 2.0V 4.0V PO-9.321
IRFC251 150V 0.070 0.0850 1.0mA 100nA 2.0V 4.0V PD-9.321
IRFC252 200V 0.09 0 0.120 1.0mA 100nA 2.0V 4.0V PD-9.321
HEX-5 IRFC253 150V 0.09 0 0.120 1.0mA l00nA 2.0V 4.0V PD-9.321
N IRFC350 400V 0.250 0.3 0 1.0mA l00nA 2.0V 4.0V PD-9.304
IRFC351 350V 0.250 0.3 0 1.0mA l00nA 2.0V 4.0V PD-9.304
IRFC352 400V 0.3 0 0.4 0 tOm A l00nA 2.0V 4.0V PD-9.304
IRFC353 350V 0.3 0 0.4 0 1.0mA l00nA 2.0V 4.0V PD-9.304
IRFC450 500V 0.3 0 0.4 0 1.0mA l00nA 2.0V 4.0V PD-9.322
IRFC451 450V 0.3 0 0.4 0 1.0mA lOOn A 2.0V 4.0V PD-9.322
IRFC452
IRFC453 I 500V
450V
0.4 0
0.4 0
0.5 0
0.5 0
1.0mA
1.0mA
l00nA
l00nA
2.0V
2.0V
4.0V
4.0V
PD-9.322
PD-9.322

A-131
Table 3. Electrical Probe Specifications for P-Channel HEXFET Power MOSFET Die
R~S(On) @ VGS(TH)@
0= lA ~=lmA,
HEXFET MAXIMUM VGS = 10V IOSS@ IGSS@ OS = VGS DATA SHEET FOR
DIE PART RATED RATEOVOS VGS= 20V CORRESPONDING
SIZE NUMBER VOS TYP MAX MAXIMUM MAXIMUM MIN MAX PACKAGED DEVICE
IRFC9110 -l00V 1.0 n 1.2n -a.SmA -l00nA -2.0V -4.OV PO-9.381
IRFC9111 -60V 1.0 n 1.2n -a.SmA -l00nA -2.0V -4.OV PO-9.381
IRFC9112 -l00V 1.2 n 1.6n -a.SmA -lOOn A -2.0V -4.OV PO-9.381
HEX-t IRFC9113 -60V 1.2 n 1.6n -a.SmA -l00nA -2.0V -4.OV PO-9.381
P IRFC9210 -200V 2.3 n 3.0n -a.SmA -l00nA -2.0V -4.OV PO-9.3S0
IRFC9211 -l50V 2.3 n 3.0n -a.SmA -l00nA -2.0V -4.OV PO-9.350
IRFC9212 -200V 3.5 n 4.Sn -O.SmA -l00nA -2.0V -4.OV PO-9.350
IRFC9213 -l50V 3.5 n 4.Sn -a.SmA -l00nA -2.0V -4.OV PO-9.350
IRFC9120 -l00V 0.5 n 0.6n -1.0mA -l00nA -2.0V -4.0V PO-9.319
IRFC9121 -60V 0.5 n 0.6n -1.0mA -100nA -2.0V -4.0V PO-9.319
IRFC9122 -l00V 0.6 n 0.8n -1.0mA -l00nA -2.0V -4.0V PO-9.319
HEX-2 IRFC9123 -60V 0.6 n 0.8n -1.0mA -l00nA -2.0V -4.0V PO-9.319
P IRFC9220 -200V 1.0 n 1.Sn -1.0mA -l00nA -2.0V -4.OV PO-9.3S1
IRFC9221 -l50V 1.0 n 1.Sn -1.0mA -l00nA -2.0V -4.0V PO-9.3S1
IRFC9222 -200V 1.5 n 2.4n -1.0mA -l00nA -2.0V -4.OV PD-9.351
IRFC9223 -l50V 1.5 n 2.4n -1.0mA -100nA -2.0V -4.OV PO-9.351
IRFC9130 -l00V 0.2Sn 0.3n -1.0mA -l00nA -2.0V -4.OV PO-9.318
IRFC9131 -60V 0.2Sn 0.3n -1.0mA -l00nA -2.0V -4.OV PO-9.318
IRFC9132 -l00V 0.3 n O.4n -1.0mA -l00nA -2.0V -4.OV PO-9.318
HEX-3 IRFC9133 -60V 0.3 n 0.4n -1.0mA -l00nA -2.0V -4.OV PO-9.318
P IRFC9230 -200V 0.5 n 0.8n -1.0mA -l00nA -2.0V -4.OV PO-9.349
IRFC9231 -l50V 0.5 n 0.8n -1.0mA -l00nA -2.0V -4.OV PO-9.349
IRFC9232 -200V 0.8 n 1.2n -1.0mA -l00nA -2.0V -4.OV PO-9.349
IRFC9233 -l50V 0.8 n 1.2n -1.0mA -l00nA -2.0V -4.OV PO-9.349

Handling and Shipping
HEXFET dice from International
Rectifier are shipped in anti-static
chip trays and sealed in plastic con-
tainers for protection during ship-
ment. Once opened, the dice must be
stored in a dry, inert atmosphere such
as nitrogen prior to assembly. Dice
should be handled with DuPont
Teflon-tipped vacuum pencils to pre-
vent mechanical damage. Any non-
conformance to the electrical or vis-
ual inspection specifications in this
brochure must be reported in writing
to International Rectifier within 60
days after shipment of the lot by
International Rectifier. International
Rectifier assumes no responsibilities
for die which have been subjected to
further processing such as mount-
down, wire bonding, or encapsula-
tion. In the interest of product im-
provement, the right is reserved to
make design or processing changes
without notification.
The anti-static chip trays are de-
signed to avoid the build-up of static
charge. International Rectifier HEX-
FETs have large gate capacitances
and thick oxide layers relative to low
level MOS devices. Though signifi-
cantly more rugged than such low
level devices, reasonable precautions
should be observed during handling
and assembly to prevent exceeding
the ±20V maximum gate-source volt-
age. The chip tray capacities are 400,
180,140,96,35and 16 die per tray for
HEX-Z, HEX-I, HEX-2, HEX-3,
HEX-4 and HEX-5 dice, respectively.
Visual Inspection of Ole
International Rectifier HEXFET
die are designed to meet the visual
inspection criteria of Mil-Standard
750B, Method 2072 with the excep-
tion of the specific criteria listed
below. HEXFET dice are visually
screened to a 1.0% AQL level. Mil-
Standard 750B, Method 2072 shall
apply except as follows (the para-
graph numbers refer to Method
2072):
PAR. 3.1. All inspection is at 30X
magnification.
PAR. 3.1.1.3 Localized areas of dis-
coloration are generally harm-
less films which are present in
varying degrees from lot to lot
and are not cause for rejection.
PAR. 3.1.3.d A die having attached
portions of the adjacent die up
to 10% of additional length is
acceptable, provided the die still
fits the chip tray cavity.
PAR. 3.2.3.1 Ink, chemical stains,
and other foreign material at-
tached to the surface of the
HEXFET die are isolated by a
vapox (silicon dioxide) layer,
except for the aluminum bond-
ing pads, and are not cause for
rejection.
Ole Mounting
The HEXFET dice have chromium-
nickel-silver drain metallization
which is suitable for solder preform
mounting using solders such as 95/5
PbSn or 92.5/2.5/5 Pb AgIn solder.
A-132
Any of the commonly used header or
substrate materials such as copper,
nickel-plated copper, and gold-plated
molybdenum, beryllia, and alumina
are acceptable. The substrate must be
freed of oxides prior to assembly
either by chemical cleaning or H 2 pre-
firing techniques. The HEXFET dice
should be cleaned prior to mount-
down in deionized water cascade
(one minute) followed by isopropyl
alcohol agitated bath (twice, one min-
ute each) and then 70°C nitrogen
chamber drying. Mounting is gener-
ally accomplished in a profiled belt
furnace. The furnace zone settings
will depend upon hybrid mass den-
sity, jigging, and belt speed. The
HEXFET die temperature must not
excee,d 400° C, nor be in the range of
350 to 400°C for greater than one
minute. A clean furnace of hydrogen
atmosphere is recommended, al-
though nitrogen atmosphere or form-
ing gas (nitrogen-hydrogen, 85% -
15%) is acceptable.
Wire Bonding
Electrical connection to the gate
and source aluminum bonding pads
is by ultrasonic wirebonding with
annealed 99% AI, 1% Si wire having
an elongation of 10%. The maximum
recommended wire diameter for
HEX-Z, HEX-I, HEX-2, HEX-3,
HEX-4 and HEX-5 is 2 mil, 4 mil, 8
mil, 10 mil, 20 mil and 20 mil, respec-
tively. Caution must be exercised
during wire bonding to insure that
the bonding footprint remains within
the bonding pad area; otherwise, HEXFET DIE and BONDING PAD DIMENSIONS
device failure can result. Likewise, (Not shown to scale)
wire bond equipment settings should
be optimized and a wire pull test per-
formed (e.g., see Method 2037, Mil- t

1
Standard 7508) to monitor wire bond Lo=Ni-
strength uniformity. Destructive sam-
ple testing and 100% non-destructive
testing is recommended. Rebonding
L"~

J
of wire bond rejects can be performed
although decreased yield can be ex-
pected from such reworks. Using
process controls as described above,
.;:;;r-
final assembly yields of 80% to 95%
can be achieved. L•• ~ I 1 SOURCE

Encapsulation
Prior to encapsulation, the diel
~w."~
W"!WI~
I
2.12
assembly must be kept in a moisture- THICKNESS" tIP
Figure 1. HEX-Z
free environment, as IGSS particularly Figure 4. HEX-3
is sensitive to surface moisture. If the
final package is non-hermetic, a high
grade electronic coating such as Dow I r

1 oj! l J
1
Corning RTV3l40 or equivalent LG"~ Lo GATE
should be applied. If the package is j
~

hermetic, the coating is optional.

Cleaning of the die in a freon vapor
degreaser prior to coating is recom-

r
mended. Immediately prior to en-
capsulation, a 1500 C, two-hour bake
should be performed to remove any
surface moisture. Capping of her- . I SOURCE I r"
0.081

metic packages should be performed

in a dry, nitrogen atmosphere.
L'"~
T
_0....
L. -f.ijf""
~
I SOURCE I
L.~WS'bn--+.1.~--iI
Ir---f--
Conclusion ~w.~~ ~ W"!!JlP~w•• ~~
4.32
I
The use of power MOSFET dice THICKNESS" ~ THICKNESS" ttl'
for hybrid assemblies can result in
significant reduction in overall pack- Figure 2. HEX-1 Figure 5. HEX-4
age size. In addition, the high gain
characteristics of the HEXFET can
allow further miniaturization by elim-
t
~ J
I J
1 1
inating complex drive circuitry. Sev-
eral HEXFET dice can readily be
Lo
"~.
~.1
GATE LG=
nr I GATE

mounted on the same heatsink to

form circuit configurations or to par-
allel devices. The HEXFET opera-

J J
tional advantages, thereby, can be
realized in very compact, custom
package configurations. D

Ls" ~
~
I SO~CE I Ls= .!O50
i'l7
i-
I SOURCE I
I ~w."~
I I ~w."~ I
~W"~--- ~W" tw-::---l
THtCKNE88" tflI THICKNES." m'

All dimensions shown in ~

mm Figure 3. HEX-2 Figure 6. HEX-5

A-133
NOTES IICiR I INTERNATIONAL RECTIFIER

A-134
INTERNATIONAL RECTIFIER IICiRI NOTES

A-135
NOTES IIC~RIINTERNAnONAL RECTIFIER

A-136
 ICiR I NOTES
INTERNATIONAL REC:TIFIER I

A-137
A-138
HEXFET SELECTOR GUIDE
BY PACKAGE, VOLTAGE RANGE AND "ON" RESISTANCE

TO-3 Package TO-220AB Package

VOLTAGE SERIES "ON" PAGE VOLTAGE SERIES "ON" PAGE

RANGE NUMBER RESISTANCE NUMBER RANGE NUMBER RESISTANCE NUMBER
6OV-100V IRFl20 0.3 Ohms 0-69 60V-100V IRF510 .6 Ohms 0-165
IRFl30 0.18 Ohms 0-75 IRF520 0.3 Ohms 0-171
IRFl40 0.085 Ohms 0-81 IRF530 0.18 Ohms 0-177
IRFl50 0.055 Ohms 0-87 IRF540 0.085 Ohms 0-183
IRF9130* 0.3 Ohms 0-263 IRF9520* 0.6 Ohms 0-275
2N6755 0.25 Ohms 0-1 IRF9530* 0.3 Ohms 0-281
2N6756** 0.18 Ohms 0-1 150V-200V IRF610 1.5 Ohms 0-189
2N6763 0.08 Ohms 0-17 IRF620 a.8 Ohms 0-195
2N6764'* 0.055 Ohms 0-17 IRF630 0.4 Ohms 0-201
150V-200V IRF220 0.8 Ohms 0-93 IRF640 0.18 Ohms 0-207
IRF230 0.4 Ohms 0-99 IRF9610* 3.0 Ohms 0-287
IRF240 0.18 Ohms 0-105 IRF9620' 1.5 Ohms 0-293
IRF250 0.085 Ohms 0-111 IRF9630' 0.8 Ohms 0-299
IRF9230* 0.8 Ohms 0-269 350V-400V IRF710 3.6 Ohms 0-213
2N6757 0.6 Ohms 0-5 IRF720 1.8 Ohms 0-219
2N6758"· 0.4 Ohms 0-5 IRF730 1.0 Ohms 0-225
2N6765 0.12 Ohms 0-21 IRF740 0.55 Ohms 0-231
2N6766*· 0.085 Ohms 0-21
450V-500V IRF820 3.0 Ohms 0-237
350V-400V IRF320 1.8 Ohms 0-117 IRF830 1.5 Ohms 0-243
IRF330 1.0 Ohms 0-123 IRF840 0.85 Ohms 0-249
IRF340 0.55 Ohms 0-129
IRF350 0.3 Ohms 0-135 ·P-Channel
2N6759 1.5 Ohms 0-9

m
2N6760*' 1.0 Ohms 0-9
2N6767 0.4 Ohms 0-25
2N6768 0.3 Ohms 0-25
450V-500V IRF420 3.0 Ohms 0-141 TO-39 Package
IRF430 1.5 Ohms 0-147
IRF440 0.85 Ohms 0-153 VOLTAGE SERIES "ON" PAGE
IRF450 0.4 Ohms 0-159 RANGE NUMBER RESISTANCE NUMBER
2N6761 2.0 Ohms 0-13
2N6762 1.5 Ohms 0-13 60V-100V IRFF110 0.6 Ohms 0-51
2N6769 0.5 Ohms 0-29 IRFF120 0.3 Ohms 0-57
2N6770 0.4 Ohms 0-29 IRFF130 0.18 Ohms 0-63
*P-Channel **Available to JAN/JANTX/JANTXV

HO-1 Package

'"
4-PIN HEXDlpTi•
NOTE: This Selector Guide lists only the first part
VOLTAGE SERIES "ON" PAGE number within a series of devices. Refer to
RANGE NUMBER RESISTANCE NUMBER appropriate listings for the complete HEXFET prod-
60V-100V IRFD110 0.6 Ohms 0-39 uct line.
IRFD1Z0 2.4 Ohms 0-33
IRFD9120* 0.6 Ohms 0-45
*P-Channel

A-139
 INDEX TO TO-3 PACKAGED HEXFETs BY VOLTAGE RATING
JEDEC Types
Listed within the TO-3 packaged HEXFETs are 16
JEDEC registered devices, sequentially numbered trom
2N6755 to 2N6770. The IRF part number immediately
following each JEDEC number is the International Rec-
tifier HEXFET equivalent.
Contact the tactory tor current JEDEC information
* JAN, JANTX, JANTXV Types.
The JEDEC numbered devices identified with a star are
available to JAN, JANTX, JANTXV specifications.
Electrical CharacteristIcs at 25°C unless noted otherwIse.

VDS RDs(on) ID Continuous IDM PD Max. VDS RDS(on) ID Continuous IDM PD Max.
Drain On-State Drain Current Pulsed Power Drain On-State Drain Current Pulsed Power
l~,ource Resist- (Amps) Drain Dissi- Source Resist- (Amps) Drain Dissl-
oltage ance Part 100°C 25°C Current Voltage ance Part 100°C 25 c C Current
(Volts) (Ohms) Numbers Case Case (Amps) W tion Page
( atts) (Volts) (Ohms) Numbers Case Case (Amps) W tlon Page
( atts)
500 0.4 2N6770 7.75 12.0 25 150 0-29 150 0.085 IPF251 19.0 30.0 120 150 0-111
500 0.4 IRF450 8.0 13.0 52 150 0-159 150 0.12 2N6765 16.0 25.0 50 150 0-21
500 0.5 IRF452 70 1?0 48 150 0-159 150 012 IRF253 16.0 25.0 100 150 D-111
500 085 IRF440 5.0 8.0 32 125 0-153 150 0.18 IRF241 110 ' 18.0 72 125 D-105
500 1.1 IRF442 4.0 7.0 28 125 D-153 150 0.22 IRF243 100 I
16.0 64 125 D-105
500 1.5 2N6762 30 4.5 7 75 0-13 150 0.4 IRF231 6.0 I 9.0 I 36 75 0-99
500 1.5 IRF430 3.0 4.5 18 75 0-147 150 0.6 2N6757 50 . 8.0 12 75 0-5
500 2.0 IRF432 2.5 4.0 16 75 0-147 150 0.6 IRF233 5.0 I8.0 I 32 75 0-99
500 3.0 IRF420 1.5 2.5 10 40 0-141 150 0.8 IRF221 5.0 20 40 0-93
500 4.0 IRF422 1.0 2.0 40 0-141 150 12 3.0 I 4.0
8 IRF223 2.5 16 40 0-93
450 0.4 IIRF451 8.0 130 52 150 0-159 100 2N6764 ! 70
450
450
450
0.5
0.5
0.85
2N6769
IRF453
IRF441
7.0 11.0
70 12.0
5.0 8.0
20
48
32
150
150
125
0-29
0-159
0-153
* 100
100
100
0.055
0055
0.08
0.085
IRF150
IRF152
IRF140
240
20.0
38.0
250 I 40.0
33.0
270
160
132
108
150
150
150
0-17
0-87
0-87
170 125 D-81
450 1.1 IRF443 4.0 7.0 28 i 125 0-153 100 0.11 IRF142 15.0 24.0 96 125 D-81
450 1.5 IRF431 4.5 18 i 0-147
450
450
450
2.0
2.0
30
2N6761
IRF433
IRF421
3.0
25
2.5
1.5
4.0
4.0
2.5
6
16
10
75
75
75
40
0-13
0-147
0-141
* 100
100
100
100
018
0.18
0.25
0.3
2N6756
IRF130
IRF132
IRF120
9.0
9.0
8.0
14.0
14.0
12.0
30
56
48
75
75
75
0-1
0-75
0-75
0-69
5.0 8.0 32 40
450 4.0 IRF423 1.0 2.0 8 40 0-141 I 100 0.4 IRF122 4.0 7.0 28 40 0-69
400 0.3 2N6768 9.0 14.0 25 150 0-25 60 0.055 IRF151 25.0 40.0 160 150 0-87
400 0.3 IRF350 9.0 15.0 60 150 0-135 60 0.08 2N6763 20.0 31.0 60 150 0-17
400 0.4 IIRF352 8.0 13.0 52 150 0-135 60 0.08 IRF153 20.0 33.0 132 150 0-87
400 0.55 IRF340 6.0 10.0 125 0-129 60
400 ,i 0.8 IRF342 5.0 8.0
40
125 0-129 60
0.085
0.11
IRF141
IRF143
17.0 27.0 108 125 0-81
32 15.0 24.0 96 125 0-81
400 1.0
* 400
400
400
1.0
1.5
1.8
2N6760
IRF330
IRF332
IRF320
3.5
35
3.0
5.5
5.5
4.5
3.0
8
22
18
12
75
75
75
40
0-9
0-123
D-123
0-117
60
60
60
60
0.18
0.25
0.25
IRF131
2N6755
IRF133
9.0
8.0
8.0
14.0
12.0
12.0
56
25
48
75
75
75
0-75
D-1
0-75
2.0 0.3 IRF121 5.0 8.0 32 40 0-69
400 2.5 IRF322 1.5 2.5 10 40 0-117 60 0.4 IRF123 4.0 7.0 28 40 0-69
350 0.3 IRF351 9.0 15.0 60 150 0-135
350 0.4 2N6767 7.75 12.0 20 150 0-25
350 0.4 IRF353 8.0 13.0 52 150 0-135
350 0.55 IRF341 6.0 10.0 40 125 I 0-129 P-Channel Types
3QO 0.8 IRF343 5.0 8.0 32 125 10-129,
350 1.0 IRF331 3.5 5.5 22 75 0-123 VDS RDS(ON) ID Continuous IDM Po Max.
350 1.5 2N6759 3.0 4.5 7 75 0-9 Drain D_n-State Drain Current Pulsed Power
350 1.5 IRF333 3.5 4.5 18 75 D-123 Source Resist- (Amps) Drain Dissi-
350 1.8 IRF321 2.0 3.0 12 40 0-117 Voltage ance Part 100°C 25°C Current Wion
350 2.5 IRF323 1.5 2.5 10 40 0-117 (Volts) (Ohms) Numbers Case Case (Amps) ( ails) Page

* 200
200
200
200
0.085
0.085
0.12
0.18
2N6766
IRF250
IRF252
IRF240
190
19.0
16.0
11.0
30.0
30.0
25.0
60
120
100
72
150
150
150
125
0-21
D-111
0-111
-200
-200
-150
0.8
1.2
0.8
IRF9230
IRF9232
IRF9231
-4.0
-3.5
-4.0
-6.5
-5.5
-6.5
-26
-22
-26
75
75
75
D-269
0-269
0-269
18.0 0-105
200 0.22 IRF242 10.0 16.0 64 125 0-105 -150 1.2 IRF9233 -3.5 -5.5 -22 75 0-269

* 200
200
200
0.4
0.4
0.6
2N6758
IRF230
IRF232
6.0
6.0
5.0
9.0
9.0
8.0
15
36
32
75
75
75
0-5
0-99
0-99
-100
-100
-60
0.3
0.4
0.3
IRF9130
IRF9132
IRF9131
-7.5
-6.5
-7.5
-12.0
-10.0
-12.0
-48
-40
-48
75
75
75
D-263
0-263
D-263
200 0.8 IRF220 3.0 5.0 20 40 0-93 -60 0.4 IRF9133 -6.5 -10.0 -40 75 0-263
200 1.2 IRF222 2.5 4.0 16 40 0-93
Dimensions in Millimeters and (Inches)
A-140
INDEX TO TO-220AB PACKAGED HEXFETs BY VOLTAGE RATING
10.66 (0.420) TO-220AB plastiC packaged HEXFETs offer a complete
range of smaller, lower cost power MOSFETs ideally
suited for commercial applications. Leads are on stand-
ard 100 mil centers for convenience in PC Board
16.51 (0.650) design. Savings in assembly costs can be realized
M~X. because these devices can be installed by working from
only one side of the board.
International Rectifier's advancements in construction
14.73 (0.580) techniques, materials and in-process production and
MAX.
quality control inspection ensure the high reliability of
N-Channel Types both the HEXFET die and the finished TO-220AB pack-
Electncal Charactenstlcs at 25'C unless noted otherwise
aged HEXFET.

VOS ROS lon } 10 Continuous 10M Po Max. VOS ROS(on) 10 Continuous 10M Po Max.
Orain On-State Oram Current Pulsed Power Drain On-State Orain Current Pulsed Power
Source Resist- (Amps) Orain Oissi- Source Resist- (Amps) Orain Oissi-
Voltage ance Part 100°C 25°C Current pat ion Voltage ance Part 100°C 25"C Current
(Volts) (Ohms) Numbers Case Case (Amps) (Watts) Page (Volts) tion Page
(Ohms) Numbers Case Case (Amps) ( atts) W
500 0.85 IRF840 5.0 8.0 32 125 0-249 100 0.6 IRF510 2.5 4.0 16 20 0-165
500 11 IRF842 4.0 7.0 28 125 0-249 100 0.8 IRF512 2.0 3.5 14 20 0-165
500 l5 IRF830 3.0 4.5 18 75 0-243 60 0.085 IRF541 17.0 27.0 108 125 0-183
500 2.0 IRF832 2.5 4.0 16 75 0-243 60 0.11 IRF543 15.0 24.0 96 125 0-183
500 3.0 IRF820 l5 2.5 10 40 0-237 60 0.18 IRF531 9.0 14.0 56 75 0-177
500 4.0 IRF822 lO 2.0 8 40 0-237 60 0.25 IRF533 8.0 12.0 48 75 0-117
450 085 IRF841 5.0 8.0 32 125 0-249 60 03 IRF521 5.0 8.0 32 40 0-171
450 11 IRF843 4.0 7.0 28 125 0-249 60 0.4 IRF523 4.0 7.0 28 40 0-171
450 l5 IRF831 3.0 4.5 18 75 0-243 60 06 IRF511 2.5 4.0 16 20 0-165
450 2.0 IRF833 2.5 4.0 16 75 0-243 60 08 IRF513 2.0 3.5 14 20 0-165
450 3.0 IRF821 l5 2.5 10 40 0-237
450
400
40
0.55
IRF823
IRF740
lO
6.0
I 10.0
2.0 8
40
40
125
0-237
0-231
400 0.80 IRF742 5.0
3.5
I 8.0
i 5.5
32
22
125 0-231 P-Channel Types
400 10 IRF730 75 0-225
400 15 IRF732 3.0 4.5 18 75 0-225 VDS ROSlon) 10 Continuous 10M Po Max
400 l8 IRF720 2.0 3.0 12 40 0-219 Drain On-State Oraln Current Pulsed Power
400 2.5 IRF722 l5 2.5 10 40 0-219 (Amps)
400 3.6 IRF710 lO 1.5 6 20 0-213 ~Iource Resist- Orain Oissi-
oitagE ance Part 100"C 25°C Current
400 5.0 IRF712 0.8 l3 5 20 0-213 (Volts) (Ohms) Numbers Case Case W tion
(AlTljlS) ( atts) Page
350 0.55 IRF741 6.0 10.0 40 125 0-231 -200 0.8 IRF9630 -4.0 -6.5 -~~ 75 0-299
350 0.8 IRF743 5.0 8.0 32 125 0-231 -200 1.2 IRF9632 -3.5 -5.5 -22 75 0-299
350 1.0 IRF731 3.5 5.5 22 75 0-225 -200 1.5 IRF9620 -2.0 -3.5 -14 40 0-293
350 1.5 IRF733 3.0 4.5 18 75 0-225 -200 2.4 IRF9622 -1.5 -3.0 -12 40 0-293
350 l8 IRF721 2.0 3.0 12 40 0-219 -200 3.0 IRF9610 -1.0 -1.75 -.7 20 0-287
350 2.5 IRF723 1.5 2.5 10 40 0-219 -200 4.5 IRF9612 -0.9 -1.5 -6 20 0-287
350 3.6 IRF711 1.0 1.5 6 20 0-213 -150 0.8 IRF9631 -4.0 -6.5 -26 75 0-299
350 5.0 IRF713 0.8 1.3 5 20 0-213 -150 1.2 IRF9633 -35 -5.5 -22 75 0-299
200 0.18 IRF640 11.0 18.0 72 125 0-207 -150 l5 IRF9621 -2.0 -3.5 -14 40 0-293
200 0.22 IRF642 10.0 16.0 64 125 0-207 -150 2.4 IRF9623 -1.5 -3.0 -12 40 0-293
200 0.4 IRF630 6.0 9.0 36 75 0-201 -150 3.0 IRF9611 -lO -1.75 -7 20 0-287
200 0.6 IRF632 5.0 8.0 32 75 0-201 -150 4.5 IRF9613 -0.9 -1.5 -6 20 0-287
I 200
200
0.8
1.2
IRF620
IRF622
3.0
2.5
5.0
4.0
20
16
40
40
0-195
0-195
-100
-100
0.3
0.4
IRF9530
IRF9532
-7.5
-6.5
12.0
10.0
-48
-40
75
75
0-281
0-281
200 1.5 IRF610 1.5 2.5 10 20 0-189 -100 0.6 IRF9520 -4.0 -6.0 -24 40 0-275
200 2.4 IRF612 1.25 2.0 8 20 0-189 -100 0.8 IRF9522 -3.5 -5.0 -20 40 0-275
150 0.18 IRF641 11.0 18.0 72 125 0-207 -60 0.3 IRF9531 -7.5 -12.0 -48 75 0-281
150 0.22 IRF643 10.0 16.0 64 125 0-207 -60 0.4 IRF9533 -6.5 -10.0 -40 75 0-281
150 0.4 IRF631 6.0 9.0 36 75 0-201 -60 0.6 IRF9521 -4.0 -6.0 -24 40 0-275
150 0.6 IRF633 5.0 8.0 32 75 0-201 -60 0.8 IRF9523 -3.5 -5.0 -20 40 0-275
150 I 0.8 IRF621 3.0 5.0 20 40 0-195
150 l2 IRF623 2.5 4.0 16 40 0-195
150 1.5 I'1F611 1.5 2.5 10 20 0-189 Characteristics common to a" TO-3 and TO-220AB HEXFETs.
150 2.4 IRF613 1.25 2.0 8 20 0-189
100 0.085 IRF540 170 27.0 108 125 0-183 TJ ~ -55'C to + 150'C Operating
100 0.11 IRF542 15.0 24.0 96 125 0-183 VGS(th) Gate Threshold = 20 to 40 Volts
100 0.18 IRF530 9.0 14.0 56 75 0-177 See Data Sheets for conditions
100 0.25 IRF532 8.0 12.0 48 75 0-177
100 0.3 IRF520 5.0 8.0 32 40 0-171 Lead Temperature = 300"C for to Seconds Max
100 0.4 IRF522 4.0 7.0 28 40 0-171
Dimensions in Millimeters and (Inches)
A-141
NUMERICAL INDEX TO TO-3 PACKAGED HEXFETs.

JEDEC Types
Listed within the TO-3 packaged HEXFETs are 16
JEDEC registered devices, sequentially numbered from
2N6755 to 2N6770. The IRF part number immediately
following each JEDEC number is the International Rec-
tifier HEXFET equivalent.
Contact the factory for current JEDEC information
* JAN, JANTX, JANTXV Types.
The JEDEC numbered devices identified with a star are
available to JAN, JANTX, JANTXV specifications.
Electrical Characteristics at 25°C unless noted otherwise

VOs, ROS (on), 10, Continuous 10M, P~' Max.

VOs, ROS (on), 10, Continuous 10M, P~, Max. Oraln On-State, Drain Pulse ower
Oram On-State, Orain Pulse ower Source Resis- Current Orain Dissi-
Source Resis- Current Orain Dissi- Part Voltage tance 100°C 25°C Current pation
Part Voltage tance 100°C 25°C Current pation Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
IRF420 500 0.3 1.5 2.5 10 40 0-141
IRF120 100 0.3 5.0 8.0 32 40 0-69 IRF421 450 0.3 1.5 2.5 10 40
IRF121 60 0.3 5.0 8.0 32 40 IRF422 500 2.0 1.0 2.0 8 40
IRF122 100 0.4 4.0 7.0 28 40 IRF423 450 2.0 1.0 2.0 8 40
IRF123 60 0.4 4.0 7.0 28 40 IRF430 500 1.5 3.0 4.5 18 75 0-147
IRF130 100 0.18 9.0 14.0 56 75 0-75 IRF431 450 1.5 3.0 4.5 18 75
IRF131 60 0.18 9.0 14.0 56 75 IRF432 500 2.0 2.5 I 4.0 16 75
IRF132 100 0.25 8.0 12.0 48 75 IRF433 450 2.0 2.5 4.0 16 75
IRF133 60 0.25 8.0 12.0 48 75 IRF440 500 0.85 5.0 8.0 32 125 0-153
IRF140 100 0.085 17.0 27.0 108 125 0-81 IRF441 450 0.85 5,0 8.0 32 125
IRF141 60 0.085 17.0 27.0 108 125 IRF442 500 1.1 4.0 7.0 28 125
IRF142 100 0.11 15.0 24.0 96 125 IRF443 450 1.1 4.0 7.0 28 125
IRF143 60 0.11 15.0 24.0 96 125 IRF450 500 0.4 8.0 13.0 52 150 0-159
IRF150 100 0.055 25.0 40.0 160 150 0-87 IRF451 450 0.4 8.0 13.0 52 150
IRF151 60 0.055 25.0 40.0 160 150 IRF452 500 0.5 7.0 12.0 48 150
IRF152 100 0.08 20.0 33.0 132 150 IRF453 450 0.5 7.0 12.0 48 150
IRF153 60 0.08 20.0 33.0 132 150 2N6755 60 0.25 8.0 12.0 25 75 0-1
IRF220 200 0.8 3.0 5.0 20 40 0-93 *2N6756 100 0.18 9.0 14.0 30 75 0-1
IRF221 150 0.8 3.0 5.0 20 40 2N6757 150 0.6 5.0 8.0 12 75 0-5
IRF222 200 1.2 2.5 4.0 16 40 *2N6758 200 0.4 6.0 9.0 15 75 0-5
IRF223 150 1.2 2.5 4.0 16 40 2N6759 350 1.5 3.0 4.5 7 75 0-9
IRF230 200 0.4 6.0 9.0 36 75 0-99 *2N6760 400 1.0 3.5 5.5 8 75 0-9
IRF231 150 0.4 6.0 9.0 36 75 2N6761 450 2.0 2.5 4.0 6 75 0-13
IRF232 200 0.6 5.0 8.0 32 75 2N6762 500 1.5 3.0 4.5 7 75 0-13
IRF233 150 0.6 5.0 8.0 32 75
2N6763 60 0.08 20.0 31.0 60 150 0-17
IRF240 200 0.18 11.0 18.0 72 125 0-105 *2N6764 100 0.055 24.0 38.0 70 150 0-17
IRF241 150 0.18 11.0 18.0 72 125 2N6765 150 0.12 16.0 25.0 50 150 0-21
IRF242 200 0.22 10.0 16.0 64 125 *2N6766 200 0.085 19.0 30.0 60 150 0-21
IRF243 200 0.22 10.0 16.0 64 125
IRF250 200 0.085 19.0 30.0 120 150 0-111 2N6761 350 0.4 7.75 12.0 20 150 0-25
IRF251 150 0.085 19.0 30.0 120 150 2N6768 400 0.3 9.0 14.0 25 150 0-25
IRF252 200 0.120 16.0 25.0 100 150 2N6769 450 0.5 7.0 11.0 20 150 0-29
IRF253 150 0.120 16.0 25.0 100 150 *2N6770 500 0.4 7.75 12.0 25 150 0-29
IRF320
IRF321
400
350
1.8
1.8
2.0
2.0
3.0
3.0
12
12
40
40
0-117 *P-Channel Types
JAN, JANTX, JANTXV Types
IRF322 400 2.5 1.5 2.5 10 40
IRF323 350 2.5 1.5 2.5 10 40 ROS (on), 10, Continuous 10M, P~, Max.
VDS'
IRF330 400 1.0 3.5 5.5 22 75 0-123 Drain On-State, Drain Pulse ower
IRF331 350 1.0 3.5 5.5 22 75 Source Resis- Current Drain Dissi-
IRF332 400 1.5 3.0 4.5 18 75 Part Voltage tance 100°C 25°C Current pation
IRF333 350 1.5 3.0 4.5 18 75 Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
IRF340 400 0.55 6.0 10.0 40 125 0-129 IRF9130 -100 0.3 -7.5 -12.0 -48 75 0-263
IRF341 350 0.55 6.0 10.0 40 125 IRF9131 -60 .0.3 -7.5 -12.0 -48 75
5.0
IRF342
IRF343
IRF350
400
350
400
0.8
0.8
0.3
5.0
9.0
8.0
8.0
15.0
32
32
60
125
125
150 0-135
IRF9132
IRF9133
IRF9230
-100
-60
-200
0.4
0.4
0.8
-6.5
-6.5
-4.0
-10.0
-10.0
-6.5
I -40
-40
-26
75
75
75 0-269
IRF351 350 0.3 9.0 15.0 60 150 IRF9231 -150 0.8 -4.0 -6.5 -26 75
IRF352 400 0.4 8.0 13.0 52 150 IRF9232 -200 1.2 -3.5 -5.5 -22 75
IRF353 350 0.4 8.0 13.0 52 150 IRF9233 -150 1.2 -3.5 -5.5 -22 75

A-142
NUMERICAL INDEX TO TO-220AB PACKAGED HEXFETs.

10.66 (0.420) TO-220AB plastiC packaged HEXFETs offer a complete

range of smaller, lower cost power MOSFETs ideally
sUited for commercial applications Leads are on stand-
ard 100 mil centers for convenience in PC Board
design. Savings in assembly costs can be realized
16.51 (0.650)
M~X.
because these devices can be installed by working from
only one side of the board.
International Rectifier's advancements in construction
14.73 (0.580) techniques, materials and In-process production and
MAX. quality control inspection ensure the high reliability of
N-ChannelTypes both the HEXFET die and the finished TO-220AB pack-
aged HEXFET
Electrical Characteristics at 25°C unless noted otherwise

VOS, ROS (on), 10, Continuous 10M, P~, Max. I

I
VD$, RDS (on), 10, Continuous
Drain On-State, Drain
10~' P~,ower
Pu se
Max.
Drain On-State, Drain Pulse ower Source Resis- Current Drain Dissi-
Source Resis- Current Drain Dissi- Part Voltage tance 100°C 25°C Current pation
Part Voltage tance 100 e 25°C Current pation
0
i Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
I
I IRF820 500 3.0 1.5 2.5 10 40 0-237
IRF510 100 0.6 2.5 4.0 16 20 0-165 IRF821 450 3.0 1.5 2.5 10 40
IRF511 60 0.6 2.5 4.0 16 20 I IRF822 500 4.0 1.0 2.0 8 40
IRF512 100 0.8 2.0 3.5 14 20 I IRF823 450 4.0 1.0 2.0 8 40
IRF513 60 0.8 2.0 3.5 14 20 IRF830 500 1.5 3.0 4.5 18 75 0-243
IRF520 100 0.3 5.0 8.0 32 40 0-171 IRF831 450 1.5 3.0 4.5 18 75
IRF521 60 0.3 5.0 8.0 32 40 I IRF832 500 2.0 2.5 4.0 16 75
IRF522 I 100 0.4 4.0 7.0 28 40 :, IRF833 450 2.0 2.5 4.0 16 75
IRF523 60 0.4 4.0 7.0 28 40 IRF840 500 0.85 5.0 8.0 32 125 0-249
IRF530 100 0.18 9.0 14.0 56 75 0-177 IRF841 450 0.85 5.0 8.0 32 125
IRF531 60 0.18 9.0 14.0 56 75 500 1.1 4.0 7.0 28 125
IRF532 100 0.25 8.0 12.0 48 75 I! i_ IRF842
IRF843 450 1.1 4.0 7.0 28 125
IRF533 60 0.25 8.0 12.0 48 75
IRF540
IRF541
100
60
0.085
0.085
17.0
17.0
27.0
27.0
108
108
125
125
0-183 i
IRF542
IRF543
100
60
0.11
0.11
15.0
15.0
24.0
24.0
96
96
125
125 I
I

IRF610 200 1.5 1.5 2.5 10 20 0-189

IRF611 150 1.5 1.5 2.5 10 20
IRF612 200 2.4 1.25 2.0 8 20
IRF613 150 2.4 1.25 2.0 8 20
IRF620 200 0.8 3.0 5.0 20 40 0-195
IRF621 150 0.8 3.0 5.0 20 40 P-Channel Types
IRF622 200 1.2 2.5 4.0 16 40
IRF623 150 1.2 2.5 4.0 16 40

I~
VD$, RDS (on), 10, Continuous 10M, P~' Max.
IRF630 200 0.4 6.0 9.0 36 75 0-201 Drain On-State, Drain Pulse ower
IRF631 150 0.4 6.0 9.0 36 75 Source Resis- Current Drain Dissi-
IRF632 200 0.6 5.0 8.0 32 75 Voltage tance 100°C 25°C Current pation
IRF633 150 0.6 5.0 8.0 32 75 Numbers (Volts) (Ohms) Case Case (Amps) (Watts) Page
IRF640 200 0.18 11.0 18.0 72 125 0-207 IIRF9520 -100 0.6 -4.0 -6.0 -24 40 0-275
IRF641 150 0.18 11.0 18.0 72 125 IRF9521 -60 0.6 -4.0 -6.0 -24 40
IRF642 200 0.22 10.0 16.0 64 125 IRF9522 -100 0.8 -3.5 -5.0 -20 40
IRF643 150 0.22 10.0 16.0 64 125 IRF9523 -60 0.8 -3.5 -5.0 -20 40
IRF710 400 3.6 1.0 1.5 6 20 0-213 ilRF9530 -100 0.3 -7.5 -12.0 -48 75 0-281
IRF711 350 3.6 1.0 1.5 6 20 IRF9531 -60 0.3 -7.5 -12.0 -48 75
IRF712 400 5.0 0.8 1.3 5 20 i IRF9532 -100 0.4 -6.5 -10.0 -40 75
IRF713 350 5.0 0.8 1.3 5 20 : IRF9533 -60 0.4 -6.5 -10.0 -40 75
IRF720 400 1.8 2.0 3.0 12 40 0-219 I IRF9610 -200 3.0 -1.0 -1.75 -7 20 0-287
IRF721
IRF722
350
400
1.8
2.5
2.0
1.5
3.0
2.5
12
10
40
40
i IRF9611
IRF9612
-150
-200
3.0
4.5
-1.0
-0.9
-1.75
-1.5
-7
-6
20
20
IRF723 350 2.5 1.5 2.5 10 40 IRF9613 -150 4.5 -0.9 -1.5 -6 20
IRF730 400 1.0 3.5 5.5 22 75 0-225 I IRF9620 -200 1.5 -2.0 -3.5 -14 40 0-293
IRF731 350 1.0 3.5 5.5 22 75 IRF9621 -150 1.5 -2.0 -3.5 -14 40
IRF732 400 1.5 3.0 4.5 18 75 IRF9622 -200 2.4 -1.5 -3.0 -12 40
IRF733 350 1.5 3.0 4.5 18 75 IRF9623 -150 2.4 -1.5 -3.0 '12 40
IRF740 400 0.55 6.0 10.0 40 125 0-231 IRF9630 -200 0.8 -4.0 -6.5 -26 75 0-299
IRF741 350 0.55 6.0 10.0 40 125 IRF9631 -150 0.8 -4.0 -6.5 -26 75
IRF742 400 0.8 5.0 8.0 32 125 IRF9632 -200 1.2 -3.5 -5.5 -22 75
IRF743 350 0.8 5.0 8.0 32 125 IRF9633 -150 1.2 -3.5 -5.5 -22 75

A-143
NUMERICAL INDEX: 4-PIN DIP HEXDIPs, TO-39, COMPLEMENTARY PAIRS

Electrical Characteristics at 25° C unless noted otherwise

Dual In-Line HEXDIPs
10 Continuous
HEXDIPs combine automatic insertion efficiency, a 1 Vos Drain Ros(on). Drain 10M Pulse Po Max.
Source On-State Current Drain Power P
watt heat sink tab with the HEXFET high performance, Part Voltage Resistance 25°C Current Dissipation age
quality, and reliability. These space saving HEXDIPs are Numbers (Volts) (Ohms) Case (Amps) (Watts)
end-stackable in rows of any length on 100 mil centers.
4-Pin. N-Channel Types
The low profile Nand P-Channel HEXDIPs can be used
on boards for cages with 0.5" board spacing. IRFD1Z0 100 2.4 0.5 2.0 1.0 0-33
IRF01Z1 60 2.4 0.5 2.0 1.0
IRF01Z2 100 3.2 0.4 1.5 1.0
IRF01Z3 60 3.2 0.4 1.5 1.0
IRF0110 100 0.6 1.0 4.0 1.0 0-39

~
IRFD111 60 0.6 1.0 4.0 1.0
IRFOl12 100 0.8 0.8 3.0 1.0
IRFOl13 60 0.8 0.8 3.0 1.0
4-Pin. P-Channel Types
IRF09120 -100 0.6 -1.0 -4.0 1.0 0-45
IRFD9121 -60 0.6 -1.0 -4.0 1.0
IRFD9122 -100 0.8 -0.8 -3.0 1.0
IRF09123 -60 0.8 -0.8 -3.0 1.0

Electrical Characteristics at 25' C unless noled otherwise

TO-39 Packaged HEXFETs. 10 Continuous
Vos Drain Ros(on). Drain 10M Pulse Po Max.
HEXFET power MOSFETs in TO-39 packages offer the Source On-State Current Drain Power
industry's lowest on-state resistance and best power Part Voltage Resistance 25°C Current Dissipation Page
Numbers (Volts) (Ohms) Case (Amps) (Watts)
ratios in this case style.
IRFF110 100 0.6 3.5 14 15 0-51
Used as switching devices, these hermetically IRFFlll 60 0.6 3.5 14 15
IRFFl12 100 0.8 3.0 12 15
sealed TO-39 HEXFETs are suitable for inter- IRFF113 60 0.8 3.0 12 15
facing logic signals in hostile environment

m
IRFF120 100. 0.3 6.0 24 20 0-57
applications such as military, instrumentation, IRFF121 60 0.3 6.0 24 20
process controls and on-site computer sys- IRFFl22 100 0.4 5.0 20 20
tems. Because the HEXFET process yields IRFF123 60 0.4 5.0 20 20
on-state resistances that are approximately IRFF130 100 0.18 8.0 32 25 0-63
30 percent lower than MOSFET technologies, IRFF131 60 0.18 8.0 32 25
signal integrity is high and component losses IRFF132 100 0.25 7.0 28 25
IRFF133 60 0.25 7.0 28 25
are low.

Electrical Characteristics at 25' C unless noted otherwise

TO-220AB Nand P-Channel
Vos Drain 10M Pulsed Po Max.
Complementary Pairs. Device Source Drain Power
Part Types Voltage Current Dissipation
Numbers Included (Volts) (Amps) (Watts) Page
Broad bandwidth and linearity make these complemen-
tary HEXFET pairs ideal for high-quality amplifiers in IRF5522 N-Channel +100 +12 40 0-255
P-Channel -100 -12 40
audio, ultrasonic, radar/sonar and general purpose
applications. Using these HEXFETs in complementary IRF5523 N-Channel +60 +12 40 0-255
P-Channel -60 -12 40
output stages allows two devices to share load current
equally and provide identical characteristics and low IRF5532 N-Channel +100 +25 75 0-259
P-Channel -100 -25 75
harmonic distortion.
IRF5533 N-Channel +60 +25 75 0-259
As presented in the table at right, each part number P-Channel -60 -25 75
covers two TO-220AB devices. Example: IRF5522
consists of one N-Channel device marked N F5522
and one P-Channel device marked P F5522.

A-144
INTERNATIONAL RECTIFIER IICiR I NOTES

A-145
II~~RIINTERNATIONAL RECTIFIER

JAN, JANTX, JANTXV and C.E.C.C. Test Capabilities.

I nternational Rectifier supplies approved to produce the C.E.C.C. devices

HEXFETs which meet the high reliability
requirements of the Military, DOE and NASA.
The manufacturing facilities and test lab of
International Rectifier at EI Segundo, CA, have
been surveyed by DESC to Appendix D of
MIL-S-19500F and have been approved to
produce the JAN, JANTX and JANTXV de-
vices listed on the pages that follow. The IR
facilities at Oxted, England have been
listed.
High reliability tests available include such
screens as pre-cap visual, oven bake,
temperature cycling, hermetic seal, constant
acceleration, burn-in with delta limits, and
tests such as salt atmosphere, altitude,
moisture resistance, vibration, shock, thermal
resistance and life tests.

A-146
A-147
A-148
MIL QUALIFIED HEXFETs

JAN, JANTX, JANTXV HEXFET POWER MOSFETs

Part Cross Current
Number Reference JAN JANTX JANTXV Voltage (25°C) MIL Spec Qualification

2N6756 IRF130 Yes Yes Yes 100V 14.0 A MIL-S-19500/542A 19500-488-81

2N6758 IRF230 Yes Yes Yes 200V 9.0 A MIL-S-19500/542A 19500-488-81
2N6760 IRF330 Yes Yes Yes 400V 5.5 A MIL-S-19500 /542A 19500-488-81
2N6762 IRF430 Yes Yes Yes 500V 4.5 A MIL-S-19500/542A "
2N6764 IRF150 Yes Yes Yes 100V 38.0 A MIL-S-195OO /543A 19500-490-81
2N6766 IRF250 Yes Yes Yes 200V 30.0 A MIL-S-195OO/543A 19500-490-81
2N6768 IRF350 Yes Yes Yes 400V 14.0A MIL-S-19500/543A "
2N6770 IRF450 Yes Yes Yes 500V 12.0A MIL-S-19500 /543A
"Qualification testing completed as of September, 1982. Consult factory for qualification approval status.

C.E.C.C. POWER HEXFET REGISTRATIONS AND APPROVALS

C.E.C.C.
Part Approval
Number Number
------~--------~~~
IRF120 CECC ............... 50-012-012
IRF120 CECC SA ........... 50-012-012
IRF120 CECC SB ............ 50-012-012
IRF120 CECC SC ............ 50-012-012
IRF120 CE~~ SO ............ ~~-~~~-~~~
IRF123 CE ............... - -
IRF130 CECC ............... 50-012-013
IRF130 CECC SA ........... 50-012-013
IRF130 CECC SB ............ 50-012-013
IRF130 CECC SC ............ 50-012-013
IRF130 ~~~~ SO ............ ~~-~~~-~g
IRF133 ............... - -
IRF150 CECC ............... 50-012-014
IRF150 CECC SA ........... 50-012-014
IRF150 CECC SB ............ 50-012-014
IRF150 CECC SC ............ 50-012-014
IRF150 ~~~~ SO ............ ~~-~~n~:
IRFl53 ............... - -
IRF220 CECC ............... 50-012-012
IRF220 CECC SA ........... 50-012-012
IRF220 CECC SB ............ 50-012-012
IRF220 CECC SC ............ 50-012-012
IRF220 ~E~~ SO ............ ~-~~~-m
IRF223 E .. .. .. .. .. .. ... - -
IRF230 CECC ............... 50-012-013
IRF230 CECC SA ........... 50-012-013
C.E.C.C. C.E.C.C.
Part Approval Part Approval
Number Number Number Number
----~~--------~~~ ~~~~~------~~--
IRF230 CECC SB ............ 50-012-013 IRF350 CECC SO ............ 50-012-014
IRF230 CECC SC ............ 50-012-013 IRF353 CECC ............... 50-012-014
IRF230 CECC SO ............ 50-012-013 IRF420 CECC ............... 50-012-012
IRF233 CECC ............... 50-012-013 IRF420 CECC SA ........... 50-012-012
IRF250 CECC ............... 50-012-014 IRF420 CECC SB ............ 50-012-012
IRF250 CECC SA ........... 50-012-014 IRF420 CECC SC ............ 50-012-012
IRF250 CECC SB ............ 50-012-014 IRF420 CECC SO ............ 50-012-012
IRF250 CECC SC ............ 50-012-014 IRF423 CECC ............... 50-012-012
IRF250 CECC SO ............ 50-012-014 IRF430 CECC ............... 50-012-013
IRF253 CECC ............... 50-012-014 IRF430 CECC SA ........... 50-012-013
IRF320 CECC ............... 50-012-012 IRF430 CECC SB ............ 50-012-013
IRF320 CECC SA ........... 50-012-012 IRF430 CECC SC ............ 50-012-013
IRF320 CECC SB ............ 50-012-012 IRF430 CECC SO ............ 50-012-013
IRF320 CECC SC ............ 50-012-012 IRF433 CECC ............... 50-012-013
IRF320 CECC SO ............ 50-012-012 IRF450 CECC ............... 50-012-014
IRF323 CECC ............... 50-012-012 IRF450 CECC SA ........... 50-012-014
IRF330 CECC ............... 50-012-013 IRF450 CECC SB ............ 50-012-014
IRF330 CECC SA ........... 50-012-013 IRF450 CECC SC ............ 50-012-014
IRF330 CECC SB ............ 50-012-013 IRF450 CECC SO ............ 50-012-014
IRF330 CECC SC ............ 50-012-013 IRF453 CECC ............... 50-012-014
IRF330 CECC SO ............ 50-012-013 IRF9130 CECC .............. 50-012-015
IRF333 CECC ............... 50-012-013 IRF9130 CECC SA .......... 50-012-015
IRF350 CECC ............... 50-012-014 IRF9130 SECC SB ........... 50-012-015
IRF350 CECC SA ........... 50-012-014 IRF9130 SECC SC ........... 50-012-015
IRF350 CECC SB ............ 50-012-014 IRF9130 SECC SO ........... 50-012-015
IRF350 CECC SC ............ 50-012-014 IRF9133 SECC .............. 50-012-015

CUSTOM HEXFET PACKAGING

Military and hi-rei requirements often
dictate special packages which opti-
mize mechanical or thermal designs
and result in weight and/or space
savings.
In addition to the T03 and T039 her-
metic packages shown in the catalog,
HEXFETs can be obtained on special
order in such industry standard pack-
ages as T061, T066, 14-pin ceramic side
braze. etc. Consult sales representative
for more information.
A-149
/ICiRIINTERNATIONAL REC:TIFIER

Radiation Resistance of HEXFETs®

(HEXFET is the trademark for International Rectifier Power MOSFETs)

This report presents test results that
demonstrate the radiation hardness
of HEXFETs in Space and Military
applications.
The effects of ionizing and neutron
radiation on HEXFETs are impor-
tant in this type of duty, and it is
necessary for the circuit designer to
know what parameters are effected
and by how much. Armed with this
information, HEXFET circuitry can
be designed to circumvent the effects
of radiation, and provide reliable
operation even in the most "hostile"
environments.
Ionizing Radiation
The main effect of ionizing radia-
tion is to introduce charges into the
gate oxide which produce a shift in
the gate-to-source threshold voltage.
VGS(th) of N-Channel HEXFETs de-
creases with increasing total dose,
while VGS(th) of P-Channel HEX-
FETs increases with increasing total
dose. This change of threshold volt-
age is essentially independent of dose
rate, and depends only on total dose.
HEXFET gate drive circuitry for
switching applications can be de-
signed to nullify these threshold volt-
age shifts by overriding them with
appropriate biasing levels.
Figure I shows typical variation of
gate-to-source threshold voltage with
total dose for IRFISO and IRF2S2
HEXFETs, for various biasing con-
ditions. The threshold voltage is tested
with a fixed applied drain-to-source
voltage. (The commonly used test
condition of the gate tied to the drain
then stays practically constant at this In a practical switching applica-
value with further increase in radia- tion, the HEXFET is switched ON
tion. The applied gate voltage of -IOV and OFF at the switching frequency,
ensures that the HEXFET remains and the above static biasing condi-
fully OFF, even after I megarad of tions are not directly applicable. It
exposure. could be expected from the above
The variation of threshold voltage results, though, that a negative gate
is about the same for the biased ON bias of say -lOY during the OFF
(Io = lA, curve 2) and biased OFF period would ensure correct switch
VGS =-IOV, curve I} test conditions, OFF for total doses up to I megarad.
for doses up to about 30k rads. There- This was verified by measuring the
after threshold voltage decreases change in threshold voltage of an
much more rapidly for the biased ON IRF ISO HEXFET in a switching cir-
condition, reaching -IOV at about cuit after a I megarad dose. The
120k rads. This relatively rapid shift operating frequency was SOkHz, and
of threshold voltage for the biased the gate was switched between ± 12.0V.
ON condition must be considered Peak drain current was about 2.SA,
and accounted for in linear applica- and peak drain voltage about 2SV.
tions, by providing a sufficient dyna- The threshold voltage after I mega-
mic range of control of gate voltage. rad was -4.4V - a shift that actually
Figure 2 shows similar relationships was less than for the above static
between threshold voltage and dose biasing conditions.
rate for the IRFl30 HEXFET. Figure 3 shows the shift of thresh-
4
r----___ -.
01R~
2
01RF1~
0
'-
"i''\'
~
0
-2
RADIATION VG~")
BIAS TE T
~ CURVE CONDITIONS CONDITIONS
Ul -4
CJ
> 1 VOS= 5V,
VGS=-1OV
10 = 4.5 rnA,
VOS=10V ~RF150
-6 10= 1A, 10=4mA,
2

\
VGS= +1OV VOS=1OV
can be misleading for high dose lev-
VOS-OV, 10 -1rnA,
els, because as VGS decreases, Vos 3
-8 VGS +1OV VOS 30V
and hence los also tend to zero, giv-
ing and "artificial" threshold voltage 4 VOS=OV, 10='1 mA ~IRF150
reading that always remains posi- VGS= +1OV VOS=3OV
tive.) -10
10" 10" 10" 10"
For the biased OFF (VGS = -IOV) DOSE - RADS (Si)
test, (curve I) the threshold voltage
reaches about -6V at 2 x 105 rads, Figure 1. Typical Gate Threshold Voltage vs. Total Gamma (COSO) Dose, IRF150 & IRF252,

A-150
old voltage with radiation dose for a
P-ChanneIHEXFET -the1RF9132
In this case, threshold voltage in-

-
4
creases with increasing dose - that
is, the P-Channel HEXFET becomes
more biased OFF as dose increases. 2
Figure 4 shows the effect on drain- ...........
~
source leakage current of total radia-
tion dose, for various N-Channel
0
HEXFET types. Notice, as would be
~
expected, that with VGS = 0 the leak-
age current increases quite rapidly
when a dose level is reached at which
...J
g -2 ~
\~
the threshold voltage approaches :2"
e
tJ)
zero. Also to be expected, the increase Cl -4
of loss with increasing dose can be >
largely nullified simply by applying a
negative bias voltage to the gate, as
shown for the IRF252 in Figure 4. -6
RADIATION
BIAS
VGljlthJ
TET
CURVE CONDITIONS CONDITIONS
\ ~ ......... ."
Figure 5 shows the relationship
between drain-source leakage current
and total dose for the IRF9132 P-
-8
1 VOS= 5V,
VGS = -10V
10-lA,
10= 4.5mA,
VOS= 10V
10-4mA,
1
Channel HEXFET. For this device 2
VGS= +10V Vos=10V CD
the leakage current tends to saturate -10 IX
at a dose of about lOOk rads, and 1()3 10' 10" 10'
does not increase further. DOSE - RADS (Si)
Table I shows typical values of on-
resistance (R OS(gn» and input capaci- Figure 2. Gate Threshold Voltage vs. Total Gamma (CO") Dose. IRF130.
tance (Cis,) for IRFI50 and IRFI30
HEXFETs, before and after I mega-
rad of radiation. These results demon- -9
strate that gamma radiation has no
practical effect on these parameters. I
-8 RADIATION VG~thl TEST
Neutron Radiation
The effect of neutron radiation is to
iii
-7
BIAS CONDITIONS
VGS =-10V
(BIASED ON)
CO DTIONS
VOS = VOS = VGS / IRF9132
produce an increase in the HEXFET's VOS= OV 10=1 mA
on-resistance. The increase of on-
I-
...J
0 -6 /
I
resistance depends on the resistivity ~
of the silicon - and hence the volt-
age rating of the HEXFET. It is ~
Cl -5
almost negligible for a 100V rated
HEXFET, but can be appreciable for
a 400V rated device at high neutron
>
/
--
-4
~
fluence.
Figure 6 shows typical measured
relationships between on-resistance -3
and neutron fluence level for 100V
and 400V rated HEXFETs. On-re-
sistance of the 100V hardly increases -2
uptoafluenceof2X lO 13 neutr/cm 2, 1()3 10' 10' 10'
while at 10 14 neutrjcm 2 it shows DOSE - RADS (Si)
about a 30% increase. The 400V
HEXFET's on-resistance increases Figure 3. Typical Gate Threshold Voltage vs. Total Dose (150KV) X-ray. IRF9132.
by about 25% at 2 X 10 13 neutr / cm2,
and by about 150%at 10 14 neutr/cm2 .
The increase of on-resistance caused TABLE 1: ROS(on) and Clss before and after 1 megarad ionizing (C060)
by neutron radiation will result in radIation.
increased conduction losses in switch-
ing applications, but will have little IRFI50 IRFI30
practical effect in linear applications.
It can be allowed for at the design ROS(on) Ciss ROS(on) Ciss
stage by appropriate choice of the ohms pF ohms pF
HEXFET/heatsink combination. Before After Before After Before After Before After
Conclusion 0.38 0.35 2480 2500 0.127 0.111 515 520
The primary effect of ionizing radi- 0.34 0.34 2500 2530 0.128 0.135 510 540
ation on HEXFETs is to cause a 0.127 0.106 673 710
decrease in the threshold voltage of 0.33 0.31 2500 2590

A-151
 RADIATION
BIAS
IDSS
TEST
! cp 1_ YGS=O
CURVE CONDmONS CONDITIONS
10' Vas- OY, V~~_==,
1 V~lOY
10'
4
Vas OY, Vas~3OV,

10'
2 VGS= + 10V
CO-
Vas OY,
VGS=-lOY

~=l00Y,
I 4
,.---
~
3
l~;-1:Y
GS=OY
I ~
11
VGS = OY, Vas = 400V,
../
l~;~'ZY
4 VGS= OY

!J ./""
~ RADIATION
BIAS CONDITIONS m;T~mONS
J(1
4
Vos l00Y
/' :t4Eo1OY
( ON)
10 Vos-OY Yos=OY
IRF350Q) JJ 10'
10' 4 10' 10'

lV
-
0IRFl50 DOSE - RAOS (SI)

01-
l"igure 5. Typical Drain-Source Leakage Current vs. Total Dose
Yos--1OY (150KV X-ray). IRF9132.

111"'10' 10' 2 4 10' 2

DOSE - RAOS (SI)

Figure 4, Typical Drain-Source Leakage Current vs. Total Dose.

IRF150.IRF252 & IRF350.

2.5

N-Channel types and an increase for

P-Channel types. The amount of
J
change of threshold voltage is a func-
tion of the biasing conditions, parti-
cularly at radiation doses which are
1-2.0
r---- RADIATION TEST CONDITION:
=VOS =OV
I
sufficient to change the polarity of
the threshold voltage (N-Channel
HEXFETs) - typically -lOY - al-
Z
::J
IX:
W
a.
VGS
I
/
lows reliable switching operation at
doses up to at least I megarad (Si). ~
o 1.5 /
The primary effect of neutron radia-
tion is to cause an increase in on-
resistance. This is almost negligible
IX:

400V HEXF:!:--- ~
/ ./
for low voltage (IOOV) HEXFETs,
but can be significant at higher neu-
tron fluence levels for higher voltage
types. By allowing for the increase of
1.0
100VHEXFET
/
on-resistance at the design stage, pre-
dictable and reliable operation of o
10" 1012 1013 1014
H EXFETs in a neutron radiation en-
vironment can be readily achieved.D NEUTRON FLUENCE (neutr./cm,)

Figure 6. On-resistance vs. Neutron Fluence Level.

A-152
INTERNATIONAL RECTIFIER IIC;R I NOTES

A-153
Life, Power-Age, Environmental and Military Test Capabilities

1. Life Tests and Power-Age Capabilities

International Rectifier has complete facilities to provide life tests and power-age
on all devices which they manufacture.
A. High temperature storage life testing up to 200°C.
B. Voltage temperature stress tests at both ambient and elevated conditions.
C. Free air operation life. Test capability, 1000 positions for power transistors, and 1SOO positions for
power diodes.
D. HTRB test capabilities. Several thousands of positions for VGS and for VDS burn-in.
E. Computerized readout equipment.

2. Environmental Test Capabilities

TEST CAPABILITY
Acceleration, Sustained (Centrifuge) SO-30,OOOg (Standard)

Altitude (Barometric Pressure, Reduced) 4S0,ooO Ft. Simulated Altitude with T A=2SoC
Capability

Moisture Resistance 2S-8SoC 8S% RH

Salt Atmosphere/Spray 2SoC to 71°C, up to 20% Salt Solution by Weight

Seal-Gross, Fine Leak 1 X 10-8 atm cc/sec, Fluorocarbons, Mineral Oils,

FC-43, Hydrostatic Pressure: 0 - 100psig

Symbolization (Resistance to Solvents)

Shock (Mechanical) Pulse Shape - Approximately Half-sine

SOO - 1500g at O.S - 1.0 msec

Solderability

Temperature Cycling -6S 0 C to 200 0 C

Terminal Strength (Lead Integrity) Lead Fatigue, Tension, Stud Torque,

Terminal Torque

Thermal Shock

Vibration, Fatigue 60Hz,5 - 20g

Vibration, Variable S - 2000 Hz as Limited by 1 inch DA and 60

inches/second Velocity; 0-20g (Standard)

A·154
 INTERNATIONAL RECTIFIER I::ICiR I

3. Military Test Standard Capabilities

TEST CATEGORY MIL-STD-202 MIL-STD-750

Barometric Pressure (reduced) Method 105 Method 1001

All Conditions All Conditions

Moisture Resistance Method 106 Method 1021

Resistance to Solvents Method 215 Method 1022

Salt Atmosphere Method 101 Method 1041

All Conditions

Seal, Gross Leak Method 112B, Conditions Method 1071

A,B &0 Conditions
C,D & F

Seal, Fine Leak Only Method 112B, Method 1071,

Condition C Condition H
Procedure lilA

Solderability Method 208 Method 2026

Soldering Heat Method 210 Method 2031

All Conditions

Temperature Cycling Method 102 Method 1051

All Conditions All Conditions

Terminal Strength Method 211 Method 2036

All Conditions All Conditions

Terminal Shock (Glass Strain) Method 107 Method 1056

All Conditions All Conditions

Acceleration, Sustained (Centrifuge) Method 212 Method 2006

All Conditions

Shock (Mechanical) Method 213 Method 2016

Conditions D,E & F

Vibration, Fatigue Method 201 Method 2046

Vibration, Variable Frequency Method 204 Method 2056

A-155
NOTES IICiR I INTERNATIONAL RECTIFIER

A-156
INTERNATIONAL RECTIFIER IICiR I NOTES

A-157
NOTES IIC)R I INTERNATIONAL RECTIFIER

A-158
INTERNATIONAL RECTIFIER IICiR I NOTES

A-159
NOTES II\)RIINTERNATIONAL REC:TIFIER

A·160
INTERNATIONAL REC:TIFIERIIC~RI NOTES

A-161
NOTES I:ICiR I INTERNATIONAL REC:TIFIER

A-162
INTERNATIONAL REC:TIFIERIICiRI NOTES

A-163
NOTES IICiR I INTERNATIONAL RECTIFIER

A-164
INTERNATIONAL REC:TIFIER IICiR I NOTES

A-165
HEXFET DEVICE
CHARACTERISTICS
AND RATINGS
The HEXFET devices listed in this DATABOOK represent
the International Rectifier power MOSFET line as of
August, 1982. Some changes to earlier published Data
Sheets have been made. Therefore the data presented
here supersedes all previous specifications.
Reference is made to all previous Data Sheets in the
upper corner of each page beginning a specific series.
This will permit holders of previous materials to
compare the current data with that appearing on the
earlier Data Sheets, if necessary.

In the interest of product improvement, International

Rectifier reserves the right to change specifications
at any time without notice.

A-166
 PO-9.333

INTERNATIONAL RECTIFIER IJ:\iR I

HEXFET® TRANSISTORS 2N6755
.JEDEC REGISTERED 2N6756
N-CHANNEL
POWER MOSFETs

100 Volt, 0.18 Ohm HEXFET Features:

The HEXFET@ technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Curr
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great • No Second Breakdow:::n:'lllllllil-"""""'"
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature a" of the we"
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of para"eling, and temperature stabil-
ity of the electrical parameters. Part Number VOS RDS(on) 10

They are we" suited for applications such as switching 2N6755 60V O.25Q 12A
power supplies, motor controls, inverters, choppers,
2N6756 100V O.1SQ 14A
audio amplifiers, and high energy pulse circuits.

22.2210.8751
CASE STYLE AND DIMENSIONS 342 MAX. DIA. 11.43 0.450
IO.l35IMAX~'5 .201

~ ttEATING
T =+LANE

k~ I~'~I OIL-j 10.1610.401 MIN.

TWO PLACES TWO PLACES

;'U1
.
61
.51 1DIA.
TWO PLACES

DRAIN
ICASEI

SOURCE

t MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO-204AA ITO-31

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-1
2N6755 and 2N6756 Devices
Absolute Maximum Ratings
Parameter 2NS755 2NS756 Units
VOS Drain - Source Voltage SO' 100' V
VOGR Drain - Gate Voltage (RGS - 1 Mil) SO' 100' V
'0@TC-250C Continuous Drain Current 12' 14' A
'O@TC=lOOoC Continuous Drain Current S.O· 9.0' A
'OM Pulsed Drain Current 25 30 A
VGS Gate - Source Voltage ±20' V
PO @TC-250C Max. Power O~ssipation 75* (See Fig. 11) W
PO@TC- 100°C Max. Power Dissipation 30' ISee Fig. 11) W
Linear Derating Factor O.S' ISee Fig. 111 W/K
'LM Inductive Current, Clamped ISee Fig. 1 and 21 L = 100 ~H
A
25 I 30
TJ Operating and
-55* to 150' °C
Tstg Storage Temperature Range
Lead Temperature 300' (O.063 in. 11.6mml from case for lOs) °C

Electrical Characteristics @ T C = 2So C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2NS755 SO - - V VGS= 0
2N6756 100 - - V '0= 1.0mA
VGSllhl Gate Threshold Voltage ALL 2.0' - 4.0' V VOS=VGS"O=lmA
'GSSF Gate - Body Leakage Forward ALL - - 100" nA VGS - 20V
'GSSR Gate - Body Leakage Reverse ALL - - 100" nA VGS - -20V

lOSS Zero Gate Voltage Drain Current - 0.1 1.0' mA VOS - Max. Rating, VGS '" 0
ALL
- 0.2 4.0· mA V OS = Max. Raling, VGS = 0, T C = 125°C

VOSlonl Static Drain-Source On~State 2N6755 - - 3.0" V VGS -10V,'0 = 12A

Voltage
0 2N675S - - 2.52' V v GS = 10V, '0 = 14A
ROSlonl Static Drain-Source On--State 2N67S5 - 0.20 0.25" n VGS = 10V,'0 = SA
Resistance CD
2N6756 - 0.14 O.lS" n VGS = 10V, '0 = 9A
ROSlonl Static Drain-Source OnooState 2N6755 - - 0.45' n VGS = 10V, '0 = SA, T C = 125°C
Resistance CD 2NS756 - - 0.33' n VGS - 10V, '0 = 9A, TC = 125°C
gf. Forward Transconductance CD ALL 4.0' 5.5 12.0' S ltil VOS = 15V,'0 = 9A
Ciss Input Capacitance ALL 350' 600 SOO' pF
VGS = 0, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL 150" 300 500' pF
See Fig. 10
C,U Reverse Transfer Capacitance ALL 50" 100 150' pF

'd lonl Turn-On Delay Time ALL - - 30' n. VOO '" 36V, '0 = 9A, Zo = 1511
I, Rise Time ALL - - 75' n. ISee Figs. 13 and 141

'd lofll Turn-Off Delay Time ALL - - 40' ns (MOSFET switching times are essentially
If Fall Time ALL 45' n. independent of operating temperature.)

Thermal Resistance
R thCS Case-to-Sink Mounting surface flat, smooth, and greased.
R thJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratings and Characteristics

- - Modified MOSF ET symbol

~
'S Continuous Source Current 2N675S 12'
IBody Oiodel A showing the integral
2N6756 14'
reverse P-N junction rectifier.
ISM Pulsed Source Current 2N67S5 25
IBody Oiodel A
2N6756 30
VSD Diode Forward Voltage CD 2N67S5 O.SS' - 1.7' V TC = 25°C, '5 = 12A, VGS - 0
2N6756 0.90' - 1.S· V T C - 25°C, 'S = 14A, VGS = 0

I" Reverse Recovery Time ALL - 300 - ns T J = 150o C,'F = 'SM,d'F/dt-l00 A/~s
ORR Reverse Recovered Charge ALL - 4.0 - ~C T J - 150°C, 'F - ISM, d'F/dt -100 A/~s

*JEDEC registered values. CD Pulse Test: Pulse Width ~ 300 ,usec, Duty Cycle ~ 2%

VARY Ip TO OBTAIN
REnUI REO PEAK Il

vGs=:EF"=L
'l4_---6---..... ......,.,.,.--I
Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms
0-2
 2N6755 and 2N6756 Devices

20

16
10VVS:V

V
sl •• pu iSETEJT _ -
I
7V_
-
20

16
r-- ~ •. PU!LSE TElT
Vas· 15V
,
J
1/

i'"
5 12 I
"
I-

J =
VGS·6V= ~
/' a'"z 8
/h
~ If/
y- ---
Q

~
E TJ = +12S OC hI
~ ,(/,
TJ = 25°C

10 20 30 40
4V-
- 50
r--- TJ:~550C
I ~V
10
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

10 10
80 #5 PU LSE TEST
lOJ ffi V f-- Iso •• p! LSE JST _ - lOy"
-9l~
/.
9~;: l'Y ~/ /' ay, ~ ~ ~
8V~
~ VI' V T"-: ~ ~ ~
~ ~ ./6~/ ~ ~6V
'/ /~ ~V

~y
~L
~

V
1-'5V
~
- ~
~
V' - ~
fo-SV- ~

~
~
-
~ ~ /"

0.4 0.8 1.2

VGS·4V
i' I
16 2.0
~ I--
~V
"
0.4
V

0.8 1.2 1.6

Vt S =4i= =
2.0
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
Fig. 6- Typical Saturation Characteristics
Fig. 5- Typical Saturation Characteristics (2N6756)
(2N6755)
50

~~
10
2N6756
10

r-H ~~ 2~s'5 r~
,
, ,
20
2N~7J6
~,. I~

ij-
.,,;
/ ' I--- - TJ ·-55 0C

T; - 250~

TJ· 125°C
5
I-
~
~
co
'-'
10

5.0
- ·2N6755
I"
"' , ," 1'.
100~,- '--- f--

z 1 ms
;;: "i

,b I
",..-i"'"

Vos = 15V
'"'"
-'"
2.0
- TJ = 150°C MAX.
'I\..
, 10 mj
SING LE PU LSE
I so(' PULjETESi 1.0
DC
2N6755 2N6756 l " - e-
0.5
10 15 20 25 4.05.0 10 20 50 100 200
10. DRAIN CURRENT (AMPERES) VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 7 - Typical Transconductance Vs. Drain Current Fig. 8 - Maximum Safe Operating Area
0-3
2N6755 and 2N6756 Devices
2000

2.2 ~GS ~ J
f~ 1 MHz
1600
i/
V
V ~ 1200
./
..
u
z
V
---
l-

~
i:;

./
,,/ ~u 800 C'SS

V
u-
\
~
c
o

'" 0.6
V VGS ~ 10V 400 1\ ~
\ I--. L
0.2
-40 40 80
I r 9A

120
I

160
- ....
m ~
.1
C'SS

~ ~ ~
TJ, JUNCTION TEMPERATURE (OCI VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI
Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitance V,. Drain-ta-Source Voltage
80
LISM,2N6756
I--
70 I'\."\ ~
A
u; 60
r'\. ~
d1S.2N6756

.
l-
I-

~ 50
z "r\'\
'"
w
a.. 10
:E
~
...z I
0 w I
;:: '"
:t 40 '":::> 1 1
~
u I J
0
'"~
~
30 \ w
u
a:
:::>
0
'"
!b
r--TJ=1500n TJ = 25 0C

.P 20
I'" I
10 ~ j J
'1]\ 1.0
o
VSO, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
20 40 60 80 100 120 140
TC, CASE TEMPERATURE (OC) Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig. 11 - Power V,. Temperature Derating Curve

Voo '" 36V

PULS:~IOTH~
VGS (on) --+r.!:::---~
911% 90% 50%
INPUT, Vi
Va 10%
--..,.--~~ TO SCOPE VGS (off) INPUT PULSE

Id (onl J: RISE TIME

'II (off)

VOS(Offl--eO%
Ir]
OUTPUT,Vo 90%
VOS (on) 1--"'-:---
......
ton ---I I..-- toff

Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-4
 PD-9.334

INTERNATIONAL RECTIFIER IICiR I

HEXFET® TRANSISTORS 2N6757
.JEDEC REGISTERED 2N675B
N-CHANNEL
POWER MOSFETs

200 Volt, 0.4 Ohm HEXFET Features:

The HEXFEP' technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis-
tors. The efficient geometry and unique processing of
• Low Drive Curr
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great
device ruggedness. • No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. VOS ROS(on) 10
Part Number
They are well suited for applications such as switching 2N6757 150V O.6n 8A
power supplies, motor controls, inverters, choppers,
audio amplifiers, and high energy pulse circuits. 2N6758 200V O.4n 9A

22.22(0.8751
CASE STYLE AND DIMENSIONS 3.42 MAX.DIA. 'B~ 18';~

(0"3y~~" SEATING
T PLANE

d·~ m';~1
DIL-II-- 10.16(0.401 MIN.
TWO PLACES TWO PLACES
26.67
(1.0501 MAX.

HI
. m'l~'1
. 1 DIA .
TWO PLACES

~.~
DRAIN
J 1
(CASEI

'1.09 (0.043)
MAX. DIA.
39.96 (1.573)
MAX.
I MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO·204AA (TO-3)

ACTUAL SIZE Dimensions in Millimeters and IInches)

0-5
2N6757 and 2N6758 Devices
Abeolute Maximum RatIngs
Parameter 2NS757 2NS756 Units
Vos Drain - Source Voltage 150' 200' V
VDGR Droin - Gatt Voltage IRGS' 1 MOl 150' 200' V
IDOTC~25oC Continuoul Drain Current 8.0· 9.0· A
ID OTC ·100"C Continuous Drain Current 5.0' S.O· A
IDM Pulsed Drain Current 12 15 A
VGS Gatt - Sou ..... Voltage .%20' V
P D OTC·25oC Mex. Power Dissipation 75' lSoa Fig. 111 W
PD OTC ·100"C Max. Power Dillipation 30' lSoa Fig. 111 W
Linea, Derating Factor O.S· lSoa Fig. 111 W/K
ILM Inductive Current. Clamped lSoa Fig. 1 and 21 L = 100 "H
A
12 I 15
TJ Operating and
-55' to 150' °C
Totg Storage Tampar.ture Range
Lnd Temperature 300' 10.063 in. 11.6mml frome ... for 10s1 uC

Eleclrlcal Charact.lltlce @ TC = 2S0 C (Un.... 0therwIee Specified)

Parameter TVPO Min. Typ. Max. Units Ta.t Conditions
BVDSS Droin - Source Brukdown VoI_ 2N6757 150 - - V VGS=O
-.
2NS756 200 - - V ID= 1.0mA
VGSlthl Gatt Th ......old VoI_ ALL 2.0' - 4.0' V VDS' VGS' ID = 1 mA
IGSSF Gatt - Body Lukoge Forward ALL - - 100' nA VGS' 20V
IGSSR Go'" - Body Lukoge Rove... ALL - - 100' nA VGS' -20V
'DSS Zero Gate Voltage Orei" Current
ALL
- 0.1 1.0' mA VDS • Max. Rating, VGS = 0
- 0.2 4.0' mA Vos = Max. Rating, VGS =0, T C = 125°C
V Dston) Static Drain·Sour<:e On-6t818
Vol_ 0
2N6757 - - 4.8' V VGS' IOV,I D =8A
2N6756 - - 3.S· V VGS = 10V,I D = SA
ROS(on) Static Drain--$ource On-&tatt 2N8757 - 0.4 O.S· a VGS = 10V,I D = 5A
Roslstan.. 0 2NS758 - 0.25 0.4' a VGS = 10V,i D - 8A
RDSlonl Static Drain·Sourc. On-Statt
RlSiltlnce CD
2NS757 - - 1.13' a VGS = 10V, Ie = 5A, TC = 1250 C
2NS756 - - 0.75' a VGS = 10V,ID = SA, Tc = 125°C
..,. Forward Transconductance (1) ALL 3.0' 5.0 S.O· SIUI VDS - 15V, Ie = SA
Ciu Input Capacitance ALL 350' 600 800' pF
VGS' 0, VDS· 25V, f· 1.0 MHz
COli OUtput Capacitance ALL 100' 250 450' pF
Soa Fig. 10
Cm Reverw Transfer Capacitance ALL 40' 80 150' pF

'" lonl
Turn·On Delay Time ALL - - 30' ns VeD ~90V,ID =SA, Zo = 15a
tr Ri.. Time ALL - 50' n. lSoa Figs. 13 and 141

'" loffl
Turn.()ff Dalay Tim. ALL - - 50' n. (MOSFET switching times are . . .ntially
t, Fall Time ALL - - 40' n. independent of operating temperature,)

Thermal R. . . .nce
I RthJC Junction-to-Case I ALL I - I - I 1.67' I KIW I I
I RthCS ca...to-5ink J ALL
J - J 0.1
J J KIWL Mounting surface flat, smooth, and greased.
J
I RthJA Junction-to-Ambi.nt I ALL I I I 30 I KIW I Free Air Operation I
Body-Drain Diode RatIngs and Characterl8t1cs
- -

~
IS Continuous Source Current 2NS757 8.0· Modifi.d MOSFET symbol
A
IBody Dioda) 2N6758 - 9.0· showing the integral
reverse P-N junction rectifier.
ISM Pulsed Source Current 2NS757 - - 12 A
IBodY Diodal 2NS756 - - 15
VSD Dioda Forward Voitogo 0 2NS757 0.75' - 1.50* V TC =25°C, IS' SA, VGS· 0
2NS758 O.SO· - 1.60' V TC = 25°C, IS = SA, VGS =0
t" Revene Recovery Time ALL - 650 - ns TJ. 150oC,iF = ISM, dlF/dt = 100 A/~.
QRR Rever.. Recovered Charge ALL - 10 - "C TJ = 150°C, iF' ISM, dlF/dt - 100 AI".

*JEOEC registerld values. CD Pulse Test: Pulse Width < 300 ",sec, Duty Cycle';;; 2%

VARY fp TO OBTAIN
REQUIRED PEAK IL

VGS-"R OUT

I L + - _ - o - - -....-.I\o..,.,.--I
Fig, 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms
0-6
 2N8757 and 2N8758 Devices

20
IOV'8V 80,... PULSE TEST 10
10 ... pU LSE TEST
r- VD~'15V ~I
IS 7V
rt
J
L
VGS'SV
TJ' >IZSOC
1£
T/'2S0 C
I'-..
TJ' -SSoc
~ [')
.........
5V
60
.ill
4V La v
20 40 80 80 lOll
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Vas. GATE·TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

10 10

1/ ~ ~ ~~
~

i" pulsE ...4!!1 ~ lL~

~~ ~~V
~)OV
I-- TEIT - 9V_ e---- c- !a.'PULETJr
~~t
,
~V- r-- r-- 9V-

~ ~ I'---~v ~ ~~V r-
V '\.~-
II ~

~~
r-- r-
J ...........
VGS=SV-
~r--VGs'SV-

i-'
~
I~ -.J. ~
J ~
,..-
rr 1
V- t- r--
I
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 5- Typical Saturation Characteristics

" VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)

Fig_ 6- Typical Saturation Characteristics

(2N6757) (2N6758)

20
2N6758
0 10";-

10 ~~.
F~~ r- ~ -, to- 1-
2N6767
8 iii
l:l 5.0
I' 100"._

6
TJ = -SSoc

TJ = 2S0~
- i
!Ii;
'~
I'.
I~
./
~
...-
~
II:
2.0
!'.
, 1'. 1m. -
4

211. V
.. V
V/ ~ .......
~
- TJ =moc '"'"z
~ 1.0
c
_0

0.5 TJ = IS00C MAX.

"'
~
~
10m. _

III
r
VOS= 15V
SINGLE PULSE
~~ l DC
~o"' pJLSE TEST 2N67S7 2N6.i58
0.2
10 5.0 10 20 50 100 zoo 500
10. DRAIN CURRENT (AMPERES) Vos. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
Fig. 7 - Typical Transconductance Vs_ Drain Current Fig. 8 - Maximum Safe Operating Area

0-7
2N6757 and 2N6758 Devices
2000

2.2 VJsoo
1= 1 MHz
...z
w 1/ 1600
~ 1.8 /
ia:1i V ...
Be
~~ 1.4
/ ...=
z
1200

=>« V ~
~
~
--
~~
~~ /~ .... 800 Cits
:!:- 1.0
«
a:
c V l\
\, ,I
"-
-=
iii V' VGS = 10V
/ 400
........
~
c 0.6 10 = 6A
a:
-I 1 ......
"'" Cns
0.2
-40 40 80 120 160 10 20 30 40 50
TJ. JUNCTION TEMPERATURE (OCI VDS. DRAIN·TO-SOURCE VOLTAGE (VOLTS)
Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage

- "'\..,
80
/ / " Ir·2N6758

70 10
, -; IS. 2N6758
'\. I

,
80
........
iii
'\ I I
~ I I
z 50
c
i= '\ I II
~ 40
ill I
i5
'\
r---"~''''~
a:
w 30
...'"31:
....; 20 I"\. TJ = 25 0 C

10 l". I I
'1\ 1.0
o
VSO. SOURCE-TO-ORAIN VOLTAGE (VOLTS)
20 40 80 80 100 120 140
TC. CASE TEMPERATURE (OCI Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig. 11 - Power Vs. Temperature Derating Curve
PULSEI~IDTH~
VGS (on) --+~~--~
INPUT. Vi ~O% 90% 50%
Vo
-·...---~TOSCOPE VGS (off) INPUTPULSE 10% INPUT PULSE
RISE TIME
L FALL TIME

VOS(Off)--8O%
OUTPUT. Vo
Id (on)

90%
1'-1 I<J (off)

90%
:]1
1 1
-+- 10%

VOS (on) IF;""-+="

lon......j I--Ioff

Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-8
 PO-9.335

INTERNATIONAL RECTIFIERII(~RI

HEXFET® TRANSISTORS 2N6759

.JEDEC REGISTERED 2N676D
N-CHANNEL
POWER MOSFETs

400 Volt, 1.0 Ohm HEXFET Features:

The HEXFETI!> technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Curr
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VOS ROS(on) 10

They are well suited for applications such as switching 2N6759 350V 1.50 4.5A
power supplies, motor controls, inverters, choppers, 2N6760 400V 1.00 5.5A
audio amplifiers, and high energy pulse circuits.

22.22 (0.87SI
CASE STYLE AND DIMENSIONS 342 MAX. DIA. 11.43 0.4S0
(0.1351 MAX~6' S o. SOl

~
T =+LANE
ttEATlNG

a;I8'~IDIL-l 10.16 (D.401 MIN.

TWO PLACES TWO PLACES

Hlm'1611DIA
. . Sl
TWO PLACES

J~ ~'
'-1.09 (0.043)
DRAIN
(CASEI

MAX.OIA.
39.96 (1.573)
MAX.
t MEASURED AT SEATING PLANE

Conforms to JEOEC Outline TO·204AA (TO·3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-9
2N6759 and 2N6760 Devices
Absolute Maximum Ratings
Parameter 2N67S9 2N6760 Units
VoS Drain - Source Voltage 350' 400' V
VoGR Drain - Gale Vollage (RGS - 1 MnI 350' 400' V
10@TC=2SoC Continuous Drain Current 4.5' 5.5" A
10@TC= l000C Continuous Drain Current 3.0" 3.5" A
10M Pulsed Drain Current 7.0 8.0 A
VGS Gate - Source Voltage ±20" V
Po @TC=2SoC Max. Power Dissipation 75" (See Fig. 11 I W
Po@TC- 100°C Max. Power Dissipation 30" (S.. Fig. 11 I W
Linear Derating Factor 0.6' (See Fig. 11 I W/K
ILM Inductive Currant, Clamped (See Fig. 1 and 2) L = 100 I'H
A
7.0 I 8.0
TJ Operating and
-55* to 150- °c
Tstg Storage Temperature Range
Lead Temperature 300· (0.063 in. (1.6mm) from case for 10s) °c

Electrical Characteristics @ TC = 250C (Unless Otherwise Specified)

Parameter Typo Min. Typ. Max. Units Test Conditions
BVoSS Drain - Source Breakdown Voltage 2N67S9 350 - - V VGS' 0
2N6760 400 - - V 10=1.0mA
VGS(lh) Gate Threshold Voltage ALL 2.0' - 4.0· V VoS = VGS. 10 = 1 mA
IGSSF Gate - BodV Leakage Forward ALL - - 100' nA VGS = 20V
IGSSR Gate - BodV Leakage Reverse ALL - - 100' nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - 0.1 1.0· mA VoS = Max. Raling. VGS = 0
ALL
0.2 4.0' mA VoS = Max. Raling. VGS - O. T C = 125°C
V 05(00) Static Drain-Source On-Stat. 2N6759 - - 7.0· V VGS = 10V. 10 = 4.5A
Vollage (0
2N6760 - - 6.7' V VGS = 10V. 10 = S.5A
RoS(on) Static Drain-Source OneState 2N6759 - 1.0 1.5' n VGS = 10V. 10 = 3A
Resistance (0 2N6760 - O.S 1.0' n VGS = 10V. 10 - 3.5A
RoS(on) Static Drain-Source On..state 2N6759 - - .. 3.3· n VGS = 10V. 10 =3A. T C = 125°C
Resistance (0 2N6760 - - 2.2' n VGS = 10V. 10 =3.SA. TC = 12SoC
gIl Forward Transconductance CD ALL 3.0' 4.5 9.0' S (U) VoS = ISV. 10 = 3.SA
Cis. Input Capacitance ALL 350' 600 800' pF
VGS =O. VoS = 2SV. I = 1.0 MHz
Coss Output Capacitance ALL 50' 150 300" pF
See Fig. 10
Cru Reverse Transfer Capacitance ALL 20' 40 80' pF

'd (onl Turn-On Delay Time ALL - - 30' n. Voo ~ 175V.10 = 3.SA. Zo - ISn
'r Rise Time ALL - - 35' ns (See Figs. 13 and 141
'd (0111 Turn-Off Delay Time ALL - - 55' ns IMOSFET switching times are essentially

It Fall Time ALL - - 35' n. independent of operating temperature.)

Thermal Resistance
RthJC Junction-to-Case
R,hCS Cose·lo-Sink Mounting surface flat, smooth. and greased.
R thJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratings and Characteristics

~
IS Continuous Source Current 2N6759 4.5' Modified MOSFET symbol
A showing the integral
(Body Diode) 2N6760 5.5'
reverse P·N junction rectifier.
ISM Pulsed Source Current 2N6759 7.0
(Body Diode) A
2N6760 - - S.O
VSo Diode Forward Voltage CD 2N6759 0.70' - 1.4" V T C = 25°C. IS - 4.5A. VGS=0
2N6760 0.75' - 1.5· V T C = 2SoC.IS = S.SA. VGS = 0
I" Reverse Recovery Time ALL - 550 - ns TJ -150°C. IF" ISM.dIFldl= 100 AIl's
ORR Reverse Recovered Charge ALL - 8.0 - I'C T J = lS00C.I F =ISM. dlFldl = 100 AI~s
* JEDEC registered values. CD Pulse Test: Pulse Width, 300 ~sec, Duty Cycle ~ 2%

VARY tp TO OBTAIN

VGS=~
REOUIREO PEAK IL

OUT
r'p-lIL~ .... ,
....../. , E,
IL+----o---_-'lM.---'
'-------
Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms
0-10
 2N6759 and 2N6760 Devices

I~J 80 /.IS PU lSE TEST

I
I
VGS > 5.5V
J 80J,lslpULSE TEJr J
Ves = 15V

f--

3
5.0V
TJ > +125 0C

TJ > 250~-......."'--.,

TJ=-550C~

4.5V

I
f'J
/'/
4iV .LL,I/
50 100 150 200 250 300
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

-
5 5

,I J J )V
Icl~ffv I--- alo /.1.5 PU~SE TElT I'~{fv
!-VGS> 5.0V- ~
A~
80",s PULSE TEST
10-- _VGS-5.0V-
4

If! ~
J ,;
If J
JV 4.5V- 10- ~ 45V- ~

If )
V
II
I 4.0V-
--- V
I 4T~ t=

10 10
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 5- Typical Saturation Characteristics Fig. 6- Typical Saturation Characteristics

(2N6759) (2N6760)

10 o 2N6760
10~s-

2N6759
~60
5. o I-r-I"'o... '. r-. I
I

~
~
_\ I\..
\2N6759
I'\.
, ,~ T
il- 100 ~s

TJ>-550C-
::;
2.0
1\ -, I

.-...-
~

TJ > 25°C ~a::: 1.0

I' I'\. I'\. !
1/t::: ....- I ~ I ms

-
TJ -12Jc_ z ,'-
~ ...
~V
I
I-- " D. 5 11'\. 1'1
_0 101m!
!JV I--'"' I'\. i
TJ ' 150°C MAX.
'l\!
ilf ves> 15V 0.2 t-- SINGLE PULSE
I DC
,80"' p~ LSE TE,ST
1
2N6759I 2~6760
D. I
4 10 10 20 50 100 200 500
'0. DRAIN CURRENT (AMPERES)
Vos. ORAIN-TO·SOURCE VOLTAGE (VOLTS)

Fig. 7 - Typical Transconductance Vs_ Drain Current Fig. 8 - Maximum Safe Operating Area
0-11
2N6759 and 2N6760 Devices
2000
7.VGS=OT
J
2.2 1= 1 MHz
..,zw I 1600
V
~ 1.8
i1i
a: V ...
~c
wW ... v !.., 1200
~~ 1.4
z
=>« V ~

~h..
./ ;:;
~~ ~
00
;3 800 Ciss
,,"Z
/

"
;!;- 1.0 .;
«
a:
c V
g-
o; V VGS = 10V 400 ~ ~L
~~
~ 0.6
Ir3.5~ '\
0.2
" 1'-~
-40 40 80 120 160 10 20 30 40 50
TJ. JUNCTION TEMPERATURE (OC) VOS. DRAIN·TO.sDURCE VOLTAGE (VOLTS)

Fig.9-Normalized Typical On-Resistance V,. Temperature Fig. 10 - Typical Capacitance V,. Drain·to-Source Voltage
80

10
- ~ I
7 1sM.2N6760
I
"\
7 , IS.2N6760

en
5~
z
60

50
"'\ \.
lZ
a:

i... 1
/ I
0
;::
... '\ z
w

/I I
a:
« a:
iii
40 ..,=>
0
a:
~ 30
...
'\ ..,a:w
=>
o ',' "'''' TJ = 25 0 C

'"""\,
0 '"~
...6 20

10
1.0 I I
o
VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (OC) Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig. 11 - Power V,. Temperature Derating Curve

VGS (on) --+~---~

INPUT, Vi
_,..-_ _ Vo
TO SCOPE VGS(off) INPUT PULSE
FALL TIME
td (on) 1== td (off)

OUTPUT, Va
VOS(Off)~O% tr-I 90%
VOS lon)~
1~_-!."::':".7
ton ---.J I.-- toft

Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-12
 PD-9.336

INTERNATIONAL RECTIFIER IIgR I

HEXFET® TRANSISTORS 2N6761

.JEDEC REGISTERED 2N6762
N-CHANNEL
POWER MOSFETs

500 Volt, 1.5 Ohm HEXFET Features:

The HEXFET'" technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VDS ROS(on) ID

They are well suited for applications such as switching 2N6761 450V 2.0n 4.0A
power supplies, motor controls, inverters, choppers, 2N6762 500V 1.5n 4.5A
audio amplifiers, and high energy pulse circuits.

22.2210.875)
CASE STYLE AND DIMENSIONS

' 't:r';J 'f~""

T
Hi I~·~;il
nNO PLACES
01'---11--
PLANE

10.1610.40) MIN.
TWO PLACES
26.67
(1.050) MAX.

Hfmall OIA.
TWO PLACES

j!~""
DRAIN
ICASE)

'1.09 (0.043)
MAX.DIA.
39.96 (1.573)
MAX.
t MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO·204AA (T().3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-13
2N6761 and 2N6762 Devices
Abeolute Maximum Ratlnge
'arameter 2N6761 2N6762 Units
VOS Drain - Source Voltage 450- 500- V
VOGR Drain - Ga.. Voltage (RGS = 1 Mn) 450- 500- V
10@TC·2SoC Continuous Drain Current 4.0· 4.5- A
10@TC· l00"C Continuous Drain Current 2.5- 3.0- A
10M Pulsed Drain Current 6.0 7.0 A
VGS Gate - Source Voltage '*20- V
PO @TC·250C Max. Power Dissipation 75- (Saa Fig. 111 W
PD. TC = l00"C Max. Power Diuipation 30- (Saa Fig. 111 W
Linear Oerating Factor 0.6- (Saa Fig. 111 W/K
ILM Inductive Current, Clamped (Saa Fig. lInd 21 L· l00,.H
A
6.0 I 7.0
TJ ()peratlng and
-55* to 150.· °c
Tstg Storage Temperature Range
Lead Temperature 300- (0.063 in. (1.6mmllrom c_lor 10s1 °c

Electrical Characterlstice @ TC = ZSoC (Un'" Otherwise Specified)

Parameter Type Min. Typ. Mox. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2N6761 450 - - V VGS=O
2N6762 500 - - V 10=4.0mA
VGS(thl GI" Threshold Voltage ALL 2.0· - 4.0· V VOS=VGS,IO=lmA
IGSSF Go.. - Body Leakage Forward ALL - - 100- nA VGS = 20V
IGSSR GI.. - Body Lelklge Rever.. ALL - - 100- nA VGS = -20V
lOSS Zero Gate Vattage Drain Current
ALL
- 0.1 1.0· mA VOS • O.B X Max. Rating, VGS - 0
0.2 4.0- mA VOS • Max. Rating. VGS = 0, T C = 2SoC to t 2SoC
VOS(on) Static Drain-Source On-State 2N6761 - - B.O- V VGS- 1OV,1 0 '4A
Voltage (£)
2N6762 - - 7.7- V VGS = 10V,I 0 = 4.5A

ROS(onl Static Drain-Source On-State 2N6761 - 1.5 2.0· n VGS = 10V,I 0 = 2.5A
Resistance CD 2N6762 - 1.3 1.5- n VGS· 10V, 10 = 3.0A
ROS(onl Static Drain-Source On-&tate 2N6761 - - 4.4- n VGS· 10V, 10 = 2.SA, T C = 125°C
Resistance 0)
2N6762 - - 3.3- n VGS - 10V, 10 = 3.0A, TC = 12SoC
lit. Forward Transconductance (£) ALL 2.5- 3.5 7.5- S(UI VOS' 16V, 10 ' 3A
Cia Input Capacitance ALL 350- 600 BOO- pF
VGS - 0, VOS = 25V,I- 1.0 MHz
COli Output Capacitance ALL 25- 100 200- pF
Saa Fig. 10
C'" Reve .... Transfer Capacitance ALL IS- 30 60- pF
td (onl Turn-On Delay Time ALL - - 30- M VOO ~ 225V, 10 = 3A, Zo = 15n
tr Ri"Time ALL - - 30- n. (Saa Figs. 13 and 141
td (0111 Turn-Off Delay Time ALL - - 55- n. (MOSFET lWitching tim.. are ....nti.lly
tl F.n Time ALL - 30- n. independent of operating temperature.)

Thermal R..lstanee
RthJC Junction-to-Case
RthCS Case-to-5ink Mounting surface flat, Imooth. and greased.
RthJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratings and Characterlatlce

2N6761 - - 4.0* Modilied MOSF ET symbol

~
IS Continuous Source Current A
(Body Diode) 2N6762 - 4.5* showing the integral
reverse P-N junction rectifier.
ISM P.ulsed Source Current 2N6761 - - 6.0
A
(Body Diode) 2N6762 - - 7.0
VSO Diode Forward Voltage CD 2N6761 0.65- - 1.3* V TC' 25°C, IS = 4A, VGS' 0
2N6762 0.7* - 1.4- V TC - 25°C, IS -4.5A, VGS - 0
trr Rever. Recovery Time ALL - 500 n. TJ = 150o C,I F -ISM,dIF/dt-l00A/,..
QRR Reverse Recovered Charge ALL - 7.0 - ~C T J - 150°C, IF - ISM, dlF/dt· 100 AI,..
-JEOEC ragist.red ,"Iull. (£) Pulse Test: Pul.. Width ~300~IOC, Duty Cycl. ~ 2%

VARY tp TO OBTAIN
REQUIRED PEAK IL VDS

vGs=!R

IL....-_<>-_-....._""""--'
Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms
0-14
 2N6761 and 2N6762 Devices

&
10V

5
I I I
~ '.0 pi lULSJTEST
5.5V
S

4
SO,.., PULSE TEST

Vos '16V
,
VGS' 5.0V
3
_ Tp +12SoC
I-- I

2
TJ;2S 0 C,
TJ' -SSOC,
~
1'-.,................ IJ
T 1 rJ./
.! JVI
100 200
T 300
~
VGS. GATE·TQ·SOURCE VOLTAGE (VOLTS)
VDS. DRAIN·TD·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

5 S

c- J. J. mJ
PU
10,VY'
V55V_
._[ f-- I-- It SIS PU !SE TEll ~~
II"'sy-
4
l# 4 l/
~ ....... so! I-:: l/I-""" soL~
3
~V 3 ~~
)
l1li"" ,/
2
1/
VGS·4.SV= j:;;;;
2 1/ VGS·45V-
~" ~ j..--"
) ~'P'
1
1
V
)
4.0j"'= ~
~~ 4y"""
If'' 10
10
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 5- Typical Saturation Characteristics Fig. 6- Typical Saturation Characteristics

(2N6761) (2N6762)

S
.I
TJ ' -S5 0':-
n~
~~
0
2N6762

-..;;;
lOllS

,
5. o~ 2N6761

4
./ Vi 2N6761 1'1..
1'-
1'.
7 Tr 2s,!- fZ
'"
~
"""\1'1.. I'
'. r" 1',11
~01- r-
2.0
1/ ./ '"
:! 1\ 100JIS
3

I l/
I- I' i, I:
2
II V . /V
~
'"
~

"z
1.0

I"'
"
I' 1 ms
~ 0.5
j / l/
'" "1'.. I' II
_0 .11
1 IJ V TJ ' 1500 c MAX.
l\.
"I\. I IIi'
I~ Vos '16V 0.2 f-- SINGLE PULSE

r 1°"' pUlLS. TOr 0.1

op±
2N67611 2N6762
10 20 50 100 200 500
ID. DRAIN CURRENT (AMPERES) VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 7 - Typical Transconductance Vs. Drain Current Fig. 8 - Maximum Safe Operat~ng Area
0-15
2N6761 and 2N6762 Devices
2000

2.2
v J=GS 0'

w
'-'
/ 1600
t= 1 MHz

:i /
~ 1.8
ffi ...
a: / ~

~3 1200

.....
W
WW / '-'
z

l'
~~ 1.4
=> ..
./ u
~~
00
'7z
~- 1.0
/ ..
:t
'-' 800 Ciss

a:
c /
U
\
-= \
..s
~ 0.6 V VGS = 10V 400
......
a:
/ Ir1.5~ \ ~
r
~ ""'-
0.2
-40 40 80 120 160 10 20 30 40 50
TJ.JUNCTION TEMPERATURE (DC) VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage
80

- I [ISM.2N6762

..
...~
70

60 '"'" ~
'\ I
I
I
I
~ IS.2N6762

~
z
0
50 i\.
'\
/
,"·,~I
;::
:t 40
iii

"'"
i5
a: TJ = 250 C
~ 30
~
...6 20

10 ~ 1.0
J I
'1\ o
VSD.SOURCE·TO·DRAIN VOLTAGE (VOLTS)
1

20 40 60 80 100 120 140

TC. CASE TEMPERATURE (DC) Fig. 12 - Typical Body·Drain Diode Forward Voltage
Fig. 11 - Power Vs. Temperature Derating Curve
VUD '" 225V PULSEt~IDTH~
VGS (on) --+I":!~----:
90% 50%
~
O%
INPUT. Vi
Vo 10%

e-l
- - - - - p T O SCOPE VGS (off) INPUTPULSE INPUT PULSE
RISE TIME FALL TIME

"., 1= "..
.~~:.~ [jl'-9_0%__-+-~";;9~0%~~
Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-16
 PD-9.337

INTERNATIONAL RECTIFIER IIC~R I

HEXFET® TRANSISTORS 2NB7B3
.lEDEC REGISTERED 2NB7B4
N-CHANNEL
POWER MOSFETs

100 Volt, 0.055 Ohm HEXFET Features:

The HEXFEP' technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Curre
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Parallelin
ance combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VOS ROS(on) 10

They are well suited for applications such as switching 2N6763 60V o.osn 31A
power supplies, motor controls, inverters, choppers, 2N6764 100V O.055n 3SA
audio amplifiers, and high energy pulse circuits.

22.2210.8751
CASE STYLE AND DIMENSIONS 342 MAX DIA. 11.43 0.450)
10.1351 MA~X6.3SI0.2S
22.23 (0.875) ~ ttEATING

:X
1'"::_1 T
1.6010.0631 DlA.
1.45 (0.0571 -,
I
lANE
1219 0.480
1118 440

a~ ~
TWO PLACES TWO PLACES
.,/~, 26.67
1.0501 MAX
4.0810.1611 OIA
ll4(D.i5jj .
TWO PLACES

DRAIN
ICASEI

j" 1.60 (0.063)

MAX. DIA.
39.96 (1.573)
MAX.
t MEASURED AT SEATING PLANE
Conforms to JEDEC Outline TO·204AE (Modified TO·3)
ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-17
2N6763 and 2N6764 Devices
Absolute Maximum Ratings
Parameter 2N6763 2N6764 Units
VOS Orain.- Source Voltage SO' 100' V
VOGR Drain - Gate Voltage (RGS = 1 Mnl SO' 100' V
10@TC=2SoC Continuous Drain Current 31' 3S' A
10@TC= 100°C Continuous Drain Current 20' 24' A
10M Pulsed Drain Current 60 70 A
VGS Gate - Source Voltage .±20· V
PO @TC-2SoC Max. Power Oinipation ISO' (See Fig. 111 W
PO @TC-l00oC Max. Power Dissipation SO' (See Fig. 111 W
Linear Derating Factor 1.2' (5.. Fig. 111 WIK
ILM Inductive Current. Clamped (See Fig. 1 and 2) L - 100 ~H
A
SO I 70
TJ ()pe~ating and
-55* to 150· °c
T"g Storage Temperature Range
Lead Temperature 300* (0.063 in. (l.6mm) from case for 10s1 °c

Electrical Characteristics @ T C = 250C (Un.... Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2N6763 SO - - V VGS=O
2N6764 100 - - V 10 = 1.0mA
VGShh) Gate Threshold Voltage ALL 2.0· - 4.0' V VOS=VGS,IO=l mA
IGSSF Gate - Sody Leakage Forward ALL - - 100' nA VGS = 20V
IGSSR Gate - Body Leakage R....rse ALL - - 100' nA VGS - -20V
lOSS Zero Gate Voltage Drain Current - 0.1 1.0' mA VOS = Max. Raling, VGS = 0
ALL
0.2 4.0· mA VOS - Max. Raling, VGS = 0, T C = 12SoC
VOS(on) Static Drain-Source On-Stat. 2N6783 - - 2.4S' V VGS -10V 10 - 31A
Voltage CD 2N6764 - - 2.09' V VGS = 10V, 10 = 3SA

ROS(on) Static Drain-Source On-State 2N6763 - 0.06 O.OS' a VGS = 10V, 10 = 20A
Resistance CD 2N6764 - O.04S O.OSS' a VGS - 10V, 10 - 24A

ROS(on) Static Drain-50urce On-State 2N6763 - - 0.136' a VGS= 10V, 10 = 20A, TC= 12SoC
Resistance G)
2N6764 - - 0.094' a VGS = 10V, 10 = 24A, TC = 12SoC
91$ Forward Transconductance CD ALL 9.0' 12.S 27' 5 (U) VOS = ISV, 10 = 24A
Cia Input Capacitance ALL 1000' 2000 3000' pF
VGS = 0, VOS = 2SV,' = 1.0 MHz
Cots Output Capacitance ALL SOO' 1000 1500' pF
See Fig. 10
Cn. Reverse Transfer Capacitance ALL ISO' 3S0 SOO' pF
'd (on) Turn-On Delay Time ALL - - 3S' ns VOO"" 24V, 10 - 24A, Zo - 4.7a
'r Rise Time ALL - - 100' ns (See Figs. 13 and 14)
'd (off) Turn.()ff Celay Time ALL - - 12S' n. (MOSFET switching times are essentially
I, Fall Time ALL 100' n. independent of operating temperature.)

Thermal Resistance
R thCS Case-to-5ink Mounting surface flat, smooth, and greased.

R thJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratlnga and Characteristics

- -

~
IS Continuous Source Current 2N6763 31* Modified MOSF ET symbol
A showing the integral
(Body Oiode) 2N6764 3S' reverse P-N junction rectifier.
ISM Pulsed Source Current 2N6763 SO
(Body Diode) A
2N6764 70
VSO Diode Forward Voltage
CD 2N6763 0.90' - I.S' V T C - 2SoC, IS = 31A,vGS ="0
2N6764 0.9S' - 1.9' V TC= 2SoC, IS - 3BA, VGS - 0

'rr Reverse Recovery Time ALL - 500 - ns TJ - lSOoC, IF - ISM, dlFldl- 100 AI~s
QRR Reverse Recovered Charge ALL - 10 - ~C TJ - lSOoC, IF - ISM, dlFldl = 100 AI~.
• JEDEC registered values. CD Pul .. Test: Pul .. Widlh .. 300 ~S8C, Outy Cycle" 2%

VARY tp TO OBTAIN
REQUIRED PEAK IL

vGs=IF=L IL+-----~----~~~~

Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms

0-18
 2N6763 and 2N6764 Devices

30
SO
lOV 119v aD pI PU LSE T~ST 16
25 f-- 80 Js PU LSE JEST r
40 JGs =8l f- VOS = 15V
I J
13 II 13 I
,.~ ,.~ 20
,//
~ 30 ~
....
....
~ 7V
~ 15
7
~
:::> '"
a TJ = +125DC...........
/I 1
'-'
z
:;;:
20 z
:;;:
10 iTJ = 251c
,/1
'"c '"c
~J'-55l.~ r.J1
6l
E E
10
"r J
S~
~'l "
4~ ~ ''/
10 20 30 40 50 4 6
Vos. ORAIN·T0-50URCE VOLTAGE (VOLTS) VGS. GATE·T0-50URCE VOLTAGE (VOLTS)

Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

20
VGS=l~Vf/
20
/ aJ..'PuJE YEs! _ - aJ '" pulE TEJ
VGS = 1~~:?'/ ./
16 -_. /J.'r
BV /
16 BV V
~:.~
VII)( 13 ~v 7:

Ii.Vir '"v'"
II /6V
,.~
~
....
~
12
~
lfl
t,.6V .",
.-- --
'"'":::>
if// J V /'
,.,
'-'
z B
~/ ;(
~V
'"c
~ Y E
~V V
.-- 5V

~ '/
~
0.4
Y
O.B 1.2
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)
Fig. 5- Typical Saturation Characteristics
1.6 2.0
-
,.J~
......

0.4 O.B 1.2

4V

1.6
VoS. ORAIN·T0-50URCE VOLTAGE (VOLTS)
Fig. 6- Typical Saturation Characteristics
2.0

(2N6763) (2N6764)
100
20 2N6764
101"- -
0--' 2N6 63 I'

- l!i6~ "- 1001"- -

~
16 TJ = I_SSDC
-:;:;;; -'-.
". r,
~
§
~V
~
.-
- TJ = 2S DC

~+12SDC-
~
~

'"
20
2N6763
~.
,
.
~
z
t;
:::>
12

/ t:/V V
~
....
z
~ 0
1
f"\ ~, 1m,

V
L~
c :::>
z '-'
~ z
.....'"
z
8
~V ~ 5.0
"
i II V
o
_0 D
f- TJ = 150 C MAX. " "- 10m.- I--

,
III
10 20 30
vos = 15V
I

40
I
YPIPrETT - I--

50
2.0

1.0
3.0
SINGLE r~lSE

5.0
II II
II II
10 20 50 100
2N6763
200
DC f- I--
2N6764

10. DRAIN CURRENT (AMPERES) VDS' DRAIN·TO·SOURCE VO LTAGE (VOLTS)

Fig. 7 - Typical Transconductance Vs. Drain Current Fig. 8 - Maximum Safe Operating Area
0-19
2N6763 and 2N6764 Devices
4000

2.2 VG~=O
I
w t= 1 MHz
'-' 3200
z
~ 1.8 \
iii
'"
~Q
v ...
~ 2400
,1
""",V
~
ww
~~ 1.4
z
~
:::>«
~~
V" U
\ I~ CiSS
~
".~"
00
":'z '-' 1600
z-
~
c
1.0
I,.....- /
..;
\ "~ ,I

~
c
o

'" 0.6
.... VGS = 10V
10 = 24AI
1
800 ~
.......
i'... '"- .r
~COSS

.... C",

I
I""--

0.2 10 20 30 40 50
-40 40 80 120 160
VDS. DRAIN·TO.sOURCE VOLTAGE (VOLTS)
TJ. JUNCTION TEMPERATURE (DC)

Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitanca Vs. Drain-to-Source Voltage

JL
ISM.2N6764 r--
140 "- I
fI
IS. 2N6764
'f\.
120
'\
ffi III
~
W
...
0:
II
I\. $'"
~ 100
1
~
0-
z lD
c :ii
~
80
'"
'"
~ :::>
ili
5
cz:
~
60
'\ '-'
w
~
:::>
lil
r-TJ = 15UOCt-ITJ=250 C

"
I
...C
0
!b
... 40

20
I\.
"' f\ 1.0
o
20 60 80 100 120 140 VSO. SOURCE-TO-DRAIN VOLTAGE (VOLTS)
TC. CASE TEMPERATURE (DC) Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig. 11 - Power Vs. Temperature Derating Curve
VOD "'25V
VGS (on)
PU LSE'PWI DTH ----1
INPUT. Vi
90% 90%'1,..1 50%
_ ...-_--.Vo 10% 10%
VGS (off) ~ INPUT PU LSE INPUT PULSE

E
TO SCOPE
RISE TIME FALL TIME
!-

['J...
td (on) td (off)

'",,:~~ VOS (on) '\'-" I ___~;;J'.

_vrjtt-ll0%

ton~ ~toff
Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-20
 PO-S.338

INTERNAnONAL RECTIFIER IICiR I

HEXFET® TRANSISTORS 2NB7B5
.JEDEC REGISTERED 2NB7BB
N-CHANNEL
PDWER MDSFETs

200 Volt, 0.085 Ohm HEXFET Features:

The HEXFET- technology Is the key to International • Fast Switchin
Rectifier's advanced line of power MOSFET transis-
tors. The efficient geometry and unique processing of
• Low Drive Curr
the HEXFET design achieve very low on-state resist- • Ease of Parallelin
ance combined with high transconductance and great
device ruggedness.
• No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VOS ROSlon) 10

They are well suited for applications such as switching 2N6765 150V O.120n 25A
power supplies, motor controls, inverters, choppers, 2N6766 200V O.085n 30A
audio amplifiers, and high energy pulse circuits.

22.22(0.875)
CASE STYLE AND DIMENSIONS 342 MAX. DIA. IW ID.4sgl

(0.'3tX~I:"'"
T PLANE

1.60 0.D63 DIA. I

1.4 . 5 7 " "
WI m·2~1
.1.
TWD PLACES TWD PLACES
26.67
11.050) MAX.

;·a
. m·I~11
. 1 DIA .
TWO PLACES

39.95
DRAIN
ICASE)

SDURCE

t MEASURED ATSEATING PLANE

Conforms to JEDEC Outline TO-204AE (Modified T0-31
ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-21
2N6765 and 2N6766 Devices
Absolute Maximum Ratings
Parameter 2N676S 2N6766 Units
VOS Drain - Source Voltage ISO" 200" V
VOOR Drain - Gate Voltage (AGS - 1 Mil) ISO" 200' V
10@TC=2SoC Continuous Drain Current 2S' 30' A
10@TC-l000C Continuous Drain Current 16' 19' A
10M Pulsed Drain Current SO 60 A
VGS Gate - Source Voltage ;,20" V
Po@' TC = 2SoC Max. Power Dissipation ISO" lSee Fig. 11) W
PO @lTC'I000C Max. Power Dissipation 60' lSee Fig. 11) W
Linear Derating Factor 1.2' lSeo Fig. 111 W/K
ILM Inductive Current, Clamped lSee Fig. 1 and 2) L = 100 I'H
A
SO I 60
TJ Operating and
-55· to 150* °C
Tstg Storage Temperature Range
Lead Temperature 300" 10.063 in. 11.6mm) I,om ..selo, 10.) °C

Electrical Characteri8tics @ TC = 250C (Un.... Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2N676S ISO - V VGS=O
2N6766 200 - - V 10= 1.0mA,
VGSlth) Gate Threshold Voltage ALL 2.0' - 4.0' V VOS = VGS, 10 = 1 mA
IGSSF Gate - Body Leakage Forward ALL - - 100' nA VGS = 20V
IGSSR Gate - Body Leakage Reverse ALL - - 100" nA VGS = -20V
lOSS Zero Gata Voltage Drain Current - 0.1 1.0" mA VOS = Mex. Rating, VGS = 0
ALL
0.2 4.0· mA Vos = Max. Rating, VGS' 0, TC - 12SoC
VOS(on) Static Drain-Source On-State 2N676S - - 3.0· V VGS = 10V, 10 = 2SA
Voltage 0 2N6766 - - 2.1" V VGS = 10V, 10 = 30A
ROSlon) Static Drain-Source On-State 2N676S - 0.09 0.12' n VGS = 10V, 10 = 16A
Resistance CD 2N6166 - 0.01 O.OBS' n VGS = 10V,I 0 - 19A
ROS(on) Sta~ic Drain-Source On-State 2N616S - - 0.216' n VGS-l0V,10-16A, TC= 12SoC
Resistance G)
2N6166 0.153" n VGS = 10V,I0 = 19A, TC = 12SoC

lit. Forward Transconductance

0 ALL 9.0' IS.S 21' S IU) VOS = ISV,I O = 19A
Ciss I nput Capacitance ALL 1000' 2000 3000' pF
VGS = 0, VOS =2SV, f = 1.0 MHz
Coss Output Capacitance ALL 4S0' 800 1200· pF
See Fig. 10
Cns Reverse Transfer Capacitance ALL ISO' 300 500' pF
td (on) Turn-On Delay Time ALL - - 3S' n. VOO S. 9SV,I 0 = 19A, Zo = 4.7n
t, RisaTime ALL - - 100" ns ISee Figs. 13 and 14)
td loll) Turn-Off Delay Time ALL - - 12S· n. (MOSFET switching times are essentially

tl Fall Time ALL 100' ns independent of operating temperature.)

Thermal Resistance
R thJC Junction-to-Case
R thCS Case-to-5ink Mounting surface flat, smooth, and greased.
R thJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratings and Characteristics

2N6165 - - 2S" Modified MOSFET symbol

~
IS Continuous Source Current A
IBody Oiode) 2N6166 30' showing the integral
reverse P-N junction rectifier.
ISM Pulsed Source Current 2N676S SO
IBody Diode) A
2N6766 60
VSO Diode Forward Voltage CD 2N676S O.BS' - 1.7* V TC' 2SoC,I S = 2SA, VGS = 0
2N6166 0.9* - 1.8* V TC= 2SoC,I S = lOA, VGS = 0

t" Reverse Recovery Time ALL - SOO - n. TJ • IS00C, IF = ISM, dlF/dt = 100 AII"
ORR Reverse Recovered Charge ALL - 10 - I'C TJ = IS00C,I F -ISM,dIF/dt'I00A/I"
*JEOEC registered values. o Pul .. Test: Pul .. Width';;; 300 1'S8C, Outy Cycle';;; 2%

VARY tp TO OBTAIN
REQUIREO PEAK IL

vGs=rF=L I L + - - - - ¢ - - -....-"i_--'

Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms

0-22
 2N6765 and 2N6766 Devices

SO
10Vf1.}SV
BV
80 .. PU LSETEST .! J 30
rl
VGS'7V- I--- fI
~ 2S I - 80.1 PULSET!ST
40 I
f- VDS = 15V
iii
w 13
:'"::IE '""-w 20
::IE
~
....
~
'"
....'":::>
30
6V-
- ~
....z
w
'"'":::>
....
z
IS

~
z 20
C C TJ = 125°C
'"C> '"C> 10
~
12
10
SV-
- 12 'ITJ=2SJC .........
lTJ' -50°CI .........
'till
4)1- ! -_
-
I~ ro
v
3.SV __
~
10 20 30 40 so
VOS. ORAIN·TO-SOURCE·VOLTAGE (VOLTSI VGS. GATE·TO·SOURCE VOLTAGE (VOLTSI
Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics
zo
i(y r-- 20
!8 '/
~
:;' 10V~
SV
- 80.!PULSE 1TEST BV 6V-- f-- 80.!PULS)TEST SV

16
Ij.I 16
~~ ~ BV
7L

13 ~~ 13 ~
~
'"
w
"-
::IE
~ 12 ~ ..!GS·SV ~ ::IE
~
....
12
17
....
~ ~ ./ / ~ 1/ VGS = 5V I--
'"
'"
....
:::>
~~ a""z / ./
V
z
c
C
V / Y

,.
'"
C> ~ ""co
12
12
~ f/
...- /
, 4V
.... 4V- I--

~ ~
0.4 O.B 1.2 1.6 2.0 0.4 O.B 1.2 1.6 2.0
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
Fig. 5- Typical Saturation Characteristics Fig. 6- Typical Saturation Characteristics
(2N6765) (2N6766)
100

.J--...-
20 2N676
T~ = -50~C 50
lOllS

~=2SJC
2~~. .... .-.::
16 ,..... 0
piI1'\j2N6766 ~-
.,... " .... 100~S-
iii
~
::IE V. V 13
:::IE"" 10
~ 2N6 76S1'... "
w
§
J. V V TJ = 125°C
~ 1m.
..............
w 12 .... 5•0
z
W1/ z
w
'"
'"
roo;;:
:::>
C>
z
....
C> JV VDS =ISV
B
z
2.0 ~ ... 10ms-

.. !J
'"
z
'"
....
I I
lOllS PULSE TEST
~
c>

_0
1.0
"" DC

£ V O. S
TJ = 150°C MAX.
2N6765 2N6766
0.2 SINGLE PULSE

O. 1
mT
10 20 30 40 50 4.05.0 10 20 SO 100 200 500
'0. DRAIN CURRENT (AMPERESI VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI
Fig. 7 - Typical Transconductance Vs. Drain Current Fig. 8 - Maximum Safe Operating Area
0-23
2N8785 and 2N8788 Devices
2.4 4000

V~S =Ilv I
VGS=O
I~ = 19A 1
2.2 'sl MHz
w 3200
'"z
<
0-
'"
r
J
\
/
$z
0-
1.8

/
~

! 2400
,\
."'
~ffi
~
./
'"
z
~ l~
\ ~
.... 1.4
~<l
0< Ciss
6~ V 1600
..
""z
z_
1.0
./
~ ",-
\ "
Q

~ l /v \. r--... ,I
..... Co..

.
e;;-
Q

0.6
...- r- 800

"" ........ _C",

:r- Io-.

I
10 20 30 40 50
0.2 VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
-40 40 80 120 160
TJ. JUNCTION TEMPERATURE (OC) Fig. 10 - Typical Capacitanca Vs. Drain·to-Source Voltage
Fig.9-Normalized Typical On-Resistance Vs. Temperature
ISM. 2N6766---
VI
140
"'~ ff. .. L
IS.2N6766
120 ~
~ '\ ,.ffi
"-
/,
~100 '- :!
II
z
o
~
'\ .
0-
15
0:
lD

80
f-
~
iii '"'"w TJ= I500C fTJ= 2SOC
Q
.. 60
'"
0:
L
'"~

'"
~
~ .!F
~40

20 ~
'\ 1.0
o 1
20 40 60 80 100 120 140 VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)
TC,CASE TEMPERATURE (DC)
Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig. 11 - Power Vs. Temperature Derating Curve
PULSEtpWIDTH ~
VGS (on)

~
O% 90%
INPUT. V, 50% 50%
Vo W% W%
_ · r - -....... TO SCOPE VGS (off) ~ INPUT PULSE INPUTPULSE
RISE TIME FALL TIME

"., 1= "'" E'~

."~::: [~i'-9_0% -:~_9;';O%J~ __

Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-24
 PD-9.33S

INTERNATIONAL RECTIFIER I:r~iR I

HEXFET® TRANSISTORS 2N6767
.JEDEC REGISTERED 2N676B
N-CHANNEL
POWER MOSFETs

400 Volt, 0.3 Ohm HEXFET Features:

The HEXFET'" technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great
device ruggedness.
• No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VOS ROS(on) 10

They are well suited for applications such as switching 2N6767 350V O.4n 12A
power supplies, motor controls, inverters, choppers, 2N6768 400V O.3n 14A
audio amplifiers, and high energy pulse circuits.

22.2210.8751
CASE STYLE AND DIMENSIONS 342 MAX. DIA. 11.4310.;~!
10.'35IMAX~6.3510. 5

22.23 (0.875) -.l... ttEATING

MAX. DIA. T =+LANE

~.~~ m·g;i! DIA.-j 10.1610.401 MIN.

TWO PLACES lWO PLACES

HI m:l!1! DIA.
TWO PLACES

~'.
DRAIN

j I
ICASEI

SOURCE
"1.09 (0.043)
MAX. DIA.
39.96 (1.573)
MAX.
t MEASURED AT SEATING PLANE
Conforms to JEDEC Outline TO-204AA (TO-3)
Dimensions in Millimeters and (Inches)
ACTUAL SIZE

0-25
2N6767 and 2N6768 Devices
Absolute Maximum Ratings
Parameter 2N6767 2N6766 Units
VOS Drain - Source Voltage 350* 400* V
VOGR Drain - Gate Voltage (RGS "" 1 Mil) 350* 400* V
10@TC'250C Continuous Drain Current 12* 14* A
10@TC'1(lOoC Continuous Drain Current 7.75* 9.0* A
10M Pulsed Drain Current 20 25 A
VGS Gate - Source Voltage ±20* V
PO @TC'250C Max. Power Dissipation 150* (See Fig. 111 W
PO @TC-l00oC Max. Power Dissipation 60* (See Fig. 111 W
Linear Derating Factor 1.2* (See Fig. 111 W/K
ILM Inductive Current, Clamped (See Fig. 1 and 21 L - 100 ~H
A
20 I 25
TJ Operating and
-55* to 150· °C
T1tg Storage Temperature Range
Lead Temperature 300" (0.063 in. (1.6mm) from case for lOs) °c

Electrical Characteristics @ TC = 2S0 C (Un.... Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2N6767 350 - - V VGS'O
2N676S 400 - - V 10·1.0mA
VGS(th) Gate Threshold Voltage ALL 2.0* - 4.0· V V OS ,VGS,IO'lmA
IGSSF Gate - Body Leakage Forward ALL - - 100* nA VGS' 20V
I GSSR Gate - Body Leakage Reverse ALL - - 100- nA V GS ' -20V

lOSS Zero Gate VC>ttage Drain Current 0.1 1.0- mA VOS - Max. Rating, VGS - 0
ALL
- 0.2 4.0· mA V OS = Max. Rating, V GS :::: 0, T C :::: 1250 C
VDS(on) Static Drain-Source On-State 2N6767 - - 5.4- V V GS = 10V, 10 = 12A
Voltage CD 2N676S 5.6- V V GS '10V, 10 -14A

ROS(on) Static Drain-Source On-State 2N6767 - 0.3 0.4* n V GS - 10V, 10 - 7.75A

Resistance (i) 2N6766 - 0.25 0.3- n V GS = 10V,I 0 - 9.0A

ROS(on) Static Drain-Source On-State 2N6767 - - O.SS- n V GS - 10V, 10 ' 7.75A, T C • 125°C
Resistance (i) 2N676S - - 0.66- n VGS - 10V,I0 - 9.0A, TC' 125°C
gfs forward Transconductance G) ALL 8.0· 11.0 24- 5 (UI VOS '15V, 10' 9.0A

Ciss I nput Capacitance ALL 1000- 2000 3000- pF

VGS' 0, VOS' 25V, f · 1.0 MHz
Co.. Output Capacitance ALL 200- 400 600- pF
See Fig. 10
C.... Reverse Transfer Capacitance ALL 50- 100 200- pF

'd (on) Turn-On Delay Time ALL - - 35- ns VOO ~ 180V, 10 ' 9.0A, Zo = 4.7,n
I, Rise Time ALL - - 65- n. (See Figs. 13 and 14)

'd (off) Turn-Off Delay Time ALL - - 150- n. (MOSFET switching times are essentially

If Fall Time ALL 75- n. independent of operating temperature.)

Thermal Resistance
R thJC Junction-to-Case

R thCS Case-to-Sink Mounting surface flat, smooth, and greased.

R thJA Junction-to-Ambient Free Air Operation

Body-Drain Diode Ratingl and Characteriatics

- -

~
IS Continuous Source Current 2N6767 12- Modified MOSFET symbol
A showing the integral
(Sody Diode) 2N676S 14-
reverse P-N junction rectifier.
ISM Pulsed Source Current 2N6767 20
(Body Diode) A
2N6766 25
VSO Oiode Forward Voltage CD 2N6767 O.S- - 1.6* V TC'250C,I S -12A,VGS-0
2N676S 0.S5* - 1.7* V TC - 25°C, IS - 14A, VGS - 0

'rr Reverse Recovery Time ALL - 1000 - n. T J - 150°C, IF - ISM, dlF/dl' 100 A/~.

ORR Reverse Recovered Charge ALL - 25 - ~C T J • 150°C, IF = ISM, dlF/dt· 100 A/~.

• JEDEC registered values. CD Pulse Test: Pulse Width <;; 300 ","sec, Duty Cycle <;; 2%

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGS'~
I L + - _ - o - - -.........,.,"""--'

Fig, 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms

0-26
 2N6767 and 2N6768 Devices

12

20 10 r- 80!SPULSE ~EST
6.0V 80~$PULSE TEST I I
f- Vos -15V

vJs - 5.15V
J
I I
L TJ - +1250 C,
II
T TJ-25OC, .........
"1/
.l TJ =-55°C,
"J IJI
T n rJ
4.~V 1/1 II
l.~V ./.V.....-
50 100 150 200 250 lOO 4
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS. GATE-TO·SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics

10 10
VW~v
fiSt
J.'PUJsElEJ - _,l., PUlSE TEll
VGS-;V

~5.0Iv

Ii JJ

1/
)V ". ........ 4.5V

JV
~v
"V ~4.5V

J
1/
J
T
.l J~
# " ~ 40r
J
II" T :r ly

VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 5- Typical Saturation Characteristics Fig. 6- Typical Saturation Characteristics

(2N6767) (2N6768)

_. I-I~
:-S --
lO
~Z!i!l
20
20
2N6ill s: r..-- 1-- lOt'I

~ ... ',- I
16 10
·1N'6768

~
.... , ~. IOU
'"
ijj
i'!'i
,..- r-
TJ - -55°C
Tr 25'C i::s'" f'-2N6767

.... ...-
I
§
"'
-
5.0
..,w TJ - +125 oC

"
..",. " I
12 I-
...z ...-
..,
I-
:::>
c
z
~ V ......
~ /'
:,.......'"
~
'"
13
i\
""
1\
, 't.,
I
1 ms

'. -.I
z 2.0
8
~ TJ = 150°C MAX.
~
;:: 1#V c

-'"
SINGLE PULSE
~
l~
I- 1.0 10 ms
~
Vos -15V

I I I
'1"'pUrTESr- f---
0.5 ""' I
L?C -
If O.l
2N6767 2N6768
12 16 20 8.0 10 20 50 100 200 500
10. DRAIN CURRENT (AMPERES) VOS' ORAIN·TO-SOURCE VOLTAGE (VOLTS)

Fig. 7 - Typical Transconductance Vs. Drain Current Fig. 8 - Maximum Safe Operating Area
0-27
2N6767 and 2N6768 Devices
4D00

2.2 ~ VG~=O
/ 3200 \ I
t= I MHz

/ ,~

/
! 2400 "'" r-....
)"
/" '"z
~
U

~ 1600
1\ , ~ Ciss

/
/'
",'
\ \.
\
c
;)l
c 0.6 ... ./
/. VGS = 10V SOD "- .........
'" lo=9A
"' ....... ~
0.2
-4D 40 80
TJ. JUNCT10N TEMPERATURE (OC)
120 160 10
---20
~
3D 40
Vas. oRAIN·TO·SOURCE VOLTAGE (VOLTS)
50

Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage

VI ISM. 2N6768

"''i\.
1
140

/11
/
120 ,IS.2N6768
in
in
....
.... '\ w
'"
,.
w 10
~ 100
~ A-

S
z
c
~ 80
'\ ....
z
w
'"
I
I

' - - TJ = 1500 e r TJ' 25 0 C

'"
'\
:::>
iii

.""-
;:; '"w
'"
w
!I:
'"d
A-
60
.'"
'"
'"
:::>

.!b
A- 40

20

'1\ 1.0
o
20 40 60 so 100 120 140 VSO. SOURCE·TO·oRAIN VOLTAGE (VOLTS)
Te. CASE TEMPERATURE (OC)
Fig. 12 - Typical Body-Drain Diode Forward Voltage
Fig_ 11 - Power Vs. Temperature Derating Curve

PULS:':vloTH~
VGS (on) --+~~--~

~
O% 90% 50%
INPUT. Vi
Vo 10%
-'~-~TO SCOPE VGS(oll) INPUT PULSE INPUT PULSE

Id (on) i=
RISE TIME
'd (oil) F FALL TIME

'":"~~~ VoS (on)

["l-
.l'-'
I" ---~~.
_VTJlt-lIO%
ton ----t l..- toff
Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-28
 PD·9.340

INTERNATIONAL RECTIFIER IICiR I

HEXFET® TRANSISTORS 2N6769
.JEDEC REGISTERED 2N6770
N-CHANNEL
POWER MOSFETs

500 Volt, 0.4 Ohm HEXFET Features:

The HEXFET'" technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis· • Low Drive Current
tors. The efficient geometry and unique processing of
the HEXFET design achieve very low on-state resist- • Ease of Paralleling
ance combined with high transconductance and great
device ruggedness.
• No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Part Number VOS ROS(on) 10

They are well suited for applications such as switching 2N6769 450V O.5n 11A
power supplies, motor controls, inverters, choppers, 2N6770 500V O.4n 12A
audio amplifiers, and high energy pulse circuits.

22.22(0.875)
CASE STYLE AND DIMENSIONS l~';l (~·~~W

'"' i' f=:::ff-:,.,

3.42 MAX.OIA.

22.23 (0.875)
T~
I"~~:A'I
PLANE

~'811~'~~1 OIA.--I1-- 10.16(0.40) MIN.

TWO PLACES TWO PLACES
,;:;SfR···'·
"\ 26.67

&
-11.050) MAX-

4:~ o:m
TWO PLACES
alA .......
'--.,(: . , J
I, ~\ lil41~ml'J
r'~'
3995
Pc~~k~-- I T \ 1 .64 11 573[i MAX.
V"P' J
'1.09 (0.043) SOURCE ) '1/ =rm
30.4011.197)

MAX.DIA. GATE ~~~====--,L

~39.96 (1.573) _
- -I f--!:lllKml'
11.17(0.44011
MAX. ro:mlmIlJ
'MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO-204AA (TO-3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0·29
2N6769 and 2N6770 Devices
Absolute Maximum Ratings
Parameter 2N6769 2N6770 Units
VOS Drain Source Voltage 4SO" 500" V
VOGR Drain - Gate Voltage (RGS - 1 MSl) 4SO" 500" V
IO@TC-250C Continuous Drain Current II" 12" A
IO@TC=I000C Continuous Drain Current 7.0" 7.75" A
10M Pulsed Drain Current 20 25 A
VGS Gate - Source Voltage .:t20· V
PO@TC=25oC Max. Power Dissipation ISO" lSee Fig. 111 W
PO @TC=I000C Max. Power Dissipation 60" lSee Fig. 111 W
Lineaf Derating Factor 1.2" lSee Fig. III W/K
ILM Inductive Current, Clamped ~s;- Fi g.land 21 L= l00"~5
l A
TJ Operating and
-55* to 150* °C
Tltg Storage Temperature Range
Lead Temperature 300" 10.063 in. 11.6mml from ca.. for 10s1 °C

Electrical Characteriatics @ T C = 25°C (Un.... Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage 2N676S 450 - - V VGS=O
2N6770 500 - - V IO=4.0mA
VGShhl GI" Thrl.hold Voitogo ALL 2.0" - 4.0" V VOS' VGS, 10 = 1 mA
IGSSF Gat. - Body Leakage Forward ALL - 100" nA VGS = 20V
IGSSR Gate - Body Leakage Rever.. ALL - - 100' nA VGS= -20V
lOSS Zero Gate Voltage Drain Current
ALL
- 0.1 1.0· mA VOS = 0.8 X Max. Rating, VGS = 0
- 0.2 4.0· mA VOS = Max. Rating, VGS = 0, T C· 25°C to 125°C
VOS(on) Static Drain-SOUrce OnoStata 2N676S - - 6.0· V
Voltoge 0)
2N6770 - - 6.0· V

ROSlonl Static Drain~Source On~State 2N676S - 0.4 0.5' a VGS' 10V,IO' 7.0A
Resistance CD 2N6770 - 0.3 OA' n V GS = 10V,IO = 7.75A

ROSlonl Static Drain-5ource On-State 2N676S - - 1.1" a VGS = 10V, 10' 7.0A, TC = 125°C
Rllistlne. 0)
2N6770 - - 0.88" a VGS = 10V,IO = 7.75A, TC = 125°C
9"Ciss Forward Transconductance CD ALL 8.0' 12.0 24' S lUI vOS = 15V,I0 = 7.75A
Input Capacitance ALL 1000" 2000 3000" pF
VGS = 0, VOS = 25V, f= 1.0 MHz
Co.. Output Cspacitanc:e ALL 200' 4DO 600' pF
See Fig. 10
Cns Reverse Transfer Capacitance ALL SO" 100 200' pF
td lonl Turn-On Delay Time ALL - - 35' n, VOO 9!! 210V, 10 = 7.75A, Zo = 4.7a
tr RiseTime ALL SO' ns (See Figs. 13 and 14)
td 10111 Turn..()ff Delay Time ALL - - ISO' ns (MOSFET switching times are essentially
tf Fall Time ALL 70' independent of operating temperature.)
"'
Thermal Resistance
I RthJC Junction·to·C... I ALL I I - I 0.83" I KIW I
I RthCS case-to-Sink I ALL I - I 0.1 I I KIW Mounting surface flat, smooth, and greased. I
I RthJA Junction·to·Ambient I ALL I - I - I 30 I KIW Free Air Operation I
Body-Drain Diode Ratings and Characteristics
- - Modified MOSFET symbol

~
IS Continuous Source Current 2N676S 11' A showing the integral
lBody Diodel 2N6770 - 12"
reverse P-N junction rectifier.
ISM Pulsed Source Current 2N676S - - 20
A
lBody Diodel 2N6770 - - 25
VSO Diode Forward Voltage CD 2N676S 0.75" 1.5' V TC=250C,I S - lIA,VGS'O
2N6770 0.60' - 1.6* V TC' 25°C, IS' 12A, VGS = 0
trr Reverse Recovery Time ALL - 400 - ns TJ • lSOoC, IF· ISM, dlF/dt· 100 AI".
ORR R....... R_rod Chlrgol ALL - 10 - "C T J - lSOoC, IF • ISM, dIF'dt· 100 AI".
*JEDEC reglltered values. 0) Pulll Tilt: Pul.. Width .. 300 ,,_, Duty Cycle" 2%

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGs="R

IL _ _ -o---.....-">,.,.,.---J
Fig. 1 - Clamped Inductive Test Circuit Fig. 2 - Clamped Inductive Waveforms
0·30
 2N6769 and 2N6770 Devices

20

20
.1
I-- Vos= 15V
J TJ = -sooc-
rt: 'TJ .J5 0C
.O~!.':
5.5V J /.IS PUILSE T~ST
...
c;; 15
I I
lOll' PULSE TEST
TJ = 125°C

iii 16
~
:IE
~
:&
~
....
~ 12 VGS= 5.0V 1!l
.... 10
...
z '"
a'"z TJ = 125°C,
'"
a'"z ;;;:
1 t"--. J
~j
TJ = 250C,
;;;: '"
Q

'"
Q E I ~

~~
4r
E TJ = -50°C,
4
I
4.~V
I
3.5V V~ ~
50 100 150
200 250 300
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Output Characteristics Fig. 4 - Typical Transfer Characteristics
10 10
VGS= ~:~ V
r-- 1-80 J. PULSJ TEST 5.5
I " - -IO.lPULSJTEST
VGS}Y--
~
~ ~.Ov ~:.~~
5.0V_
-
AP' '1/'"
~, ~
~ ",.. I--
4.5V
;
~' ~ 4.SV= ~

~~
V
J
". ~,
J 4.0V
~ / 4.0V""" ~
I~
/
1
3.5V
4
I
3.SV_
-
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 5- Typical Saturation Characteristics Fig. 6- Typical Saturation Characteristics

(2N6769) (2N6770)
20
TJ=-~

",..
~J = 25JC
" ".........-- ..--
..-- ~r-
16
c;;
1!l ./ TJ = 125°C
...§
:IE

.
... 12 / ./ ~
~V
z
~ j
l'm~
..'" J'/~ /
:::>
Q
zQ 2.0 ',oof
II
z
«
....
'"
~ II VDS = 15V

r l
1.0

0.5
TJ = 150°C MAX.
SINGLE PULSE
" 10m.

rt 10 PULl TEs
0.2
I
DIC

2Nr761 2r 7?t
0.1
10 15 20 25 50 10 20 SO 100 200 500
10. DRAIN CURRENT (AMPERES) Vos. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 7 - Typical Transconductance v,. Drain Current Fig. 8 - Maximum Safe Operating Area
0-31
2N8789 and 2N8770 Devices
4000

~ VG~'O
,
2.2
~
I
.......
z
L 3200
I-I MHz

< / \.
....~
1.8

l\, "
= ~ ... ~
~s
........
... N 1.4 ~ ...z~ 2400
j"-.... ~Ci..
=::;
"'<
0:;; ./ ...~
.......~
""0:
00
,","Z
z - 1.0 /" 1600
:;;:
=
0 l/ \ \.
g
en
c 0.6 ,. . /
V VGS = 10V 800
\ ~
=

0.2
40
10 = 7.7SA

120
" 10
~

20
'""""'" ~
r--
30
~DSS

40 50
-40 80 160
TJ. JUNCTION TEMPERATURE (DC) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig.9-Normalized Typical On-Resistance Vs. Temperature Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage

140 "- If ISM. 2N6770

120
'r\. / I
@ '\ 13
If IS.2N6770
...:;;ffi
~ 100
z
o
"'\ S
I-
10

I
I
I
~ 80 liS
0:
I I
iJi
is
a: 60
'\ 0:
.......'"
u
a:
TJ = IS00 C HTJ=2S 0 C

~ '"
~40 I'" 5l
.!fo I L

"
20
I
"1\ 1.0
o
I
20 40 60 80 100 120 140
VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)
Tc. CASE TEMPERATURE (DC)

Fig. 11 - Power Vs. Temperature Derating Curve Fig. 12 - Typical Body-Drain Diode Forward Voltage

PULSEI~IOTH~
VGS (on) --+.~::---~
INPUT. V, 50% ~O% 90% SO%
-Y---'TO SCOPE
Vo
VGS (off)
10%

VOS(Offl-eD%
OUTPUT. V0
~

90%
INPUT PULSE
RISE TIME
Id (on) i=
1'-1
Id (off)

90%
10%

r INPUTPULSE
FALL TIME

jll-ll0%

VOS (on) Ii'---~";';';'"

ton ----+J I.-- toft
Fig. 13 - Switching Time Test Circuit Fig. 14 - Switching Time Waveforms

0-32
 PD-9.380

INTERNATIONAL RECTIFIER II'~RI

HEXFET® TRANSISTORS IRFD~ ZD

N-CHANNEL IRFD~Z~
HEXDlpTM
IRFD~Z2
1-WATT RATED POWER MOSFETs
IN A 4-PIN, DUAL IN-LINE PACKAGE
IRFD~Z3

100 Volt, 2.4 Ohm, 1-Watt HEXDIP • For Automatic Insertion

HEXFET technology is the key to International Recti- • Compact, End-Stackable
fier's advanced line of power MOSFET transistors. • Fast Switching
Efficient geometry and unique processing of the • Low Drive Current
HEXFET design achieve a very low on-state resist-
ance combined with high transconductance and
• Easily Paralleled
great device ruggedness. HEXFETs feature all of the • No Second Breakdown
established advantages of MOSFETs such as voltage • Excellent Temperature Stability
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature sta-
bility of the electrical parameters. Product Summary
The HEXDIP 4-pin, Dual In-Line Package brings the Part Number VOS ROS(on) 10
advantages of HEXFETs to high volume applications
where automatic PC Board insertion is desirable, IRF01Z0 100V 2.4n. O.5A
such as circuit boards for computers, printers, tele- IRF01Z1 60V 2.4n. O.5A
communications equipment and consumer products. IRFD1Z2 100V 3.2n. O.4A
Their compatibility with automatic insertion equip-
ment, low-profile and end-stackable features, repre- IRFD1Z3 60V 3.2n. O.4A
sent the state-of-the-art in power device packaging.

NOTES:
CD APPLIES TO SPREAD OF LEADS PRIOR TO INSTA.LLATION.
CD APPUESTO INSTALLED LEAD CENTERS.
case Style HD-1 (Similar to JEDEC Outline MO-DD1)
ACTUAL SIZE Dimensions in Millimeters and CInches)

0-33
IRFD1Z0, IRFD1Z1, IRFD1Z2, IRFD1Z3 Devices

Absolute Maximum Ratings

Parameter IRF01Z0 IRF01Zl IRF01Z2 IRF01Z3 Units

VOS Drain - Source Voltage G) 100 60 100 60 V

VOGR Drain - Gate Voltage IRGS - 1 Mil) (j) 100 60 100 60 V
10@TC~25°C Continuous Drain Current 0.5 0.5 0.4 0.4 A
10M Pulsed Drain Current 2.0 2.0 1.5 1.5 A
VGS Gate - Source Voltage ±20 V
PO@TC ~ 25°C Max. Power Dissipation 1.0 ISee Fig. 13) W
Linear Derating Factor O.OOB ISee Fig. 13) W/K
ILM Inductive Current, Clamped ISee Fig. 14 and 15) L - 100!,H
A
2.0 I 2.0 I 1.5 J 1.5
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF01Z0
100 - - V VGS ~ OV
IRF01Z2
IRF01Zl
IRF01Z3
60 - - V 10 ~ 250!,A

V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS ~ VGS, 10 ~ 250!,A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS ~ 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 !,A VOS ~ Max. Rating, VGS ~ OV
- - 1000 !,A. VOS ~ Max. RatingxO.B, VGS ~ OV, TC ~ 125°C
1010n) On-State Drain Current ® IRF01Z0
0.5 - - A
IRF01Zl
VOS >1010n) x ROSlon) max.' V GS ~ 10V
IRF01Z2
0.4 - - A
IRF01Z3
ROS(on) Static Drain-Source On-State IRF01Z0
Resistance ® IRF01Zl
- 2.2 2.4 0
VGS ~ 10V, 10 ~ 0.25A
IRF01Z2
IRF01Z3
- 2.B 3.2 0

9ls Forward Transconductance ® ALL - 0.35 - Sllll VOS >1010n) x ROSlon) max.' 10 - 0.25A
Giss Input Capacitance ALL - 50 70 pF
VGS ~ OV, VOS ~ 25V, I ~ 1.0 MHz
Coss Output Capacitance ALL - 20 30 pF
See Fig. 9
Crss Reverse Transfer Capacitance ALL - 5.0 10 pF
tdlonl Turn-On Delay Time ALL - 10 20 ns VOO = 0.5 BV OSS ' 10 ~ 0.25A, Zo ~ 500
tr Rise Time ALL - 15 25 ns See Fig. 16
tdloff) Turn-Off Delay Time ALL - 15 25 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 10 20 ns
Q9 Total Gate Charge
ALL - 2.0 3.0 nC
V GS = 10V, 10 ~ 1.2A, VOS ~ O.B Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 17 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 1.0 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 1.0 - nC

LO Internal Drain Inductance - 4.0 - nH Measured from the Modified MOSFET

drain lead, 2.0mm symbol showing the
10.OB in.) from internal device
ALL package to center of inductances.
die.

LS Internal Source Inductance ALL - 6.0 - nH Measured from the

source lead, 2.0mm
10.OB in.) from
package to source
bonding pad.
$
Thermal Resistance
RthJA Junction-to-Ambient Free Air Operation

D-34
 IRFD1Z0, IRFD1Z1, IRFD1Z2, IRFD1Z3 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFD1Z0 Modified MOSFET symbol
- - 0.5 A
(Body Diode) IRFD1ZI showing the integral
reverse P-N junction rectifier.
IRFD1Z2
- - 0.4 A

~
IRFD1Z3
ISM Pulse Source Current IRFD1Z0
- - 2.0 A
(Body Diode) IRFD1ZI
IRFD1Z2
IRFD1Z3
- - 1.5 A

VSD Diode Forward Voltage ® IRFD1Z0

- - 1.4 V TC ~ 25°C, IS ~ 0.5A, VGS ~ OV
IRFD1ZI
IRFD1Z2
IRFD1Z3 - - 1.3 V TC ~ 25°C, IS ~ O.4A, VGS ~ OV

trr Reverse Recovery Time ALL - 100 - ns TJ 150°C, IF O.SA, dlFldt 100AI~s

ORR Reverse Recovered Charge ALL - 0.2 - ~C T J - 150°C, IF - 0.5A, dlFldt - 100AI~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO-

CD TJ ~ 25°C to 150°C. @ Pulse Test: Pulse width" 300~s, Duty Cycle" 2%.

1.2
2.0
lOV
9l so J. PU L~ETEJT rJII
-I' VDS> lo(on) x RoS(on) max.
'1
1.6 r- Lso., PJSE TEJ
1.0
I
~ ~
...i:'i al '"
~ 0.8
l
,
:; :;
!3. 1.2 !3.
....
~
'"'"
I
7\,
1:5
cr 0.6
cr
J
::.
'-' r ::.
'-'

"'* ,
z 0.8 z
«
~
c
ci VGS =
I
6t
cr
c
12
0.4
TJ= 1250~"
I
0.4 / TJ ~250~"
I 0.2
5l
TJ -)-550~" 7J'I
r I
4V ~VJ
10 20 30 40 50 2 4 10 12
VDS, DRAIN·TD·SDURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOU RCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

3.0
2.0 ....-..-..,...-,..--..-..,...-,........,-......-.,.........
2.0
IRFolZ0,IZ1·Hi
101 1';
'lIRFolZ2,IZ3
1.0

1.6 IRFD1Z0,IZI
~ 0.5
cr
~ I RFDlz}, l'z".!,
~ 0.2
.... 1001"
~ 0.1
IX:
cr
az 0.05
1 m,
«
'"c 0.02 - TJ = 1500C MAX.
- SINGLE PULSE 10l mi'
0.01 DC
0.4
0.005
)RFD1Zl,IZ3 IRFD1Z0,IZ2 f-
0.002

1.0 10 20 50 100 200 500

VoS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
VDS, DRAIN·To·SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area
0-35
IRFD1Z0, IRFD1Z1, IRFD1Z2, IRFD1Z3 Devices

0.6
I. II. I i
10~~~
u;
zw
:Ii
w
!ii
w
<.)
Z
0.5

0.4
- Vos> 10(on) x ROS(on) max.

/
/'
/
--
i.
TJ = -550C

TJ·250C iii
~
'"5
-
<t
I-
<.) 0.3
J / TJ -125°C I-
1li 1.0
'"
'"Z
Q
I / ~ '"'"
.
co
<.)

z
::i
0.2
~
<.)
z
;;: 0.5
'"c I I
I

I- /,/ E I I
.f
0.1 I 0.2 f--f- TJ = 1500c.,.l--,I---+_-+-_+--t--+--I
I
I U TJ = 250C-+-+---1I---+--I

0.1 II I
L-....j,_...I.......L-.L.I._...I.._"-.....I_...I.._........
0.25 0.5 0.15 1.0 1.25 1.5 o 0.4 0.8 1.2 1.6 2.0
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 5 - Typical Transconductance Vs. Drain Current Fig. 6 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

~
c> 1.15
w
<.)
:z 2.0 - I--
vls =lJV ,
" ,~ ~
> 10 =0.5A
/
~ ". iii
Q
""", '"
~a
,,/
~s 1.05 ww
1.5
g;~ ", <.)N

./
V
~~ / g~
/'~
",:Ii
",'" ~~
./
/
5; ~ 0.95 ~~ 1.0
~ V ;;: ~
;;:
'"
Q
'"c
c
o
...- . /
~ 0.85 1!l 0.5
1; '"

0.75 o
-40 o 40 80 120 160 -40 o 40 80 120 160
TJ, JUNCTION TEMPERATURE (OC) TJ,JUNCTION TEMPERATURE (OC)

Fig. 7 - Breakdown Voltage Vs. Temperature Fig.8 - Normalized On-Resistance Vs. Temperature

0-36
 IRFD1Z0, IRFD1Z1, IRFD1Z2, IRFD1Z3 Devices
100 20

V~S=ot
.1 f= I MHz 1 1 v;
80 Cjss = Cgs. Cgd. Cds SHORTED_ .... VDS = 20V,,-
Cr.. = Cgd c5 15

~V
~ VDS=50~~
Coss = Cds + Cgs Cgd - w
co
u.. Cgs. Cgd « VDS = SOV.IRFIZO. IZ2,
Q.
~
W
'"z
«
....
60

\' r--..... I
Ciss
'" Cds. Cgd -
'"
>
~ 10
171V
~ f/
;:;
::« 40 \ '"
'"
v,>
'"
",'
~ '":-;;
!:,(
J 10 = 1.2A

\ f'.. r-- Coss

co 5
FOR TEST CIRCUIT-

/
U,
co
20
\
cL - > ~EE FIG~RE 17 I

V
w ~ W ~ ~ ~ ~ % W 1.0 2.0 3.0 4.0
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)

Fig. 9 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 10 - Typical Gate Charge Vs. Gate-to-Source Voltage

0.5
...........
2.6
RDS(on) MEASURED WITH CURRENT PULSE OF
......
~
2.0 MS DURATION. INITIAL TJ = 25 0 C. (HEATING
~ EFFEGT OF 2.0 I" PULSE IS MINIMAL.)
'"
8
0.4
....... .......
.........
. . . r--... "-
~
z 13 ~OIZO.IZI
« 0:
~
~ 2.2 :;;
0.3
....
~
0:
z
'"
w
A=20V ....
~
0: IRFOIZ2.~ '" ~
~~ ~
""
a:
'"
a:
'"'"v,>
'"~
"'"
a:
1.8
- -- / '"
'"
z:

"
a:
'"12
0.2

~
~
0.1

0:
''"* 'l
1.4 o
o 1.0 2.0 3.0 25 50 75 100 125
10 , DRAIN CURRENT (AMPERES) Tc. CASE TEMPERATURE (DC)

Fig. 11 - Typical On-Resistance Vs. Drain Current Fig. 12 - Maximum Drain Current Vs. Case Temperature

1.4

1.2
I
RthJA <; 120
J K1W- -
v;
S 1.0

"'""
~
z
'"
;:: 0.8
::
iii
0 0.6
~
a:

'"
w
~
~ 0.4
.P
0.2
~
20 40 60 80 100
TC. CASE TEMPERATURE (DC)

Fig. 13 - Power Vs. Temperature Derating Curve

120
" ~
140

0-37
IRFD1Z0, IRFD1Z1, IRFD1Z2, IRFD1Z3 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

vGs=:EF=L _DU~_T~•.-:".
IL _ _ _l ) - _ -..........,........J

Fig. 14 - Clamped Inductive Test Circuit Fig. 15 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR D.U.T.
r------,
I
0---- TO SCOPE
I D.om
I HIGH FREQUENCY
L_ SHUNT

Fig. 16 - Switching Time Test Circuit

, - - - 0 +VOS
(ISOLATED
SUPPLY)

DI'J}·smA
- IG 10
CURRENT -::- CURRENT
SHUNT SHUNT

Fig. 17 - Gate Charge Test Circuit

0-38
 PD-9.328

INTERNATIONAL RECTIFIER 1l:(~R I

HEXFET@TRANSISTORS IRFD11D
N-CHANNEL IRFD111
HEXDlpTM IRFD112
1-WATT RATED POWER MOSFETs
IN A 4-PIN, DUAL-IN-LiNE PACKAGE IRFD113
100 VOLT, 0.6 Ohm, 1-WaH HEXDIP • For Automatic Insertion
HEXFET technology is the key to International Recti- • Compact, End Stackable
fier's advanced line of power MOSFET transistors. • Fast Switching
Efficient geometry and unique processing of the • Low Drive Current
HEXFET design achieve a very low on-state resistance
combined with high transconductance and great • Easily Paralleled
device ruggedness. HEXFETs feature all of the estab- • No Second Breakdown
lished advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast • Excellent Temperature Stability
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. Product Summary
The HEXDIP 4-pin, Dual-In-Line Package brings the
advantages of HEXFETs to high volume applications Part Number VOS ROS(on) 10
where automatic PC Board insertion is desirable, IRF0110 100V o.an 1.0A
such as circuit boards for computers, printers, tele-
communications equipment and consumer products. IRF0111 aov o.an 1.0A
Their compatibility with automatic insertion equip- IRF0112 100V o.sn O.SA
ment, low-profile and end-stackable features repre-
sent the state-of-the-art in power device packaging. IRF0113 aov o.sn O.SA

OJ
o
,
I
s
G

•
3.8t
3.55(0.1401
3.1810.125)
REFERENCE
t
(0.150)
MAX.

043(00111 II
O.31(O.OI2)--1~

NOTES
CD APPLIES TOSPREAQ OF LEADS PRIOR TO INSTALLATION.
CD APPLIes TO INSTALLED LEAD CENTERS.
case Style HO-1 (Similar to JEOEC Outline MO-Q01)
ACTUAL SIZE Nominal Dimensions in Millimeters and (Inches)

0-39
IRFD110, IRFD111, IRFD112, IRFD113 Devices

Absolute Maximum Ratings

Parameter IRF0110 IRFOlll IRF0112 IRF0113 Units
VOS Drain - Source Voltage (j) 100 SO 100 SO V
,.
VOGR Orain - Gate Voltage (RGS - 1 Mill (j) 100 SO 100 SO V
10@TC - 25°C Continuous Drain Current 1.0 1.0 O.B O.S A
10M Pulsed Drain Current 4.0 4.0 3.0 3.0 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 1.0 (See Fig. 13) W
Linear Derating Factor O.OOS (See Fig. 13) W/K
ILM Inductive Current, Clamped (See Fig. 14 and 15) L = loo"H
A
4.0 I 4.0 I 3.0 I 3.0
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRFOll0
100 - - V VGS = OV
IRF0112
IRFOlll
IRF0113
60 - - V 10 = 250"A

V GS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 250"A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 "A VOS = Max. Rating, VGS = OV
- - 1000 "A VOS = Max. Rating x O.S, VGS = OV, T C = 125°C
10(on) On-State Drain Current ® IRFOll0
1.0 - - A
IRFOlll
V OS ) 1010n) x ROS(on) max.' V GS = 10V
IRF0112
IRF0113
O.S - - A

ROS(on) Static Drain-Source On-State IRFOll0

Resistance ® IRFOlll - 0.5 O.S II
VGS = 10V, 10 = O.SA
IRF0112
IRF0113
- 0.6 O.B II

9fs Forward Transconductance ® ALL O.B 1.2 - SUl) VOS ) 10(on) x ROSlon) max.' 10 O.BA
Ciss Input Capacitance ALL - 135 200 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - BO 100 pF
See Fig. 9
Crss Reverse Transfer Capacjtance ALL - 20 25 pF
td(on) Turn-On Delay Time ALL - 10 20 ns VOO = 0.5 BV OSS ' 10 = O.SA, Zo = 5011
tr Rise Time ALL - 15 25 ns See Fig. IS
tdloffJ Turn-Off Delay Time ALL - 15 25 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 10 20 ns
Qg Total Gate Charge V GS = 10V, 10 = 4.0A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Orain)
ALL - 5.0 7.0 nC
See Fig. 17 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 2.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 7.0 - nC

LO Internal Drain Inductance - 4.0 - nH Measured from the Modified MOSFET

drain lead. 2.0mm symbol showing the
(O.OS in.) from internal device
ALL package to center of inductances.
die .

LS Internal Source Inductance ALL - S.O - nH Measured from the

source lead. 2.0mm
(O.OB in.) from
package to source
bonding pad.
.@)
Thermal Resistance
RthJA Junction-to-Ambient Free Air Operation

0-40
 IRFD110, IRFD111, IRFD112, IRFD113 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFDll0 Modified MOSFET symbol
(Body Diode) IRFDlll - - 1.0 A
showing the integral
IRFDl12 reverse P~N junction rectifier.
- - O.B A

~
IRFDl13
ISM Pulse Source Current IRFDll0
(Body Diodel IRFDlll - - 4.0 A

IRFDl12
IRFDl13
- - 3.0 A

VSD Diode Forward Voltage @ IRFDll0

IRFDlll - - 2.5 V TC = 25°C, IS = 1.0A, VGS = OV
IRFD112
IRFDl13
- - 2.0 V TC = 25°C, IS = O.SA, VGS = OV
t" Reverse Recovery Time ALL - 100 - ns TJ 150·C, IF LOA, dlF/dt = 100A/ps
QRR Reverse Recovered Charge ALL - 0.2 - pC T J - 150·C, IF = LOA, dlF/dt = 100 A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'
<D TJ = 25°C to 150°C. @PulseTest: Pulse width .. 300ps, Duty Cycle .. 2%.

5.0 5.0
~fr--l0V
8r p. PU~E TES~
t-9V
I "/
tJ
t-"PBV

4.0 4.0
+J = -5~OC, III!
If ;rJ = 2~OC,- ~ r//
fl
'"
~
:Ii
~
fl
...ffi
:Ii
::; 3.0
i J' ,2j"C'-
~ I(f
....
z
w
3.0
....
~
80 I
Il' PULSE TEST
I I
I A
'"'" - r-- VOS > 10(on) , ROS(on) .ma"
'"
,
:::I
a:
'-'
BV :::I
'-'
z 2.0 z 2.0

,
;;: ;;:
'"c '"c
E
1.0
E
1.0
J
5~

0 4l o
(J
0 10 20 30 40 50 o 4 10
VOS, ORAIN·T0-80URCE VOLTAGE (VOLTS) VGS, GATE·T0-80URCE VOLTAGE (VOLTSI

Fig. 1 - Typical Output Characteristics Fig, 2 - Typical Transfer Characteristics

5.0
10

~7
I--80LpuJE TEJ- /
!~
5.0 ~~110, 111
-'"':'~ 10 ps
4.0 BV Imwl~, '1'3,\ II
in
w AV ...-
./
-VGS=7V-
'"w
2.0
IRFOll0, III
-
.. -
1001'S
'"
~
:Ii
::; 3.0
,,;V ~
:Ii
::;
1.0

0.5
IRF0112,113
1 ms

~V
.... ....
~ ffi
'" '"a: 101m~
~
0.2
'"
:::I
'-' 6V- ~
z 2.0 z 0.1
lJO~s
~ ~ '"
;;: ;;:
'"
c a:
c 0.05
E
1.0
if/ _0 TJ =1500C MAX.
SI~G,LE PULSE

J.,..
0.02
5Y- II
0.01

o~
o
J_ 0.005
0.5 1.0 10 20
IRFOl1l,113
50 100 200 500
DC
IRFOllD,112

VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTSI

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

D-41
IRFD110, IRFD111, IRFD112, IRFD113 Devices

4.0 10

3.B I - - L", pJ
I I
LSE JST
I I I /.
VOS> 10(on) x ROS(on) max.

"'iii
~
3.2

2.B
i'"
::;
/ V
'/1
/

§
~ 2
w
c..>
z
2.4 0: I I
II II
0:
cc TJ =-55°C
I-
c..> 2.0 ~
z 1.0
~~
'"z
'"
0 L 1J =251o C ~ TJ-250C
1.5
'"
1/[.....0-' .....-
l;l w
z TJ =125°C I--TJ = 150 0 CI
cc '"
0:

h~ ~ ....-
W
0: 1.2
I- ;:;;
~ 0: I
O.B

1/1 P'" I
0.4

o
o
r
O. 1
0.2
.I
I

0.4 0.6 0.8

,
1.0 1.2 1.4 1.6 1.B 2.0
10. DRAIN CURRENT (AMPERES) VSO.SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 5 - Typical Transconductance Vs. Drain Current Fig. 6 - Typical Source-Drain Diode Forward Voltage

1.25 2.50

w 1.20 2.25
'"cc~ 1.15
w
c..>
z 2.00
0
>. .,/ ~
z
;;: 1.10 ./ ~ 1.75 ./
. /V V"
0 0:
0
z
'"ti5 c 1.05 0 0 1.50
~~
w .... 1.00
V
./
Ww
~!:::!
5 « 1.25 ./
,./
c..>CC
0:,"
",0: V ;g~ /'
00
<.?~
0
>-;-
0.95
/' "" ~~
;;:
0:
1.00

./
V'
./

z
« 0.90
"" '"
c
0.75
i-""'"
0:

'"~ 0.B5 ~
o
0.50 "'" VGS = 10V

.'"
>
O.BO
0:

0.25
10 = O.BA
i I
0.75 o
-60 -40 -20 20 40 60 80 100 120 140 -60 -40 -20 20 40 60 BO 100 120 140
TJ• JUNCTION TEMPERATURE (oC) TJ • JUNCTION TEMPERATURE (OC)

Fig. 7 - Breakdown Voltage Vs. Temperature Fig. 8 - Normalized On-Resistance Vs. Temperature

0-42
 IRFD110, IRFD111, IRFD112, IRFD113 Devices
500 20

JGsJ
.1 f=lMHz 1. J
400 Ciss =Cgs+Cgd.Cd,SHORTEO_
C", = Cgd ~ V~S = 2~V "-.
o 15

~V
CgsCgd - - ? Vps = 5~V "-.
w
Coss = Cds + Cus + Cgd to
~ ~ - I- VDS=BOV. IRFDll0. 112 .....
.., 300 - -
/~
w
Z
"'Cds + Cgd
C>
>
Y

,
c(
I- ~ 10

~
<; 11
c( '"
=>
.., I
Q. C>
c( 200 "?
o
<i
\ :-;;

\ ......... .........
tiss

C~
!;;:
to
,;,
5 V
100

\ >'" I 10 =4A

-- 10 20
C~
30 40
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)
50
/
4
1Ig. TOTAL GATE CHARGE (nC)
FOR TEST CIRCUIT- I--
SEE FIGURE 17
I
6
I I
10

Fig. 9 - Typical Capacitance V,. Drain·to-Source Voltage Fig. 10 - Typical Gate Charge V,. Gate-to-Source Voltage
1.0
2.0 ........
RDS(an) MEASURED WITH CURRENT PULSE OF ~
,.'" 2.0 ~ DURATION. INITIAL TJ = 25 0 C. (HEATING

'"
~
EFFECT OF 2.0 ~ PULSE IS MINIMAL.)
O.B
~
w I I ......... .......

'" "
'-' 1.5
z
tli ......
'"
t; I I ,.~ j'-.....
,,0110.111

~ V GS = 10V
~ 0.6

'"w
0
..,
'"=>0
1.0

J
I-

~
'"
~
z 0.4
IRF0112~ "' r'\..
......... ~,
~

~
"?
0
~
>-:-
z

"
'"0 0.5 V ~~
V GS = 20V- r---
0

E
0.2 ~
~
c
<%
0

'"
o
10 15 20 25 50 75 100 125 150
10 , DRAIN CURRENT (AMPERES) Tc. CASE TEMPERATURE (OC)

Fig. 11 - Typical On-Resistance V,. Drain Current Fig. 12 - Maximum Drain Current Vs. Case Temperature
1.6

1.4

.,
l-
1.2 RthJA'; 120 KIW- -

i
z 1.0
0
>=
;:t D.B
~
"- ~
........
i5
'"
~
~
0.6

""
.P 0.4

0.2

o
o 20 40 60 80
"
100
~
120 " ~
140
Tc. CASE TEMPERATURE (OC)

Fig. 13 - Power Vs. Temperature Derating Curve

0-43
IRFD110, IRFD111, IRFD112, IRFD113 Devices

VARY Ip TO OBTAIN

. i5
r,r-"L
YGS =
EAK
ILOUT

IL_-~>---"JVV~.J

Fig. 14 - Clamped Inductive Test Circuit Fig. 15 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIED ID Rl
Vi
PULSE

r-----'
I
GENERATOR

o - - - T O SCOPE
I
I 500
L_

Fig. 16 - Switching Time Test Circuit

r - - - O +V DS
(ISOLATED
SUPPLY)

SAME TYPE
ASDUT

O.-Cn·5mA - OUT

--'\J"\A_.....-V\J'V--o -VDS
IG ID
CURRENT ':' CURRENT
SHUNT SHUNT

Fig. 17 - Gate Charge Test Circuit

'.

0-44
 PD-9.331

INTERNATIONAL RECTIFIER IICiR I

HEXFET®TRANSISTORS IRFC912D
P-CHANNEL IRFC9121
HEXDlpTM
1-WATT RATED POWER MOSFETs
IRFC9122
IN A 4-PIN, DUAL IN-LINE PACKAGE
IRFC9123
-100 VOLT, 0.6 Otlm, 1-Watt HEXDIP • P-Channel Versatility
HEXFET technology is the key to International Rectifier's advanced
• For Automatic Insertion
line of power MOSFET transistors. Efficient geometry and unique • Compact, End Stackable
processing of the HEXFET design achieve a very low on-state
resistance combined with high transconductance and great device • Fast Switching
ruggedness. HEXFETs feature all of the established advantages of • Low Drive Current
MOSFETs such as voltage control, freedom from second break-
down, very fast switching, ease of paralleling, and temperature • Easily Paralleled
stability of the electrical parameters. • No Second Breakdown
The P-Channel HEXDIPs are designed for applications which
• Excellent Temperature Stability
require the convenience of reverse polarity operation or the simpli-
fication of complementary circuit configurations. For example, the
P-Channe11RFD9121 type is essentially the electrical complement to
Product Summary
the N-Channel IRFD111 type HEXDIP.
Part Number VOS ROS(on) 10
The HEXDIP 4-pin Dual In-Line Package brings the advantages of
HEXFETs to high volume applications where automatic PC Board IRF09120 -100V O.6il -1.0A
insertion is desirable, such as circuit boards for computers,
printers, telecommunications equipment and consumer products. IRF09121 -60V O.6il -1.0A
Their compatibility with automatic insertion equipment, low-profile
and end-stackable features represent the state-of-the-art in power IRF09122 -100V O.Sil -O.SA
device packaging.
IRFD9123 -SOV o.sn -O.SA

(0.140)
D
CJ",
I
,G

3.8zt:,
(0.150) . :1'
MAX. J 043{00111
031(o012l-ir
II

NOlES
CD APPLIES TO SPREAD OF LEADS PRr JR TO INSTALLATION

CD APPLIES TO INSTALLED LEAD CENTERS

Case Style HD·' (Similar to JEDEC Outline MO'()()11

ACTUAL SIZE Nominal Dimensions in Millimeters and \lnchesl

0-45
lRFD9120, IRFD9121, IRFD9122, IRFD9123 Devices

Absolute Maximum Ratings

Parameter IRF09120 IRF09121 IRF09122 IRF09123 Units
VOS Drain - Source Voltage Q) -100 -60 -100 -60 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) Q) -100 -60 -100 -60 V
10@T<=-= 25°C Continuous Drain Current -1.0 -1.0 -0.8 -0.8 A
10M Pulsed Drain Current -4.0 -4.0 -3.0 -3.0 A
VGS Gate - Source Voltage ±20 V
PO@TC-25OC Max. Power Dissipation 1.0 (See Fig. 13) W
UnBar Derating Factor 0.008 (See Fig. 13) W/K
ILM Inductive Current, Clamped (See Fig. 14 and 15) L =
loo"H
A
-4.0 I -4.0 I -3.0 I -3.0
TJ Operating Junction and
-55to 150 °c
T stg Storage Temperature Range

Electrical Characteristics @TC = 25°C (Unless Otherwise SpecHied)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF09120
IRF09122
-100 - - V VGS = OV
IRF09121
IRF09123
-60 - - V 10 = -250"A

V GSlthl Gate Threshold Voltage ALL -2.0 - -4.0 V VOS - V GS ' 10 - -250"A
IGSS Gate-Source Leakage Forward ALL - - -500 nA VGS - -20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA VGS - 20V
lOSS Zero Gate Voltage Drain Current - - -250 "A VOS - Max. Rating, VGS - OV
ALL
- - -1000 p.A VOS - Max. RatingxO.B, VGS - OV, TC - 125°C
10(on) On-State Drain Current ® IRF09120
-1.0 - - A
IRF09121
VOS ) 10(on) x ROS(on) max.' V GS = -10V
IRF09122 - -
-O.B A
IRF09123
ROS(on) Static Drain-Source On-State IRF09120
Resistance ® IRF09121 - 0.5 0.6 II
VGS = -10V,1 0 = -O.BA
IRF09122
IRF09123 - 0.6 0.8 II

gls Forward Transconductance ® ALL 0.8 1.2 - S(1lI VOS ) 10(on) x ROS(on) max.' 10 = -0.8A
Cjss Input Capacitance ALL - 300 450 pF
VGS - OV, VOS - -25V, I . 1.0 MHz
Coss Output Capacitance ALL - 200 350 pF See Fig. 9
erss Reverse Transfer Capacitance ALL - 50 100 pF
td(on) Turn-On Delay Time ALL - 25 50 ns VOO • 0.5 BVOS S ' 10 - -0.8A, Zo = 5011
tr Rise Time ALL - 50 100 ns See Fig. 16
tdloffl Turn-Olf Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperatura.)
tf Fall Time ALL - 50 100 ns
Qg Total Gate Charge VGS = -10V,1 0 - -4.0A, VOS - 0.8 Max. Rating.
(Gate-Source Plus Gate-Orainl
ALL - 16 20 nC
See Fig. 17 for test circuit. (Gate charge is essentially
independent of operating temperature.)
QgS Gate-Source Charge ALL - 9.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 7.0 - nC

LO Internal Drain Inductance - 4.0 - nH Measured from the Modified MOSFET

drain lead, 2.0mm symbol showing the
10.08 in.) from internal device
ALL package to center of inductances.
die .

LS Internal Source Inductance ALL - 6.0 - nH Measured Irom the

source lead, 2.0mm
(0.08 in.) Irom
package to source
bonding pad.
.$
Thermal Resistance
I RthJA Junction-to-Ambient ALL 120 KIW Free Air Operation

0·46
 IRFD9120, IRFD9121, IRFD9122, IRFD9123 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFD9120 Modified MOSFET symbol
(Body Diode) IRFD9121
- - -1_0 A
showing the integral
reverse P~N junction rectifier.
IRFD9122

~
IRFD9123 - - -0.8 A

ISM Pulse Source Current IRFD9120

- - -4.0 A
(Body Diode) IRFD9121
IRFD9122
IRFD9123
- - -3.0 A

VSD Diode Forward Voltage ® IRFD9120

- - -6.3 V TC = 25·C, IS = -1.0A, VGS = OV
IRFD9121
IRFD9122
IRFD9123
- - 6.0 V TC = 25·C, IS = -O.SA, VGS = OV
t" Reverse Recovery Time ALL - 150 - ns TJ = 150·C, IF = 4.0A, dlF/dt - 100 AIl's
ORR Reverse Recovered Charge ALL - 0.9 - I'C T J - 150·C, IF - -4.0A, dlF/dt - 100AII's
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'

(j) T J = 25·C to 150·C. ® Pulse Test: Pulse width'; 300I'S, Duty Cycle'; 2%.

-5
-5.0

-lOr
I- -7V sl 1" PulSE T E J - r-
J ..I.
I--BOI"PULSETEST.,
J. TJ,= -55 0,C,,---
ITJ=250~ ________
I IJ
-4.0 -4
I I I I
I-- VOS > 10(on) x ReS(on) max. _ TJ = 1250C
I
rL VI
~ ~
i'"
!!. -3.0 VGS=-6V- ~
ffi
"-
'"
!!. -3 /I
f-
ill
r f-
ill ill
:: '"'"
a
z
:;;:
-2.0
::>
u
z -2 if
'"
'"P
~
c
P
/J
5V- ~ A V
-1.0 -1

/.V
o
o -10 -20 -3~

Fig. 1 - Typical Output Characteristics

-40
VOS, ORAIN·TO-SOURCE VOLTAGE (VOLTS)
-4V- ~

-50
o
-2 -3 -~~
-4
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 2 - Typical Transfer Characteristics

-5 -6 -7

-5 -10

~z/
~
-SOJ,PULS!TEST f--
..... / -5.0 IRFD9120.9121
I/~~f. V -8V ~
lOll'
,
-4
:l!~j'912~
h't
-2.0
V-7V
" lriO~'
i'" -3 I/J ~ .'"
:i1
w
:E
!!.
-1.0

-0.5
IRFD9120,9121

IRFD9122,9123
1m.

....
!!.
f-
Z
w II 'I V=-6V-
r-
ill
~ -0.2
I'. 10ms
'"'"
::> fl V ::>
u
I
J. rr
u -2
z Z -0. 1
;;: lOOms
~ '"~
'" -0.05

If! ....- -
TJ = 1500C MAX.
P !---5V SINGLE PULSE
-1
-0.02
~V
r -1 -2
-4~
-3 -4 -5
-0.01

-0.005
-0.5 -1.0 -2 -5 -10 -20
IRFD9121,9123

-50 -100 -200 -500

DC
lIiFD9120, 9122

VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS) Vos, ORAIN-TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig.4 - Maximum Safe Operating Area

0-47
IRFD9120, IRFD9121, IRFD9122, IRFD9123 Devices

-10

-5
, ,
/
'"w //
'"
~
0;
z
w '"
~
.... -2 'I
~ z
w TJ'150 DC / /
iii
w
<.>
'"'"
",
<.> / if
z z -1
....
'"
<.>
;;:
",
0
'"0
z w
I
0
l;l
'"
'"w -0.5
I
~
Z

'"'"
.... Ii
I !TJ.25DC
~ E'
-11.2
I
I I
-0.1 I
o -1 -2 -3 -4 -5 -6
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TD·DRAIN VOLTAGE (VOLTS)

Fig. 5 - Typical Transconductance Vs. Drain Current Fig. 6 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w 1.20
w
'"'"
:; 1.15
<.>
z 1.8
0
> ,,/ '"
I;;
;;;
/
z ./
;:
0
0
1.10

. /V
w
'"06
z
1.4
,/
'"~ffi 1.05 Ww
V"
III!::!
./
V <'>N
a:-
", .... ./
",,,,
~~ 1.00 0'"

",,,,
0 0
.... ;; 0.95
.,. / .... :E
0'"
I-;-~
z - 1.0
./
V
0
'":"
z 0.90
... V
;;:
a:
0 ./ V
;;: .",
~
'"
0

>
III
!li
0
0.85

0.80
0
a: 0.6 V VGS' -10V
IO·-·8A -
I I
--
0.2
0.7~0 -40 -20 20 40 60 80 100 120 140 -40 40 80 120
TJ.JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 7 - Breakdown Voltage VI. Temperature Fig.8 - Normalized On-Resistance Vs. Temperature

0-48
 IRFD9120, IRFD9121, IRFD9122, IRFD9123 Devices
SOD
.. 1. .1
\ l I I
Ciss = Cgs + Cgd. Cds SHORTED
I

~ I~=J I
VGS 0 _
I--crss = Cgd -

400
\\ t= 1 MHz
Cgs Cgd
- I--

~~
Coss = Cds + egs + Cgd

"'Cds + Cgd
.-
~ \ FOR TEST CIRCUIT
SEE FIGURE 17

,
~ -5

~
..,zw 300
r\- I"'-- Ciss
I w
'"
""
':::;
r\
«
.... ~ '">w
\ i'- C~ ......
U
«
..,~ 200
..........
--.
~
:::>

'"".'
-10
r-- ~ ~
U

100
\
~
--- ~
!;[
~ -15
VOS = -SOV.IRF09120. 9~22/

VOS = -50V"
:) ~ ~
to
/
f""'. r-- _Crss
>
vIOS' JOV/'

-20
-10 -20 -30 -50 o 12 16 20
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 9 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 10 - Typical Gate Charge Vs. Gate-to-Source Voltage
-1.0
2.0
ROS(on) MEASURED WITH CURRENT PULSE OF
........ .......
2.0 ~s DURATION. INITIAL TJ = 25°C. (HEATING
'"
'"
:r
EFFECT OF 2.0 Ps PULSE IS MINIMAl.)
"'-
, ""'"
1
8
..,wz 1.6 -0.8
......... .......
« VGS l-10V '"
W
........ ,09120.9121
.... II:
~
......
'"
iii
II: 1.2 ~ -0.6

IRF091:.~ "" '"

z ....
15
..,'"w II:
.......
/
II:
II: :::>

" '"
:::>
~ ~ -0.4

",
0.8
..,'"z ~ :
- ./ c
:'" I--
VGS -20V_
E
\\
~ 0.4 r-- -0.2
.2
gs
II:

o
·5 ·10 ·15 ·20 ·25 25 50 75 100 125 150
10 , DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (OC)

Fig. 11 - Typical On-Resistance Vs. Drain Current Fig. 12 - Maximum Drain Current Vs. Case Temperature
1.6

1.4

1.2 RthJA ~ 120 KIW- I--

i
z 1.0
'"
~
~
Q
II:

....,~
o.s

0.6
" "' "'-r"oo..

...Ci 0.4

0.2

o
o 20 40 60 80
"'"
100
TC. CASE TEMPERATURE (OC)
120
"-i'..
140

Fig. 13 - Power Vs. Temperature Derating Curve

0-49
IRFD9120, IRFD9121, IRFD9122, IRFD9123 Devices

, ,, r---
VARY tp TO OBTAIN
REQUIRED PEAK IL
", ,
VGS fr:J
=
~
..,OU_T~_.--"
IL +----<1>--_-'11Il10--'
I
f--
IL./"
" ,
tp-----j
"

Fig. 14 - Clamped Inductive Test Circuit Fig. 15 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
GENERATOR O,U,T,
r-----.,
I
50n I o - - _ T O SCOPE
I I o,om
I
L_
I
_ __ ...1 50n
10
+ HIGH FREQUENCY
SHUNT

Fig. 16 - Switching Time Test Circuit

10
CURRENT
SHUNT

o...,---rr.
L-J.r: 5mA
OUT

'-----111-----4____ ---_----0 -VOS

(ISOLATED
SUPPLY)
Fig. 17 - Gate Charge Test Circuit

0-50
 PO-9.343

INTERNATIONAL RECTIFIER IICiR I

HEXFET@TRANSISTDRS IRFF11D
N-CHANNEL IRFF111
POWER MOSFETa IRFF112
TO-39 PACKAGE
IRFF113
100 Volt, 0.60 Ohm HEXFET@ Features:
The HEXFETI!> technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state
resistance combined with high transconductance and • No Second Breakdown
great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature sta- Part Number VOS ROS(on) 10
bility of the electrical parameters. IRFFll0 100V 0.6n 3.5A
They are well suited for applications such as switching IRFFlll 60V 0.6n 3.5A
power supplies, motor controls, inverters, choppers, IRFFl12 100V o.sn 3.0A
audio amplifiers, and high energy pulse circuits. IRFFl13 60V o.sn 3.0A

CASE STYLE AND DIMENSIONS

4.57 (0.18) 5.08(0.20)

~:~~;;:l::)
MAX.
9.14 (0.36) DIA. ~
~ 0.4510.018)
4.57 !O.lS()l
4.3010.169)

t
1422 (0.56) MAX.
0.36(0.014)

r'9i=i'i"'ii"W-'-,8.0310.7,)

i 14.22 (0.56)
12.7010.50) ~.
REF

~ ~~:~ ~~~t DlA.

3 PLACES
Conforms to JEDEC Outline TO·205AD (TO·39)
All Dimensions in Millimeters and (Inches)

0-51
IRFF110, IRFF111, IRFF112, IRFF113 Devices

Absolute Maximum Ratings

Parameter IRFFll0 IRFFlll IRFFl12 IRFFl13 Units
VOS Drain - Source Voltage <D 100 60 100 60 V
VOGR Orain - Gate Voltage (RGS ~ 1 Mill CD 100 60 100 60 V
10@TC ~ 25°C Continuous Drain Current 3.5 3.5 3.0 3.0 A
10M Pulsed Drain Current ® 14 14 12 12 A
VGS Gate - Source Voltage ±20 V
PO@TC ~ 25°C Max. Power Dissipation 15 (See Fig. 14) W
Linear Derating Factor 0.12 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L ~ 100pH
A
14 I 14 I 12 I 12
TJ Operating Junction and
-55to 150 °c
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °c

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRFFll0
IRFFl12
100 - - V VGS = OV
IRFF111
IRFFl13
60 - - V 10 = 250pA
VGSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 - 250pA
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS ~ -20V
lOSS Zero Gate Voltage Drain Current - - 250 pA VOS - Max. Rating, VGS - OV
ALL
- - 1000 pA VOS ~ Max. Rating x 0.8, VGS ~ OV, TC ~ 125°C
10(on) On-State Drain Current ® IRFF110
3.5 - - A
IRFFll1
V OS ) 10(on) x ROS(on) max.' V GS ~ 10V
IRFF112
IRFF113
3.0 - - A

ROS(on) Static Drain-Source On-State IRFF110

- 0.5 0.6 0
Resistance ® IRFF111
IRFFl12
VGS ~ 10V, 10 = 1.5A
IRFF113 - 0.6 0.8 0

gfs Forward Transconductance ® ALL 1.0 1.5 - S(U) VOS ) 10(on) x ROS(on} max.' 10 - 1.5A
Ciss Input Capacitance ALL - 135 200 pF
VGS = OV, VOS ~ 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 80 100 pF
See Fig. 10
e r5S Reverse Transfer Capacitance ALL - 20 25 pF
td on Turn-On Delay Time ALL - 10 20 ns VOO ~ 0.5 BV OSS ' 10 ~ 1.5A, Zo ~ 500
tr Rise Time ALL - 15 25 ns See Fig. 17
td(off) Turn-Off Delay Time ALL - 15 25 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 10 20 ns
Qg Total Gate Charge V GS ~ 10V, 10 = B.OA, VOS ~ 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 5.0 7.5 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 2.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 3.0 nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured from the Modified MOSFET
drain lead, 5 mm (0.2 symbol showing the
in.) from header to internal device
center of die. inductances .

LS Internal Source Inductance ALL - 15 - nH Measured from the

source lead, 5mm (0.2
in.) from header to
source bonding pad.
.@)
Thermal Resistance
RthJC Junction-to-Case
RthJA Junction-ta-Ambient Free Air Operation

0·52
 IRFF110, IRFF111, IRFF112, IRFF113 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFFll0 Modified MOSFET symbol
(Body Diode) )RFFlll - - 3.5 A
showing the integral
IRFF112 reverse P~N junction rectifier.
- - 3.0 A

~
IRFF113
ISM Pulse Source Current IRFFll0
(Body Diode)@ IRFFlll
- - 14 A

IRFF112
- - 12 A
IRFF113
VSD Diode Forward Voltage ® IRFFll0
IRFFlll
- - 2.5 V TC = 25°C, IS = 3.5A, V GS = OV

)RFFI12
)RFFI13
- - 2.0 V TC = 25°C,)S = 3.0A, V GS = OV

t" Reverse Recovery Time ALL - 200 - ns TJ - 150°C, IF = 3.5A,d1 F/dt = 100A/~s
QRR Reverse Recovered Charge ALL - 1.0 - ~C TJ = 150°C, IF = 3.5A, dlF/dt = 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'

<DTJ = 25°C to 150°C. ®Pulse Test: Pulse width .. 300~s, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

8.0 8.0

J~PUJSET~_ f-- _ID!~'PU+TE~

IOVJ9V / I
7.2 7.2

B.4 I •.4 -
VDS> ID(on) x
ROS(on) max. - TJ. \25OC / /
8 i = Fo-
........
;;r
5.B
...
;;r
..."- 5.•
I "-....
TJ = 25 C0 1. I J

t
II<
"-
I I "-.... IJ

......... ,
:IE :IE TJ = -55 0 C
~ 4.8
.... ......z~ 4.8
z
4.0
VGS·7r- ~
II< 4.0 'I ~/
::>
I ...z
II<
::>
Ii /
..
z 3.2
C
CI ~- ~
;;C
II<
CI
3.2

2.4 '-
/.,
2.4
P
I.B I P
1.6 I
5~- I--
0.8 0.8

0
4~_ I-- o ~ ~
0 10 20 30 40 50 o 10
VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTS) VGS. GATE·TO.sOURCE VOLTAGE (VOLTS)

Fig, 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
••0
50
7.2 OPERATION IN THIS
AREA IS LIMITED
6.4 20 IRFFIIO. I BY ROS(on)

.....
en

~
:IE
5.6
'"w
~
::E
~
10 ~~I2.i' 10~,

4:

........
....
z
II<
::>
ffi
'"'"::>
IRFFIIO,I

IRFFI12,3 I',
106 ~,

z 3.2
'"
z 1m,
C
II<
CI

P
2.4
~
c

- 0.5
Q
1.0

=
='TC = 25 0 C
TJ = 1500 C MAX.
" lor'
_ RthJC = B.33 KIW
IRFFll1,3 100m,
0.2 _ISI~GLr PULS E
OC
II .111 IRtTO'I2 I
0. I
~ ~ U ~ U ~ » u u " 1.0 10 20 50 100 200 500
VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTS) Vos, ORAIN·TO.sOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area
0-53
IRFF110, IRFF111, IRFF112, IRFF113 Devices

NOTES:
iiiii""'"
~~
!;;ill
lf1JL
~2~
1. OUTY FACTOR. 0 = :~
~
"
SINGLE PULSE (TRANSIENT 2. PER UNIT BASE = R'hJC = 8.33 OEG. CIW.
- mERMi l iMPEiAiTI II 3. TJM - TC = POM Z'hJC(t)·

10-4 10-3 10-2 10-1 1.0 10

'1. SQUARE WAVE PULSE DURATION (SECONDS)
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

4.0 10

3.6 f--J., PU!SETES~

I~(on);
I
m.~.
..
~
3.2
V'OS > ROS(on)
13
~ / V
-'
/

~
2.8
'">-
~
"I
...z I I
..
w

t; 2.0
::>
2.4

,.,
TJ' -55 0 C
IE0:
II:
13
2 1.0 II II
0 TJ' 250 C ;;:
z
/
.....'"
0:
0
1.6 0
I-""'" TJ' 125 0 C ~ TJ= 150·C I
z
II: 1.2 J. L ~
_
>- ~
~ ~ I
r "'"
0: TJ = 25 0 C
0.8
'"
0 I
0.4

o 0.1 I
o 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0 o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO-DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.50

...
..
'"~
1.20

1.15
w
u
z
«
t;
2.25

2.00
0
> ,/ iii0:
z
1.10 ./ 1.75 /
i50 w
i"
. /V
>-
""
:is 1.05
«
>--
' 1 0 1.50
:/
. /V
w
g;~ ,,/" 2
ON
w ....
w .... 1.00 ./ u« 1.25
li1! ,/ 0:'"
::>0: ,,/"
~~ -"
00
0.95 -" 6~ 1.00
0
,,/" ':" ,/
':" JI' z ./
z 0.90 ;;: 0.75
~
0
0:
0 I ....... I-""'" VGS = 10V
~ 0.85 cQ 0.50
0
10 = 15A
1;; '"
~ 0.25 I I
0.80

0.75 o
-60 -40 -20 20 40 60 80 100 120 140 -60 -40 -20 20 40 60 80 100 120 140
TJ• JUNCTION TEMPERATURE (DC) TJ.JUNCTloN TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-54
 IRFF110, IRFF111, IRFF112, IRFF113 Devices
500 20

J GS ' 0'
'i 1 MHI' .I .l.
400 Vas = 20V"",
Cill - CII ' Cgo!. Cd. SHORTED

~r
- VpS-5~V"",
C.. - Cgo!

~
Ei: Vas = BOV, IRFFll0, 112
.....
~

z
~
300 C.-Cdl+
"'Cd.' CgoI
+C
II go! - r--
./ ~
~
./~ 1./
~
U
c

..3 zoo I

"\ ", /
'
cL
\ ........ C!..
100
/
-
10 = BA

C~ Ii
FOR TEST CIRCUIT- -

10 20 30 40 50
V 4
Si E FIGiRE

6 10
Vos. DRAIN·TO-SOURCE VOLTAGE (VOLTS) Dg, TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

2.0
RDS(on) MEASURED WITH CURRENT PULSE OF
2.0 p. DURATION. INITIAL TJ = 250 C. (HEATING
i:z: EFFECT DF 2'r' PULSE IS MINIMAL.)
...S
u
~ 1.5 iii
vis a: ........ ..........
i ~

--......... ............. ..................

-10V
:E
a: !!'. 3
z
...~
c ~
z
w
.............. ;::~0,111
1.0 a:
::. a:
::.
!ij u
.,.z
c z
~
2 IRFF112, 113 ~~

;;:
a: / i.-
c
p
~
,
c, 0.5
VGS = 20V
~
c
a: ~
o
10 15 20 25 50 15 100 125 150
10. DRAIN CURRENT (AMPERESI TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On,Resistance Vs. Drain Current Fig. 13 - Maximum Drain CUrrent Vs. Case Temperature
20

" ,,
r\..

'r\..

" "- r'\..

'""
20 40 60 80 100
TC, CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

120 140
"
0·55
IRFF110, IRFF111, IRFF112, IRFF113 Devices

r,p-l
R
VARY,p TO OBTAIN

VGS= I...,~U_T-"'r-"'r I
L'y .....
"" \
\
E,

IL_--<>--~~w.---' " '-------

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST Rl
TO OBTAIN

PULSE
GENERATOR D.U.T.
r------,
I
50n I 0---+ TO SCOPE
I o.om
I ___ .JI SOn HIGH FREQUENCY
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

,--__<> +VDS
(ISOLATED
SUPPLY)

oI=n·5mA - IG
\,...._~''''',,-o -VOS
ID
CU RRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-56
 PO-9.342

INTERNATIONAL RECTIFIERI:rORI

HEXFET@TRANSISTDRS IRFF12D
N-CHANNEL IRFF121
POWER MOSFETa IRFF122
TO-39 PACKAGE
IRFF123
100 Volt, 0.30 Ohm HEXFET@ Features:
The HEXFET'I' technology is the key to International
• Fast Switching
Rectifier's advanced line of power MOSFET transis- • low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state
resistance combined with high transconductance and • No Second Breakdown
great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
esta'blished advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature sta- Part Number VOS ROS(on) 10
bility of the electrical parameters. IRFF120 100V O.30n 6.0A

They are well suited for applications such as switching IRFF121 60V O.30n 6.0A
power supplies, motor controls, inverters, choppers, I RFF122 100V O.40n 5.0A
audio amplifiers, and high energy pulse circuits. IRFF123 60V O.40n 5.0A

CASE STYLE AND DIMENSIONS

DRAIN
;.f
GATE
:./2:
SO
• ~
0.86(0,0341
0.72 (0.02.,
rvo.B81 0.03SI

SOURCE

S.0810.201

9.14 (0.36) DIA.

~:~ l~:mi: DlA.

3 PLACES
Conforms to JEDEC Outline TO-206AD (T0-391
All Dimensions in Millimeters and (Inches)

D-57
IRFF120, IRFF121, IRFF122, IRFF123 Devices

Absolute Maximum Ratings

Parameter IRFF120 IRFF121 IRFF122 IRFF123 Units
VOS Drain ~ Source Voltage <D 100 60 100 60 V
VOGR Orain - Gate Voltage (RGS = 1 Mil) (j) 100 60 100 60 V
10@TC - 25°C Continuous Drain Current 6.0 6.0 5.0 5.0 A
10M Pulsed Drain Current @ 24 24 20 20 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 20 (See Fig. 14) W
Linear Derating Factor 0.16 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = lOOI'H
A
24 I 24 I 20 I 20
TJ Operating Junction and
T stg Storage Temperature Range
-55to 150 °c
Lead Temperature 300 (0.063 in. (1.6mm) from case for 105) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRFF120
IRFF122
100 - - V VGS = OV

IRFF121
IRFF123
60 - - V 10 = 25Ol'A

VGS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL.
- - 250 I'A VOS - Max. Rating, VGS - OV
- - 1000 I'A VOS = Max. Rating x O.B, VGS = OV, T C = 125°C
10(on) On-State Drain Current ® IRFF120
6.0 - - A
IRFF121
V OS ) 10(on) x ROS(on) max.' V GS = 10V
IRFF122
IRFF123
5.0 - - A

ROS(on) Static Drain-Source On-State IRFF120

Resistance ® IRFF121 - 0.25 0.30 Il
VGS = 10V, 10 = 3.0A
IRFF122
IRFF123
- 0.30 0.40 Il

9fs Forward Transconductance ® ALL 1.5 2.9 - SUl) V OS ) 10(on) x ROS(on) max.' 10 = 3.0A
CISS Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 200 400 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 50 100 pF
td(on) Turn-On Delay Time ALL - 20 40 ns VOO ~ 0.5 BVOSS,IO = 3.0A, Zo = 501l
tr Rise Time ALL - 37 70 ns See Fig. 17
td(off) Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
Fall Time ALL - 70 ns independent of operating temperature.)
tf 35
Qg Total Gate Charge V GS = 10V, 10 = lOA, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 10 15 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 6.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 4.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured from the Modified MOSFET
drain lead, 5 mm (0.2 symbol showing the
in.) from header to internal device
center of die. inductances .

LS Internal Source Inductance ALL - 15 - nH Measured from the

source lead, 5mm (0.2
in.) from header to
source bonding pad.
.@)
Thermal Resistance
RthJC Junction-to-Case
RthJA Junction-to-Ambient Free Air Operation

0-58
 IRFF120, IRFF121, IRFF122, IRFF123 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFF120 Modified MOSFET symbol
(Body Diode) IRFF121
- - 6.0 A
showing the integral
IRFF122 reverse P-N junction rectifier.

~
- - S.O A
IRFF123
ISM Pulse Source Current IRFF120
(Body Diode)@ IRFF121
- - 24 A

IRFF122
- - 20 A
IRFF123
VSD Diode Forward Voltage ® IRFF120
- - 2.S V TC = 2S·C, IS = 6.0A, V GS = OV
IRFF121
IRFF122
IRFF123 - - 2.3 V TC = 25·C, IS = 5.0A, V GS = OV
trr Reverse Recovery Time ALL - 230 - ns T J - 150·C, IF - 6.0A, dlF/dt - 1 OOA/~s
ORR Reverse Recovered Charge ALL - 1.2 - ~C T J - 150·C, IF 6.0A, dlF/dt - 100A/!,s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j)TJ = 25·C to 150·C. @PulseTest: Pulse width" 300I'S, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

10

-J"'PUlETES~
10
/IOJ 80 ~ PULSE TEST
I
/1
1./ 9r- I-- 16
VOS> 10(on) x ROS(on) max. II,
16
I ~
TJi'1501~
AI /
l~ BV- I-- ~
~ 11
Ty15·1~ f) rY
... TJ"5501~
I ~
'1J
VGS 7
1- I-- az h 'I
6 l - I--
~ 'I'
'I E
J
5V- r- .J"
4~- I-- ~~
10 10 30 40 50 10
VDS. DRA1NTO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS

--
10 50 AREA IS LIMITED

~J
w
BY AOS(on)
80 PUlSE1TEST -
YIf
tiV'"~ i-""'" ;~~~
I}V ..I........ 10 lOll'

J. iv i
~ 7
i,. 10 -ttU. "
100ll'
= IRFFI20. 1
I!. 'f' ~
... IAFF122,3 ,
II '/ VGS·6V- ~ 1 m,
'"
::::> I
§L /" «
'-'
z I"-
I
\
J. 'I'
1.0
'"
c 10ms

)
t-
Iff
~ - I -1--5Y

4y
E =TC 15 0C
0.5 =TJ 150 0C MAX.
_ R, hJC - 6.25 K/W

0.2 -[SliGLi ~U~SIE[I

I IIIII I~FF~211' ~
100 m,

DC
I RfF1120. 12
0.1
1.0 10 20 50 100 200 500
VOS. DRA1N·TO·SOURCE VOLTAGE (VOLTS) VDS, DRAIN·TO·SOU RCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-59
IRFF120, IRFF121, IRFF122, IRFF123 Devices
.....
ili
~
'"
a:_

. . ....
........ 1.0
wz
>::>
0=0.5
fi ffi 0.5 NOTES:
$~
~~
:nt~
0.2
l-b.l
0.2

-- ~
lJlJL
~2~
*
~!! 0.1
a: ....
1=0.05
~~ 0.05

j~
-a:
"'w ra.02 .,. 1. DUTY FACTOR. 0 =
0.01
E.., 0.02
i'"""'T"
....SINGLE PULSE (TRANSIENT 2. PER UNIT BASE = RthJC = 6.25 OEG. CIW.
THER,MA,L I,MrE,O,~~CE) , 3. TJM - TC = POM ZlhJC{t)·
~ 0.01
10-5 10-4 10-3 10-2 1.0 10
11. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

/
./
./'
i--"""
V
- -I-'" -1 I
TJ -550

TJ!1250b
L_-::
I-'" .... J=250~- 1--=
~ 0;
w
a:
~
~
....z
w
a:
a:
..,::>
10
~
~
~
;
~
....

I-'"
IV ........ f.- z
C

~ V a:

'" 11

,
0
w
lLlI' '"
0:
W
>
W f - - TJ = 1500 C
III
I
vos> 10(on) x ROS(on) max.
/ I/
0:
ci:
E' TJ =25 0 C
80,1 PULSj TEST
I I

o· 12 16 20
1.0
o
I
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.50

W
to
1.20 ..,zw 2.25

~
o 1.15 ~ 2.00
>
........ iii
~
o
1.10
V~
~
~
1.75
,/
....'"
~a 1.05 ~
~~ 1.50
:i~ ...... V ~~
./'
V
~~ 1.00 ~;i 1.25

......V ...... /
0:'"
::>a: ::>
0:
00
~~ 0.95 6~ 1.00

~C V ..,.
........ "....
a:
o
0.90

0.85
./ :iz
o
c
0.75

0.50
,., ~
VGS = 10V
)0= 3A
~
0.80 ~ 0.25 i I
0.15 o
-60 -40 -20 20 40 &0 &0 100 120 140 -60 -40 -20 20 40 60 80 100 120 140
TJ.JUNCTION TEMPERATURE (OC) TJ• JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs_ Temperature
0-60
 IRFF120, IRFF121, IRFF122, IRFF123 Devices
1000

J GS '0'
20

I f,= 1 MH,' I
800 CilS = Cgo + Cgd. Cd. SHORTED
C'" = Cgd
- in
~
15
VOS ~ 20V "-
- "
~~
~
~
~
VOS = 50V
... w
I

"1'
COlI = Cd. + go + Cgd <.0
"- « VOS = BOV, IRFFI20, 122
... 600 - ~

..!::...
w

........
~Cds+ Cgd ~
">w ~
~

- I
Z

Ciss 10 ~

.....~ ~ '-'
co
400
=>
"'1 ~
"':"w
'"
U
I
\ ......... r-. Coa
>-
«
<.0 5 II
200
\ '"
<.0

J
I~= IDA

) >
FOR TEST CIRCUIT
r---

10 20 30
'"
40 50
/ 12
TFTREr

16 20
VOS' ORAIN·TO-SOURCE VOLTAGE (VOLTS) 0g' TOTAL GATE CHARGE (nCI

Fig. 10 - Typical Capacitance Vs_ Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

0,8 6.0
~~
u;
:IE
:I:
B 4.8
1'00.. ~
w
VGS '10V ~ 1'00.. .......
~
'-' 0.6
z IRFF120.121
«
>- '"cow
r--.... ~
'" ""
'"
fij ~
co ~ 3.6
~
z >-
"
w
'-' 0.4
~
IRFFI2D
~
~
co
=>
"
'1 ) =>
'-'
z 2.4

- "~
,
"':"z :;;:
:;;:
- ~
~
~
co
c
i?
"'~
co
c 0,2 VGS = 20V
c 1.2

co'""
0

I- ROS(on) MEASURED WITH CURRENT PULSE OF

I
2.0~sOURATION. INITIAL TJ=25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.l
o
10 20 30 40 25 50 75 100 125 150
TC. CASE TEMPERATURE (DC)
10. DRAIN CURRENT (AMPERES)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
20

..~
~
z
c
15 '"" \.
'\
~
a- \.
0; ID
'"0
co
w
'\
~

"'"
a-
,,;
a-

i\
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-61
IRFF120, IRFF121, IRFF122, IRFF123 Devices

VARY., TO OBTAIN

i5PEAKI~UT
VGS-:r.r-t,L
I L _ - - - ( l _ -_ _ _ _--'

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TOOSTAIN
SPECIFIED 10 RL
Vi
PULSE
D.U.T.
r-----'
GENERATOR

I !iOn TO SCOPE
I I
I
L_ ___ .JI !iOn lot O.Ola
HIGH FREQUENCY
SHUNT

Fig. 17 - Switching Time Test Circuit

r - - - O +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

oI ] I l . 5 m A - IG
OUT

ID
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0·62
 PD-9.341

INTERNATIONAL RECTIFIER I I\)R I

HEXFET@TRANSISTORS IRFF'-'3D
N-CHANNEL IRFF'-'3'-'
POWER MOSFETs IRFF'-'32
TO-39 PACKAGE
IRFF'-'33
100 Volt, 0.18 Ohm HEXFET@) Features:
The HEXFETI8 technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state
resistance combined with high transconductance and • No Second Breakdown
great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature sta- Part Number VOS RDS(on) 10
bility of the electrical parameters.
IRFF130 100V O.18n 8.0A
They are well suited for applications such as switching IRFF131 60V O.18n 8.0A
power supplies, motor controls, inverters, choppers, IRFF132 100V O.25n 7.0A
audio amplifiers, and high energy pulse circuits.
IRFF133 60V O.25n 7.0A

CASE STYLE AND DIMENSIONS

5.0810.201
, 1410.361
[)IA.
9.14 (0.36) 01

0.4510.0181
r8.25()~~~1251 4.5710.1801
4.3010.1691
0.3610·
L,.""ii'"ii"'i'W-L
I 18.0310.711
14.2210.561 REF
12.7010.501 ~.

~:l; :~:~~i: OIA.

3 PLACES

Conforms to JEDEC Outline TO·205AD (TO·39)

All Dimensions in Millimeters and (Inches)

0-63
IRFF130, IRFF131, IRFF132, IRFF133 Devices

Absolute Maximum Ratings

Parameter IRFF130 IRFF131 IRFF132 IRFF133 Units
VOS Drain - Source Voltage CD 100 60 100 60 V
VOGR Drain - Gate Voltage IRGS - 1 Mil) (j) 100 60 100 60 V
10@TC-25'C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10M pulsed Drain Current (~)" 32 32 28 28 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25'C Max. Power Dissipation 25 ISee Fig. 14) W
Linear Derating Factor 0.2 ISee Fig. 14) W/K
IlM Inductive Current, Clamped ISee Fig. 15 and 16) l = 1OO~H
A
32 I 32 I 28 I 28
TJ Operating Junction and
Tsta Storage Temperature Range
-55to 150 'c
Lead Temperature 300 10.063 iA. 11 .6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRFF130
IRFF132
100 - - V VGS = OV
IRFF131
IRFF133
60 - - V 10 = 250~A
VGS~tl:!L Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS' 10 - 250~A
IGSS Gate-Source Leakage Forward All - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ~A VOS - Max. Rating, VGS - OV
- - 1000 ~A VOS = Max. Rating x 0.8, VGS - OV, TC - 125°C
1010n) On-State Drain Current ® IRFF130
8.0 - - A
IRFF131
V OS ) 1010n) x ROSlon) max.' V GS = lOV
IRFF132
IRFF133
7.0 - - A

ROSlon) Static Drain-Source On-State IRFF130

Resistance ® IRFF131
- 0.14 0.18 0
VGS = 10V, 10 = 4.0A
IRFF132
IRFF133
- 0.20 0.25 0

Forward Transconductance ® ALL 4.0 5.5 - SIIll VOS ) 1010n) x ROSlon) max.' 10 4.0A
9fs
Ciss Input Capacitance ALL - 600 800 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 300 500 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 100 150 pF
tdlonl Turn-On Delay Time ALL - 30 50 ns VOO = 0.5 BV OSS ' 10 = 4.0A, Zo = 500
tr Rise Time ALL - 80 150 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 80 150 ns
Qg Total Gate Charge V GS = 10V, 10 = 18A, VOS = 0.8 Max. Rating.
ALL - 18 30 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Ogs Gate-Source Charge ALL - 9.0 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 9.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured from the Modified MOSFET
drain lead, 5 mm 10.2 symbol showing the
in.) from header to internal device
center of die. inductances .

LS Internal Source Inductance ALL - 15 - nH Measured from the

source lead, 5mm (0.2
in.) from header to
source bonding pad.
.@)
Thermal Resistance
RthJC Junction-to-Case
Rth A Junction-to-Ambient Free Air Operation

0-64
 IRFF130, IRFF131, IRFF132, IRFF133 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRFF130 Modified MOSFET svmbol
(Body Diode) IRFF131
- - 8.0 A
showing the integral
reverse P-N junction rectifier.
IRFF132
- - 7.0 A

~
IRFF133
ISM Pulse Source Current IRFF130
(Body Diode) @ IRFF131 - - 32 A

IRFF132
IRFF133
- - 28 A

VSD Diode Forward Voltage ® IRFF130

- - 2.5 V TC = 2S"C,I S = B.OA, V GS = OV
IRFF131
IRFF132 = 2S"C,I S = 7.0A, VGS
IRFF133
- - 2.3 V TC E OV

trr Reverse Recovery Time ALL - 300 - ns TJ = 150"C,I F = B.OA, dlF/dt - 100A/~s
QRR Reverse Recovered Charge ALL - 1.5 - ~C TJ = 150"C,IF - B.OA, dlF/dt = 100AJ~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LOo

(j)TJ = 2S"C to IS0"C. @PulseTest: Pulse width .. 300~s, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5),

20 20
10VJla:V
LpulETEJT _ f-- ~ lO.,JLSE TElT I 1/
I ~.x. I(
~
16
/
7V_
--- ~
16
VDS> lO(on) 'x ROS(on)

J
..
~
~ 12
.
II:
le
~ 12
I
~

~ VGS=6~=
~
~

~
II:
rI
B V- I
II:
:>
/h
z '"z
::'" :: '(II
Si-r- '"
E
r E TJ' +1250 C Ii rJ
-
TJ·250C
--::: fj)
10 20 30 40
4r-r-
50
TJ=t c
av 10
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATHO.sOU RCE VOLTAGE (VO LTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
10 AREA IS LIMITED
ao .. PULSE TEST
lOJ /. ~V 50
r-:-~130,1
BY RDS(on)

9~--::: ~ ~V ./ 20 IRrF:32,~.t 10!,s

8V~
~ :/1v ,/ ill
.
II:
w 10 '=:
1= :R~F~io ' \ r, "- lOa!'.

~ 'l ~ :e
5
~
IRFF132,3
1m.
~~ / ~ I

--
II:
II:
I
~V
:>
~ '"
z 10 m'

;~ y
....... 5V ;;: 1 l
1.0
V II:
'"
E t:: _
TC = 25°C 100 ms

~ ~,/
0.5 :==TJ = 150°C MAX.
_ _ RthJC = 5.0 KIW
~ I

-
DC
0.2 _ _ ISINFL~ ~~~~~ (
~ IGS ' 41
0.1
j I 111111 I~FFI31(, ~ 'Rf F13o,(2

0.4 0.8 1.2 1.6 2.0 1.0 10 20 50 100 200 500

VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS. ORAIN·TD.sDURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-65
IRFF130, IRFF131, IRFF132, IRFF133 Devices

I-
~
iii«
a:_
I-!:: 1.0
wz
>::> D = 0.5
t ffi 0.5

-
NOTES:
tt:; ~~.2 ~
w'-'

FUL
---
~ ~ 0.2
......
~ffi ~~.1
~!! 0.1
EO.05
~2~
--
a: ....
0«
z_~ 0.05
'-'w
:;:!o::
f-- 0•02 1. DUTY FACTOR. D = :~
.rl- f--O.o1
2. PER UNIT BASE = RthJC = 5.0 DEG. CIW.
E 0.02 """'SINGLE PULSE (TRANSIENT
'-'
:;:!
~ TIHE~MA~ l~p~Dm~\ 3. TJM - TC = PDM ZthJC(t).
N 0.01
10-5 10-4 10-3 1.0 10
tl. SQUARE WAVE PULSE DURATION (SECDNDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to·Case Vs. Pulse Duration

10

~
.h~ .... -
i'" /

~~
V
.......
.....- - TJ =-55 0C

T; = 250~

TJ = 1250C
~
I-

~a:
az
;;:
a:
10 //
I
A

0
w
, - - -TJ = 150 0 cI II
i . . .V '"wa:
~ I
I IITJ=25 0 C

,~ V ,I I a:

I
VDS> ID(on) x RDS(on) max.

80(' PUlE TEi '"

.!? I
I
10 15 20 25
1.0
o 0.5
J 1.0
J
1.5 2.0 2.5 3.0
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.50

1.20 w 2.25
'-'

1.15
'"
«
to 2.00

1.10
. . .v iiia:
w 1.75
......
/ V I-
«
1--
V~
1.05 '10 1.50

. /V
/
/ Zw
o~
w ....
1.00 "'« 1.25

....... ."", ......V

a:",
::>a:
00
0.95 '1'" 1.00

.......V
0 -

0.90
I-
z
;;: 0.75 ....... / VGS= 10V- -
a:
c ....... i-""'" I
IO=4A
I

0.85 c 0.50
0

0.80 '"
of 0.25

0.75 o
-60 . -40 -20 20 40 60 80 100 120 140 -60 -40 -20 20 40 60 80 100 120 140
TJ.JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 ....: Normalized On·Resistance Vs. Temperature
0·66
 IRFF130, IRFF131, IRFF132, IRFF133 Devices
20

2000

I1 ~Gs' 6 u; Vas = 20V

.1 1'1 MHz 1 1 ::;
1600 Ciss = Cgs + Cgd. Cd, SHORTED _ c 15 Vas' 50V
1
~

~~
2:

'"~
Crss = Cgd w I
Cgs Cgd - '"
<i Vas = BOV.IRFFI30. 132
Coss = Cd, + Cg, + Cgd ::;
~ 1200 - 0
>
~
~Cd,+Cgd w
z '-' 10
;: 1
A~
co

-
:0

~
u 0
::
~ 800
"?
0 I
u'
\ c!" I-
w
I- I
"'"<h
\
'--" - .I / 10= lBA
400 >'"
\
CO"

C~" / T Ii
FOR TEST CIRCUIT
FIGtURE
I--

10 20 30 40 50 16 24 32 40
Vos. DRAIN TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
10
0.6

~
:>:
Ros(~n3 MEASJREO WITJ CURREN~ PULSE OIF
2.0 I-" URATION. INITIAL TJ = 25°C. (HEATING
S 0.5 I-- EFFECT OF 2.0 I-" PULSE IS MINIMAL.) -
w ..........
...... r-....
'-'
Z

"
t;
iiico 0.4 r-.... !"-o.......... r-.... ~.131
z
0
V GS = 10V i""-
~

IJ~
co 0.3

J
:0
0
"?
0
I-
:i:
~
0.2
/
"~ ~
c
~~
'"
~
c
0
0.1
vr = 20V
,
1,\
o
10 20 30 40 50 60 25 50 75 100 125 150
10, DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (OC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig_ 13 - Maximum Drain Current Vs. Case Temperature

40

35

30
~
I-

"z
~
25

""
0
;::
"iii"- 20 ~
Ci
co
~ 15 ~
~
.P 10
"-
20 40 60 BO
TC. CASE TEMPERATURE (OC)
100
" 120
.........
140
......

Fig. 14 - Power Vs. Temperature Derating Curve

0-67
IRFF130, IRFF131, IRFF132, IRFF133 Devices

VARY tp TO OBTAIN

VGS'RIL_DU_T_~r-:::r
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL TO OBTAIN
SPECIFIED 10
RL
Vi
PULSE
D.U.T.
r-----'
GENERATOR

I
o--_TO SCOPE
I D.DIn
I IiOCI HIGH FREOIIENCV
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

,......--0 +Vos (ISOLATED

SUPPLY)

o I':']}.5 mA - - J \ I \ I \ _......
IG
-.N'\_--o
10
-VOS

CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-68
 PD-9.312

INTERNATIONAL RECTIFIER IIC)R I

HEXFET® TRANSISTORS IRF120
IRF121
N-Channel IRF122
IRF123
100 Volt, 0.3 Ohm HEXFET Features:
The HEXFETIJ!) technology is the key to International Recti- • Fast Switching
fier's advanced line of power MOSFET transistors. The effi- • Low Drive Current
cient geometry and unique processing of the HEXFET design
achieve very low on-state resistance combined with high • Ease of Paralleling
transconductance and great device ruggedness. • No Second Breakdown
The HEXFET transistors also feature all of the well estab-
• Excellent Temperature Stability
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Product Summary
paralleling, and temperature stability of the electrical param-
eters. Part Number VOS ROS(on) 10

IRF12D 1DOV O.30n S.OA

They are well suited for applications such as switching power
supplies, motor controls, Inverters, choppers, audio amplifi- IRF121 60V O.30n S.DA
ers, and high energy pulse circuits. IRF122 100V OAOn 7.0A
IRF123 60V O.40n 7.0A

22.2210.8151
CASE STYLE AND DIMENSIONS 342 MAX. OIA. 11.43 0.450

""'L
T~ R~r""" PLANE

~.~! I~'~nl
OIL-I1- 101610401 MIN.
TWO PLACES TWO PLACES

almWIOIA.
. . 1
TWO PLACES

DRAIN
ICASEI

SOURCE

1.09 (0.043)
MAX. DIA.
14-_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO·204AA (TOol)

Dimensions in Millimeters and lInches)

0-69
IRF120, IRF121, IRF122, IRF123 Devices

Absolute Maximum Ratings

Parameter IRF120 IRF121 IRF122 IRF123 Units
VOS Drain - Source Voltage (j) 100 60 100 60 V
VOGR Drain - Gate Voltage IRGS - 1 Mil) (j) 100 60 100 60 V
10@TC - 25°C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10 @TC = 100°C Continuous Drain Current 5.0 5.0 4.0 4.0 A
10M Pulsed Drain Current ® 32 32 28 28 A
VGS Gate - Sou~ce Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 40 ISee Fig. 14) W
linear Derating Factor 0.32 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = IOOI'H
A
32 I 32 I 28 I 28
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF120
IRF122
100 - - V VGS = OV

IRF121
IRF123
60 - - V 10 = 250J<A

V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 250J<A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source leakage Reverse ALL - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VOS - Max. Rating, VGS - OV
- - 1000 J<A VOS = Max. RatingxO.8, VGS = OV, TC = 125°C
1010n) On-State Drain Current ® IRF120
8.0 - - A
IRF121
VOS >1010ni x ROSlonl max.' VGS = 10V
IRF122
IRF123
7.0 - - A

ROSlon) Static Drain-Source On-State IRF120

- 0.25 0.30 n
Resistance ® IRF121
IRF122
VGS = 10V,I0 = 4.0A
- 0.30 0.40 n
IRF123
9fs Forward Transconductance ® ALL 1.5 2.9 - Sllll VOS >1010n) x ROSlonl max.' 10 - 4.0A
Cjss Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output CapaCitance ALL - 200 400 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 50 100 pF
tdlonl Turn-On Delay Time ALL - 20 40 ns VOO = 0.5 BVOSS,IO - 4.0A, Zo = 50n
tr Rise Time ALL - 35 70 ns See Fig. 17
tdloffl Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 35 70 ns

Og Total Gate Charge

ALL - 10 15 nC
V GS = 10V, 10 ~ lOA, VOS - 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 6.0 - nC

Ogd Gate-Drain ("Miller"l Charge ALL - 4.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
10.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth. and greased.
RthJA Junction-to-Ambient Free Air Operation

D-70
 IRF120, IRF121, IRF122, IRF123 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF120 Modified MOSFET svmbol
(Body Diode) IRF121 - - B.O A
showing the integral
IRF122 reverse P-N junction rectifier.

~
IRF123
- - 7.0 A

IRF120
ISM Pulse Source Current
(BodyDlode)@ IRF121 - - 32 A

IRF122
IRF123
- - 2B A

Diode Forward Voltage ® IRF120

VSD
IRF121
- - 2.5 V TC = 25·C.IS = B.OA. VGS = OV
IRF122
IRF123 - - 2.3 V TC = 25·C.IS = 7.0A. VGS = OV
t" Reverse Recovery Time ALL - 2BO - ns T J - 150·C.I F = B.OA. dlF/dt - l00A/~s
QRR Reverse Recovered Charge ALL - 1.6 - ~C TJ - 150·C.IF - B.OA. dlF/dt - l00A/~s
ton Forward Turn-on TIme ALL Intrinsic turn-on time is negligible. Turn-on speed Is substantially controlled by LS + LO'
<DTJ = 25·Cto 150·C. ®Pulse Test: Pulse width" 300~s. Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
Sea Transient Thermal Impedance Curve (Fig. 5).

20
20
1/1DJ SOps PULSE TEST
r-8~"'PUL~Em~ //
16 ~ sr- r-- 16
VOS > 10(on) x
r-- ROS(on) max. TJ·I125·I~
IJ
I // I
..~
iii
.'"
~
:> 12 l 8Y- f-- ~
:> 12
Ty25·1~ ./) Y
I-
I
I- TJ'-55·1~
7/
~
'"'-'
"
z
VGS'7V-
I
r-- !
z
II.V
<1
'"
0 6 l - f--
~
0
E
'I'
E OJ
/I
5Y- r-- ~"
4~- f-- ~~
10 20 3D 40 50 10
VDS. DRAIN·TD·SDURCE VOLTAGE IVDLTS) VGS. GATE·TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS

--
10 AREA IS LIMITED
50
8oJ,uLselTEST I-- , BY ROS(on)

-li1/'1./7V
f-IRFI20.1-
SV
YIf
8V..I......... 20 f-.IRFI22.3

J. ;;;
F=(RLJ..,~ '\ IY'I

...
iii
'" ~ 10

~~
100~.

I ~ r=.'RFI22.3
I-
~ DV VGS'6V-
I-
i5 I'
1'.\

, -
'" '" 1m.
'"B
z 4 ~V a'"
z
J. ~
I
~
o :
0
1.0
f=Tc =25·C _.
10m.
E
J--
_5Y E 0.5 f=TJ =150·C MAX.
100 m,
OC I
f- RthJC =3.12 KIW
~
J 01 f-SINGLE PULSE .- IRF121.3 IRIFI~O. 2
It- 4y
0.1
1.0
J 1 JIIIII
ID 20
I II
50 lao
I
200 500
Vas. DRAIN·TD·SOURCE VOLTAGE IVOLTSI VOS. DRAIN·TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0·71
IRF120, IRF121, IRF122, IRF123 Devices

0=0.5

i NOTES:

-6.2

-0.1
•
m.JL
=0.05
-0.02
~- ~2~
;;;0.01 1. DUTY FACTOR, 0 = :~
-r "SINGLE PULSE (TRANSIENT
THERMAL IMPEDANCE) 2. PER UNIT SASE = RthJC = 3.12 DEG. crw.
3. TJM' TC = PDM ZthJC(t)·
I 111111 I I
10.4 10.3 10-2 10.1 1.0 10
tl,SQUAREWAVE PULSE OURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

./
,., -
--
.......
r-
l L-=
TJ .55 0
=
TJ=250~- -=
~
'"
~

...'"
102

TJ = 25 0 C
~

-
5
/ . /,/' TJ ~ mot iii )III"""
:;;;.-
,..- ..", TJ;-,500C
i/ ,.,. I-- '"'":::I
U ~
'-

i#'

,
II
Z
/~ ~ 10
c
1)1' w
'"
~
vos> 'O(on) x ROS(on) max. a: '-TJ = 1500 C
1
'"
8°TPUlSjTEST
E '"' 'II
I ~
TJ = 25 0 C
1.0 I
12 16 10 o
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

1.25 2.2

w
'"~ w
~ 1.8
./
1.15
o V'
>
z .".
", ~
0; ./
~ .,- ~
o
~a 1.05 ~ z
os 1.4 /
Ww
"" ...
"':i ..... ~
Ww
UN
g~
/
w'"
~~ ,/' ~~ ~
~~ 0.95
..", ~g 1.0 ./
V
..,.o
z
<
'"'"
~ 0.S5
"" <
'"
c

~c 0.6
".,
./
~
VGS'= 10V
10=3A - -
i:;
'"
II
0.15 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPEIlATURE (DC) TJ,JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On· Resistance V,. Temperature
0·72
 IRF120, IRF121, IRF122, IRF123 Devices
1000
20
.I.VGS = J
0
I fl= I MHI' I I
800 Ci.. = Cgs+Cgd.CdsSHORTEO-
5 VDS ~ 20V I'--.
Crss • Cgd '" 15

~~
Cgs Cgd
- 2:-
w
VDS = 50V V
~
0-
600 l\ Coss = Cd. + egs + Cgd
-
'"'"~ I-- Vas = 80V.IRFI20. 122
I

,,t~
-
~ "'Cds + Cgd
'"
z \' 1'... I >
'"
t-
r.- eiss ~ 10
~
o;

u
~ 400
\ :::.
'"
"I
'"
::;;
r"\.
/
<.i
~
\ .........r- Coss '"U, 5
200 IO=10A
>'" j
\ J FOR TEST CIRCUIT
I--

10 20
C"S

30 40 50
V yeFTRElt

12 16 20
VOS' ORAIN-TO-SOURCE VOLTAGE (VOLTS) ag. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to·Source Voltage
0.8 10
.,
::;;
"w
8
u
z 0.6 VGS = 10V .............
'"'"
t- i'-..
...........
iii
'"
z
r--.... 'r-o.,...... i'r---..
-..Io... . . . 'RFI20.121
'"
w
u
0.4
~~
IRF122.123 "':".
'"
,)
:::.
'"
"I ~ .......

-
..,.
'" 1/
- --~OV
'"'"
z
;;: ~
'"
c

.§
0.2
~~
'"
:g _RDS(on) MEASURED WITH CURRENJ PULSE 10F . _
2.0 ps DURATION. INITIAL TJ = 250C. (HEATING
- ~
EFFECT OF 2.0 ps PULSE IS MINIMAL.)

10 20 30 40
o
25 50 75 100 125
"'
150
'0. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (OC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35 '\
~
t-

~
z
'">=~
~
i5
'"
~
30

25

20

15
" \.
\
~

'\
'""-ci
"-
10
~

20 40 60 80 100
Tc. CASE TEMPERATURE (OC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-73
"'"
120 140
IRF120, IRF121, IRF122, IRF123 Devices

VARY Ip TO OBTAIN
REQUIREO PEAK IL

vGs=n IL _--<>---4........w..--'
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r------,
I
50n I o - - _ T O SCOPE
I 10 I O.o1n
I I 50n " HIGH FREQUENCY
L_ ----' SHUNT

Fig. 17 - Switching Time Test Circuit

.----0 +VOS
(lSOLATEO
SUPPLYI

12V
BATTERY

o~·5mA - --"'v'v-_-'V'v,,.---Q -VOS

IG 10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

D-74
 PD-9.303

INTERNATIONAL RECTIFIER II~)R I

HEXFET® TRANSISTORS IRF13D
IRF131
N-Channel IRF132
IRF133

100 Volt, 0.18 Ohm HEXFET Features:

The HEXFET® technology is the key to International Rectifier's • Fast Switching
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve • Ease of Paralleling
very low on-state resistance combined with high transconductance
and great device ruggedness. • No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well established
advantages of MOSFETs such as voltage control, freedom from Product Summary
second breakdown, very fast switching, ease of paralleling, and
temperature stability of the electrical parameters. Part Number VOS ROS(on) 10
IRF130 100V O.18!1 14A
They are well suited for applications such as switching power
supplies, motor controls, inverters, choppers, audio amplifiers, IRF131 60V O.18!1 14A
and high energy pulse circuits. IRF132 100V O.25!1 12A
IRF133 60V O.25!1 12A

222210.875)
CASE STYLE AND DIMENSIONS 342 MAXOIA 1143(0450)

"''j' j:=={'r:,,,"
T~ PLANE

J~ll~·~ilOIA--I1- 10.16(0.40) MIN

TWO PLACES TWO PLACES

408(0.161) OIA
3.84(0.1511 .
TWO PLACES

DRAIN
ICASE)

1
'1.09 (0.043)
MAX. DIA.
~_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO·204AA (TO·3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-75
IRF130, IRF131, IRF132, IRF133 Devices

Absolute Maximum Ratings

Parameter IRF130 IRF131 IRF132 IRF133 Units
VOS Drain - Source Voltage <V , 100 60 100 60 V
VOGR Drain - Gate Voltage (RGS = 1 MO) CD 100 60 100 60 V
10@TC= 25·C Continuous Drain Current 14 14 12 12 A
10@TC =' l00·C Continuous Drain Current 9.0 9.0 8.0 8.0 A
10M Pulsed Drain Current @ 56 56 48 48 A
VGS Gate - Source Voltege t20 V
PO@TC ~ 25·C Max. Power Dis8lp~ion 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 1 5 and 16) L = lOOI'H
A
"
56 I 56 I 48 I 48
TJ Operating Junction and
-55to 150 ·C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 In. (1.6mm) from case for lOs) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain· Source Breakdown Voltage IRF130
IRF132
100 - - V VGS = OV

IRF131
IRF133
60 - - V 10 = 250l'A

VGS thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 - 250!<A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source leakage Reverse ALL - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VOS - Max. Rating, VGS = OV
- - 1000 I'A VOS = Max. RatingxO.8, VGS = OV, TC = 125·C
On-State Drain Current ~
10(on) IRF130
IRF131
14 - - A
V OS ) 10(on) x ROS(on) max.' V GS = 10V
IRF132
IRF133
12 - - A

ROSton) Static Dr,ain-Source On-State IRF130

Resistance ® IRF131
- 0.14 0.18 0
VGS = 10V, 10 = 8.0A
IRF132
IRF133 - 0.20 0.25 0

9fs Forward Transconductance__<ID_ ALL 4.0 5.5 - S(U) vOS> O(on) x "OS(on) max.' 10 - 8.0A
Clss Input Capacitance ALi. - 500 800 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 300 500 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 100 150 pF
tdlonl Turn-On Delay Time ALL - - 30 ns VOO = 36V,I 0 = 8.0A, Zo = 15!l
tr Rise Time ALL - - 75 ns See Fig. 17

td{offl Turn-Off Delay Time ALL - - 40 ns (MOSFET switching times are essentially
tt Fail Time ALL - - 45 ns independent of operating temperature. I

Og Total Gate Charge V GS - 10V, 10 = 18A, VOS = 0.8 Max. Rating.

(Gate~Source Plus G8te~Drain)
ALL - 18 30 nC
See Fig. 18 for test circuit. IGate charge is essentially
independent of operating temperature.)
Ogs Gate-Source Charge ALL - 9.0 - nC

°gd Gate-Drain ("Miller") Charge ALL - 9.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die .

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in. I from header
and source bonding
pad.
.@)
Thermal Resistance
Junction-to-Case
Case-to-Sink Mounting surface flat, smooth, and greased.
Junction-to-Ambient Free Air Operation

0-76
 IRF130, IRF131, IRF132, IRF133 Devices

Source-Drain Diode Ratings

-
and Characteristics
IS Continuous Source Current IRF130 Modified MOSFET symbol
IBody Diode) IRF131
- - 14 A
showing the integral
IRF132 reverse P-N junction rectifier.
- - 12 A

~
IRF133
ISM Pulse Source Current IRF130
IBody Diode) ® IRF131
- - 56 A

IRF132
- - 48 A
IRF133
VSD Diode Forward Voltage ® IRF130
- - 2.5 V TC = 25°C,IS = 14A, VGS = OV
IRF131
IRF132
IRF133 - - 2.3 V TC = 25°C,IS = 12A, VGS = OV
trr Reverse Recovery Time ALL - 360 - ns T J - 150·C, IF - 14A, dlF/dt - 1OOAI ~s
ORR Reverse Recovered Charge ALL - 2.1 - ~C T J = 150°C, IF - 14A, dlF/dt - 100A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by lS + LO'

<DTJ = 25°C to 150°C. ® Pulse Test: Pulse width .; 300~s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20

16
lOV~V

if
sl" PU iSE TEITI _ -
7V=
=
20

16
-lO",P)lSETElT
VOS >'IOlon)' x RO~lon) ~.x. ,
J
/1

i,.
:; 12 1 .-
VGS=6V= ~
>-

~
fl
/' =>
u
z
~
~ f/I
I" y- I-- '"
E TJ = +125 0 C II ~
~ VJI
TJ = 25 0 C
- TJ=t"C
4~- I--
~~
10 20 30 40 50 10
VOS, ORAIN·TO·SOURCE VOLTAGE IVOLTS) VGS, GATE·TO·SOURCE VOLTAGE IVOLTSI

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
f=IRF130, 1.= AREA IS LIMITED BY ROSlon)
50
r-IRFI32,3

20 ~IIRLJ,l 1'.
~
w
~
~w 10 -'IRFI32,3
w
~ ~
~
:'> l-
i-
~ ~
~
~
=> =>
u u
z 4 z
~ ~
'"
.9
'"E
1.0~~sm.
=
0.5 =TJ
=TC - 25 0 C
1500 C MAX.
- RthJC =1.67 K/W +-++-+-t-+t+I-tt---+-+-+-+++t+H
0.2 -ISI~GLF PIU~SIEII -H RF )31), ~
0.1 II IIII II
1.0 10 20 50
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, ORAIN·TO·SOU RCE VOLTAGE IVOLTS)

Fig. 3 - Typical Saturation Characteristics Fig, 4 - Maximum Safe Operating Area

0-77
IRF130, IRF131, IRF132, IRF133 Devices

...ffi
II I
iii<
"'-
...... 1.0 II I
wz
>:> 0=0.5
t; ffi 0.5 NOTES:
~!:
... w
wu
~~ 0.2
~~
1-6.2

f-- 0.1 ~ iii--

.. ~
JJLJL
~!! 0.1 f--0.05
a:...J
0< 0.02- ~2~ ::
z.~ 0.05
Uw
}~
~o.oj':::
-...., ~= SINGLE PULSE (TRANSIENT
mrAf I~PEOtNfEL LJ
1. DUTY FACTOR. D' :~
2. PER UNIT BASE' RthJC • 1.67 DEG. CIW.
:2 0.02

N~
3. TJM - TC' PDM ZthJC(t).
0.01 III I II I
10-5 10-4 10-3 2 10-2 2 5 10-1 1.0 10
tl, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

10

102
iii TJ - 25 0 C
'"

--
ll:!
TJ =-55 0 C
~ ~
...fri
V ~
~~ - 25 b
0
a:
a:
:>
U .AI
./ "" r'-TJ = 150aC

&" TJ = 1250 C Z

~ 10
//
II -" vI"'"
Q
W
V>
'"
W TJ=1500 C,

'/" vos> 10(on) x ROS(an) max.

>
w
a: -,
I 80(' PUljE TES, '"
S?
,I TJ = 25 0 C
1.0 I I J
10 15 20 25 o 1
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig, 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.2

w
~
~ 1.15
>
./
".. '/
! .",
V
'"Ww
~s 1.05 ~ ./
~I"'"
"'N
"':; ".. V
~i ",.,. V
~~ 0.95
./ /
...,o
z
;;:
V' ... V
'"o ,/ VGS= lDV_
::l 0.85
I .... r--
>
Q 1=6A I
'"
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ.JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-78
 IRF130, IRF131, IRF132, IRF133 Devices
2000

I ~Gs· d
20

1600
I \.1 M~' .l J
Ciss • Cgo + Cgd. Cd. SHORTEO _ 0; VOS·20V

"'" ~
C'" • Cgd
!::; I
0 15 VOS·50V
CO,,·CdS+~ - ~
1 ~
"'~"
w
go gd Vos· 80V.IRFI30. 132
u.
'"
«
~ 1200 "'Cd. + Cgd - !::;
~
J
0
'"z >
~ w
'"a: 10
~ ~ ~~
'"
",'
800
\ -- ct
=>
0
"?
0
~
I-
« I
,
\ "-
400
- cl..
'"
"'
>'"
I 10·18A

-
~
\ .1
FOR TEST CIRCUIT
~

10 20 30
C'SS

40 50
V 16
sr FIGrRE Ii

24 32 40
VOS. ORAIN-TO·SOURCE VOLTAGE (VOLTS) ag. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to·Source Voltage
20
0.6
;;;
!2!
:z:
ROs(L MEASUIREO WITH 1
J CURREN~
PULSE O~
2.0 IJS URATION. INITIAL TJ • 25 0 C. (HEATING
e 0.5 - EFFECT OF 2.0 IJS PULSE IS MINIMAL.) - 16
w
'"z
~
iii'"a:
.......
0.4 r-....... .....
z = lOV .......
r-....... ........ ........... ~F130.131
VGS
0
w
'"a:=> 0.3
. . . . . r---., r-.... r-...
J
0
"? IRF132.133
.,.
0

z ~~
0.2
;;:
a:
0 ./ l.--- V ~
g
;;; 0.1
0
VGS 20V
~.,
1
a:

o
10 20 30 40 50 60 25 50 75 100 125 150
10 , DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

80

70
- l'\. ,
60
f\.
0;
l-
I- '\I\..
~ 50
z
0
;:
~ 40
'\
ill
i5
a:
~ 30
'\
'""
0
""ci
"" 20

10

'i\
20 40 60 80 100 120 140
Tc. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-79
IRF130, IRF131, IRF132, IRF133 Devices

VARY tp TO OBTAIN
REoUIREo PEAK 'L

VGs=R ~oU_T--....r-,.
'L+--~>-----<~"",,---1

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

Voo '" 36V

Vo
---~TO SCOPE

Fig. 17 - Switching Time Test Circuit

,....---0() +Vos
(ISOLATED
SUPPLY)

12V
BATTERY

o-.r=rr1.5 mA - 16 10
CURRENT ..,. CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0·80
 PD-9.369

INTERNATIONAL RECTIFIERII(~RI

HEXFET® TRANSISTORS IRF14D

N-CHANNEL
IRF141
POWER MOSFETs IRF142
IRF143
100 Volt, 0.085 Ohm HEXFET Features:
The HEXFET«' technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing
of the HEXFET design achieve very low on-state
• Ease of Paralleling
resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as volt- Product Summary
age control, freedom from second breakdown, very
Part Number VDS RDS(on) ID
fast switching, ease of paralleling, and temperature
stability of the electrical parameters. IRF140 100V 0.08Sn 27A

They are well suited for applications such as switch- IRF141 60V 0.08Sn 27A
ing power supplies, motor controls, inverters, chop- IRF142 100V O.lm 24A
pers, audio amplifiers, and high energy pulse circuits. IRF143 60V O.lm 24A

22,2210,8751
CASE STYLE AND DIMENSIONS 3,42 MAX, DIA, 11,;~ !~,4!~1

"'~~HJ.m"
TTt PLANE

1,60 0,063 DIA, II 12,1910,4801

1450,7 II ~
TWO PLACES TWO PLACES
26,61
1.050) MAX.

HJm:1WDIA,
TWO PLACES

(,'" (O·~:I
DRAIN
ICASEI

MAX.OIA.
39.96 (1.573)
MAX.
t MEASURED AT SEATING PLANE

Conforms to JEDEC Outline T0-204AA (T0-3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-81
IRF140, IRF141, IRF142, IRF143 Devices

Absolute Maximum Ratings

Parameter IRF140 IRF141 IRF142 IRF143 Units
VOS Orain - Source Voltage <D 100 60 100 60 V
VOGR Orain - Gate Voltage (RGS = 1 Mill <D 100 60 100 60 V
IO@TC=25·C Continuous Drain Current 27 27 24 24 A
IO@TC=100 D C Continuous Drain Current 17 17 15 15 A
10M Pulsed Drain Current @ 108 108 96 96 A
VGS Gate - Source Voltage ±20 V
PO@TC=25·C Max. Power Dissipation 125 (See Fig. 141 W
linear Derating Factor 1.0 (See Fig. 141 WIK
ILM > Inductive Current, Clamped (See Fig. 15 and 161 L = 1OOl'H
A
108 I 108 I 96 I 96
TJ Operating Junction and
-55to 150 ·C
Tstg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mml from case for 10s1 ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions

BVOSS Drain - Source Breakdown Voltage IRF140

IRF142
100 - - V VGS = OV
IRF141
IRF143
60 - - V 10 = 25Ol'A
V GS(thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VOS = Max. Rating, VGS = OV
- - 1000 I'A VOS = Max. Rating x 0.8, VGS = OV, TC = 125 D C
10(onl On-State Drain Current ® IRF140
27 - - A
IRF141
V OS } 10(onl x ROS(onl max.' VGS = 10V
IRF142
IRF143
24 - - A

ROS(on) Static Drain-Source On-State IRf140

- 0.07 0.085 II
Resistance ® IRF141
IRF142
VGS = 10V, 10 = 15A
IRF143
- 0.09 0.11 !l

9fs Forward Transconductance ® ALL 6.0 10 - S(1J) VOS } ID(onl x HOS(onl max.' 10 - 15A
Ciss Input Capacitance ALL - 1275 1600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 550 800 pF
See Fig. 10
erss Reverse Transfer Capacitance ALL - 160 300 pF
td(onl Turn-On Delay Time ALL - 16 30 ns VOO '" 30V, 10 = 15A, Zo = 4.711
tr Rise Time ALL - 27 60 ns See Fig. 17
td(off) Turn-Off Delay Time ALL - 38 80 ns (MOSFET switching times are essentially
Fall Time - independent of operating temperature.)
tf ALL 14 30 ns

Og Total Gate Charge

ALL - 38 60 nC
V GS = 10V, ID = 34A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
OgS Gate-Source Charge ALL - 17 - nC

°gd Gate-Drain ("Miller") Charge ALL - 21 - nC

LD Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.1 from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-82
 IRF140, IRF141, IRF142, IRF143 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF140 Modified MOSFET symbol
(Body Diode) IRF141 - - 27 A
showing the integral
reverse P~N junction rectifier.
IRF142

~
- - 24 A
IRF143
ISM Pulse Source Current IRF140
(Body Diode) ® IRF141 - - 108 A

IRF142
- - 96 A
IRF143
VSD Diode Forward Voltage ® IRF140
- - 2.5 V TC = 25°C, IS = 27A, VGS = OV
IRF141
IRF142
IRF143
- - 2.3 V TC = 25°C, IS = 24A, VGS = OV
t" Reverse Recovery Time ALL - 500 - ns T J - 150°C, IF = 27 A, dlF/dt - 100A/I's
QRR Reverse Recovered Charge ALL - 2.9 - I'C T J = 150°C, IF - 27 A, dlF/dt = 100A/I's
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by lS + LO'

<DTJ = 25°Cto 150°C. ®Pulse Test: Pulse width'; 3001'5, Duty Cycle'; 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 51.

50 50

V 801" PULSETEST
801"!PULSE!TEST /"
4()
10V 9V
BV
40
VOS> 10(on) x Tr-551° C' - r/ /
iii
0:
ROS(on) max.
TJ =26 0C""
Z' /
~
:IE
5 3D
TJ = 1250C""
lU V
.... 7y
z
W
0:
lf7
Il
0:
a
z 20
;;:
0:
Q
VGS = at 1(/
E
10 10 I
5t
10 20 3D
4~
40
VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTS)
50
~
VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)
10

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

1000
50
~ /' 500 OPERATION IN THIS
AREA IS LIMITED

"
/V

40 - 80 LPU JETESJ
~ 9V .,......
200
BY ROS(on)

~... 'l " IRF140,1

:IE
5 3D ~ ',/"
"BV
i"
5
100
f-IRF142,3
I- I-

50
~ .... ...-
.... I'" _7V .... 10 I'S
ffi
~
~
0:
IRF140,1
~
1
10 1'S

~
~
0:
:::>
a 20 f-IRFI42.3
"- I~S
'-'
z 20 z
;;:
0:
Q
VGS= 6V ~
Q
10 "' I

~~
E E f='TC - 25°C

10
f= TJ 150°C MAX. 10 ms
f- RthJC = 1.0 K!W
5V
r-ISI~G~E~Um I lOr i'
~
I.R~141r 3
4V
1.0 II II I RF140. 2 DC
I.D 10 20 50 100 200 500
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VDS. ORAINTD·SOU RCE VO LTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

D-83
IRF140, IRF141, IRF142, IRF143 Devices
....
~
iii<
"'-
........
wz 1.0

-
>=>
0=0.5
;:: '" 0
~~ .5 NOTES:
w",

fa ~
!:::!~
0.2
-0.1
0.2

;;iii!II ""'"
:;;",.
""'"
mJL
~2~
~o,.

~:;!! 0.1 =0.05

'"
~
0<
z.~ 0.05
-0.02 """
SINGLE PULSE (TRANSIENT _ tl
"'w
:;1:r:
_0.01 1. OUTY FACTOR. 0 -12 .
,ro .... iHlliiiIMPjOiNCE! 1 2. PER UNIT BASE = RthJC = 1.0 OEG. CfW.
E 0.02
'"
S 3. TJM - TC = POM ZthJcltl.
N 0.01 I II III I
1oJ.; 10-3 10-2 10-1 1.0 10
tl. SQUARE WAVE PULSE OURATION ISECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

15
TJ = -55~C
~
50
~

",'" tJ ",

~
i!!l
§
w
'"
2:

~
12

IV
/
'I
'"
;'

..".
- Tl=1251c
ill
'l
.A ~

=>
o
z
~ 6
VV I
I I

z
< rj I
....'" ~IJ..PU~ETE~T
r-- TJ = 150°C 1/
£ vos> 'Olon) x ROSlon) max.
TJ = 25°C
I I

1.0
I II
10 20 30 40 50 0.4 0.8 1.2 1.& 2.0
10. ORAIN CURRENT IAMPERES) ° VSO. SOURCE·TO·ORAIN VOLTAGE IVOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5
w
'"z
~ 2.0
",
iii ~
..........
'"w
!;(
,,-
./ \;;61.5 ./
zw
", " ON
w::l
u< ".
."
""V
"'2
=>",
00 ~
."
:g~ 1.0
..,.
." z l,....o-' ~
:c ,- vGS = 10V
'"
o
I
10= l&A
I

1" 0.5
~
'"
0.75
-40 40 80
TJ. JUNCTION TEMPERATURE 10C)
120 1&0 °-40 40 80
TJ. JU NCTI ON TEMPE RATU RE 10C)
120 160

Fig.8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-84
 IRF140, IRF141, IRF142, IRF143 Devices
2000

VG~ = OV Ci... CIII + Cgd. Cd. SHORTED

-CIII·Cad -
20
'·1 MHz
CIIICgd
l. COD • Cd. + c;+c;d
1600 -
~~ "'Cd.- Cgd ~
'" 15

~ 1200 \, i"oooo.. Ci.. ~

w
'"
~
VOS=30~~
I

I
I
Vos = 50V
I ........
. . .A ~
~
u
z VOS=80V.IRFI40.14~~
~ '">
~ 10
~
u 800
\. :::>
'"
"1 1£
~
U ["'.. ..... '"~
\ -..,.--r-
COD

""-
!;(
to
.;,
I 10 = 34A
FOR TEST CIRCUIT-
400 to

/ SjE FIGUtE 18 I

'"
>
"- cL
10 15 20 25 30 35 40 45 50
I 20 40 60 80
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

30
0.3
;;;
:Ii
RDS(On)' MEASURE~ WITH CU'RRENT pulSE OF
2.0 jI' DURATION. INITIAL TJ = 25 0C. (HEATING .........
:r::
ew - EFFECT OF 2.0 jII PULSE IS MINIMALl 24
.........
u ........ ..........
z ......... ........
~
fa
'"z
'"
w
u
0.2

VGS '10V
~
'"
~
~
I-
iii
18
.......
'r:::IRFI42~~~
. . ~RFI40.,4,
'":::> :::::>
'""1
J
u
z 12
'"zt-;-
;;: o.1
;;:
'"'" "~"I
'"'"
.e
-2 .. ~
V
-~::
~
~
'"
~ \,
60 80 100 120
o
20 40 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE 10C)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig_ 13 - Maximum Drain Current Vs. Case Temperature

-"
140

~
120 -
'", ,
~100
~
z
'" 80
S
iii
:;: 60

I
~40
" " '", ~

20

20 40 60 80 100
Te. CASE TEMPERATURE (DC)
'" 120 140
~

Fig. 14 - Power Vs. Temperature Derating Curve

0-85
IRF140, IRF141, IRF142, IRF143 Devices

VARY., TO OBTAIN
REQUIRED PEAK Il

VGS'~ OUT

I l _ - - o - - -....._II/\,---J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

JOV
ADJUST Rl TO OBTAIN J.on
SPECIFIED 10
VOS

Ir;U~ - - O-li---_<>-_....lI....J~ O.U.T.

GENERATOR

I ;J~RCE
IMPEDANCE
.fl I
L ___ J

Fig. 17 - Switching Time Test Circuit

..----0 +VOS
(ISOLATED
SUPPl YI

12V
BATTERY

or=J}.5 mA - IG
__ ~'A"~-n

10
-VOS

CURRENT ~ CURRENT
SHUNT SHUNT
Fig. 18 - Gate Charge Test Circuit

0-86
 PO-9.30S

INTERNATIONAL RECTIFIER IIC)R I

HEXFET® TRANSISTORS IRF150
IRF151
N-Channal IRF152
IRF153
100 Volt, 0.055 Ohm HEXFET Features:
The HEXFETe technology is the key to International Rectifier's • Fast Switching
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve
very low on-state resistance combined with high transconductance
• Ease of Paralleling
and great device ruggedness. • No Second Breakdown
The HEXFET transistors also feature all of the well established
• Excellent Temperature Stability
advantages of MOSFETs such as voltage control, freedom from Product Summary
second breakdown, very fast switching, ease of paralleling, and
Part
temperature stability of the electrical parameters. 10
Number VOS ROS(on)
They are well suited for applications such as switching power IRF150 100V 0.05511 40A
supplies. motor controls. inverters, choppers, audio amplifiers. IRF151 60V 0.05511 40A
and high energy pulse circuits. IRF152 100V 0.0811 33A
IRF153 60V 0.0811 33A

22.22(0.875)
CASE STYLE AND DIMENSIONS
(0"3Ix~MAX'OIA~'
~
SEATING
22.22 (0.875) T PLANE
MAX.DIA.
1.60 0.063) OIA . I 12.19 0.480
1.45 (0.057 . ..., 11.18 .44
TWO PLACES TWO PLACES
26.67
1.050) MAX.

;~
. m'1 61 !
. 51 OIA .
TWO PLACES

DRAIN
(CASE)

SOURCE

1+-_ _ _ 39.95 (1.573) _ _-+1

MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEOEC Outline TO·204AE (Modified T0-31

Dimensions in Millimeters and (Inches)

0-87
IRF150, IRF151, IRF152, IRF153 Devices

Absolute Maximum Ratings

Parameter IRF150 IRF151 IRF152 IRF153 Units
VOS Drain - Source Voltage <D 100 60 100 60 V
VOGR Drain - Gate Voltage IRGS - 1 MOl <D 100 60 100 60 V
10@TC = 25 DC Continuous Drain Current 40 40 33 33 A
10@TC= 100°C Continuous Drain Current 25 25 20 20 A
10M Pulsed Drain Current @ 160 160 132 132 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25°C Max. Power Dissipation 150 ISee Fig. 14} W
Linear Derating Factor 1.2 ISee Fig. 14} W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16} L = lOOI'H
A
160 I 160 I 132 I 132
TJ Operating Junction and DC
-55to150
Tstg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm} from case for lOs} DC

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF150
IRF152
100 - - V VGS = OV

IRF151
IRF153
60 - - V 10 = 25Ol'A

V GSlth} Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - - 250 I'A VOS = Max. Rating, VGS = OV
ALL
- - 1000 I'A VOS = Max. RatingxO.B,VGS = OV,TC = 125°C
1010n} On-State Drain Current ® IRF150
40 - - A
IRF151
VOS ) 1010n} x ROSlon} max.' V GS = 10V
IRF152
33 - - A
IRF153
ROS(on) Static Drain-Source On-State IRF150
- 0.045 0.055 0
Resistance ® IRF151
VGS = 10V, 10 = 20A
IRF152
IRF153 - 0.06 O.OB 0

gfs Forward Transconductance ® ALL 9.0 11 - SIIlI VOS ) 1010n} x ROSlon} max.' 10 - 20A
Ciss Input Capacitance ALL - 2000 3000 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 1000 1500 pF
See Fig. 10
e rss Reverse Transfei Capacitance ALL - 350 500 pF
tdlon} Turn-On Delay Time ALL - - 35 ns VOO = 24V, 10 = 20A, Zo = 4.70
tr Rise Time ALL - - 100 ns See Figure 17.
tdloff} Turn-Off Delay Time ALL - - 125 ns (MOSFET switching times are essentially
Fall Time - - independent of operating temperature.)
tf ALL 100 ns
Qg Total Gate Charge V GS = 10V, 10 = 50A, VOS = O.B Max. Rating.
ALL - 63 120 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qg. Gate-Source Charge ALL - 27 - nC

Qgd Gate-Drain I"Miller"} Charge ALL - 36 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die .

LS ~nternal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
10.25 in.} from header
and source bonding
pad. .$
Thermal Resistance
Junction-to-Case
Case-to-Sink Mounting surface flat, smooth, and greased,
Junction-to-Amblent Free Air Operation

0-88
 IRF150, IRF151, IRF152, IRF153 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF150 Modified MOSFET symbol
- - 40 A
(Body Diode) IRF151 showing the integral
IRF152 reverse P-N junction rectifier.
- -

~
33 A
IRF153
ISM Pulse Source Current IRF150
- - 160 A
(Body Diode) @ IRF151
IRF152
- - 132 A
IRF153
VSD Diode Forward Voltage ® IRF150
- - 2.5 V TC ~ 25°C, IS ~ 40A, VGS ~ OV
IRF151
IRF152
- - 2.3 V TC ~ 25°C, IS ~ 33A, VGS ~ OV
IRF153
Reverse Recovery Time ALL - 600 - ns T J - 150°C, IF - 40A, dlF/dt - 100A/"s
t"
QRR Reverse Recovered Charge ALL - 3.3 - "C T J - 150°C, IF - 40A, dlF/dt - 100Al"s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO-

cDTJ ~ 25°C to 150°C. (g)Pulse Test: Pulse width ~ 300,,5, Duty Cycle ~ 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

30
50
10V~9V 80 /.AS PU lSE T~ST 18
~ 80JsPUlSE+EST W
40

If
tJ 13
25
I I
f- Vos > 10(.n)x ROS(.n) max.
I
/I
i'" ~ 20
II
~
... 30
...'"
~

rrr
~
JV
~ 15

a'" a'" TJ=+125.C~

11If
z
~
20 z
;;:
'"c 10 ITJ=25 Cb .II
c 6l
E "J 'II
E
10 ",
5~
t= -5sic
h J
/'l'
4~ ~~ : /
10 20 30 40 50 4 6
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig, 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

20
VGS= I /
l~Vf aJ JlS PU llE TES~ _
1000.~
500 OPERATION IN THIS
AREA IS LIMITED
BY ROS(.n)
16 lis"? / 200 -IRF150,1
lZ
i'"
~ 12
!//J1(

AI'll V - ffi
~
;:
100

50
'iRti5t3
~IRF150, 1
10JLS
100 ps
...
~
IJIJ )v ~
'"
B
f=;.IRF152,3 lms

az l// 20

~ lV
:c~ 101~~~~I~I~i~lillllttJtltli
10 ms
c
6 1= TC = 25·C
E
r//V Y r=
~ TJ 150.C MAX.
RthJC - 0.83 K/W
100 ms

~ V
~~I~GL~P~~~EII'+-++-+++~~++-+++~
I/--- y 1.0 I IIIIIII
1--H--++l-l+I-I+-+-I---+--+-H+-m-0C-I--+-++++l~
IRF151,3 IRF150,2
0.4 0.8 1.2 1.6 2.0 1.0 10 20 50 100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-89
IRF150, IRF151, IRF152, IRF153 Devices

....
z
w
~
:L
I- I- 1.0
wz
>:::>
t= a::
~e .
05
0=0.5

- -.
NOTES:
~~.2
JfUL
wu
ffi ~ 0.2
!:::!5J
~o..
f---O.l

~2~
~~ 0.1 1==0.05
a: ~
0< 1-- 0.02
z.~ 0.05
Uw
}~
f---O.Ol

I
..... SINGLE PULSE (TRANSIENT
1. DUTY FACTOR. D = ~

::.
-;:,
0.02 T~EJ~AhlrrE01NCIE) I 2. PER UNIT BASE = RthJC = 0.B3 OEG. CIW.
3. TJM - TC = POM ZthJC(t)·
]. 0.01 I 111111
10-5 10-4 10-3 2 10-2 10-1 1.0 10
tl. SIlUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

20
I ~
_ 10 2 f - - I- TJ = i5 0 C ~
~ TJ = 150°C
TJ }55 0C f-:::;
ffi
~
I-- !iii I
...... - :!
L~ V
TJ - 25 0 C
.... I
~+1250C- ~
a: 'IL
/ ~V
~ a:
13 t-TJ=15~
1/
/!0-V z
:
o
10

~
w
U>
ffi 5 .L

!J V ~ TJ = 25°C

,III
a:
vos> 10(on) x ROSlon) max. -
'"
'O"SPU~SETEf+
E
2

I
1.0
10 20 30 40 50
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

2.2
1.25

w
~ 1.8
~
~ ~

5 ~~
~
--- a:
z
~s 1.4
U W
~~
L
V
.... ~ a:~
:::>~
0«
"?'"'
,.
./
"". oa:
.... 0
~~ 1.0 L V
V
-
5
~ .".......
o V
C
Q

vGS = 10V
5 ~ 0.6 r---
a: 10=14A -
"I I

07 5 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATU RE (OCI Tj,JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-90
 IRF150, IRF151, IRF152, IRF153 Devices
4000

VG~
20
=0
I
f=) MHz
3200 '---
~ vO~=20L,
\ C'ss = Cgs + Cgd, Cd, SHORTED -
Crss = Cgd -r--- ~ 15

,\ ~~
Vos = 50y-........
... Cgs Cgd
CO" = Cd. + Cgs + Cgd
w
'"~ I
_VOS=80V,IRFI50,152
I
;: 2400 -,--
.,z
~ l\\ "'Cd,+ Cgd
o
>
w I~ 'f'
~ 10
!':~_ 1600 \ ~ Cia =>
o
1
/ U

.,' \, "~ '~"

o
v
~
\.. ......... i'oo.. CO"
.1
'"V, 5
800

:r- '" /
" -
> 10 = 50A
~
""- FOR TEST CIRCUIT --
~
,--Crss
SjE FlyRE Ii

10 20 30 40 50 28 56 84 112 140
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) Qg' TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

0.20 40
in
:;; ROS(O~' MEAS~REO WiTH CUR'RENT P0LSE OF ' ...........
........
:>: 2.01" DURATION. INITIAL TJ = 25 0 C. (HEATING
~ EFFECT OF 2.0 1" PULSE IS MINIMAL)
,~
..
.,w
Z
I
32 to-..
....
to
~
0.14
I
VGS=IOV
in

~
...........
,~i'-.
~FI50,151

",,"I\.
z :;;
0
~ 24 IRFI52,15r;-...
.,w
0
a:
=>
0.10
>-
~a: i'-
........
'"z>:-
0
.,=>
z 16

'"r\.\
,
~ <
0
) a:
0

'~
c
0 0.06 E
'"
0
a:
V
.-- ~~
----
0.02 o
o 40 80 120 160 25 50 75 100 125 150
'0, DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

140 '\.
'\
120
I\.
.
~
>-
~ 100
z
0
;::
"r\.'\
:: 80
i3i
i5
a: 60
'\
'"
~
~
~ 40

20
~
"\
20 40 60 80 100 120 140
Tc, CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-91
IRF150, IRF151, IRF152, IRF153 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGS-R

IL_---<~--<........vv..---J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL TO OBTAIN RL
SPECIFIED 10

VDS

r;ULSE - - 0_l.--__--O_ _-'l...~ O.U.T.

I GENERATOR
I ~~~RCE
IMPEDANCE
Sl
I
L ___ J

Fig. 17 - Switching Time Test Circuit

r---O +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

o~1.5mA - IG
OUT

10
CURRENT "':" CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-92
 PD-9.316

INTERNATIONAL RECTIFIERIIC)Ri

HEXFET® TRANSISTORS IRF22D

IRF221
N·Channel IRF222
IRF223

200 Volt, 0.8 Ohm HEXFET Features:

The HEXFETe technology is the key to International Recti- • Fast Switching
fier's advanced line of power MOSFET transistors. The effi-
cient geometry and unique processing of the HEXFET design • Low Drive Current
achieve very low on-state resistance combined with high • Ease of Paralleling
transconductance and great device ruggedness. • No Second Breakdown
The HEXFET transistors also feature all of the well estab- • Excellent Temperature Stability
lished advantages of MOSFETs such as voltage control, free- Product Summary
dom from second breakdown, very fast switching, ease of
paralleling, and temperature stability of the electrical param- Part Number VOS ROS(on) 10
eters.
IRF220 200V o.an 5.0A
They are well suited for applications such as switching power IRF221 150V o.an 5.0A
supplies, motor controls, inverters, choppers, audio amplifi- IRF222 200V 1.2n 4.0A
ers, and high energy pulse circuits.
IRF223 150V 1.2n 4.0A

22.2210.8751
CASE STYLE AND DIMENSIONS 3.42 °
MAX. IA. 11.;! m';~~1
10'135IMA~X6' .
22.22 (0.875) J.... ttEATING
MAX.DIA. T =+LANE

&.r,m'~~1 OIL..j 10.1610.40) MIN.

TWO PLACES TWO PLACES

Hfm:I;JIOIA.
TWO PLACES

DRAIN
ICASEI

1.09 (0.043)
MAX.DIA.
1+-_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO-204AA (T0-31

Dimensions in Millimeters and !lnchesl

0-93
IRF220, IRF221, IRF222, IRF223 Devices

Absolute Maximum Ratings

Parameter IRF220 IRF221 IRF222 IRF223 Units
VOS Drain - Source Voltage CD 200 150 200 150 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) (j) 200 150 200 150 V
10@TC- 25°C Continuous Drain Current 5.0 5.0 4.0 4.0 A
10@TC= 100°C Continuous Drain Current 3.0 3.0 2.5 2.5 A
10M Pulsed Drain Current @ 20 20 16 16 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 40 ISee Fig. 14) W
Linear Derating Factor 0.32 ISee Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L - 100~H
A
20 I 20 I 16 I 16
TJ Operating Junction and
-50to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 10.063 in. 11.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF220
IRF222
200 - - V VGS = OV

IRF221
IRF223
150 - - V 10 = 250"A

VGSlthl Gete Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS' 10 - 250"A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ~A VOS = Max. Rating, VGS = OV
- - 1000 .p.A VOS - Max. Rating x 0.8, VGS = OV, TC - 125°C
1010n) On-State Drain Current (2) IRF220
IRF221
5.0 - - A
VOS >1010n) x ROS(on) max> V GS = 10V
IRF222
IRF223
4.0 - - A

ROS(on) Static Drain-Source On-State IRF220

- 0.5 0.8 11
Resistance ® IRF221
VGS = 10V,I0 = 2.5A
IRF222
IRF223
- 0.8 1.2 11

9fs Forward Transconductance ® ALL 1.3 2.5 - S (0) VOS >10(on) x ROSlon) max.' 10 - 2.5A
Ciss Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 150 300 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 40 80 pF
td(onl Turn-On Delay Time ALL - 20 40 ns VOO ~ 0.5 BVOSS,IO = 2.5A, Zo = 5011
tr Rise Time ALL - 30 60 ns See Fig. 17
tdioffL Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 30 60 ns
Qg Total Gate Charge
ALL - 11 15 nC V GS = 10V, 10 = 6:0A, VOS m 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
QgS Gate-Source Charge ALL - 5.0 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 6.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

-$
LS Internal Source Inductance ALL - 12.5 - nH Measured from the
source pin. 6 mm
10.25 in.) from header
and source bonding
pad.

Thermal Resistance
Junction-to-Case
Case-to-Sink Mounting surface flat, smooth, and greased.
Junction-to-Ambient Free Air Operation

0-94
 IRF220, IRF221, IRF222, IRF223 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF220 Modified MOSFET symbol
(Body Diode) IRF221
- - 5.0 A
showing the integral
IRF222 reverse P-N junction rectifier.

~
IRF223
- - 4.0 A

ISM Pulse Source Current IRF220

- - 20 A
(Body Diode) @ IRF221
IRF222
IRF223
- - 16 A

VSD Diode Forward Voltage ® IRF220

- - 2.0 V TC = 25·C, IS = 5.0A, V GS = OV
IRF221
IRF222
- - 1.B V TC = 25·C, IS = 4.0A, V GS = OV
IRF223
t" Reverse Recovery Time ALL - 350 - ns T J = 150·C, IF - 5.0A, dlF/dt - 1 OOA/~s
QRR Reverse Recovered Charge ALL - 2.3 - ~C TJ l50·C, IF 5.0A, dlF/dt - 100Al~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'

<DTJ = 25·C to l50·C. (IDPulse Test: Pulse width ... 300~s, Duty Cycle ... 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

10 10
10V
II""
IV
t-- ,10", pulSE T.JT
I I
I '/
, , I
1/11
r-f r---JOJ.l.S pulsE TElT _ Vos > 10(on) x ROS(on) max.

'II
sv 'I
~
f
I
VGS 0 5V t - - TJ = 125°C
I t - - I-TJ 250C
0
I ~ .J
t - - TJ"' -55°C
I I'J rJ/
y I ~ rj
20 40 so 80 100 10
VOS. ORAIN·TO·SOU RCE VO LTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

iV V
8V

80,u,lPUlSE ~EST //. sf

~
J ~VGso5V

V-
I
/
1

l 4V

If
10
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-95
IRF220, IRF221, IRF222, IRF223 Devices

I-
i:i
..
~
e:wz j::" 1.0

•
>::> 0=0.5
t; ffi 0.5 NOTES:
:t~
FUL
- -.....
w.o f-b.2
ffi ~ 0.2
NC
::::i~
~::!!
r---O.l
0.1 FO.05 - ~2~
"'C"..... f-=
'-~
f-0.02
z.~ 0.05 _ 11
~0.01 12 .
f-
~""
.ow 1. DUTY FACTOR, 0 -
2:r:
~INGLE PULSE (TRANSIENT
",I-
~ 0.02
r-r THERMAL IMPEDANCE) 2. PER UNIT BASE = RlhJC = 3.12 OEG. CIW.

2 3. TJM - TC = POM ZlhJC(t).

N 0.01 I I I III I I
10-5 10-4 10-3 10-2 10-1 1.0 10
II, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

TJ l.ss,J i 10
2

-
TJ = 25'C

~
~ ~
..... ~

, --
I-"" ffi
./ ~ ~ TJ;-150 0C
--
125,JTJ ~
I ,,/
,.,.--
::>
.o
z
'1/ V ~
C
10

V/ V'
"
:Jj
~ I
1:;
Vi '"ri:
f'-TJ = 1500C
I

IV vos> 10(on) x ROS(,n) max. E 111

r '"j"'PULi'TESiT 1.0 I
I "-
TJ 7250C

4 6 10 o
10, DRAIN C.URRENT IAMPERESI VSO, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.2

..
w
to

~ 1.15
v
>
.."., ~ V
~
C
~s 1.05
Ww
"'N .."., ~
.,.'" ~

/
LV
"':::; ./
~i ~ /;'
§~ 0.96 ./
,.,.
C
~ ,/
Z

~ V
C
~ 0.86 I
'"
0.6
./
"..
./
vGS -10V

Ir 2A
~

0.75 O. 2
-40 ·40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE lOCI TJ,JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs .. Temperature

0-96
 IRF220, IRF221, IRF222, IRF223 Devices
1000 r--r--r--,---r--r--r--,---r--,--, 20
J
GS =J

in
~
Vas ~ 40V
~ 15
I "-----
~
'"
- Vas - 100V
w
to I I ~
""~ t--- VOS =160V.IRF220. 222
-
~~
o
>
w
~

~r
10
::>
5l
6
:;;
I--
"".;,
to
to
5 II
200 \ >
J ID=6A
FOR TEST CIRCUIT r---

10 20 30 40 50
V 12
sr FIG1URE Ii

16 20
Vos. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

1.5 ...........
.........
~ ,,~
e'"w
I I""- ........... .....
u
z
'"en
VGS = 10V 1il
~ ......... "'- IRF220.221

'" "-
I--

iii
'"z
1.0
'"
S t--- -IRF222.~ .........
0
w ) I--
Z
w .........
'"'"
u

-- " ""
'"
::> V' k-~ 13
~ f-- ~
0
z
~
..,z
;;;:
0.5
VGS = 20V ;;;:
'"
c r\.\
'"
0
E '\ ~
.,
§
0 RDSlon) MEASURED WITH CURRENTPULSE OF '\
'" 2.01" DURATION. INITIAL TJ = 250 C. (HEATING
EFFECT OF 2.0 1" PULSE IS MINIMAL.)
o
10 15 20 25 50 75 100 125 150
10. ORAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35
'\
30
~
'"
I--
I--
'"~
z 25
\.
0
>= '\
;!t
20 '\..
iii
i5
'"~ 15
'\
~

'"'"
,p
10

'\
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-97
IRF220, IRF221, IRF222, IRF223 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGs=R
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

AOJUST RL El
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
GENERATOR O.U.T.
r------,
I
50n I o----TO SCOPE
I O.Oln
I
L_
___ .JI 50n HIGH FREQUENCY
SHUNT

Fig. 17 - Switching Time Test Circuit

r - - - O +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

o~1.5mA - OUT

V\.,...-....."""JV'v--o -VOS
IG 10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-98
 PO-9.306

INTERNATIONAL RECTIFIERII\)RI

HEXFET® TRANSISTORS IRF23D

IRF231
N·Channal IRF232
IRF233

200 Volt, 0.4 Ohm HEXFET Features:

The HEXFET~ technology is the key to International Recti- • Fast Switching
fier's advanced line of power MOSFET transistors. The effi-
cient geometry and unique processing of the HEXFET design
• Low Drive Current
achieve very low on-state resistance combined with high • Ease of Paralleling
transconductance and great device ruggedness.
• No Second Breakdown
The HEXFET transistors also feature all of the well estab- • Excellent Temperature Stability
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Product Summary
paralleling, and temperature stability of the electrical param-
eters. Part Number VOS ROS(on) 10
IRF230 200V O.4n 9.0A
They are well suited for applications such as switching power
supplies, motor controls, inverters, choppers, audio amplifi- IRF231 150V O.4n 9.0A
ers, and high energy pulse circuits. IRF232 200V o.an S.OA
IRF233 150V o.an S.DA

22.22(0.8151
CASE STYLE AND DIMENSIONS 3 42 MAX. DIA. 11.43 0.450

22.22 (0.875)
MAX. DIA.
(O"3tx~r",,,
T PLANE

A'r, m'8;il
DIA.--j 10.16 (0.401 MIN.
TWO PLACES TWO PLACES
26.61
(1.0501 MAX.
4.08(0.161 DIA
.4 . 51 .
TWO PLACES

39.95
DRAIN (1.5731 MAX.
(CASEI

1•
"1.09 (0.043)
MAX. DIA.
f4-_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE

Conforms to JEOEC Outline T0-204AA (T0-3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

D-99
IRF230, IRF231, IRF232, IRF233 Devices

Absolute Maximum Ratings

Parameter IRF230 IRF231 IRF232 IRF233 Units
VOS Drain - Source Voltage <D 200 150 200 150 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) CD 200 150 200 150 V
10@TC=25 DC Continuous Drain Current 9.0 9.0 8.0 8.0 A
10@TC=100 DC Continuous Drain Current 6.0 6.0 5.0 5.0 A
10M Pulsed Drain Current @ 36 36 32 32 A
VGS Gate - Source Voltage ±20 V
PO@TC=25 DC Max. Power Dissipation .7 5 ISee Fig. 14) W
Unear Derating Factor 0.6 ISeeFig.14) W/K
ILM Inductive Current, Clamped (Sae Fig. 15 and 16) L = 100"H
A
36 I 36 I 32 I 32
TJ Operating Junction and DC
-55to 150
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for 10s) DC

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF230
IRF232
200 - - V VGS = OV
IRF231
IRF233
150 - - V 10 ='250"A

VGSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 = 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ,.A VOS = Max. Rating, VGS = OV
- - 1000 ,.A VOS - Max. Rating x 0.8, VGS - OV, T C - 125 DC
1010n) On-State Orain Current ® IRF230
9.0 - - A
IRF231
V OS ) 10(on) x ROS(on) max.' V GS = 10V
IRF232
IRF233
8.0 - - A

ROS(on) Static Drain-Source On-State IRF230

Resistance ® IRF231 - 0.25 0.4 II

IRF232
VGS = 10V, 10 = 5.0A
IRF233 - 0.4 0.6 II

9fs Forward Transconductance ® ALL 3.0 4.8 - S«(J) VOS ) 10(on) x ROS(on) max.' 10 - 5.0A
Ciss Input Capacitance ALL - 600 800 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss >
Output Capacitance ALL - 250 450 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 80 150 pF
tdlonl Turn-On Oelay Time ALL - - 30 ns VOO = 90V,I 0 - 5.0A, Zo = 1511
tr Rise Time ALL - - 50 ns See Fig. 17
ld(off) Turn-Off Delay Time ALL - - 50 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fallnme ALL - - 40 ns
Clg Total Gate Charge VGS = 10V, 10 - 12A, VOS - 0.8 Max. Rating.
(Gate-Source Plus Gate-Orain)
ALL - 19 30 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qas Gate-Source Charge ALL - 10 - nC

Qgd Gate-Orain ("Miller") Charge ALL - 9.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

~
LS Internal Source Inductance ALL - 12.5 - nH Measured from the
source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Amblent Free Air Operation

0-100
 IRF230, IRF231, IRF232, IRF233 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF230 Modified MOSFET symbol
- - 9.0 A
(Body Diode) IRF231 showing the integral
IRF232 reverse P-N junction rectifier.

~
- - S.O A
IRF233
ISM Pulse Source Current IRF230
- - 36 A
(Body Diode) ® IRF231
IRF232
- - 32 A
IRF233
VSD Diode Forward Voltage @ IRF230
IRF231
- - 2.0 V TC = 25·C.IS = 9.0A. VGS = OV
IRF232
IRF233
- - I.S V TC = 25·C. IS = S.OA. VGS = OV
trr Reverse Recovery Time ALL - 450 - ns TJ = 150·C.IF - 9.0A. dlF/dt - 100A/~s
ORR Reverse Recovered Charge ALL - 3.0 - ~C TJ = 150·C.IF 9.0A. dlF/dt 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'
<DTJ = 25·Cto 150·C. @PulseTest: Pulse width'; 300"s. Duty Cycle'; 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20
10
10VI/8V 80 ~s PU LSE TEST
80 ~s PU lSE TEST I hI
- VOS'>IO(on)'X ROS(on) max.
16 7V III
/)
I,.
~ 12 I
....
~ VGS =6V
TJ = +1250 C
~
=>
u
z TJ = 25 0 C ~
I
J
~
~'III
I
c
TJ = -55 0 C
E 5V ~

Iiii"J"
4V ./L/I
20 40 60 80 100 5
VDS. DRAIN·TD.sOURCE VOLTAGE (VOLTS) VGS. GATHO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

10
100g~~.
50 -IRF230. 1-
OPERATION l~fTHIS
AREA IS LIMITED
~ BY ROS on
~~ .,.r- ~

20 -IRF232.3

I-- JO"' pulSE TElT ~ ~ r-;:I9V_

OV
I--
~ v< ~
~~V
7V- r--
'"~
0-
~
10 IRF230.1 10~s

100~s

~~
=IRF232.3
~~V ....
1li

"
0:
0:
VGS=5V- ~ ..,=>
J I-"'"

I~
~ iE l'O~~~~~~~~!§§!II~~,~ol~-ms~~
=TC - 25 0 C
od-L
0.5 =TJ= 1500 CMAX.
100 ms

- RthJC = 1.67 K/W -t--+-l-+--f++-H++--+-+:":~H'1f+H++l

J" 0.2 -ISI~GL~n~EII't-+-+-++IRF231.3 IRb~0.2
'r i
V- ~

0.1 ':--'-7-'I.......I-:'-I.u.I~
III :--'-::'::-'--'::'::"
IIU-III:,::
111:-'-:::=-.....1-,::
I ==-1L.......
1.0 10 20 50 100 200 500
VDS. DRAIN·TO·SDURCE VOLTAGE (VOLTSI VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area
0-101
IRF230, IRF231, IRF232, IRF233 Devices

....
~
!li<
"'-
........
wz 1.0
>:> D" 0.5
t; ffi 0.5 NOTES:
~~
w<.>
ffi:i
~~
0.2
1-6.2
f--- 0•1 :. ... mIL
~;;!! 0.1 1--0.05
"' ....
0<
z_~ 0.05
0.02 ~2~
<'>w ~0.01 SINGLE PULSE (TRANSIENT 1. DUTY FACTOR. D" :~
2::.:
rE .... -+-" mRMA~ I~PEDfN~E\ I I 2. PER UNIT BASE" RlhJC" 1.67 OEG. CIW.
~ 0.02
3. TJM - TC" PDM ZlhJC(I).
j 0.01 IIII 1 11 II
10-5 10-4 10-3 10-2 10-1 1.0 10
11. SQUARE WAVE PULSE DURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to·Case Vs. Pulse Duration

10 I
10 2
~ TJ" 25 0 C
a:
w
Q.

TJ" -55°C
'...."
!5.
IL'"
~
C::TJ" 150 0 C
~ /'
TJ=250~
a:
./
V i"'" :>
<.> -<II
. . .V ~
z
: /I
V TJ" 125°C
0
10

V./ V....... ~ ~
w

1-
'"~ TJ" 1500 C I

hV ~
a: ~

III VDS> 10(on) x RDS(on) max.

EO '" I
I
r 10., ,JLSE rJsT iJ
TJ" 25 0 C
I
1.0
10 o
10. DRAIN CURRENT (AMPERES) VSD. SOU RCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.2

w
'"~ w

.,. /
<.>
1.15 1.8
~
o
~
V
,.., ,..,
>
~ i3
o V'
~
o a:
z:
~E 1.05
Ww os 1.4
"'N
"'::::;
w<
.,.,. ./
Ww
<'>N
g~
V
~~
~~ 0.9 5
V ./ 6~
~~ 1.0 L "
:
..,.o
z
;;:
'"
c V
o

>
~
o
0.8 5
a:
~o 0.6
./
./
"" VGS" 10V

IDC 3.5~
'"
0.7 5 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTiON TEMPERATU RE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-102
 IRF230, IRF231, IRF232, IRF233 Devices
2000 20
.1
1 VGS=O

I I f=11 MHZI I 0; VDS 1= 40V

1600 I--
CilS = Cgo + Cgd. Cd. SHORTEO ':;
~ 15
J"-...
I

~ [)j1P'
Cns = Cgd Vos = 100V

u.
~
I--
.'"
w
Vos =1S0V, IRF230, 232
1

r
Coss=Cd,· .C
go gd

~
;;; 1200 I-- ':;
..., "'Cd •• Cgd o
z >
I

-
~ ~ 10
~
<3 =>
~
~
o

::;'"
~ 800 cln
~\
o
...,' 1
,I
.... If
400
\ "- .........
'"U, 5
to

I 10 =12A

" --~
'\ >

c".
1 V
FOR TEST CIRCUIT
SjE FlyRE Ii I--

10 20 30 40 50 16 24 32 40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) ag. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to-Source Voltage
0.8 10
0;
:!!
'"w
!2
I
VGS = 10V .........
....., r--....
'"
Z

In .........
0.6
~ .......
fli0:
Z !~ IRF23~
"RF230,231
..........
,"'-
0
...,
w
...z 6
0:
......

--
::> W
0 0.4 0:
"I
......... l'\.
V
0:
..,.0 a
z z 4
«
"'~
0:
~ l...-- ~ VGS = 20V «0:
'";} I
o

"\ ,
12
0
~ 0.2 ~
0:

RDS(on) MEASURED WITH CURRENT PULS1E OF

2.0~.DURATION. INITIAL TJ=25 0 C. (HEATING
EFFECT OF 2.0~. PULSE IS
MINIMALl
o
10 20 30 40 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
80

70
- ~

60
"r\.
~
... '\ \.
~ 50
z
0

...~ 40
'\
iii
Q
0:

~ 30
'\
~
.e 20

10
"'- ~
'r\
20 40 60 80 100 120 140
Tc, CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-103
IRF230, IRF231, IRF232, IRF233 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGs·R
Fig. 15 - Clamped Ind'!ctive Test Circuit Fig. 16 - Clamped Inductive Waveforms

VOO'" 90V

15.511
PRF=lkHz Vi Vo
tp'" llJ.s -".,----~TO SCOPE
r-----.,
I 20
I I
I I
20 IS11
IL.:_
lOV
_ __ ...JI

Fig. 17 - Switching Time Test Circuit

,...---0 +VOS
I1S0LATEO
SUPPLY)

SAME TYPE
AS OUT

o~I.5mA - 16
OUT

10
CURRENT ':' CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-104
 PD-9.370

INTERNATIONAL RECTIFIERI:rORI

HEXFET® TRANSISTORS IRF24D

N-CHANNEL
IRF241
POWER MOSFETs IRF242
IRF243
200 Volt, 0.2 Ohm HEXFET Features:
The H EXF~ technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state
resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as volt- Product Summary
age control, freedom from second breakdown, very
Part Number VOS ROS(on) 10
fast switching, ease of paralleling, and temperature
stability of the electrical parameters. IRF240 200V O.lan 18A
IRF241 150V 0.18n 18A
They are well suited for applications such as switch-
ing power supplies, motor controls, inverters, chop- IRF242 200V 0.22n 16A
pers, audio amplifiers, and high energy pulse circuits. IRF243 150V 0.22n 16A

22.22(0.875)
CASE STYLE AND DIMENSIONS 3.42 MAX. DIA. 1~.:: IC.tsgl
(0'135)MAX~'
~
.5

ttEATlNG
T ==l2LANE

L§~:J)DIA.
1.45 (o~orn I I Rl;I~':rol
.1.
TWO PLACES TWO PLACES
26.67
(1.050) MAX.

;-32
. m·1~11
.1 OIA.
TWO PLACES

DRAIN
(CASE)

SOURCE

11.17 (O.440)t
!lmllmIIJ
t MEASURED ATSEATlNG PLANE

Confonns to JEDEC Outline TO·204AA (T0-3)

ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-105
IRF240, IRF241, IRF242, IRF243 Devices

Absolute Maximum Ratings

Parameter IRF240 IRF241 IRF242 IRF243 Units

VOS Drain - Source Voltage (j) 200 150 200 150 V

VOGR Drain - Gate Voltage (RGS = 1 Mil) (j) 200 150 200 150 V
10@TC=25°C Continuous Drain Current 18 18 16 16 A
10@TC=100oC Continuous Drain Current 11 11 10 10 A
10M Pulsed Drain Current ® 72 72 64 64 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 125 (See Fig. 14) W
Linear Derating Factor 1.0 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = IOOI'H
A
72 I 72 I 64 I 64
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range
Lead Temperature 300 (0.063 in. 11.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF240
IRF242
200 - - V VGS = OV
IRF241
IRF243
150 - - V 10 = 250"A
VGSCthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS, 10 - 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - - 250 I'A VOS - Max. Rating, VGS - OV
ALL
- - 1000 I'A VOS - Max. RatingxO.8, VGS = OV, TC = 125°C
1010n) On-State Drain Current ® IRF240
18 - - A
IRF241
VOS } 10(on) x ROSlon) max.' VGS = 10V
IRF242
IRF243
16 - - A

ROS{on) Static Drain-Source On-State IRF240

Resistance ~ IRF241
- 0.14 0.18 Il

IRF242
VGS = 10V, 10 = IDA
IRF243
- 0.20 0.22 Il

gfs Forward Transconductance ® ALL 6.0 9.0 - S 10) VOS } 10(on) x HOS(on) max.' 10 IDA

Ciss Input Capacitance ALL - 1275 1600 pF

VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 500 750 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 160 300 pF
tdJooJ Turn-On Delay Time ALL - 16 30 ns V OO = 75V, 10 = lOA, Zo - 4.71l
tr Rise Tirne ALL - 27 60 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 40 80 ns (MOSFET switching times are essentiaUy
independent of operating temperature.)
tf Fall Time ALL - 31 60 ns
Qg Total Gate Charge
ALL - 43 60 nC
V GS = 10V, 10 = 22A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 16 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 27 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
10.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-106
 IRF240, IRF241, IRF242, IRF243 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF240 Modified MOSFET symbol
(Body Diode) IRF241
- - 18 A
showing the integral
IRF242 reverse P-N junction rectifier.
- - 16 A

~
IRF243
ISM Pulse Source Current IRF240
(8ody Diode) @ IRF241 - - 72 A

IRF242
IRF243
- - 64 A

VSD Diode Forward Voltage @ IRF240

IRF241
- - 2.0 V TC = 25°C, IS = 18A, VGS = OV
IRF242
IRF243 - - 1.9 V TC = 25°C, IS = 16A, VGS = OV
trr Reverse Recovery Time ALL - 650 - ns T J = 150°C, IF = 18A,dl F/dt - 100Al"s
QRR Reverse Recovered Charge ALL - 4.1 - "C
T J - 150°C,I F = 18A,dlF/dt = 100All's
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'
<DTJ = 25°Cto 150°C. @PulseTest: Pulse width'; 300I'S, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

40 40

rlIBV.!. //
32 -
10V
~9V l", pJSETJT - r- 3Z
1-55~C"
~J=25~C" ""-
IJ I
iii -Il'
VI
0:
~ 7V Tr 125 0 C"..... "'-
:E
~ 24
I-
z
W
I-- so 1"
j f

,!I
0: PULSE TEST
0: I I I I
..,'" Vos> ID(on) x RDS(on) max .
z 16
;;: VGS= 6~
0:
C

P
I
5~ i.f
4~ ~
10 20 30 40 50 B 10
VOS. DRAIN·TO.sOURCE VOLTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
40 t::: IRF240, 1= PER TON N HIS A EA IS LIMITED
' BY ROS(on)
1=-1 RF242, 3
-sL,pulsETESl
50
,
k~
.~,

32
~?
20 IRFZ40,1 ['.
, ~ 101"_
10 ~s
1
iii iii "
"
IRF24Z,3
0:
~
~~
10
~
_)V- :E 1 ms
~ 24 ~

~~
~
i' 1'\
I- I-
z Z
W W
0: 0:

~ V
0: 0:
10ms
'" 13
~ 16 z
~ ~V
~ VGS-f V - ~ 1.0 :' 100 ms
c
p
~ V"
c
-
'" 0.5
=
= TC=Z5 0 C
TJ -IS00 C MAX.
DC=

~ ~V-
_ R,hJC = 1.0 KIW
0.2 .....tlGLj iUiSIEl1 IRFZ41,3 IR 1F240, Z
I~ Jv_ 0.1 II IIIII I IIIII I III
1.0 10 20 50 100 100 500
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VDS. DRAIN·TO.sOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-107
IRF240, IRF241, IRF242; IRF243 Devices

I-
Z
w 1 UI
~ I I II
l=E
wz
1.0

--
>:::0
0=0.5
tffi
wo..
0.5 NOTES:
~;;

~
wu 0.2
ffi~ 0.2
..- :oiIIIII
~~ r - 0.1
~;!! 0.1 ,==0.05
"'
0< ....
z.~ 0.05
r-0.02 ~2~
SINGLE PULSE (TRANSIENT _ 'I
Uw
2:>:
, ~0.01
1. DUTY FACTOR. 0 -12 .
.<1-
::. I iHiiililMPjOjNCEI I 2. PER UNIT BASE = R'hJC = 1.0 DEG. CIW.
T. 0.02
3. TJM' TC = POM Z'hJC(')'
j 0.01 _L II III I
10-5 10-1 1.0 10
'I. SQUARE WAVE PULSE DURATION (SECONDS)
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

19.0 50
~
V-
15.2 A r
iw TJ' -55 0C
q
1!i .'
1e
~ 11.4
/ 'V T~ = 25JC JJ
z
t / JI' ~
T~= 12JoC- r-- I I
:::0
C
Z
o 7.8 l/ I
[j! r-- r- TJ = 1500C I
< /I r/ 1
'" TJ = 25 0 C

"
I-

~ 3.8 ., 80 lIS PULSE TEST

I I I
VOS> 10(on) x ROS(on) max.

1.0
o 0.4
I 0.8
I
1.2 1.6 2.0
16 24 32 40
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

.. u
z
~ 2.0
1/
",.- ~ iii
'"
w
~
. /V
!;;: ~
t?s 1.5

. /V
ZW
ON
w::;
u<
./'
.."
/' "':IE
:::0",
00 ./
V
6~ to
V /
'"
z
;;:
'"
c "...
./

l 0.5
VGS= 10V
10=9A
c
'"
1 I
0.75
-40 40 80 120 160 40 80 120 160
TJ.JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-108
 IRF240, IRF241, IRF242, IRF243 Devices
J .l.
t
2000
C'IS =Cgs+Cgd.Cd,SHORTEO
l--c", =Cgd _VGS=ov 20

CgsCgd t= 1 MHz
Co.. =Cd'+~
1600

--
"'Cd. + Cgd
, ~
~ -'
~ 15
r- _Ciss VOS = 40V""
,
\ ~
... w ,
~ 1200 '"
« VOS = 100V .........
..,z ~ , '''''-.
~
o
«
.... i\ > VOS = 160V, IRF240, 242"",
~
~
.., 800 \ \ :::J
o
u;o
10

~
ti
\ 1"- o
:;:;
/
-
........ !;(
'~ ~ '!, 5 10 = 22A -
400
'"
/
""" r---..
--
> FOR TEST CIRCUIT
"'- cl _jEE FIGrRE 18 -

I 1

10 15 20 25 30 35 40 45 50 20 40 60 80
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Dg. TOTAL GATE CHARGE (nCI
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs_ Gate-to-Source Voltage

20
0,5

~ ..........
:z:
ew 16 ~
0,4 .......... I""-
'"z
« ~
......... r-....
........
~~ IRF240.241
~ 0:
V S = 10V ~
~ 0.3 ! 12

IRF:.~~
z
0 ....
z
w W
'":::J0: 0:
0:
13 ,~
0
u;o 0,2 IJ z 8

..V "'" ~"'I

0
....z <
0:
.." K;=20V o
< E
~
0:
C
c 0.1
'\,
0

0:
i:3 ROS(onl MEASUREO WITH CURRENT' PULSJ OF
2,0 ps OURATION, INITIAL TJ = 25 0 C. (HEATING
p:
EFF~CT Of 2.0 PULSf IS MIINIMA~.1
I
20 40 60 80 100
o
25 50 75 100 125 150
10. ORAIN CURRENT (AMPERES) Tc. CASE TEMPERATURE (UCI
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

--
140

120

~
~ 100
" ,
~
z
o
~ 80 "' ,
gj
C
0:

~
60
"
rP 40
" "', ~

"',
20

20 40 60 80 100 120 140

TC. CASE TEMPE RATU RE (OCI
Fig. 14 - Power Vs_ Temperature Derating Curve
0-109
IRF240, IRF241, IRF242, IRF243 Devices

VARY tp TO OBTAIN
REOUIREO PEAK Il

VGS'~ ,OUT

Il_-~t>---_J\NII-'"

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

75V
ADJUST Rl TO OBTAIN B.511
SPECIFIED 10
VOS

r;u~---l D.U.T.
I GENERATOR O--r----~:>---'U-....

I :J~CE Sl I
LIMPEDANCE
___ J

Fig. 17 - Switching Time Test Circuit

.----0 +VDS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

o~·5mA - IG
OUT

\. . ._-""J'v-O -VDS
10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-110
 PD-9.321

INTERNATIONAL RECTIFIER II~)R I

HEXFET® TRANSISTORS IRF25D
IRF251
N-Channel IRF252
IRF253

200 Volt, 0.085 Ohm HEXFET Features:

The HEXFET® technology is the key to International
• Fast Switching
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the
HEXFET design achieve very low on-state resistance
• Ease of Paralleling
combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast
Part Number VOS ROS(on) JO
switching, ease of paralleling, and temperature
stability of the electrical parameters. JRF250 200V O.085n 30A
JRF251 150V O.085n 30A
They are well suited for applications such as switching
JRF252 200V O.120n 25A
power supplies, motor controls, inverters, choppers,
audio amplifiers, and high energy pulse circuits. JRF253 150V O.120n 25A

22.2210.8751
CASE STYLE AND DIMENSIONS 3 42 MAX. OIA. 11.43 0.4501
(O'135')MAX~'5 .25

.-.l. ttEATING

T
1.60 00631 OIA I
:X LANE

12.1910.4801
1.451 057 I 11.18104401
TWO PLACES TWO PLACES
26.67
11.0501 MAX.

Hi m:l!lI OIA
TWO PLACES

DRAIN
ICASEI

SOURCE

11.1710.44011
~_ _ _ 39.95 (1.573) ----+-I ru:mmm
MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO-204AE (Modified T0-31

Dimensions in Millimeters and (Inchesl

0-111
IRF250, IRF251, IRF252, IRF253 Devices

Absolute Maximum Ratings

Parameter IRF250 IRF25.1 IRF252 IRF253 Units
VDS Drain - Source Voltage (1J 200 150 200 150 V
VDGB Drain - Gate Voltage (RGS = 1 MOl <D 200 150 200 150 V
ID@TC = 25°C Continuous Drain Current 30 30 25 25 A
ID@TC - 100°C Continuous Drain Current 19 19 16 16 A
IDM Pulsed Drain Current @ 120 120 100 100 A
VGS Gate - Source Voltage ±20 V
PD.@TC - 25°C Max. Power Dissipation 150 (See Fig. 14) W
linear Derating Factor 1.2 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 100!,H
A
120 I 120 I 100 I 100
TJ Operating Junction and DC
-55to 150
Tstg_ Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) DC

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage IRF250
200 - - V VGS = OV
IRF252
IRF251
IRF253
150 - - V ID = 250!,A

VGSlthl Gate Threshold Voltege ALL 2.0 - 4.0 V VDS - VGS, 16 - 250!,A
)GSS
IGSS
Gate-Source Leakage Forward
Gate-Source Leakage Reverse
ALL
ALL
-- -
-
100
-100
nA
nA
VGS - 20V
VGS = -20V
IDSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VDS = Max. Rating, VGS = OV
- - 1000 I'A VDS - Max. Rating x O.B, VGS - OV, TC - 125°C
On-State Drain Current ® IRF250
ID(on)
IRF251
30 - - A
V DS ) ID(on) x RDS(on) max.' V GS - 10V
IRF252
IRF253
25 - - A

RDS(on) Static Drain-Source On-State IRF250

Resistance (2) IRF251 - 0.07 0.OB5 Il
VGS = 10V,ID = 16A
IRF252
IRF253 - 0.09 0.120 Il

gfs Forward Transconductance. CID ALL B.O 14 - 5(11) VOS) ID(on) x RDS(on) max.' ID - 16A
Ciss Input Capacitance ALL - 2000 3000 pF
VGS = OV, VDS = 25V, f = 1.0 MHz
Coss Output CapaCitance ALL - BOO 1200 pF
See Fig. 10
Grss Reverse Transfer Capacrtance ALL - 300 500 pF
td(on) Turn-On Delay Time ALL - - 35 ns VOO = 95V,I D = 16A, Zo = 4.71l
tr Rise Time ALL - - 100 ns See Fig. 17
tdloffl Turn-Off Delay Time ALL - - 125 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 100 ns
Qg Total Gate Charge
ALL - 79 120 nC
V GS = 10V, 10 - 3BA, VDS - O.B Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 37 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 42 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

$
LS '{lternal Source Inductance ALL - 12.5 - nH Measured from the
source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.

Thermal Resistance
RthJC Junction-ta-Case
Case-to-Sink Mounting surface flat. smooth, and greased.
RthJA Junction-ta-Ambient Free Air Operation

0-112
 IRF250, IRF251, IRF252, IRF253 Devices

Source-Drain Diode Ratings

-
and Characteristics
IS Continuous Source Current IRF250 Modified MOSFET symbol
(Body Diode) IRF251
- - 30 A
showing the integral
IRF252 reverse P·N junction rectifier.
- -

~
25 A
IRF253
ISM Pulse Source Current IRF250
(Body Diode) @ IRF251 - - 120 A

IRF252
IRF253
- - 100 A

VSD Diode Forward Voltage @) IRF250

IRF251
- - 2.0 V TC = 25 a C, IS = 30A, VGS = OV

IRF252
IRF253 - - 1.8 V T C = 25 a C, IS = 25A, VGS = OV

t" Reverse Recovery Time ALL - 750 - ns TJ - 150 a C, IF - 30A, dlF/dt - 1 OOA/~s
QRR Reverse Recovered Charge ALL - 4.7 - ~C T J = 150a C, IF = 30A, dlF/dt - 100A/~s
ton Forward Turn·on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

<DTJ = 25 aC to 150a C. @)PulseTest: Pulse width" 300I'S, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

50
10V rt.}9V 80~sPULSE TEST .! J. 30
'/
y
BV VGS=7V- r--
1
25 r-80 JJS PULSE r!ST
40 I I
r-
VDS > ID(on) x RDS(on) max.
'"w
'"'
W
~
w 20
0- 0-
lE lE
~ 30 ~
... ...z
ill 6V- I-- w
0: 15
'"' 0:
a'"'
z 20
:::>
'"'z
«
0:
c
«
0:
c 10
TJ = 125 0 C !J
12 5~- r-- 12 'ITJ = 25JC
L
" --Jl
10 I"
TJ = -50 oC JlJ
4,V- r--
1'/ 'U
~"
3.5V ___

10 20 30 40 50 4
VDS, DRAIN·TO·SDURCE·VOLTAGE (VDLTS) VGS, GATE·TD·SOURCE VDLTAGE (VOLTS)

Fig, 1 - Typical Output Characteristics Fig, 2 - Typical Transfer Characteristics

20 , 500

~
OPERATlDN IN THIS L

'l6~~ -
9V 7V AREA IS LIMITED
I--- BO"!PULSE1TEST BV 200
I BY RDS(on)

~~~

-
16

~~
100
0; IRF252,3
13 W
0:

!l!lE ~ !-GS = 5V ,.
i!: 50
IRF250,1 10",
~
...z~
12
... r,- ',- 100p.~
W
0:
IA ./
,;'" ill
0:
20
,
I Rf252, 3
l~s
~V "'
0: 0:
:::> :::>
10
'"'z 'z"'

,
;;:
«
0:
c ~ V 0:
C
12 lOT'
~~
12
TC = 25 0 C 100m,
~ TJ = 1500 C MAX.

, 4V
- RthJC = 0.B3 K/W
1.0 t=SINGLE PULSE
IRF251.3~

~
- r- IRF250,2_ OC-
0.5
0.4 0.8 1.2 1.6 2.0 1.0 10 20 50 100 200 500
VDS, DRAIN·TO·SDURCE VOLTAGE (VOLTS) VDS. ORAIN·TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-113
IRF250, IRF251, IRF252, IRF253 Devices

....
i:5
Vi
z
,
<
a: _
........ 1.0
wz
>::> 0-0.5
t; ffi 0.5
NOTES:
tt~ f-b.2
w,",

ffi~ 0.2
!:::!Ea
-'''-
1--0.1

-- ... mIl.
~O.05
~2~
~~ 0.1
a:-'
0< r-0.02
z.~ 0.05
'"'w
2:>:
r-~.Ol
....... 1. OUTY FACTO R. D = :~
~ .... SINGLE PULSE (TRANSIENT
~ 0.02 T~E~~AILmpED~NCIE) I 2. PER UNIT BASE = RlhJC = 0.83 DEG. CIW.
c;,
~ II III 3. TJM - TC = PDM ZlhJC(11.
N 0.D1
10-5 10-4 10-3 2 10-2 2 10-I 1.0 10
II. SQUARE WAVE PULSE DURATION (SECONDS)

Fig.5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

20
T~ = -50~C J-- i"""
~

16
~-25JC
f""'" ~
102
TJ = 25 0 C h "
."

'"z
~
/. ."" ~
::;; , TJ - 150 0 C

§
w 12 i/ TJ = 125 0 C ~
....
i'a:l'i
F
'"'z
<
1/ ./" ."
a:
f/
1:;
::> G TJ=150 0 C '
c
z
0 l/ VOS> 10(on) x ROS(on) max.-
z
<1
a: 10
IY~
~
z
;;§ II 80' /J.S PU LSE
I '''I
TEST
0
w
'"
:.:; TJ = 25 0 C
....
j
IL 1:;
a:

E '"
1.0
10 20 30 40 50 o
10. DRAIN CURRENT (AMPERES) VSO' SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.4

1.25
V~S=
I
IL
I
10 = 15A
2.2

.
w
'"
~ 1.15
w
.
'"'
z
t;;
~

iiia: /
. /~
> 1.8
z
~ 06 /
~ Ww

~
~~
::>-'
",,,,
0< 1.4 V
~
..",.
~~
z-
V
./ V
fI'" ~
0 1.0 l/
/"
./
'"c
a:
0

~
..-
0.6

0.75 0.2
-40 40 80 120 160 ~ ~ w m ~
TJ. JUNCTION TEMPERATURE laC) TJ. JUNCTION TEMPERATURE (DC)
Fig.8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-114
 IRF250, IRF251, IRF252, IRF253 Devices
4000
20
VGl = 0
I
f= 1 MHz
~
3200

\ Ci.. = Cgs + Cgd, Cd, SHORTED -

C", = Cad - ~ Hi VOS = 40V
~
~
I I
...
~ 2400
,\ Cgs Cad
Co.. = Cd,+ Cgs+ Cgd
-
w
'"
'"c~ -Vos = 160V, IRF250, 252
~os = \OOV,
t--..,

l~ ~ ".
'-' "'Cds+ Cgd

,..
z >
~ I w
~ 10
:<;~_ 1600 \ ~ Cjss ::>
~
~
\. " 6
~
.... I
\. ........... .... ,I
Coss '"'"v,
800

" ........ __ C ,m Ii-- > "' / 10 = 38A

Ii
FOR TEST CIRCUIT I---

10 20 30 40 50
/ 28 56
SjE FIG1U RE

84 112 140
VDS, ORAIN-TO-SOURCE VOLTAGE (VOLTS) Qg' TOTAL GATE CHARGE InC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage

0.22 30
ROS(on) MEASURED WITH l"'- t'--..
~ CURRENT PULSE OF
2.0p,OURATION.
E'"w INITIAL TJ = 25 0 C.
24 r...... r--....r-,.
(HEATING EFFECT OF 2.0 P'
'-'
z 0.18 VGS = 10V - PULSE IS MINIMAl.) f"".. r--.... . . . . ,
'"
.... '"w IRF250,251
i:i'" ~
z
c
'"
:E
:! 18
....
............
IRF252,25;-'" ""-
w
'-'
'"
0.14 ~
'" ""'-"
~"
::>
c '" .........
1:l
'>:-z" z

,,
c 12

~
;;:
;;: '"
'" J / '"E
'"c 0.10
~
V "
--
0

'" ./ VVGS=20V
'"'" .....
~
0.06 o
o 40 80 120 160 25 50 75 100 125 150
10, ORAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (OC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

140 '\.
'r'\.
,
120

~ '\
~ 100
z:
'"
~ 80
'\
~
C
'" 60
'\
~
3:
~
~ 40

20

20 40 60 80 100
Te' CASE TEMPERATURE (OC)

Fig. 14 - Power Vs. Temperature Derating Curve

'"
120
'[\
140

0-115
IRF250, IRF251, IRF252, IRF253 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGS-R ~OU_T_____,----"
IL---<>--~'-'\M,--'

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

E,
ADJUST RL TO OBTAIN RL
SPECIFIED 10
VDS

f;u-; - - -o-l.------o----l!.J-1f O.U.T.

I GENERATOR
I ~~~RCE Jl
___ JI
LIMPEOANCE

Fig. 17 - Switching Time Test Circuit

r-----00 +V DS
.(lSOLATED
SUPPLY)

o-.Jr---1T1.5mA
____ LL - IG
_ _-",",,,,-u -VDS
10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0·116
 PD-9.314

INTERNAnONAL RECTIFIER II(iR I

HEXFET® TRANSISTDRS IRF32D
IRF321
N-Channel IRF322
IRF323

400 Volt, 1.8 Ohm HEXFET Features:

The HEXFET«!) technology is the key to International Recti-
• Fast Switching
fier's advanced line of power MOSFET transistors. The effi- • Low Drive Current
cient geometry and unique processing of the HEXFET deSign • Ease of Paralleling
achieve very low on·state resistance combined with high • No Second Breakdown
transconductance and great device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well estab- Product Summary
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Part Number VDS ROS(on) 10
paralleling, and temperature stability of the electrical param-
IRF320 400V 1.8n 3.0A
eters.
IRF321 350V 1.8n 3.0A
They are well suited for applications such as switching power IRF322 400V 2.5n 2.5A
supplies, motor controls, inverters, choppers, audio amplifi-
ers, and high energy pulse circuits. IRF323 350V 2.5n 2.5A

22.22 {0.8751
CASE STYLE AND DIMENSIONS 342 MAX. DIA. 11.43 0.450
10'13"IMA~X' {.25

22.22 (0.875) -L ttEATING

MAX. DIA. T =+LANE

6'~ !8'~~1 OIA.-j 10.16 {Q.401 MIN.

TWO PLACES TWO PLACES

H~
. 1~1611
. 51 DIA .
TWO PLACES

DRAIN
ICASEI

1.09 (0.043)
MAX. DIA.
1+-_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE
Conforms to JEDEC Outlin. TO-204AA (TO-3)
ACTUAL SIZE Dimensions in Millimeters and (lnch.s)

0-117
IRF320, IRF321, IRF322, IRF323 Devices

Absolute Maximum Ratings

Parameter IRF320 IRF321 IRF322 IRF323 Units
VDS Drain - Source Voltage CD 400 350 400 350 V
VDGR Drain - Gate Voltage IRGS = 1 Mil) CD 400 350 400 350 V
. ID @ T C = 25°C Continuous Drain Current 3.0 3.0 2.5 2.5 A
ID@TC - 100°C Continuous Drain Current 2.0 2.0 1.5 1.5 A
IDM Pulsed Drain Current @ 12 12 10 10 A
VGS Gate - Source Voltage ±20 V
PD@TC-25°C Max. Power Dissipation 40 ISee Fig. 14) W
linear Derating' Factor 0.32 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig,. 15 and 16) L = 100~H A
12 I 12 i 10 i 10
TJ '. Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
lead Temperature 300 10.063 in. 11.6mm) from case for 105) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage IRF320
IRF322
400 - - V VGS = OV
IRF321
IRF323
350 - - V ID = 250~A
V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VDS = VGS' ID = 250~A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS - -20V
IDSS Zero Gate Voltage Drain Current - - 250 ~A VDS = Max. Rating, VGS = OV
ALL
- - 1000 ~A VDS = Max. Rating x 0.8, VGS = OV, T C = 125°C
IDlon) On-State Drain Current @ IRF320
IRF321
3.0 - - A
V DS >IDlon ) x RDSlon) max.' V GS = 10V
IRF322
2.5 - - A
IRF323
ROSlon) Static Drain-Source On-State IRF320
Resistance ® IRF321
- 1.5 1.8 11

IRF322
VGS = 10V, ID = 1.5A
- 1.8 2.5 11
IRF323
gfs Forward Transconductance @ ALL 1.0 2.0 - S 1tJ) VDS >IDlon) x RDS(on) max.' ID - 1.5A
Ciss Input Capacitance ALL - 450 600 pF
VGS = OV, VDS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 100 200 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 20 40 pF
td!on) Turn-On Delay Time ALL - 20 40 ns V DD = 0.5BV DSS ,I D = 1.5A,ZO = 5011
tr Rise Time ALL - 25 50 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 25 50 ns
Qg Total Gate Charge
ALL - 12 15 nC
V GS = 10V, ID = 4.0A, V DS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 6.0 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 6.0 - nC

LD Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-ta-Ambient Free Air Operation

0-118
 IRF320, IRF321, IRF322, IRF323 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF320 Modified MOSFET symbol
IBody Diodel IRF321
- - 3.0 A
showing the integral
IRF322 reverse P-N junction rectifier.

~
IRF323
- - 2.5 A

ISM Pulse Source Current IRF320

IBody DiodeJ @ IRF321
- - 12 A

IRF322
IRF323 - - 10 A

VSD Diode Forward Voltage @ IRF320

IRF321
- - 1.6 V TC = 25·C, IS = 3.0A, VGS = OV
IRF322
IRF323
- - 1.5 V TC = 25·C, IS = 2.5A, VGS = OV
trr Reverse Recovery Time ALL - 450 - ns T J - 150·C, IF - 3.0A, dlF/dt= 100AII's
ORR Reverse Recovered Charge ALL - 3.1 - I'C T J = 150·C, IF = 3.0A, dlF/dt - 100A/!,s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + lOo

<DTJ = 25·C to 150·C. @PulseTest: Pulse width .. 300I'S, Duty Cycle .. 2% @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

13
0:
~
1~(
~J5~ - 80~1 PULSE TEST f--
I-- 80
I--
~s PULtETES~ I
VOS> 1010n) x ROSlon) max.
I I

I.
~
/I
rJl

i
5
0:
~
1/
VGS Jov ,.1
0:
a
z 2 J J
:;;:
0:
!. 4.5V
TJ • 125°C /I
TJ~250L "'---.. J,~.
Q

E V'
"'---.. VI
TJ ·-55 OC......
l 4.0V ~ rtJ
'r ~ %.: V
12 16 20
Vas, ORAIN·T0-50URCE VOLTAGE IVOLTSJ VGS, GATE·TO·SOURCE VOLTAGE (VOLTSI

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

50
OPERATION IN THIS
10V, 6.0V AREA IS LIMITED
J. 20
80 PULtETEJT

u;
10
IRF320,l

IRF322,3
- BY ROSlon)
~. r- to- r-
5.~V w
~
'"'
5
f-
IRF320,l
"'
,~,
10#.
Z IRF322,3
W 110hL

"' ....
0:
0:

VG ' 5 f ..,
:::0
1.0
~,.
1
z
:;;:
0:
.II~·I·
4.5V
'"
.P
0.5
,
I-- TC' 250C
0.2 I-- TJ' 150 0C MAX.
,", l'o~.
I-- RthJC = 3.12 KIW
O. 1 ~SINGLE PULSE IRF321, ~,., IO~~
II
DC
4'rv IRF320,2

100 200 300 1.0 10 20 50 100 2QO 500

VOS, ORAIN·T0-50URCE VOLTAGE IVOLTS)
VDS, DRAIN·T0-50URCE VOLTAGE IVOLTS)

Fig. 3 - Typical Saturation Characteristics Fig.4 - Maximum Safe Operating Area

0-119
IRF320, IRF321, IRF322, IRF323 Devices

!E
w
0;
Z
<
:;!:;: 1.0
wz
>::> 0= O.S
t; ffi 0.5 NOTES:
:f~
fii
.... w
wu 1-6.2
FUL
-
~:i 0.2
1-0.1
~~ I"'" _
~l!! 0.1 FO'OS
"'0<.... f-0.02 i-= i;;o~
~2~
z.il!! O.OS
Uw ~0.01 f- ~~ 1. DUTY FACTOR. 0 = :~
2%
~ ... SINGLE PULSE (TRANSIENT
E 0.02
i"'""T THERMAL IMPEDANCE) 2. PER UNIT BASE = R,hJC = 3.12 OEG. CIW.
U
3. TJM - TC.~ POM Z'hJC(')'
~ 0.01 I 111111 I I
lO-S 10-3 2 S 10-2 2 S 10-1 1.0 10
'I, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to·Case Vs. Pulse Duration

r- 801.puJsETE1T I I
I I I I
r- VOS> 10(on) x ROS(on) max.

~ Tr 2S OC
.....-:
'~" 4 TJ= ·SSOC-
= ::;;.--

, ~ i""""" :-150 C'-

w
I-'"!'" TJ 0
"
e
::>
'"z
8
!
~
V
V
,
L
....... I"""
....... ~ - TJ = 2SOC

T) 12S!C- -
~

if~ ..:,. ~-
2
I-
;i I-TJ = ISOOC
I
Ii ~ ill
IT I ~
TJ = 250 C
1.0
I
o 1
10, DRAIN CURRENT (AMPERES) VSD,SOURCHO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25
1/
/
W
<.0
< w
(.) 1.8
~
~
1.15
>
z ~
~
~
/
~ ~
o
~a 1.05 V '"
z
0 1.4
/
.
0
Ww ww
".. ~ /
UN
"'N
:::;
w< ~~
~I ~ :gil!!
/
~~ d.9S ./ ~~ 1.0
",.
~ ~co /
~
c

~
~
0.85 I
'"
0.6
./
, ,/ YGS" 10V
ID,"1.5A,-
-

0.75 0.2
·40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE IOC) TJ, JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Tamperature
0-120
 IRF320, IRF321, IRF322, IRF323 Devices
1000

V~S =a I
20

Ciss
I f ~ 1 MH~ .1 J
= Cgo + Cgd. Cds SHORTEO_
800 0;
:;
\ Crss = Cgd
Cgo Cgd - ~ 15
VOS = 80V

~ "'- ~~
~
~

w 600
1\ Co.. = Cds + Cgs + Cgd

"'Cds + Cgd -
w
to
«
:;
~os= ~oov
r---.-

~
-
Vos = 320V
'-'
z
« \ ..... I <>
>
~
I-
Ciss ~ 10
U
~
5 400
\ I--
'"=>
<>
'? A W
1 <>

\,
'-'-
:;;
I-
'//
«
to 5 I
>"'
200 to
\ ..........
r- ~ Coss J lo=4A
FOR TEST CIRCUIT r--
......
10
"""- ....
20
C'SS

30 40
/ 8
yE FliURE 18

12
1

16 • 20
50
VDS. DRAIN·TO·SOU RCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

/
RDS(on) MEASURED WITH CURRENT PULSE OF
2.01's DURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 I's PULSE IS MINIMAL.)

,If/
V
VGS=l~
VGS = 20V
-- ......... .........
"""- """- ~
......
r--...r-..,
......... r--.....~
IRF320.321

----
..;
i-""'" IRF322. 323.... ~~

~ ,
a
10 12 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) Tc. CASE T~MPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35 '\
~
l-
I-
«
~
z
<>
>=
~
Bi
0
30

25

20
'" I\.
'\
"\
'"
~ 15
~
,p
10 '\
20 40 80
Tc. CASE TEMPERATURE IOC)

Fig. 14 - Power Vs. Temperature Derating Curve

D-121
100
"
120
"\
140
IRF320, IRF321, IRF322, IRF323 Devices

VARY. p TO OBTAIN
REQUIRED PEAK 'L

TO OUT
VGs=!.r"'L
'L _---<>-----4........w.--'
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIEO 10 RL
Vi
PULSE
GENERATOR O.U.T.
r-----.,
I
50n I -o---+TO SCOPE
I O.DIn
I I 50n HIGH FREQUENCY
_ __ .J
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

,----00 +VOS
(ISOLATED
SUPPLY)

D~1.5mA - IG
\r"-'-'V'V,,-"U -VOS
10
CURRENT ":'" CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-122
 PO-9.302

INTERNATIONAL RECTIFIER II\~R I

HEXFET® TRANSISTORS IRF330
IRF331
N-Channel IRF332
IRF333

400 Volt, 1.0 Ohm HEXFET Features:

• Fast Switching
The HEXFET® technology is the key to International Rectifier's
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve • Ease of Paralleling
very low on-state resistance combined with high transconductance
and great device ruggedness.
• No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well established
advantages of MOSFETs such as voltage control, freedom from
Product Summary
second breakdown, very fast switching, ease of paralleling, and
Part Number VOS ROS(on) ID
temperature stability of the electrical parameters.
IRF330 400V 1.0n 5.5A
They are well suited for applications such as switching power
IRF331 350V 1.0n 5.5A
supplies, motor controls, inverters, choppers, audio amplifiers,
and high energy pulse circuits. IRF332 400V 1.5n 4.5A
IRF333 350V 1.5n 4.5A

22.2210.875)
CASE STYLE AND DIMENSIONS 3 42 MAX. OIA. 11.43 0.450
10.135) MA~X 3 1.50

~
T =+LANE
ttEATING

6~! m'ra~! OIL.J 10.1610.40) MIN.

TWO PLACES TWO PLACES

4.08 0.161 OIA

.64 .151) .
TWO PLACES

DRAIN
, 1 ICASE)

1
'1.09 (0.043)
MAX. DIA.
11.1710.44011
14-_ _ 39.95 (1.573) ~
t MEASURED AT SEATING PLANE
MAX.
Conforms to JEDEC Outline TO·204AA (TO·31
ACTUAL SIZE Dimensions in Millimeters and (lnchesl

0-123
IRF330, IRF331, IRF332, IRF333 Devices

Absolute Maximum Ratings

Parameter IRF330 IRF331 IRF332 IRF333 Units
VOS Drain - Source Voltage CD 400 350 400 350 V
VOGR Orain - Gate Voltage (RGS ~ 1 Mil) CD 400 350 400 350 V
10@TC ~ 25°C Continuous Drain Current 5.5 5.5 4.5 4.5 A
10@TC - 100·C Continuous Drain Current 3.5 3.5 3.0 3.0 A
10M Pulsed Drain Current @ 22 22 18 18 A
VGS Gate - Source Voltage ±20 V
PO@TC ~ 25·C Max. Power Dissipation 75 (See Fig. 14) W
linear Derating Factor 0.6 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15and 16) L ~ IOOI'H
A
22 I 22 I 18 I 18
TJ Operating Junction and
-55to 150 ·C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF330
400 - - V VGS ~ OV
IRF332
IRF331
IRF333
350 - - V 10 ~ 25Ol'A

V GS(thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS ~ VGS' 10 ~ 250l'A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS ~ -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 i<A VOS ~ Max. Rating, VGS ~ OV
- - 1000 I'A VOS - Max. Rating x 0.8, VGS - OV, TC - 125·C
10(on) On-State Drain Current ® IRF330
5.5 - - A
IRF331
V OS >10(on) x ROS(on) max.' V GS ~ 10V
IRF332
4.5 - - A
IRF333
ROS(on) Static Drain-Source On-State IRF330
Resistance ® IRF331
- 0.8 1.0 II
VGS ~ lOY, 10 ~ 3.0A
IRF332
IRF333
- 1.0 1.5 II

gfs Forward Transconductance ® ALL 3.0 4.0 - SUJ) VOS >10(on) x ROS(on) max.' 10 - 3.0A
Ciss Input Capacitance ALL - 700 900 pF
VGS ~ OV, VOS ~ 25V, f ~ 1.0 MHz
Coss Output Capacitance ALL - 150 300 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 40 80 pF
tdlonl Turn-On Delay Time ALL - - 30 ns VOO = 175V, 10 ~ 3.0A, Zo - 15!l
tr Rise Time ALL - - 35 ns See Fig. 17
td(off) Turn-Off Oelay Time ALL - - 55 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 35 ns
Qg Total Gate Charge V GS ~ 10V, 10 ~ 7.0A, VOS - 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 18 30 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Clgs Gate-Source Charge ALL - 11 - nC

Qgd Gate-Orain ("Miller") Charge ALL - 7.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-124
 IRF330, IRF331, IRF332, IRF333 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF330 Modified MOSFET symbol
(Body Diodel IRF331
- - 5.5 A
showing the integral
reverse P-N junction rectifier.
IRF332
- -

~
4.5 A
IRF333
Pulse Source Current IRF330
ISM
(Body Diodel@ IRF331 - - 22 A

IRF332
IRF333
- - 18 A

VSD Diode Forward Voltage @ IRF330

IRF331
- - 1.6 V TC = 25·C,IS = 5.5A, VGS = OV
IRF332
IRF333 - - 1.5 V TC = 25·C,IS = 4.5A, VGS = OV
t" Reverse Recovery Time ALL - 600 - ns T J - 150·C, IF = 5.5A, dlF/dt = 1 OOA/~s
QRR Reverse Recovered Charge ALL - 4.0 - ~C T J = 150·C, IF - 5. SA, dlF'dt = 1 OOAI ~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + lO'
<DTJ = 25·C to 150·C. ~Pulse Test: Pulse width" 300~s, Duty Cycle" 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

I~J
'j
...
80 ~s PULSE TEST

VG!" 5.L
80.,lpUlSE TEiT
,
VOS> 10(on) x ROS(on) max.
.. -

5.0V
TJ" +125 oC

TJ"250b~-""""'r'-
TJ"-550C~ IJ
4.5V
rtJ
I J fl
4'jV
Lh
50 100 ISO 200 250 300
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
50 AREA IS LIMITED

.t .l J J'/
10~Jfv BY ROS(on)
80~sPULSETEST
....- ~VGS"5.0V- ~
20
IRF330,l
""'"!::
13 -iRi332j3
~
!f/ 0:: 10

J i -IRF330,l lOp.

'I ~
.
0::
0::
:::>
,-IRF332,3

, ~" , TIt
1~ 4.5V- I--
z
~ ,,' 11~.1-

J' Q

E
1.0
f - TC=25C
0.5
f:: TJ " 15QoC MAX. 10m.

l f-RthJC" 1.67 K/W

ppW, I " 1~~li
II
4.0V- I--

10
0.2

O. 1
HI~GL~

1.0
" "I 10 20 50
IRF331,3
IIII
IRF330,2

100
I
::::::::
200
,C

500
ln
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) V OS' ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-125
IRF330, IRF331, IRF332, IRF333 Devices

....
z
w
0;
z
<
0:_
........ 1.0
wz
>'" 0- O.S
ti ffi 0.5 NOTES:
$~ ~b.2
~:i 0.2
.......
!::::!ffi -0.1
:;;0,.,. FlJL
~~ 0.1
0: ....
O.OS
~2~
=~
0< 1--0.02-
z_~ O.OS
<>w ~~1::' SINGLE PULSE (TRANSIENT 1. OUTY FACTOR. 0= :~
}~ mRMA~ I~PEOtNfE\ 1 1 2. PER UNIT BASE = R,hJC = 1.67 OEG. C/W.
~ 0.02
3. TJM - TC = POM Z'hJC(tI·
~ 0.01 III I II
10-S 10-2 10-1 1.0 10
'I. SQUARE WAVE PULSE OURATION (SECONOS)
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

10
I

TJ = 25 0 C

~
1..00""'" C::TJ = 150 0 C

t::: -
TJ=-SSOC-
/'
r- TJ = 2S OC ..oI!II

/. r- J //

-
T}- 125 C_

~ '/ j.---
ISOOC I
....... TJ
Ii V ~

Ilf vos> 10(on) x ROS(on) max. I

I I TJ = 2SOC
to"'~lSETEr
1.0 11 J
10 o
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w
'"< w
<> .LV
~ 1.1 S z 1.8
>
<
V
z
~
o
o
~a 1.0 S
Ww
".,.
V
",..
'" ~
iii0:
z
08 1.4
Ww
V
LV
O:N
/ <>N
/
"':::;
w< ./ "'0<....
0: -

~~
"'0 i..,...o-" ~
""",
00:
.... 0
/~
~!5. 0.9 z~ 1.0
....o
Sv
;;;;
0: V
""o~ 0

.;
[!:l
0.8 S
~
.
oS
c
0.6
'/
,/ VGS = 10V

10 - 2.0A
~ /' -I .1
0.7 5 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATURE (OC) TJ• JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-126
 IRF330, IRF331, IRF332, IRF333 Devices
2000
tGs =J 20

1-1 MHz
I I I I I
1600 Ciss • Cgs + Cgd. Cds SHORTED I - - on .,1 J.
CIIS • Cgd
r--
':;
0 15
VOS=80V,,--

,-
,.-~
Cgs Cgd
2: VpS = 2~OV '-
w
~
Coss = Cds + Cgs + Cgd '"« Vos = 320V,
~ 1200 I--

,.
"'Cds + Cgd ':;
'-'
~
0
z >
«
t- w
a: 10
~
o; '-'
;!t
~ 800
Ciss
-,...... .1-- '"
0

'" 4
u"
\ 0
>-;-
w
t-
...d ".

\ ~L
«
'"<h 5
400
I
~
>'" 10 = 7A
~ FOR TEST CI RCUIT -
I-- V SIEE FliuRE Ii

10 20 30 40 50 16 24 32 40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
10

in

ew'"
%

u
Z

~~ 2
VGS' I0 v.
/ VGS=20V-
~
~
ji'
----- -r-..
z
~ 6

~
o
w
'-'
a: a:
a:
'"
o
"1 /~ '"
'-' r--..... I RF330. 331

-
o z 4
;;:
--r-..~r--..
~
;;:
a:
o
I
....- a:
o
E
I RF332. 333 ........::"
~~

,
c

~
o
-........
'"o
a: ROSlon) MEASURED WITH CURRENT PULSE OF
2.0 ~s ~URATION. INITIAL TJ = 250C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.)
o
10 15 20 25 30 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE IOC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig_ 13 - Maximum Drain Current Vs_ Case Temperature
80

70
- I\.
'\
60 ~
~
t-
« '\I\..
~ 50
z
0
;::
;!t 40 '\
iii
c
a:
~ 30
'\
'"
...
0

.P 20

10 ~
'~
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-127
IRF330, IRF331, IRF332, IRF333 Devices

VARY tp TO OBTAIN
REOUIREO PEAK Il

VGs·R I l ."- - - 6 - - -......-"I',;.-...J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

Vo
-..----~TO SCOPE

Fig. 17 - Switching Time Test Circuit

.----0 +VOS
(lSOlATEO
SUPPLY)

o~1.5mA - --"'v'v-_-'V'v,,___'O -VOS

IG ID
CURRENT "':" CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-128
 PO-U71

INTERNATIONAL RECTIFIER IIC~R I

HEXFET® TRANSISTORS IRF34D
N-CHANNEL
IRF341
POWER MOSFETs IRF342
IRF343
400 Volt, 0.55 Ohm HEXFET Features:
The H EXFE-r' technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing
of the HEXFET design achieve very low on-state
• Ease of Paralleling
resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as volt- Product Summary
age control, freedom from second breakdown, very
Part Number VOS ROS(on) 10
fast switching, ease of paralleling, and temperature
stability of the electrical parameters. IRF340 400V O.55n lOA
IRF341 350V O.55n lOA
They are well suited for applications such as switch-
ing powersupplies, motor controls, inverters, chop- IRF342 400V O.BOn B.OA
pers, audio amplifiers, and high energy pulse circuits. IRF343 350V O.BOn B.OA

22.22 {O.8751
CASE STYLE AND DIMENSIONS
{0.13Ix~MAX.DIA~.
~
SEATING
T PlANE

~·~l m·ml DIL-I 10.16 {D.4DI MIN.

nVD PLACES TWO PLACES

4.08 0.161 DIA

.84 0.51 .
TWO PLACES

J ff~«
".09 (0.043)
DRAIN
{CASEI

SOURCE
MAX.DIA.
39.96 (1.573)
MAX.
la~m::~!t
t MEASURED AT SEATING PLANE
Conforms to JEDEC Outline TO-204M (TO-3)
ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-129
IRF340, IRF341, IRF342, IRF343 Devices

Absolute Maximum Ratings

Parameter IRF340 IRF341 IRF342 IRF343 Units
VOS Orain - Source Voltage <D 400 350 400 350 V
VOGR Orain - Gate Voltage (RGS = 1 Mill <D 400 350 400 350 V
10@TC - 25°C Continuous Drain Current 10 10 8.0 8.0 A
10@TC - 100°C Continuous Drain Current 6.0 6.0 5.0 5.0 A
10M Pulsed Drain Current @ 40 40 32 32 A
VGS Gate - Source Voltage ±20 V
PO@TC - 25°C Max. Power Dissipation 125 (See Fig. 14) W
Linear Derating Factor 1.0 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L - 100MH
A
40 I 40 I 32 I 32
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range
lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF340
IRF342
400 - - V VGS = OV
IRF341
IRF343
350 - - V 10 = 250~A
V GS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS. 10 = 250~A
IGSS Gate-Source leakage Forward All - - 100 nA VGS = 20V
IGSS Gate-Source Leak~ge Reverse All - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
All
- - 250 MA VOS = Max. Rating. VGS = OV
- - 1000 ~A VOS = Max. Rating x 0.8, VGS = OV, TC = 125°C
10(on) On-State Drain Current ~ IRF340
IRF341
10 - - A
V OS ) 10(on) x ROS(on) max.' V GS = 10V
IRF342
IRF343
8.0 - - A

ROS(on) Static Drain-Source On-State IRF340

Resistance ® IRF341
- 0.47 0.55 !l
IRF342
VGS = 10V,I0 = 5.0A
IRF343
- 0.68 0.80 !l

Qfs Forward Transconductance ® All 4.0 7.0 - S(1lI VOS ) 10(on) x ROS(on) max.' 10 = 5.0A
Ciss Input Capacitance All - 1250 1600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance All - 300 450 pF
See Fig. 10
erss Reverse Transfer Capacitance All - 80 150 pF
td(on) Turn-On Delay Time All - 17 35 ns VOO = 175V, 10 = 5.0A, Zo = 4.7!l
tr Rise Time All - 5.0 15 ns See Fig. 17
td(off) Turn-Off Oelay Time All - 45 90 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 16 35 ns
Qg Total Gate Charge
All - 41 60 nC
V GS = 10V, 10 = 12A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
QgS Gate-Source Charge All - 18 - nC

Qgd Gate-Drain ("Miller") Charge All - 23 - nC

lO Internal Drain Inductance All - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance All - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-130
 IRF340, IRF341, IRF342, IRF343 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF340 Modified MOSFET symbol
(Body Diode) IRF341 - - 10 A
showing the integral
IRF342 reverse P-N junction rectifier.

42l
IRF343
- - 8.0 A

ISM Pulse Source Current IRF340

(Body Diode) @ IRF341 - - 40 A

IRF342
IRF343 - - 32 A

VSD Diode Forward Voltage @ IRF340

IRF341
- - 2.0 V TC = 25°C, IS = lOA, VGS = OV
IRF342
IRF343 - - 1.9 V TC = 25°C, IS = a.OA, VGS = OV
trr Reverse Recovery Time ALL - 800 - ns T J - 150°C, IF - lOA, dlF/dt - 1OOAl~s
ORR Reverse Recovered Charge ALL - 5.7 - ~C T J - 150°C, IF - 10A,dlF/dt - 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

CDTJ = 25°C to 150°C. @PulseTest: Pulse width .. 300~s, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

25 25

,,.,10VL:~v /I I
80~. PU LSE TEST

J
VI
TJ.!55 OC
7~
V

20 20
I
TJ = 250 C
"--...
'-..,
iii
""~
iii
""
I
TJ = 125 0 C 'I
~
'j
,I
:& :&
5 15 515
....
z
w
""""
'"z
<.:I
, J
VGS = BV
....
z
w

a""""
z 10
r- 80 '" PU LSE TEST
J J J
VOS > 10(on) x ROS(on) max.

,
10
;;:
""
c I ~
c J
§ §
L
5~
~
4~ Jj~
20 40 60 BO 100 10
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
25
AREA IS LlMITEO
_81",pu~sETJT 50 r- IRF340,1 ~ BY ROS on
~ j2' r
iii
20
10V
20
11 F3
~ ... .< "- ~L"
""~
:&
5 15
9V- f--
BV,
...... i"
5
10

;=
I RF340, 1

I RF342, 3 " L.... ~ 10 ~s

100~s

....
~ ....... ~ ~V
.... ,. I'\.
~ ... .... WI-
""""'"
<.:I
Z 10
~ ~ ~BV- t-- a:
::>
'"';;:z ,,-'
~,

,
;;: 1101~s
""c
§
, .J ~
l-'
"" i GS =5 V - t--
a:
c
!?
1.0

0.5
f= TC = 25°C
t: TJ - 150°C MAX .
e- RthJC = 1.0 K/W
100 ms

~ I ...... SINGLE PULSE IRF341,3 ICI

0.2
/ jv
10
0.1
1.0
'11 111111
III
10 20 50
IIII

:~WO/
I

100
-
200
II
500
Vas, ORAIN·TO.sOURCE VOLTAGE (VOLTS) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-131
IRF340, IRF341, IRF342, IRF343 Devices

!iwO
in
I I II
z
<
0:_
........ 1.0 I I II
wz
>::0
D' 0.5
ti ffi 0.5 NOTES:
~~ -~
w",
fa:i
~ffi 1--0.1
0.2
0.2
.... :;;;0",
HL.lL
~2~
..... 0..
;!!!l 0.1 t::=0.05
0: .....
0< r--0.02
~ffi 0.05
~"
,c ....
~0.01 SINGLE PULSE (TRANSIENT
iHiiii,'MPjDiNCEI I
1. DUTY FACTOR. 0 = *"
2 0.02 2. PER UNIT BASE = R'hJC = 1.0 DEG. CIW.
'" 3. TJM - TC = PDM Z'hJC(')'
~ 0.01 11 III IJ I
10-5 10-3 10-2 10-1 1.0 10
'1. S(lUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case V,. Pulse Duration

15

I--J", PU1E TEJ

If
20
V'DS > I~(on) ~ RDS{~n) m.!. I
'"z
w
ill
12

TJ' _55 0 C
!
:;;
~ 10
{
Ie ....
w ./ fl'i
'"
~ )' TJ = 25 0 C
0:
0:
::0
'"
~ T~
::0 Z
o
2
o
l;l
= 12JoC "
0:
0 TJ =150 0 C

II 1/ W

,
z .......... 1
< '"
0:
W
....
0:
i;;
~ V 0:
<i: - TJ =2JC
E'
i I
10 15 20 25
1.0
o
I
'0. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)
Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w
w
co '" ~
~o 1.15
,. ~ 2.0 ./
V'
> iii0:
....... /
!o
~c 1.0S
........ ...- S
"1_ 1.5 ./
20
/
Ww
O:N
"':::; .."
........ ow
w!::!
"'::0:;;.....
~i ~
V V
0:<

~~
00:
6~ 1.0
./
o
I-;'
0.95
.", ....
Z
- .... / vGs= 10V
2
;;(
0:
;;(
0:
o ,.- 'D-5.5A - '---

c 0.85 c 0.5
~ ~
a

iii 0:

0.75 o
-40 40 80 120 160 -40 40 80 120 160
Tj, JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE lOCI

Fig. 8 - Breakdown Voltage Vs_ Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-132
 IRF340, IRF341, IRF342, IRF343 Devices
2000
Ci,. = Cgs + Cgd. Cd, SHORTEO.! J 20
_ c,.. = Cgd _ VGS=oV
CgsCgd f=IMHz

1600
~ Coss = Cd,+ Cgs+ Cgd
"'Cd,+ Cgd in
!::;

\ " r--... r-... I

C:,.
~ 15
w

;o'"
VOS·8o~.~
I
VOS·200V
I
A~
\, >
w
~ 10
, I I~
VDS=320~~
~
~
~
:::>
o

\ :;:;'"
""
o

!;;:
I
400
""- ~
........
~ """""
......... _Crss
'"<i>
> '"
I
/
10 = 12A
FOR TEST CIRCUIT
SEE FIGr E 18 -
1
-

10 15 20 25 30 35 40 45 50 20 40 60 80
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nCI

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

10
1.6
in
:E
"
£!
w
'-'
z
«
RDS(on) MEASURED WITH CURRENT PULSE OF
2.0I',OURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 1" PULSE IS MINIMALl
II
VGS~lOVI /
" .....
..........
~
........
..........
'"
l;; 1.2
~

~=20V
Hi
~

""
'"z ................. 100...
0
~ 6 IRF340.341- -

l/
w

IRF34~
'-' I-
'"
:::>
0 0.8
Z
~ ......
..,'z"
0
V '"
:::>
'-'
z 4
"~"".~r\..

-
./
<1
'"co -'
<1
'"'" ",,\
12
~ 0.4
co "~
'"
'\,
10 20 30 40
o
25 50 15 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig_ 13 - Maximum Drain Current V,. Case Temperature

140

120 - -
~
~IOD
" ,
~
z
co
~ 80
" ,
ili
c;
'"
w 60
;::
~
rP 40
"" ~

20
" ", r'\.

20 40 60 80 100 120 140

TC. CASE TEMPERATURE (DC)

Fig. 14 - Power V,. Temperature Derating Curve

0-133
IRF340, IRF341, IRF342, IRF343 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGs.IF=L ",D~UT--..• .--'9

I L _ - - 6 - - -....JIi\i_~

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

175V
ADJUST RL TO OBTAIN 33!l
SPECIFIED 10
VOS

O.U.T.
O-li----O----.lI............
Ii;ULSE --
GENERATOR

I :g~CE
IMPEDANCE
n I
L ___ J

Fig. 17 - Switching Time Test Circuit

......- - 0 0 +VOS
(ISOLATED
SUPPL Y)

SAME TYPE
AS OUT
12V
BATTERY

r=-TI.
o
-
5 mA
OUT

IG 10
CURRENT '::" CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-134
 PO-9.304

INTERNATIONAL RECTIFIER IICiR I

HEXFET® TRANSISTORS IRF35D
IRF35~

N-Channel IRF352
IRF353

400 Volt, 0.3 Ohm HEXFET Features:

The HEXFET«!) technology is the key to International Rectifier's • Fast Switching
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve
very low on-state resistance combined with high transconductance
• Ease of Paralleling
and great device ruggedness. • No Second Breakdown
The HEXFET transistors also feature all of the well established
• Excellent Temperature Stability
advantages of MOSFETs such as voltage control, freedom from Product Summary
second breakdown, very fast switching, ease of paralleling, and
temperature stability of the electrical parameters. Part
Number VOS ROS(on) 10
They are well suited for applications such as switching power tRF350 400V O.3n 15A
supplies, motor controls, inverters, choppers, audio amplifiers,
IRF351 350V O.3n 15A
and high energy pulse circuits.
IRF352 400V O.4n 13A
IRF353 350V O.4n 13A

22.2210.S75)
CASE STYLE AND DIMENSIONS 3.42'HI Im~1
MAX.OIA.

10"3yX~~'.
SEATING
22.22 (0.875)
MAX. DIA.
T PLANE

~.~ m'~1 OIA.-I1-- 10.1610.40) MIN.

nNO PLACES lWO PLACES

H m· B
s 16
. 4 .16 01A.
lWO PLACES

DRAIN
ICASE)

1'-1.09 (0.043)
SOURCE

MAX. DIA.
14-_ _ 39.95 (1.573) 1~:~~ m::;~lt
t MEASURED AT SEATING PLANE
MAX.
Conforms to JEDEC Outline TO-204AA (TO-3)
ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-135
IRF350, IRF351, IRF352, IRF353 Devices

Absolute Maximum Ratings

Parameter IRF350 IRF351 IRF352 IRF353 Units
VOS Drain - Source Voltage (j) 400 350 400 350 V
VOGR Drain - Gate Voltage (RGS - 1 MDl (j) 400 350 400 350 V
10@TC - 25·C Continuous Drain Current 15 15 13 13 A
10@TC= 100·C Continuous Drain Current 9.0 9.0 8.0 8.0 A
10M Pulsed Drain Current @ 60 60 52 52 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25·C Max. Power Oi.ssipation 150 (See Fig. 141 W
linear Derating Factor 1.2 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L - 1OO~H
A
60 I 60 I 52 I 52
TJ Operating Junction and
-55to 150 ·C
Tstg Storage Temperature Range
Le~d Temperature 300 10.063 in.I1.6mm) from case for lOs) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions

BVOSS Drain - Source Breakdown Voltage IRF350

IRF352
400 - - V VGS = OV

IRF351
IRF353
350 - - V 10 = 250~A

V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 = 250~A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = ·20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ~A VOS = Max. Rating, VGS - OV
- - 1000 ~A VOS = Max. RatingxO.8, VGS = OV, TC = 125·C
On-State Drain Current ® IRF350
1010n)
IRF351
15 - - A
VOS ) 10(on) x ROSlon) max.' V GS - 10V
IRF352
IRF353
13 - - A

ROS(on) Static Drain-Source On-State IRF350

Resistance ® IRF351 - 0.25 0.3 0
VGS = 10V, 10 = 8.0A
IRF352
IRF353 - 0.3 0.4 0

9fs Forward Transconductance ® ALL 8.0 10 - S(Ol VOS ) 1010n) x ROSlon) max.' 10 ,8.0A
Cjss Input Capacitance ALL - 2000 3000 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 400 600 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 100 200 pF
tdlonl Turn-On Delay Time ALL - - 35 ns VOO = 180V,I 0 - B.OA, Zo = 4.70
tr Rise Time ALL - - 65 ns See Fig. 17
tdloffl Turn-Off Delay Time ALL - - 150 ns IMOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 75 ns
Qg Total Gate Charge
ALL - 79 120 nC V GS = 10V, 10 - 18A, VOS - 0.8 Max. Rating.
IGate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
QgS Gate-Source Charge ALL - 38 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 41 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin. 6 mh't
10.25 in.) from header
and source bonding
pad.
-$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to· Sink Mounting surface flat. smooth. and greased.
'RthJA Junction-to-Ambient Free Air Operation

0-136
 IRF350, IRF351, IRF352, IRF353 Devices

Source-Drain Diode Ratings

-
and Characteristics
IS Continuous Source Current IRF350 Modified MOSFET symbol
IBody Diode) IRF351 - - 15 A
showing the integral
IRF352 reverse P~N junction rectifier.
- - 13 A

~
IRF353
ISM Pulse Source Current IRF350
- - 60 A
IBody Diode) ® IRF351
IRF352
IRF353
- - 52 A

VSD Diode Forward Voltage ® IRF350

- - 1.6 V TC = 25°C, IS = lSA, VGS = OV
IRF351
IRF352
JRF353
- - 1.5 V TC = 25°C, IS = 13A, VGS = OV

trr Reverse Recovery Time ALL - 1000 - ns T J = lS0oC, IF - 15A, dlF/dt - 100A/"s
ORR Reverse Recovered Charge ALL - 6.6 - "C T J - 150°C, IF = 15A, dlF/dt - 100A/"s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'
<DTJ = 25°Cto 150°C. ®Pulse Test: Pulse width .. 300,,5, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

12

20
10 t- ao 1. PULSE ~EST
6.OV 80 pS PU LSE TEST I I
I-- VOS> 1010n) x ROSlon) max.

16 VdS)5V

I
:;;
~ 12
'1

I
f-
.~ TJ=+125 0C,
I
~
il
z
T
,l
TJ=2S oC,

TJ=-S50C,
........
"j 1/
'/
~
Q

E 4 T r-. l/
4.bv 1///
3.kv ./.V. . .
50 100 ISO 200 250 300
VoS, ORAIN·TO·SOURCE VOLTAGE IVOLTS) VGS. GATE·TO·SOURCE VOLTAGE IVOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
10
f= IRF35o, 1'= OPERATION IN HI AREA IS liMITED

VGS=~V
aL.puJsETEJ -
50
r-: R~3S2i 3
BY ROSIO!")1

'. ...
I?r
,.
20 I-- iRJ3so 1 l, .
jol~s
ioiJ~s
Ii
........ 4.5V
i:;;
~
10 I-- IRF352, 3 I'
1 ms

j '/ ~
'"
'" I.... lOms
VI i3
z
ms
"
100
~
J 1.0

r.l
c
6 ~ TC-2S oC
lV O.S f::
TJ = ISo oC MAX.
r-- R,hJC = 0.B3 K/W IRF351.3 'h{
j 0.2 I-ISI~GLf pnSIEl1
11111 I
IRF350,2 II
r 3f
0.1
1.0
IIIII
10 20 50
IIIII I
100 200
II
SOD
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, DRAIN-TO·SOURCE VOLTAGE IVOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-137
IRF350, IRF351, IRF352, IRF353 Devices

D· O.S
NOTES.
f-~.2
0.1 HLJL
~2~
'--I"'" III
FO.OS

-
r-- 0.02
r--0.01 1. DUTY FACTOR, D· ~
SINGLE PULSE (TRANSIENT
T7E~~AILI'rrED~NCIE) I
2. PER UNIT BASE' RthJC' 0.B3 DEG. C/W.
3. TJM - TC' PDM ZthJc(t).
1111111
10-4 10-3 2 10-2 2 10-1 1.0 10
tl,SDUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance. Junction-to-Case Vs. Pulse Duration

20
I I.~

- f- TJ - isoc ~
~ 10 2 TJ·1S0oC
16
in
a'i TJ = -55°C ~
~
.........-
J
ai TJ - 2Soc
I

--
§ !zW
,/ I.--- TJ' +1250C
W
u
z
12 ..... '"'" 1/
«
t; V;V I-- '"uz -TJ'IS~
I
'"cz i j/ V ~ 10
8 c
~
~
....
R /" w
'"
'"
W
> TJ - 2SoC

, "V W
~ I
VDS> 'D(on) x RDS(on) max. - '"
I i '"
ar
I
PU
11"+
LISE TESf
E

1.0
12 16 20 o
'0, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig_ 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.2

W
to
«
~ 1.15
w
u
z I.B
.,v
> ."
«
t;; V
~
o
'"wwC
:! 1.05
,.,..,.,- --- [Ii
'"z_
co 1.4 ./
V
L

.,., V
WW
"'N
"'::;
We(
,/ V uN
"'::;
"'« /'
0::;;
;q~
"'0 ./
"/,,,
00 /V'
~ ~ 0.95 ~~ 1.0
..,.c
z
V ;;:
'"0 V
~
c -- c /' VGS·l0V
0
,/
0.B5 0.6 ..... -
~ '"
c
co
'D'S.SA -
>
'"
I I
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE (OC) TJ, JUNCTION TEMPERATURE 10C)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig_ 9 - Normalized On-Resistance Vs. Temperature
0-138
 IRF350, IRF351, IRF352, IRF353 Devices
4000

VG~=
20
0

3200 ~ , I
t= 1 MHz

~
'" 15
)DS =aL '-

t'--- ~ ~
~
V~S =20~V '"'- "-
"
w
~
... 2400 \ i'.. '"<t VOS = 320V
~
......
w

l\ r-..... ~~
u
z I-o-..CiSS '">w
<> u 10

~~
Ciss = Cgs + Cgd. Cds SHORTEO a:

..
~ =>
1600 Crss = Cgd '"
\ ,\..
u 0:>
Cgs Cgd '">;-w
Coss = Cds + Cgs + Cgd
.... ~V
\ ~
«
'" Cds + Cgd to 5
BOO

" i'.. I '~. > "'

to
/ 10 = 18A
FOR TEST CIRCUIT- r--

10
r-. ~
20 30 40 50
V 28 56
SEj FlGjRE 18

84
1

112 140
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE InC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

O.B 20

~
0.7
I
vGS = 10V
II
I/
:J::
16
8
~ 0.6 VGS=20V _ ..........

£
z
~ :--... .... ~r-....
r-'350.351
~ ..........

"
0.5
-IRF352.~ .........
/
z -
'"w~ 0.4
=> II" ..................
'"
0:>
V ..........
~,
'"~
~
l
'"
'"
a:
0.3

0.2
- V
ROSlon) MEASURED WITH CURRENT PULSE OF
2.0 ~s DURATION. INITIAL TJ = 25 0 C. IHEATING
4 ~
,
r\
EFFECT OF 2.0 ~s PULSE IS MINIMAl.l
o
10 20 30 40 50 60 70 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) Tc. CASE TEMPERATURE (OCI

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs_ Case Temperature

140 '\.
"\
120
\.
..........
~

~ 100
"-'-
z
'";;:>= 80
'\
iii
c
a: 60
'\
~
~
~

40
'\.
20
~
'[\
20 40 60 80 100 120 140
TC. CASE TEMPERATU RE lOCI

Fig. 14 - Power Vs. Temperature Derating Curve

0-139
IRF350, IRF351, IRF352, IRF353 Devices

VARY tp TO OBTAIN
REQUIREO PEAK Il

VGS-R

Il+--~)--"""'~"""--'

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL TD OBTAIN
SPECIFIED 10

VDS

r;U~ --
I GENERATOR
-<>...,l;-__O--_--'lJ~ O.U.T.

I ~~~RCE Jl
___ JI
LIMPEDANCE

Fig. 17 - Switching Time Test Circuit

...---0 +VDS
(ISOLATED
SUPPl YI

SAME TYPE
AS OUT

oI]I1.5mA - IG
OUT

,...........--"JVv--<l -v OS
10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-140
 PD-9.323

INTERNATIONAL RECTIFIER II()R I

HEXFET® TRANSISTORS IRF42D

IRF421
N-Channel IRF422
IRF423

500 Volt, 3.0 Ohm HEXFET Features:

The HEXFET® technology is the key to International • Fast Switching
Rectifier's advanced line of power MOS FET transistors. • Low Drive Current
The efficient geometry and unique processing of the
HEXFET design achieve very low on-state resistance • Ease of Paralleling
combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature Part Number VOS ROS(on) 10
stability of the electrical parameters. IRF420 500V 3.0n 2.5A
IRF421 450V 3.0n 2.5A
They are well suited for applications such as switching
power supplies, motor controls, inverters, choppers, IRF422 500V 4.0n 2.0A
audio amplifiers, and high energy pulse circuits. IRF423 450V 4.0n 2.0A

22.2210.875}
CASE STYLE AND DIMENSIONS 342 MAX. DIA. 11.43 0.450}

22.22 (0.875)
MAX. DIA. Tc::rr
"'i"H J:,"""PLANE

ai !i'~:1 OIL.j1-
rwo PLACES
MIN.
10.16 (D.40)
TWO PLACES
26.67
(1.050) MAX
4.08 (O.161) OIA
U4f[T5jj .
TWO PLACES

DRAIN

i '
"1.09 (0.043)
ICASE}

SOURCE

MAX. DIA .
......_ _ 39.95 (1.573)
MAX. t MEASU REO AT SEATING PLANE

ACTUAL SIZE Conform. to JEDEC Outline TO-204AA (TO·31

Dimensions in Inches and (Millimeters)

0-141
IRF420, IRF421, IRF422, IRF423 Devices

Absolute Maximum Ratings

Parameter IRF420 IRF421 IRF422 IRF423 Units
VOS ~rain - Source Voltage <D 500 450 500 450 V
VOGR Orain - Ga~e Voltage IRGS - 1 MOl (l) 500 450 500 450 V
10@TC=25·C Continuous Drain Current 2.5 2.5 2.0 2.0 A
10@TC = 100·C Continuous Drain Current 1.5 1.5 1.0 1.0 A
10M Pulsed Orain Current @ 10 10 8.0 8.0 A
VGS Gate - Source Voltage ±20 V
PO@TC. 25·C Max. Power Dissipation 40 ISee Fig. 14) W
Linear Derating Factor 0.32 ISeeFig.14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = 1OO~H
A
10 I 10 I 8.0 I 8.0
TJ Operating Junction and
-55to 150 ·C
'1"stg Storage Temperature Range
Lead Temperature 300 10.063 in. 11 .6mm) from case for 10s) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions

BVOSS Drain - Source Breakdown Voltage IRF420

500 - - V VGS = OV
IRF422
IRF421
450 - - V 10 = 25Ol'A
IRF423
VGSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 = 250"A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 "A VOS = Max. Rating, VGS - OV
- - 1000 I'A VOS = Max. Rating x 0.8, VGS = OV, TC = 125·C
1010n) On-State Drain Current ® IRF420
2.5 - - A
IRF421
VOS >1010n) x ROSlon) max.' VGS = 10V
IRF422
IRF423
2.0 - - A

ROS(an) Static Drain-Source On-State IRF420

Resistance ® IRF421 - 2.5 3.0 Il
VGS = 10V, 10 = LOA
IRF422
IRF423
- 3.0 4.0 Il

9fs Forward Transconductance ® ALL 1.0 1.75 - SIUI VOS >1010n) x ROSlon) max.' 10 = LOA
Ciss Input CapaCitance ALL - 300 400 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 75 150 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 20 40 pF
tdlon Turn-On Delay Time ALL - 30 60 ns VOO ~ 0.5 BV OSS ' 10 = 1.0A, Zo = 501l
tr Rise Time ALL - 25 50 ns See Fig. 17
tdloffl Turn-Off Oelay Time ALL - 30 60 ns IMOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 15 30 ns
Qg Total Gate Charge VGS - 10V,I 0 = 3.0A, VOS = 0.8 Max. Rating.
ALL - 11 15 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operat,ing temperature.)
Qgs Gate-Source Charge ALL - 5.0 - nC

Qgd Gate-Orain I"Miller") Charge ALL - 6.0 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate'pins inductances.
and center of die.

- -

$
LS Internal Source Inductance ALL 12.5 nH Measured from the
source pin, 6 mm
10.25 in.) from header
and source bonding
pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case·to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-142
 IRF420, IRF421, IRF422, IRF423 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF420 Modified MOSFET symbol
(Body Diodel IRF421
- - 2.5 A
showing the integral
IRF422
reverse P-N jl.."Tlction rectifier.

~
- - 2.0 A
IRF423
ISM Pulse Source Current IRF420
- - 10 A
(Body Diode) @ IRF421
IRF422
IRF423
- - 8.0 A

VSD Diode Forward Voltage ® IRF420

- - 1.4 V TC = 25°C, IS = 2.5A, VGS = OV
IRF421
IRF422
IRF423
- - 1.3 V TC = 25°C, IS = 2.0A, VGS = OV
trr Reverse Recovery Time ALL - 600 - ns T J - 150°C, IF = 2.5A, dlF/dt = 100A/~s

QRR Reverse Recovered Charge ALL - 3.5 - pC T J -150·C,I F - 2.5A,dI F/dt - 100A/I's

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j)TJ = 25·C to 150·C. @PulseTest: Pulse width", 300I'S, Duty Cycle'" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5),

S
7.SV 7.0V
.1 L
VGS = 6.SV
_ aL. PU!SE TEJ III
I
~r- aD l. PuJE TEST
I I II
VOs> 10(on) x ROS(on) max. /I
V

6.0V

"
r-- r--ITJ=12SIoC J
T TJ=2S 0 C, ~ 11
1. ~ ~J
TJ = -SSOC '-.

T /} 'Y
~~
4.SV
I
4.0V
SO 100 lS0 200 2S0 4 10
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

SO
OPERATION IN THIS

aL, PJSETEsl ~7.0V J AREA IS LlMITEO

r-- ~~ 6.V""""- = 20
BY ROS(on)

IRF420 1
10
/ iii
~
f=1 RF422 ,3
~ 6.0V- r-- "-
'">- .'. 1'-
~~
:5
~
0:
f-IRF420,1

f-IRF422,3
'\1' "- Wi
lrrrl'
'/
0:
I\.

,
B 1.0
z
F= ;;:
J S'r= 0:
0

E
O.S

r - TC = 2S oC l"- .... 1 ms
,',~
VGs=sL= r= 0.2
r - TJ = lS0 0 C MAX.
f-- RthJC = 3.12 KIW l~l~s
L
12
T
16
I
4.SV-i--
4.0V===
20
0.1 r-,SINGLE PULSE

0.05
1.0 10 20 SO 100
IRF421 3....
IRF420,2

ZOO
=
~
SOO
VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTS) Vos, ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-143
IRF420, IRF421, IRF422, IRF423 Devices

ffi
in
z
<
:=wzt=: 1.0
>:::> 0=0.5
5::5
w,,-
0.5 NOTES:

i-'--~.2
HUL
:t;:;;

- -......
w..,
ffi:i 0.2
!:::!ffi f--O.l
~~
~2~
*
0.1 1=0.05

-
0: ....
0< 1-0.02 -=~
z.~ 0.05
"'w ~0.Q1 I"::; 1. DUTY FACTOR, 0 =
}~
E.., 0.02
n- 'SINGLE PULSE (TRANSIENT
THERMAL IMPEDANCE) 2. PER UNIT 8ASE = RthJC = 3.12 OEG. CIW.
3. TJM - TC = POM ZthJCIt) .
j 0.01 I 111111 I I
10-5 10-3 10-2 10-1 1.0 10
tl,SQUAREWAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to·Case Vs. Pulse Duration

80",PULSETEST
I I I
I I 102
I-- vos > 10(on) x RDS(on) max.
~
13
< T~ ~
0:

ill :IE
§ ~- Tj=250~_ ~
..,
w
,., - ' ~ 0-
Z
TJ = 25 0C......

,., - ' I
W

~:::> V 0:
0:

o
z VV TJ ~ 1250~ _
1:l
z
<f 10 I- TJ -150 0C ~
'"
.......... TJ=1500~=
~ 2 0:

1£~ to-
Q
z W
<
0: ~

.1. ~
0- W
J
£ ~ I I I"TJ=25 0C
<i
/I E' II I I
II I I
If 1.0
I
o
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

1.25 2.6

I-- I- V~s= Jov II

w 10' 2.5A
..,z J
~
w 2.2
o
>
1.15 <
Iii
/
~o ~
/ " [fl
0: 1.8 J
~s 1.05 ~ ;;Sa
wW
~"""
Ww
O:N
ID::; /
..,N
0:::;
:::>< 1.4
V
~~
!:!io:
~~ 0~95
o
'7
",
./
"".
0:&
~o:
00
'7z
z-
<f
0: 1.0
, /

z Q V'
<f
0: c ./
0
Q
.;
:g
0.85
'"
Q
0: 0.6
,/
I""
~ V
0.75 0.2
-40 40 80 120 160 -40 40 80 120 160
TJ, JUNCTION TEMPERATURE (DC) TJ,JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-144
 IRF420, IRF421, IRF422, IRF423 Devices
1000
20
I
VGS = 0
1 1 f= 1,MHz 1 1
VOS = 100V
f--
~
800 Ciss = Cgo + Cgd. Cd. SHORTED -
I I "'-..,
Crss = Cgd
2. 15 Vos = 250V

~~
Cgo Cgd - r-- I I "'-..,
...
~
COlI = Cd. + Cgo + Cgd
w
to
«
Vos = 400V
600 - r-- !:;

~~
w "'Cds + Cgd
'"
z '"w
>
'"e:;
l-
~ 10
...'"
~~
::>
\ '"
'"'"
400
",'

!\ \ :--...... Ciss :;;'""" U

:<to If
\' '"
5
200

\ ....... .1
r--.... ~ CO..
>
to
/ 10= 3A
FOR TEST CIRCUIT -
I...........
""'- C~"" / SjE FIG1URE lj

10 20 30 40 50 8 12 16 20
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) ~. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to·Source Voltage
3.0
I
VGS= 10VJ
~8
:>::
ew 2.4 ~

'" tGS= 20V ~ I'....

z 7 '"w
~ ~
i3
~ 6
I , :.;
5 1.8
I-
~ ........
r---.
I"--- ~
~420.421

r-- -IRF422.~ .........

'"
w
'"
'"
~ 5
V
I ~
'"
'"
::>
'"
z 1.2 I"-...
",,-...."-
.,.'"""z ;;: .........
;;: 4 / '"'"
~
E
'"
c
/ 0.6

". V
./
ROS(on) MEASURED WITH CURRENT PULSE OF
2.0/.lS DURATION. INITIAL TJ = 250C. (HEATING
~ ,
EFFECT OF 2.0 p. PULSE IS MINIMAL)
2 o
o 10 12 14 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (OC)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35
'\
30
I\.
i
z
25 \.
\
'"
;::
;t 20
iii
c
'"
w
"\
3: 15

"
~
~
10

~
20 40 60 80 100 120
"1\
140
TC. CASE TEMPERATURE (OC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-145
IRF420, IRF421, IRF422, IRF423 Devices

VARY tp TO OBTAIN
REQUIRED PEAK I L

TO DUT
vGs=trtPL
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r-----.,
I
( > - - _ TO SCOPE
I O.Oln
I 50U HIGH FREQUENCY
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

,..-_ _Q +VOS
(ISOLATED
SUPPL Yi

12V
BATTERY

0~1.5mA - IG
\,..._~''''''\r---<O -VOS
10
CURRENT -=
CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-146
 PD-9.310

INTERNATIONAL RECTIFIERII\)RI

HEXFET® TRANSISTORS IRF43D

IRF431
N-Channel IRF432
IRF433

500 Volt, 1.5 Ohm HEXFET Features:

• Fast Switching
The HEXFET® technology is the key to International Rectifier's
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve • Ease of Paralleling
very low on-state resistance combined with high transconductance • No Second Breakdown
and great device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well established Product Summary
advantages of MOSFETs such as voltage control, freedom from
second breakdown, very fast switching, ease of paralleling, and Part Number VOS ROS(on) 10
temperature stability of the electrical parameters.
IRF430 500V 1.5S1 4.5A
They are well suited for applications such as switching power IRF431 450V 1.5S1 4.5A
supplies, motor controls, inverters, choppers, audio amplifiers, IRF432 500V 2.0S1 4.0A
and high energy pulse circuits.
IRF433 450V 2.0S1 4.0A

22.22 (O.875)
342 MAX.DIA. 11.430.450)
CASE STYLE AND DIMENSIONS 1O.'3J:~.35(0.250
22.22 (0.875)
MAX, DIA. Tcu-+-1~~~~NG
~~; I~m: OIA--I1- 10.16 (0401 MIN.
TWO PLACES TWO PLACES
26.67
(1.0501 MAX.

i~! :~:;:: OIA.

TWO PLACES

DRAIN
(CASEI

1
"1.09 (0.043)
MAX, DIA.
~_ _ 39.95 (1.573) lU7W.440)t
10.67 (0.420)
MAX, t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO-204AA (TO-3)

Dimensions in Millimeters and (Inches)

0-147
IRF430, IRF431, IRF432, IRF433 Devices

Absolute Maximum Ratings

Parameter IRF430 IRF431 IRF432 IRF433 Units
VOS Drain - Source Voltage (j) 500 450 500 450 V
YOGA Drain - Gate Voltage (RGS = 1 MOl (j) 500 450 500 450 V
10@TC- 25°C Continuous Drain Current 4.5 4.5 4.0 4.0 A
10@TC - 100'C Continuous Drain Current 3.0 3.0 2.5 2.5 A
10M Pulsed Drain Current @ 18 18 16 16 A
VGS Gate - Source Voltage ±20 V
PO@TC-25°C Max. Power Dissipation 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 141 W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 1OO~H
A
18 I 18 I 16 I 16
TJ Operating Junction and
-55to 150 'c
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °c

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF430
IRF432
500 - - V VGS = OV
IRF431
IRF433
450 - - V 10 = 250~A
V GSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS.IO - 250~A
IGSS Gate-Source Leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ~A VOS = Max. Rating. V GS = OV
- - 1000 ~A VOS = Max. RatingxO.8. VGS = OV. TC - 125°C
10(onl On-State Drain Current ® IRF430
4.5 - - A
IRF431
VOS ) 10(on) x ROS(on) max.' VGS = 10V
IRF432
IRF433
4.0 - - A

ROSton) Static Drain-Source On-State IRF430

Resistance (i) IRF431
- 1.3 1.5 I!

IRF432
VGS = 10V,I0 = 2.5A
- 1.5 2.0 I!
IRF433
9fs Forward Transconductance ® ALL 2.5 3.2 - S(!11 V OS ) 10(onl x ROS(on) max.' 10 = 2.5A
Ciss Input Capacitance ALL - 600 800 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 100 20Q pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 30 60 pF
td(ont Turn-On Delay Time ALL - - 30 ns VOO = 225V,I 0 - 2.5A, Zo = 151!
tr Rise Time ALL - - 30 ns See Fig. 17
tdloffl Turn-Off Delay Time ALL - - 55 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 30 ns
Qg Total Gate Charge V GS ~ 10V,I 0 - 6.0A;V OS = 0.8 Max. Rating.
ALL - 22 30 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 11 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 11 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on ' symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source, Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.1 from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-ta-Case
RthCS Cose-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-148
 IRF430, IRF431, IRF432, IRF433 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF430 Modified MOSFET symbol
IBody Diode) IRF431
- - 4.5 A
showing the integral
IRF432 reverse P-N junction rectifier.
- -

~
4.0 A
IRF433
ISM Pulse Source Current IRF430
IBody Diode) @ IRF431
- - 18 A

IRF432
IRF433
- - 16 A

VSD Diode Forward Voltage @ IRF430

IRF431 - - 1.4 V TC = 25°C,IS = 4.5A, VGS = OV
IRF432
- - 1.3 V TC = 25°C, IS = 4.0A, VGS = OV
IRF433
trr Reverse Recovery Time ALL - 800 - ns T J - 150°C, IF - 4.5A, dlF/dt = 100A/~s

OAA Reverse Recovered Charge ALL - 4.6 - ~C T J - 150°C, IF - 4.5A, dlF/dt - 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(1)TJ = 25°C to 150°C. @PulseTest: Pulse width" 300~s, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

10V 5.5V

_Iso •• lu LSEIm) 80jJsPULSE TEST

VOS> 10(on) x ROS(on) max.

r
VGS·5.0V

- r- TJ" ~1250C ....

TJ;25.0C,
TJ"-550C,
~
T i'...."--""w
iJJ
1. /, ~I
100 200
T 300 I
~
VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
50 AREA IS LIMITED

l 1O~;r.' BY ROS(on)
r 80 /olSPUJETESJ /.5.5[- - IRF430,1 1/
1# 20
IRF432, J
\..
l/.... 5.0~= -:: 10

L-V =iRF430,l
10~.

1
J'" _IRF432,3
, r, i;m.
1/ ~'

£- I--
VGS·4.5V=
= 1.0
~. 1m.

I 0.5 =TJ "1500C MAX.

10m.
- RthJC : 1.67 KIW f.f'---j1-+-t-+H-IHtI-H"'d-'lii-l ooHm
+l. +
4.0,""'" !!!!!!!! 0.2 t11~GL~ PPW11tt.,:--, +-+-+-+t+:m 31 '1 3 boo W.\
~ I I I II IRF430,2 ::: 9~ III
0.1 1-I....I......I....u..J..U.............O"-........................-.L.............u.L.u
10 1.0 10 20 50 100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-149
IRF430, IRF431, IRF432, IRF433 Devices

...
a::
u;
z
<
a:_
...... 1.0
wz
>:::> o O.S
;:: a: 05
NOTES:
~~ .
~~ 0.2
!:::!~ -0.1
-6.2

3nJL
~2~
~Q.

~~ 0.1 O.OS
a: ~
-0.02-

~~
0<
,..~ 0.05
'-'w ~~1'::' SINGLE PULSE (TRANSIENT 1. DUTY FACTOR, 0 = :~
}~ mRMA~ I~PEOtNfEl I I 2. PER UNIT BASE = R'hJC = 1.67 OEG. CIW.
f, 0.02
3. TJM - T C = PDM Z'hJC(t)·
~ 0.01 1111 I I I
IO-S 10-3 10-2 10-1 1.0 10
'I, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

"I
TJI= -sso~
;..--
- ~
10 2
I

V
./
TJ=~ - i'"
::!.
TJ = 25°C

~
...
/ ~12S0l- "" "TJ = IS0oC_

............ -
/' a::
a: /'
I V a:

,.13 ..0IIII

/ / ./
/' ~ 10
//
'"w
// / '"a:w TJ - 150 0 C I

1 /, '/ G:;
a:
<i:
-,
IVI Vos> ID(on) x ROS(on) max. .9 I
V 10 po PUllSE TEi'
1.0 I I
TJ = 2SoC
I
o
ID' DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

22
1.2S
/
..,w
~
o 1.15
w
'-'
z
< 1.8 /
~
> "". u; /
z
;:
o
c
~c 1.05
.",
...- --- w
a:
z
c8
Ww 14 /
Ww '-'N

. /~
a:N 0: -
"'::;
w< 5~
v,>'"
/
~I / ,,.
cO:

~~ 0.95 ./
... 0
z-
;;: 1.0
/
..,.o
z
V' 0:
C /
;;: C
a:
c
~ 0.85
~
'"
0: 0.6 / VGS = 10V
IO=1.SA - r--
~ , / -I 1

0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE (OC) TJ, JUNCTION TEMPERATURE (OC)
Fig.8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-150
 IRF430, IRF431, IRF432, IRF433 Devices
2000
20
)GS = 01

1600
I I i i MHI I
Ciss • Cgs + Cgd. Cd. SHORTEO -
J in
:;
Cns • Cgd 0 15 VDS = 100V
-
~
Cgo Cgd
~
w
I
VDS =.250V "-.. /
~
Coss ' Cd,+ Cgo+ Cgd
'"
-a
'""-
~

w
u
1200
"'Cd, + Cgd
- '"'
:;
0
VDS·400V
/
z >
'"'
l- w
u 10
~
e;

~ '/
0:
;t =>
0
5 800 Ciss 0;>
0
U
\ :L
I-
~V
\\ '"'".;,'
400

\ .......
~
>'"
/ IO'6A
FDR TEST CIRCUIT- r--
~ ""'- / SEj FIGiRE 18
1

10 20 30 40 50 16 24 32 40
VDS. DRAIN-TO-SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

RDS(o.) MEASURED WITH CURRENT PULSE OF

2_0", DURATION_ INITIAL TJ' 25 0 C_ (HEATING
~ EFFECT OF 2.0 IlS PULSE IS MINIMAL.), .........
:z:
E! .........
w
lil 4
......... ......... ........ j'-....
~ VGS" 10V~ '"w
~ ......... ~F430.431

iii0: VGS '20V r-- ~ IRF432~ r-...

Z
o
w
U
V ~
w
0: ....... "'~
0:
=>
o
'/
0:

13
z
f".. ~
.,.
0;>
«
~
o .......
z
«0:
o
/ 0:
o

'" 'I ~
c ~
,/
\,
o

'"
~
.,-'
1 o
o 10 15 20 25 25 50 75 100 125 150
ID. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)
Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
80
~

in
l-
I-

'z~"'
70

60 " "\
r\.
'\
t\.
50
0
;::
;t 40
gj
'\
C
0:

~ 30
'\
~
,p
20 '\
10

20 40 60 80 100
TC. CASE TEMPERATURE (OC)

Fig. 14 - Power Vs_ Temperature Derating Curve

0-151
'"
120
"\

140
1\
IRF430, IRF431, IRF432, IRF433 Devices

VARY,p TO OBTAIN
REQUIRED PEAK IL

TO OUT
vGs·r.r-'PL ~---"'-'-"
IL+------<~-~........\M.-J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

VOO "225V

Vo
- " ' - - - " T O SCOPE

Fig. 17 - Switching Time Test Circuit

....---<1 +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

or=Il. -
5 mA

IG
OUT

10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-152
 PD-9.372

INTERNATIONAL RECTIFIER IIC~RI

HEXFET® TRANSISTORS IRF44D

N-CHANNEL
IRF441
POWER MOSFETs IRF442
IRF443
500 Volt, 0.85 Ohm HEXFET Features:
The HEXF~ technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFETtransis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state
resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The H EXFET transistors also feature all of the well
established advantages of MOSFETs such as volt- Product Summary
age control, freedom from second breakdown, very VOS ROS(on) 10
Part Number
fast switching, ease of paralleling, and temperature
stability of the electrical parameters. IRF440 SOOV 0.8SU S.OA
IRF441 4S0V O.SSU S.OA
They are well suited for applications such as switch-
ing power supplies, motor controls, inverters, chop- IRF442 SOOV 1.10U 7.0A
pers, audio amplifiers, and high energy pulse circuits. IRF443 4S0V 1.10U 7.0A

22.22 (O.875)
CASE STYLE AND DIMENSIONS
{D'13Ix~MAX'D1A~'
~
T SEATING
PLANE

~'~im'~1 DIA.-II- lD.16{D.4D) MIN.

TWD PLACES TWD PLACES

UfIK1WDIA.
TWO PLACES

j i ~.' DRAIN
(CASE)

"1.09 (0.043)
MAX.DIA.
39.96 (1.573)
MAX. lWI8'l;&t
1.7.
t MEASURED AT SEATING PLANE
Conforms to JEDEC Outline TO·204AA (T0-3)
ACTUAL SIZE Dimensions in Millimeters and (Inches)

0-153
IRF440, IRF441, IRF442, IRF443 Devices

Absolute Maximum Ratings

Parameter IRF440 IRF441 IRF442 IRF443 Units

VOS Drain - Source Voltage (j) 500 450 500 450 V

VOGR Orain - Gate Voltage (RGS = 1 Mil) (j) 500 450 500 450 V
10@TC= 25°C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10@TC - 100°C Continuous Drain Current 5.0 5.0 4.0 4.0 A
10M Pulsed Drain Current @ 32 32 28 28 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 125 (See Fig. 141 W
Linear Derating Factor 1.0 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 100/LH
A
32 I 32 I 28 I 28
TJ Operating Junction and
-55to150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions

BVOSS Drain - Source Breakdown Voltage IRF440

IRF442
500 - - V VGS = OV

IRF441
450 - - V 10 = 25Ol'A
IRF443
V GS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 = 250/LA
IGSS Gate-Source leakage Forward ALL - - 100 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 /LA VOS = Max. Rating. VGS = OV
- - 1000 /LA VOS - Max. Rating x 0.8. VGS - OV. T C - 125°C
10(onl On-State Drain Current ® IRF440
8.0 - - A
IRF441
VOS >10(on) x ROS(on) max.' VGS = 10V
IRF442
IRF443
7.0 - - A

ROSlon) Static Drain-Source On-State IRF440

- 0.8 0.85 II
Resistance ® IRF441
VGS = 10V, 10 = 4.0A
IRF442
IRF443
- 1.0 1.1 II

9fs Forward Transconductance ® ALL 4.0 6.5 - S (0) VOS >10(on) x ROS(on) max.' 10 = 4.0A
Ciss Input Capacitance ALL - 1225 1600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 200 350 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 85 150 pF
td(on) Turn·On Delay Time ALL - 17 35 ns VOO = 200V, 10 = 4.0A, Zo = 4.711
tr Rise Time ALL - 5 15 ns See Fig. 17
td(off) Turn-Off Delay Time ALL - 42 90 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 14 30 ns
Qg Total Gate Charge V GS = 10V, 10 = lOA, VOS = 0.8 Max. Rating.
(Gate~Source Plus Gate-Drain)
ALL - 42 60 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 20 - nC

Qgd Gate-Orain ("Miller") Charge ALL - 22 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-154
 IRF440, IRF441, IRF442, IRF443 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF440 Modified MOSFET symbol
(Body Oiodel IRF441 - - B.O A
showing the integral
reverse P-N junction rectifier.

~
IRF442
IRF443 - - 7.0 A

ISM Pulse Source Current IRF440

- - 32 A
(Body Oiodel ® IRF441
IRF442
IRF443
- - 2B A

VSO Diode Forward Voltage ® IRF440

- - 2.0 V TC = 25°C,IS = B.OA, VGS = OV
IRF441
IRF442
IRF443 - - 1.9 V TC = 25°C,IS = 7.0A, VGS = OV

trr Reverse Recovery Time ALL - 1100 - ns TJ - 150°C, IF = a.OA, dlF/dt - 1OOA/~s

ORR Reverse Recovered Charge ALL - 6.4 - ~C T J = 150°C, IF - a.OA,dlF/dt - 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by lS + LO'

<DTJ = 25°C to 150°C. @PulseTest: Pulse width .. 300!,s, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
bV max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

,,
20
20
~v sf"' ~ETEJT -S~",PU~SETE~T l If
10,
PU - I )

16 16
VOS> ID(on) x ROSlon) max. I /
VGS = 6t II
I /}
II fj
0
I !J / ' TJ=-55 0 C
b- -
Y 5V
lL, Tl=25 0
-:::: TJ' = 125 0C

I ~V
20 40 60
4V
80 100
~ W
4 B 10
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
10 OPERATION IN THIS

f-80I',l pULS)TEST 10V

..... ~ 50
- IRF440,l
AREA IS LIMITED
BY RDSlon)
9V ",.
~
BV
7V~ ,... 20
IRF442,3
"
r,
~
.~

"'~
w
10 = I~F4do, \ V t', ....... ::::..

~
6V 101"
::;;
O~t
~
= IRF442,3

/
V-
VGS = 5V
>-
ffi
::i r, 11 !,
~ I :::>
'-'
z , " ~ ...
:;;: I" II
~ DO
0
1.0
Om
~~ E 0.5
=
=TC- 25OC
TJ = 1500 C MAX.
'f~m'

,.,
If' 0.2
- R'hJC = 1.0 KIW
t---,sI~GL~ PIU~SIEI IRF441,3
OC

y 0.1 I I II II ,lr; r, ~
F44
II
10 1.0 10 20 50 100 200 500
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTSI

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-155
IRF440, IRF441, IRF442, IRF443 Devices

!Ew
in
z
<
0:_
.... !: 1.0
wz
>::>
D-0.5
~ffi 0.5
tt~ Iii ... NOTES:
w<.>
ffi~ 0.2
~ffi
....... -0.1
0.2
~
mIL
~l!i 0.1 =0.05
0: ....
~ ~2~
iE~ r SJNGLE PULSE (TRANSIENT
0< 0.02
z_~ 0.05
<'>w
2",
_0.01 1. DUTY FACTDR. D= :~
"'....
E<.>
0.02
iHiiiiilMPnNCEI I 2. PER UNIT 8ASE' R1nJC = 1.0 DEG. CIW.
2 3. TJM - TC = PDM ZlhJC(I).
N 0.01 II III
10-5 10-3 10-2 10-1 1.0 10
11. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

16.0

f-tpulSETeh
I I I I I
20
,
~ 12.8
vDS> ID(onl x ROS(on) max. ;;;
w 10 /
~::E
~ ~
1e ....z
~ 9.6 TJ = -55 0 C W
0:

~
0:
". I I ::>
<.> L TJ = 150 0 C
::> z
CI ~ TJ·25 0 C :;;:
z
o 6.4 / 0:
1.0
r
0'
~
<
....
'" TJ'125lc
~
'"
w
~
0.5
r== Tr25 0 C

~ 3.2 L ~ a:
Ii:

If E
0.2

0.1
4 12 16 20 o
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Tvpical Transconductance Vs. Drain Current Fig. 7 - TVPical Sou rca-Drain Diode Forward Voltage

1.25 2.5

w w ~
<.>
'"~ z
/
o 1.15 ~ 2.0
> ,/ iiia: /'f'
~ ~
~
o
'"~s 1.05 JI'~ t; E' 1.5 /
zw
g;~
~~
./' ~
ON
w::i
<.><
V
/ .V . /V
a::&
::>0: ::>a:
~~
00
... ~ 0.95 1.0
~
z
~ ,..,
z V vGS -10V
:;;: :;;: 10=4.5A - -
~
0: 0:
o CI
~ 0.85 C 0.5
ii; i
0:

0.75 o
-40 40 80 120 160 -40 40 80 120 160
TJ. JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-156
 IRF440, IRF441, IRF442, IRF443 Devices
2000
Cia = Cgs+Cgd.Cd,SHORTED J .l. 20
r - C", =Cgd _VGS=OV
~ f=IMHz
Kc.os=cd.+ gs+Cgd
1600
"Cds + Cgd
I "'
~
0 15 ~OS = I~OV"",-

~~
~

"""""" r-..... .'"

..: Ciss w
.vos = 2~QV ""'-
~ 1200
..
z
>-
u
\ ~
0
>
w
Vos = 400V"",-

~
~
'"' 800
\ '"'=>
0:

0
10

~
U
\ r\. '"..,
0

..'"
w
>-
~~

\ 'I"\.."I\................ .;,
5
I 10= lOA
-
400

.......
.... Coss
to
>
I FOR TEST CI RCUIT
seE FIGURE 18

V
---
C,ss

10 15 20 25 30 35 40 45 50 20 40 60 80
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
10
3.5

RDS(O~) MEASU~EO WIT~ CURRE~T PULSE10F

"''"8 f-~.Ol'sOURATION. INITIAL TJ=25 0 C. (HEATING

,
% 3.0 EFFECT OF 2.0 I" PULSE IS MINIMAL.)
w ........
.
'"'z
>- 2.5
I
i .........
~t....
'"
iii0:
VGS = 10V
r-.... r--... .........
Z
2.0 ~ ~ 6
>- ........ ~441
0
w ,VGS= 20V ;:;
'-' 0:

L IRl~ ........
0: 0:
=>
0
1.5 13
z 4
..,'1'z
,.V
"
0 :;;:
:;;:
0:
o ~
1.0 P
~~
0:
0

0:
~
0
c

0.5 -----
10 15 20 25 30 35
o
25 50 75 100 125
!\ ,150
10. ORAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig_ 13 - Maximum Drain Current Vs_ Case Temperature

--
140

120
'\
~
!
z
o
~
ill
100

80
" '\
r\.
"\
Ci
0: 80
I\..
I "\
re 40

20
" '\
~
~

20 40 80 80 100
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

120
"
140

0-157
IRF440, IRF441, IRF442, IRF443 Devices

VARY tp TO OBTAIN
REQUIRED PEAK Il

vGs="R OUT

Il _ _ _O - - -...JV>I_....

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

200V
ADJUST Rl TO OBTAIN 45!1
SPECIFIED 10
VOS

o....,li---_o-_...lI...J~ O.U.T.
Ii;UlSE - -
GENERATOR

I ;ri~CE
IMPEDANCE
n I
L ___ J

Fig. 17 - Switching Time Test Circuit

r - - - O +VOS
(ISOLATED
SUPPLY I

o L=tI:.5 mA
- IG
__ ~',,","'~_n

10
-VOS

CURRENT -=- CURRENT

SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-158
 PD-9.322

INTERNATIONAL RECTIFIER II~~R I

HEXFET® TRANSISTDRS IRF45D
IRF45~
N-Channel IRF452
IRF453

500 Volt, 0.4 Ohm HEXFET Features:

The HEXFETe Technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the
HEXFET design achieve very low on-state resistance • Ease of Paralleling
combined with high transconductance and great • No Second Breakdown
device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage Product Summary
control, freedom from second breakdown, very fast -------r-----.-----~--­
switching, ease of paralleling, and temperature Part Number VDS RDS(on)
stability of the electrical parameters. IRF450 500V O.4n 13A
They are well suited for applications such as switching IRF451 450V O.4n 13A
power supplies, motor controls, inverters, choppers, IRF452 500V O.5n 12A
audio amplifiers, and high energy pulse circuits. IRF453 450V O.5n 12A

22.2210.875)
CASE STYLE AND DIMENSIONS 342 MAX.OIA. 11.4310.450)
10.135)MAX~'3510250)
22.22 (0.875) ~ ttEATlNG
MAX.OIA. T =+LANE

6·r,!~·Wal 01A.--/
TWO PLACES
10.1' 10.40) MIN.
TWO PLACES

HI. !Kl"l
. 51 OIA .
TWO PLACES

1~ DRAIN
ICASE)

SOURCE

"1.09 (0.043)
MAX.OIA.
14-_ _ 39.95 (1.573)
MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO-204AA (TO-3t

Dimensions in Millimeters and (Inchest

0-159
IRF450, IRF451, IRF452, IRF453 Devices

Absolute Maximum Ratings

Parameter IRF450 IRF451 IRF452 IRF453 Units
VOS Drain - Source Voltage (j) 500 450 500 450 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) (j) 500 450 500 450 V
10@TC=25'C Continuous Drain Current 13 13 12 12 A
10@TC = 100°C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10M Pulsed Drain Current @ 52 52 48 48 A
VGS Gate - Source Voltage ±20 V
PO@TC= 25'C Max. Power Dissipation 150 (See Fig. 14) W
Linear Derating Factor 1.2 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 14 and 15) L = 100pH
A
52 I 52 I 48 I 48
TJ Operating Junction and
T stg Storage Temperature Range
-55to 150 'c
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) 'c

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
8VOSS Drain - Source Breakdown Voltage IRF450
IRF452
500 - - V VGS = OV

IRF451
IRF453
450 - - V 10 = 250pA

V GSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS, 10 - 25Ol'A
IGSS Gate-Source Leakage Forward . ALL - - 100 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -100 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VOS - Max. Rating, VGS - OV
- - 1000 I'A VOS = Max. Rating x 0.8, VGS = OV, TC = 125'C
10(on) On-State Drain Current ® IRF450
13 - - A
IRF451
VOS ) 10(onl x ROS(on) max.' VGS = 10V
IRF452
IRF453
12 - - A

ROS(on) Static Drain-Source On-State IRF450

Resistance ® IRF451 - 0.3 0.4 n
VGS = 10V, 10 = 7.0A
IRF452
IRF453
- 0.4 0.5 n
9fs Forward Transconductance ® ALL 6.0 11 - Sill) VOS ) 10(on) x ROS(on) max.' 10 = 7.0A
Ciss Input CapaCitance ALL - 2000 3000 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 400 600 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 100 200 p.F.
td(onl Turn-On Delay Time ALL - - 35 ns VOO = 210V,I 0 = 7.0A, Zo - 4.70
tr Rise Time ALL - - 50 n. See Fig. 17
td(off) Turn-Off Delay Time ALL - - 150 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 70 ns
Qg Total Gate Charge V GS = 10V, 10 = 16A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 82 120 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
QgS Gate-Source Charge ALL - 40 - nC

Ogd Gate-Drain ("Miller") Charge ALL - 42 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die .

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
.$
Thermal Resistance
Junction-to-C.8e
C.8e-to-Slnk Mounting surface flat, smooth, and greased.
Junction-to-Ambient Free Air Operation

0-160
 IRF450, IRF451, IRF452, IRF453 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF450 Modified MOSFET symbol
(Body Diode) IRF451
- - 13 A
showing the integral
reverse P-N junction rectifier.
IRF452
- -

~
12 A
IRF453
ISM Pulse Source Current IRF450
(Body Diode) @ IRF451
- - 52 A

IRF452
IRF453
- - 48 A

VSD Diode Forward Voltage @ IRF450

IRF451 - - 1.4 V TC ~ 25°C, IS ~ 13A, VGS ~ OV

IRF452
IRF453
- - 1.3 V TC ~ 25°C, IS ~ 12A, VGS ~ OV

trr Reverse Recovery Time ALL - 1300 - ns T J - 150°C, IF = 13A, dlF/dt - 100A/~s
QRR Reverse Recovered Charge ALL - 7.4 - ~C T J = 150°C, IF - 13A, dlF/dt - 100A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO-

<DTJ = 25°C to 150°C. @Pulse Test: Pulse width " 300~s, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20
I I .1 TJ=-ISOOV'
rt: TJ .JSOC
20 6.0k.
, ,
r---VDS> ID(on) x RDS(on) max.
aJ ps PUILSE T~ST
TJ = 12S oC
5.5V 80 ItS PU LSE TEST
15
~
16 ::;
'"w ,."-
,.~ S
....
S 12
I-
VGS = 5.0V
~ 10
~ ..,"':::> TJ = 12S 0 C......
"'El z
~
I I"---.... J
z
~
c
c
E
TJ = 2S 0 C......
I I'-.... ~J
tJ ~
4r TJ = -SOOC ......
E
I
4.~V
50 100 150 200
I
3.5V
250 300 1
Vh V
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)
Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
10 OPERATION IN THIS _
VGS= ~~~ V SO
==lRF45o, 1~ Z AREA IS LIMITED BY RDS(on)=
5.S
r-- 1-80J. PULSl TEST -IRF452,3

~ ~.Ov 20 I I '\. 1',

~~
,-IRF450,1
lPf,s.
i'"
"

10 ::::IRF4S2,3 100~

J.~ S 1m,
I-- 4.SV
~V
I-
;
~ .... 1~1~,
~~ ..,"':::>
z
~
J I" lOOms
;(
1.0
'"
c
E ¢: 'TC = 2S oC
~" 4.0V
O.S ~ TJ IS00 C MAX.
~ RthJC = 0.B3 K/W
~
DC
IRF4S1,3 ....
0.2 ,-SINGLE PULSE
'1 I I 111111
/ 3.SV I IIIII1 ill~F4~0'r ,II
0.1
1.0 10 20 50 100 200 sao
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, DRAIN·TD·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-161
IRF450, IRF451, IRF452, IRF453 Devices

....
z
w
iii<
:=E
wz
1.0
>'" 0=0.5
fi ffi 0.5
NOTES;
~!:
... w '-~.2
3:flJL
w ....
53:i 0.2
.......
!::::!ffi 1--:0.1
...
i=~.05
Sf ~2~
~::!! 0.1

-
cz: ....
0< 1--:.0•02
z.~ 0.05
.... w
2%
1--:~.01 1. OUTY FACTOR. 0 = ~
or .... I
SINGLE PULSE (TRANSIENT
~ 0.02 T7Er~Ah'rtEO~NC~) I 2. PER UNIT BASE = RthJC = 0.B3 OEG. CIW.

j 0.01 I II III I 3. TJM - TC = POM ZthJc(t).

10-5 10-4 10-3 2 5 10-2 2 5 10-1 1.0 10

tl. SQUARE WAVE PULSE DURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to·Case Vs. Pulse Duration

20
TJ=-~

, /~ d;-.
I ,
~ io""'"

- U
)J.2. C
16
;;;
V .---rr.: 125~C ;;; 10 2
w
T; =25 0 C

~ ,... ....-
iii ./ cz:
i!i ~ TJ =1500 C
iii
/ ./ ~
....wz
<
....
....
12
j ~ Vi"'"
~cz:
cz:
'"
....
TJ = 150 0 C
(' ~

'"
0
z
0
~
V. / z
~ 10
I
z
<
....cz:
J'/ o
w

~
~
'1
I
VOS> 10(on) x ROS(on) max.

80 r
PUliE TEST
I
>
w
cz:
p
a: J
.... TJ = 25 0 C
[
I

1.0
I I
10 15 20 25 o
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)
Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25
2.2 ~GsJov
W
to w
I I ~
.... lOS = 5A
o~
z
1.15 <
I;;
I'
"". ~
> 1.8
~ iiicz: )~
o
o ." z
~a 1.05
Ww
"" 0-
w O
.... w /
V"

""
CZ:N cz:~ 1.4
"'::i
w< ~ "'0<.... ./
~~
"'0 ./
V ~~
~ ~ 0.95 :2:~ /
.,.z ;;:
""
o 1.0
cz:
0
/
;;:
.. c

- V
cz: 0
o
.; 0.85 0
0.6
cz:
:g io""'"
iii
0.75 0.2
-40 40 80 120 160 -40 40 80 120 160
TJ. JUNCTION TEMPERATUR~ (OC) TJ, JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-162
 IRF450, IRF451, IRF452, IRF453 Devices
4000
Ci.. - Cgs+Cgd.Cd,SHORTEO I 20
k- C'" = Cgd VGS=O
~C... = Cds + C;Cgd
CCgd t= I1 MHz
3200
"'Cd.+ Cgd
~
-'
~ VOS = 100V
I '"w~ 15

~~~
l\, " ,
I I
...
~

w 2400
...... ..
to

~
VOS = 250V
I I
VOS = 400V

.....
'"z
<3
.1
..... Ci.. '"
>
~ 10
'F
~~
::;'3 :::.

""'"'"..,.w
1600
","
\ \. rTf

\ !;;: I
~ '" 5
800

"" -.... ........... ~ .. >

~
I 10 -16A
FOR TEST CIRCUIT r--
~ I SyFIGrEj

10 20 30 40 50 28 56 84 112 140
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) e.g. TOTAL GATE CHARGE (nC)

,
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to-Source Voltage

1.0 15

e~
w
'"
Z
~ 0.8
0.9
VGS= I °1 J
12
r--....
f"".. ~ ..............
~450.451

IRF:.~
VVGS=20V
i1i
a:
~ 0.7
w ......... ~~
~
:::.
~ 0.6 I r" ~
V
,
'"..,.
~
z
:
c
c
c
~ 0.4
0.5

~DS(Dn) MEASURED WITH CURRENT

PULSE DF 2.0 ~s DURATION.
" '" ~
a:

.,.- /
INITIAL TJ' 25 DC. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.)

10 20 30 40 50 60 70
o
25 50 75 100 125· 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current V,. Case Temperature

140

120
""' '\.
~ '\
~ 100 ~
z
'"~ 80
'\
iii
c
a: 60
~

'""
~
~
~ 40

20

"'~
20 40 60 80 100 120 140
TC' CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-163
IRF450, IRF451, IRF452, IRF453 Devices

VARY'. TO OBTAIN

VGs=R
REnUIRED PEAK IL

OUT

'.' IL_--o---"'..JV\I'.-""

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL TO OBTAIN RL
SPECIFIED ID

VDS

r;U~ - - -o-lr----()---'l.J~ D.U.T.

I GENERATOR
I ~g~RCE
IMPEDANCE
Sl
I
L ___ J

Fig. 17 - Switching Time Test Circuit

...---0() +VDS
(lSDLATED
SUPPL VI

o..r==TI1.5 -
mA

- ....."rv'~.r-_-'V'''''r--oQ -VDS
IG ID
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-164
 PD-9.325

INTERNATIONAL RECTIFIER II')R I

HEXFET® TRANSISTDRS IRFEi1D
IRFEi11
N·Channel IRFEi12
IRFEi13

100 Volt, 0.6 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFET® technology is the key to International
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the • Ease of Paralleling
HEXFET design achieve very low on-state resistance • No Second Breakdown
combined with high transconductance and great
device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Part Number VOS ROS(on) 10
switching, ease of paralleling, and temperature stabil- IRF510 100V 0.6n 4.0A
ity of the electrical parameters.
IRF511 60V 0.6n 4.0A
They are well suited for applications such as switching IRF512 100V 0.8n 3.5A
power supplies, motor controls, inverters, choppers,
audio amplifiers, and high energy pulse circuits. IRF513 60V 0.8n 3.5A

~
CASE STYLE AND DIMENSIONS 10.6610.42011
3.4210.13~ 9.6610:3801

tm;"
2.5410.1001 4.08 (0.1611

10.66 (0.420)
MAX. TERM 3 - SOURCE

16.5110.6501

+-j
14.2310.5601

1~~:rFIN. T
6.35102501
MAX.
5.3310.2101
t
14.73 (0.580) :t~j ~. ,J-
4.8310.1901

.f...SECTION X-x
1.1410.0451
0.3110.0121
0
TI-----I
1.1410.0451
1.7710.0701 -I
2.9210.1151
0.5110.0201
1.1510.0451
"2.0410.080)

ACTUAL SIZE Case Style To-220AB

Dimensions in Millimeters and (Inches)

0-165
IRF510, IRF511, IRF512, IRF513 Devices

Absolute Maximum Ratings

Parameter IRF510 IRF511 IRF512 IRF513 Units

VDS Drain - Source Voltage (j) 100 60 100 60 V

VDGR Drain - Gate Voltage IRGS = 1 MO) (j) 100 60 100 60 V
ID@TC=25°C Continuous Drain Current 4.0 4.0 3.5 3.5 A
ID@TC=100°C Continuous Drain Current 2.5 2.5 2.0 2.0 A
IDM Pulsed Drain Current ® 16 16 14 14 A
VGS Gate - Source Voltage ±20 V
PD@TC=25°C Max. Power Dissipation 20 ISee Fig. 14) W
Linear Derating Factor 0.16 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = 1 OO~H
A
16 1 16 I 14 I 14
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage IRF510
100 - - V VGS = OV
IRF512
IRF511
IRF513
60 - - V ID = 250~A

VGSth Gate Threshold Voltage ALL 2.0 - 4.0 V VDS = VGS' ID = 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
IDSS Zero Gate Voltage Drain Current
ALL
- - 250 ~A VOS - Max. Rating, VGS - OV
- - 1000 ~A VDS = Max. Rating x 0.8, VGS = OV, TC = 125°C
IDlon) On-State Drain Current ® IRF510
4.0 - - A
IRF511
VDS ) IDlon) x RDSlon) max.' VGS = 10V
IRF512
IRF513
3.5 - - A

ROSlon} Static Drain-Source On-State IRF510

- 0.5 0.6 0
Resistance ® IRF511
VGS = 10V, ID = 2.0A
IRF512
IRF513
- 0.6 0.8 Il

9fs Forward Transconductance ® ALL 1.0 1.5 - SIu) VDS ) IDlon ) x RDSlon) max.' ID - 2.0A
Ciss Input Capacitance ALL - 135 150 pF
VGS = OV, VDS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 80 100 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 20 25 pF
td(onl Turn-On Delay Time ALL - 10 20 ns V DD = 0.5 BV DSS ' ID = 2.0A, Zo = 501l
tr Rise Time ALL - 15 25 ns See Fig. 17
tdLoffl Turn-Off Delay Time ALL - 15 25 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 10 20 ns
Qg Total Gate Charge
ALL - 5.0 7.5 nC
V GS = 10V,I D = B.OA, VDS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gS Gate-Source Charge ALL - 2.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 3.0 - nC

LD Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm 10.25
in.) from packag~ to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
10:25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

D-166
 IRF510, IRF511, IRF512, IRF513 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF510 Modified MOSFET symbol
(Body Diode) IRF511 - - 4.0 A
showing the integral
reverse P-N junction rectifier.
IRF512
- -

~
3.5 A
IRF513
ISM Pulse Source Current IRF510
(Body Diode) @ IRF511
- - 16 A

IRF512
IRF513
- - 14 A

VSD Diode Forward Voltage ® IRF510

IRF511 - - 2.5 V TC = 25·C,IS = 4.0A, VGS = OV
IRF512
IRF513
- - 2.0 V TC = 25·C, IS = 3.5A, VGS = OV
t" Reverse Recovery Time ALL - 230 - ns T J = 150·C,I F = 4.0A, dlF/dt - 100A/I's
QRR Reverse Recovered Charge ALL - 1.4 - I'C T J = 150·C, IF = 4.0A, dlF/dt - 100A/I's
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j) T J = 25·C to 150·C. ® Pulse Test: Pulse width .. 300l'S, Duty Cycle .. 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

B.o 8.0

7.2
loVJ9V
BL. PU~E TEJ _ - 7.2 I - B01l"PULlE TES! I If
I
I I

6.4
= 6.4
VoS> 10(on) x
I-- TJ = (25 0 C / /
ui
BV= I - RDS(on) max.
I '-...... 1. I )
I :>E
5.6

I
iil
::;
...::;;
5.6 TJ·25 0 C
I '-...... Ui
z
~
....
w
a: 4.0
a:
4.B
I, VGS=7~- t--
~
....
1i'i
a:
a:
4.B

4.0
TJ =-55 C0

'I 1/
...z:=> 3.2 I ...z:=> 3.2 lit
6~- I--

, JI
~
0
~
0
2.4 2.4
E E
1.6 I 1.6
}
5~- I--
o.B

0
0 10 20 3D
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics

4~_
40 - 50
0.8

o
o
~ W
A

VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 2 - Typical Transfer Characteristics

10

100
B.o

7.2 t--lo 1" JSE TElT I ..,/ ' 50

OPERATION IN THIS
AREA IS LIMITED

6.4 /.~~
V 9V - ;::;;; 20 -IRF510,l
BY RoS(on)

'"
w 5.6 ~ 8~~ - "'
w
a: IRF512,3
lOt'!

Q /'" ... -r
10
a:
...:>E
w ...
w
::;;
100~s
<C
....
z
::!
4.b

4.0
~~ ...
"..,VGS=7V- - ~
....
1i'a:i
-IRF510,l

~RF512,3
1'.

~~ I
a: a: I....
...z=> 13
.
a:
0
3.2

2.4
~V 6~- - .
z
a:
0
1.0 I
I'
~
1 is

E
1.6
~~
~
I E 0.5 =
=·TC=25 0 C
TJ - 150 0 C MAX. lOms

~ 5~- -
_ RthJC = 6.4 K/W I I
lOOms
_)SINGLE PULSE
o.B
Ilf 4~_ -
0.2

I
(
I
"")
II111
IRF511.3
DC .J.
IRF510.2
o 0.1
o 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.0 10 20 50 100 200 500
VDS, DRAIN·TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN·TO-SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area
0-167
IRF510, IRF511, IRF512, IRF513 Devices

....
ill
0;
z
'" !::
=-
....
wz
1.0
~~ D=0.5
(,)w 0.5 NOTES:
wo.

~
u. -
u. w
~~ 0.2
w « 0.2 -l
~~ 1-- 0.1
~~ 0.1 i::::=:
~;;! F:::::0.05 ~2~
~'" 1. DUTY FACTOR. 0 = :;
.l'....
'" -""f'
0 02 ....
.o.oj" 1-
;+~""'f""'-+SI NG LE PU LSE (TRANSI ENT t-t-ttt--t-+-+-t-++-I-!+l--+-+--+-++-II-H-++--H- 2. PE R UNIT BASE' RlhJC =6.4 0 EG. crw.
~. J.o'
~ 0.01 IA'I ~H~~r~LI~PE~AN~E)1 I 3. TJM - TC = POM ZlhJC(t)·

10-5 10-4 10-3 10-2 10-1 1.0 10

11. SQUARE WAVE PULSE DURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance. Junction-to-Case Vs. Pulse Duration

4.0 10

3.6 I--J~'PUJSETESl I
I I I
I ./
VOS> ID(on) x RDS(on) max. 13 1
3.2
'ill" ....ffi /1/
'"w
§
2.8 '"
~
.... I
w 2.4
ill
= I I
U
z
....
TJ = -55°C
=
:::>
II II
'"
U
:::>
2.0
i'" TJ = 25°C
U
z 1.0
;;:
Q
z
0 1.6
/ =
Q TJ = 25°C
:;l ~ w

'"....= 1.2 I V
TJ = 125°C I - - TJ =150°C I
z '"ffi
~ I
~
0.8
IIIV =Ii;
S' I
0.4
If
o 0.1
IJ
o 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0 o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10. ORAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.50

0 2.25
w
5 ~ 2.00

0
. /V ~
ill 1.75
~

..,. V = 1/....
5 i5 a 1.50
..,. l..--'" Ww
UN
./
V
~~ 1.25

5
~
V ~~
~~ 1.00 ~
V
V .2:-
;;: ,~
l..--'"
~ g;
.
c
0.75
,...... I.;""
VGS = 10V
5 in'
Q
0.50 10= 1.5A
= 0.25
i I

0.75 0
-60 -40 -20 20 40 60 80 100 120 140 -60 -40 -20 20 40 60 80 100 120 140
TJ• JUNCTION TEMPERATURE (oC) TJ.JUNCTION TEMPERATURE 1°C)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-168
 IRF510, IRF511, IRF512, IRF513 Devices
500 20
JGsJ
f= 1 MHz
I I _ ;;;
400
Cisa = Cgo. Cgd. Cd. SHORTEO :; )OS = 2bv '""
~ 15
VpS=5~V,-----
~V
C", = Cgd -
... Cgs Cgd
w
to Vas = 80V,IRF510, 51~
~

300
COlI = Cd.· ego. Cgd
- '"
:;
0Y
w
u o
...z>- "'Cd•• Cgd >
w
~ 10
/
;:;
~
Iff
=>
~
u 200
o
"I I
.I o

" t\.. :;;

u-

1\ I 'r--
Ciss

C~
...'">-
u, 5 IL
100

\
to
>
I 10 =8A

~ C~
V sr
FOR TEST CIRCUIT
FIGiRE lj
r---

10 20 30 40 50 4 10
VOS. ORAIN·TO.sOURCE VOLTAGE (VOLTS) Og' TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to-Source Voltage

2.0
ROS(on) MEASURED WITH CURRENT PULSE OF
2.0!,s DURATION. INITIAL TJ = 25 0 C. (HEATING .. r--' -

EFFECT OF 2.,"S PULr IS MINIMALl

f"""

'"r--.. IRF5~3' ~~
5
.1 .,1 ..........
VGS = 10V
........~ "RF510, 511

........
~!'.
V ~
VGS=20V '" ~

10 15 20
o
25 50 75 100 125
~ ,
150
10, DRAIN CURRENT (AMPERES) TC. CASETEMPERATURE (OC)

Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
20

'\
'" r\
'\
I\..
\

o
o 20 40 60 80 100
TC. CASE TEMPERATURE (OC)
'"'" 120
~.
140

Fig. 14 - Power V,. Temperature Derating Curve

0-169
IRF510, IRF511, IRF512, IRF513 Devices

VARY tp TO OBTAIN

iDEAKI~uT
VGS"trtPL'

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN,
SPECIFIED 10 RL

PULSE
O.U,T.
r-----..,
GENERATOR

I
50n I o - - - T O SCOPE
I O.OIn
I I 50n HIGH FREUUENCY
L_ _ __ .J SHUNT

Fig. 17 - Switching Time Test Circuit

,----0 +VOS
(lSOLATEO
SUPPL YI

SAME TYPE
AS OUT

o~1'5mA - OUT

V\.f\,_ _-,,"IV'''''''-o -VOS

IG 10
CURRENT -::.- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-170
 PD-9.313

INTERNATIONAL RECTIFIER II~iR I

HEXFET® TRANSISTDRS IRF52D
IRF521
N-Channel IRF522
IRF523

100 Volt, 0.3 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
The HEXFET® technology is the key to International Recti-
• Fast Switching
fier's advanced line of power MOSFET transistors. The effi- • Low Drive Current
cient geometry and unique processing of the HEXFET design • Ease of Paralleling
achieve very low on-state resistance combined with high • No Second Breakdown
transconductance and great device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well estab- Product Summary
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Part Number VOS RDS(on) 10
paralleling, and temperature stability of the electrical param-
IRF520 100V O.30n B.OA
eters.
IRF521 60V O.30n B.OA
They are well suited for applications such as switching power IRF522 100V O.40n 7.0A
supplies, motor controls, inverters, choppers, audio amplifi-
ers, and high energy pulse circuits. IRF523 60V O.40n 7.0A

CASE STYLE AND DIMENSIONS

10.66 (0.420)
TERM 3 - SOURCE
MAX.

5.3310210)

t 4.8310.190)

.i!ECTlON x-x
14.73 (0.580)
MAX. 1.1410.045)
0.3110.0121
D
i ~
aII0.1I5)
TI----l
1.1410.045)
0.5110.020)
1.0410.080)

ACTUAL SIZE Case Style TO-220AB

Dimensions in Millimeters and (Inches)

0-171
IRF520, IRF521, IRF522, IRF523 Devices

Absolute Maximum Ratings

Parameter IRF520 IRF521 IRF522 IRF523 Units
VOS Drain - Source Voltage (j) 100 60 100 60 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) (j) 100 60 100 60 V
10 @ TC_ = 25°C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10@TC=100oC Continuous Drain Current 5.0 5.0 4.0 4.0 A
10M Pulsed Drain Current @ 32 32 28 28 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 40 (See Fig. 14) W
Linear Derating Factor 0.32 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = l00I'H
A
32 I 32 I 28 I 28
TJ Op~rating Junction and
-55to 150 °C
Tstg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF520
IRF522
100 - - V VGS = OV

IRF521
IRF523
60 - - V 10 = 25Ol'A

VGSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 250J.<A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
All
- - 250 I'A VOS = Max. Rating, VGS = OV
- - 1000 J.<A VOS- - Max. Rating x 0.8, VGS - OV, TC - 125°C
10(on) On-State Drain Current ® IRF520
8.0 - - A
IRF621
VOS ) 10(on) x ROS(on) max.' V GS = 10V
IRF522
IRF523
7.0 - - A

ROS(on) Static Drain-Source On-State IRF520

Resistance ® IRF521
- 0.25 0.30 !l
Vmi = 10V, 10 = 4.0A
IRF522
IRF523 - 0.30 0.40 II

9fs Forward Transconductance ~ All 1.5 2.9 - S (0( V OS ) 10(on) x ROS(on) max.' 10 = 4.0A
Ciss Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss .output Capacitance ALL - 200 400 pF
See Fig. 10
erss Reverse Transfer Capacitance ALL - 50 100 pF
tdlonl Turn-On Delay Time ALL - 20 40 ns VOO = 0.5 BV OSS ' 10 - 4.0A, Zo = 500
tr Rise Time All - 35 70 ns See Fig. 17
td(off)' Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
Fall Time All - 35 70 ns independent of operating temperature.)
tf
Qg . Total Gate Charge V GS = 15V, 10 = lOA, VOS s 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 10 15 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature:)
Qgs Gate-Source Charge ALL - 6.0 - nC

Qgd Gate,Orain ("Miller"l Charge ALL - 4.0 - nC

lO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

$
center of die.

lS Internal Source Inductance All - 7.5 - nH Measured from the

source lead, '6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-ta-Sink Mounting surface flat. smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-172
 IRF520, IRF521, IRF522, IRF523 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF520 Modified MOSFET symbol
(Body Diode) IRF521 - - B.O A
showing the integral
IRF522 reverse P-N junction rectifier.
-

~
- 7.0 A
IRF523
ISM Pulse Source Current IRF520
(Body Diode) ® IRF521
- - 32 A

IRF522
IRF523 - - 2B A

VSD Diode Forward Voltage ® IRF520

- - 2.5 V TC = 25°C, IS = B.OA, VGS = OV
IRF521
IRF522
IRF523 - - 2.3 V TC = 25°C, IS = 7.0A, VGS = OV
trr Reverse Recovery Time ALL - 2BO - ns TJ 150°C, IF B.OA, dlF/dt - 100Al"s
ORR Reverse Recovered Charge ALL - 1.6 - "C T J - 150°C, IF = B.OA, dlF/dt = 100A/"s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'
<D TJ = 25°C to 150°C. ® Pulse Test: Pulse width .. 300"s, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20

-~",PUl~ETEst il
20
/IOJ ao lIS PULSE TEST
I I

IS
I
1/ 9~- - IS
vas> 10(on) x ROS(on) max. IJ
iii I // /
TJ=112501~

ffi
!I!
5 12 L 8V-
- \25°1~
11 Y
TJ - _55 0,,,,,,
>- 1
I '11
~ i-
az VGS- 7 ~
I~ V
~
c sl-
- rJ'
E
"r /I
5V-
- ~"
10 20 30 40
VOS, ORAIN·TO.sOURCE VOLTAGE IVOLTS)
4~-
- 50 2
~ W
4
VGS, GATE·TO.sOURCE VOLTAGE (VOLTS)
B 10

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

10
100m~~
50
OPERATION IN THIS
AREA IS LIMITEO

tV;
-IRF520 1 BY RDS(on)
80 ,IJ PU LSE' TEST r-- .......10-
//V"~J/
r ~
20 :-11 R~522r 3 K.1"l+lct-'·'*+-ct-'''I:+-t+t~10t'.--t--t-1H-Hf-H

h If//,,7V
~ 10 c:IRJ520~~
... 100",

WJ if' ~ ~,1RF522,3

IiV VGS=sv-

)
,
~
Vii V
J. ~
~ I--
_5Y

It- 4y
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTSI VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-173
IRF520, IRF521, IRF522, IRF523 Devices

~
in
z
<
cc_
1-1- 1.0
wz
>'" 0=0.5
tffi 0.5

..
NOTES:
~e:.

~
u..w
w .... f-b.2
ffi!i 0.2
NO
::;~
f--O.l
.........
~! 0.1 FO.05
"'0<....
z_~ 0.05 r-0.02 ~ ~2~
....w 1. DUTY FACTOR, 0 = :~
}~ ~~
E.... 0.02 wrn
SINGLE PULSE (TRANSIENT
AL Irp~OANICE\ I 2. PER UNIT BASE = RlhJC = 3.12 OEG. CIW.
3. TJM - TC = POM ZlhJC(I).
~ 0.01 I IIII I I I
10-5 10-1 1.0 10
11. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs_ Pulse Duration

~ -550~--= C::=
-... -
TJ

V
f..- -TT=250b-
-= i 10
2

TJ = 25 0C
./ ~ :E
--.
/ /'~ TJ ~ 1250~
:!
~

~ ..,""""" ..... ~
TJ;150 0C
--
// ....- l.-I-- a:
13
z
'#'

,
J)~
!J . . . V
vos> 10(on) x ROS(on) max.
80 is r
PULS TEST
~
o
W

'"
a:
w
G;
0::
,r
E
10

. -TJ = 1500C

'II
I
I

I ~
TJ7250C
1.0 I
12 16 20 o
10. DRAIN CURRENT (AMPERESI VSO. SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs_ Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.2

w
to
w
....
~ 1.15 z 1.8 ~
o <
/~
".. ~
> I;;
~ in
w
",. i--""""
o cc
o
~s 1.05
z
06 1.4
Ww
/
ww
CCN
"'::;
w< ./
.".,. .... N
cc-
"'0<.... ./
~~ .".,. "1'"
OCC V
"'0
5Jo ~ 0.95 ./ ~o
z·z- 1.0
/'
V
..,.
z
~
o
~
0.85
" <i
cc
0
]
;;;
0 0.6
./
~ VGS = 10V
10=3A - f--

" r
0::
0
1;; I
0.15 0.2
-40 40 BO 120 160 -40 40 80 120
TJ.JUNCTION TEMPERATURE (OCI TJ. JUNCTION TEMPERATURE (DC)
Fig_ 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-174
 IRF520, IRF521, IRF522, IRF523 Devices
1000
20
GS = 0
1J
I I f= 1 MHz I
Cia = CIIl + Cgd. Cd. SHORTED _
BOO r--
Cra = Cgd ~ VoSt20V,,-
'" 15
- r-- <::
~~
C... =Cds+~
C Cgd Vos = 50V ~
...
.e 1\ III gd
w
'"~«
I
Vos = BOV, IRF520, 522
600 "'Cds + Cgd - r-- r--
...zw r-
«
....
t;
...
«
.......
« 400
\' ~
\ -- 1
Ciss
'">
~ 10
a:
:::>

'""I
'"~
~
~ ~
~
200 \ r-.... ........ Co..
!;;:
'"U, 5
II 10= lOA
J
to

\ T
CISS
>
FOR TEST CIRCUIT
~

w w 40 ~ ~
V rFlrEJ

12 16 20
VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTS) Ilg, TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to·Source Voltage
O.B 10
0;
:IE
:.:
g
...zw VG = 10V .........
« 0.6 .........
~
in
w
--. .........
a: 1-0.......................
,
IRF520 521
z ............... '

...'"a:w 0.4 IRF522, 523

:::-......t'-.
........... . ' "

,)
:::>

'""I l,..oo r-..... ~

'"~
;;:
a:
'" 0.2
-f-- -""-J:;:"20V
I':~
~~
~
a: '" -~OS(on) MEASURED WITH CURRENtULSEiOF _
2.0 itS DURATION. INITIAL TJ = 25 0 C. (HEATING - '\,
EFFECT OF 2.0". PULSE IS MINIMAL.)
o
10 20 30 40 25 50 75 100 125 150
10• DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (OC)
Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35 '\
0;
30 ~
l=
«
~
z 25 ~
'" '\
::>= 20 r\.
ill
E
a:
w
;= 15
'\
...'"
.P 10
"\
i".,
\
20 40 60 BO 100 120 140
TC, CASE TEMPERATURE (OC)
Fig. 14 - Power Vs. Temperature Derating Curve
0-175
IRF520, IRF521, IRF522, IRF523 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGS-R
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
GENERATaR O.U.T.
r-----.,
I
I
50n I 0---.
O.Oln
TO SCOPE

I ___ ..II son 10! HIGH FREQUENCY

L_ SHUNT

Fig. 17 - Switching Time Test Circuit

. - - - 0 +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

o~·5mA - IG
OUT

,..-......--"''''-0 -VOS
10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-176
 PD-9.307

INTERNATIONAL RECTIFIER II'~R I

HEXFET® TRANSISTDRS IRF53D

IRF531
N·Channel IRF532
IRF533

100 Volt, 0.18 Ohm HEXFET Features:

TO·220AB Plastic Package • Compact Plastic Package
The HEXFETe technology is the key to International Rectifier's • Fast Switching
advanced line of power MOSFET transistors. The efficient • Low Drive Current
geometry and unique processing of the HEXFET design achieve
very low on-state resistance combined with high transconductance
• Ease of Paralleling
and great device ruggedness. • No Second Breakdown
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well established
advantages of MOSFETs such as voltage control, freedom from Product Summary
second breakdown, very fast switching, ease of paralleling, and
temperature stability of the electrical parameters. Part Number VOS ROS(on) 10
IRF530 100V 0.18n 14A
They are well suited for applications such as switching power
supplies, motor controls, inverters, choppers, audio amplifiers, IRF531 60V 0.18n 14A
and high energy pulse circuits. IRF532 100V 0.25n 12A
IRF533 60V 0.25n 12A

CASE STYLE AND DIMENSIONS

~
10'66 (0'4201~ TERM 4-
3.42 (0.1351 9.66 (0.3801 DRAIN

10.66 (0.420)
MAX. T*~~ TERM 3 - SOURCE

16.51 (0.6501

+-J
14.23 (0.5601

1~:r-~IN. T
6.35 (0.2501
MAX. 5.33 (0.2101
f 14.13 (0.5601 X ~ 4.83(0.1901

L
14.73 (0.580) .i!ECTION x-x
0
Mr· 1.14 (0.D451
a:mn:mJ T J-...--.I
1.14 (0.D451
1.11 (0.0101
-i
2.92 (0.1151
ffi1D]2tii
1.15 (0.D451 2.D4 (0.D601

ACTUAL SIZE Case Stvle TO·220AB

Dimensions in Millimeters and (Inches)

0-177
IRF530, IRF531, IRF532, IRF533 Devices

Absolute Maximum Ratings

Parameter IRF530 IRF531 IRF532 IRF533 Units
VOS Drain - Source Voltage <D 100 60 100 60 V
VOGR Drain - Gate Voltage (RGS - 1 Mil) (j) 100 60 100 60 V
10@TC=25°C Continuous Drain Current 14 14 12 12 A
10@TC = 100·C Continuous Drain Current 9.0 9.0 8.0 8.0 A
10M Pulsed Drain Current @ 56 , 56 48 48 A
VGS Gate Source Voltage
M ±20 V
PO@TC= 25·C Max. Power Dissipation 75 (See Fig. 141 W
Linear Derating Factor 0.6 (See Fig. 141 W/K
ILM Inductive Current, Clamped (See Fig. 15 and 161 L = 100"H
A
56 I 56 I 48 I 48
TJ Operating Junction and
-55to 150 ·C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mml from case for 10s1 ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF530
IRF532
100 - - V VGS = OV

IRF531
IRF533
60 - - V 10 = 250,..A

V GS(thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS' 10 = 250"A
IGSS Gate-Source leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 "A VOS = Max. Rating, VGS - oy
- - 1000 "A VOS = Max. Rating x 0.8, VGS = OV, TC = 125·C
10(onl On-State Drain Current ® IRF530
14 - - A
IRF531
V OS ) 10(onl x ROS(onl max.' V GS = 10V
IRF532
IRF533
12 - - A

ROS(on) Static Drain-Source On-State IRF530

- 0.14 0.18 II
Resistance ® IRF531
VGS = 10V, 10 = 8.0A
IRF532
IRF533
- 0.20 0.25 II

9fs Forward Transconductance @ ALL 4.0 5.5 - S(!J1 VOS ) 10(onl x ROS(on) max.' 10 - 8.0A
Ciss Input Capacitance ALL - 600 800 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 300 500 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 100 150 pF
td(onl Turn-On Delay Time ALL - - 30 ns VOO = 36V, 10 = S.OA, Zo = 1511
tr Rise Time ALL - - 75 ns See Fig. 17
td offl Turn-Off Delay Time ALL - - 40 ns , (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 45 ns
Qg Total Gate Charge V GS = 10V,I 0 = 1·8A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate·Drain)
ALL - 18 30 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gS Gate-Source Charge ALL - 9.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 9.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25

$
in.) from package to
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.1 from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to·Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-178
 IRF530, IRF531, IRF532, IRF533 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF530 Modified MOSFET symbol
- - 14 A
(Body Diode) IRF531 showing the integral
reverse P-N junction rectifier.

~
IRF532
IRF533
- - 12 A

ISM Pulse Source Current IRF530

(Body Diode) @ IRF531
- - 56 A

IRF532
IRF533
- - 48 A

VSD Diode Forward Voltage ® IRF530

- - 2.5 V TC ~ 25°C, IS ~ 14A, VGS ~ OV
IRF531
IRF532
- - 2.3 V TC ~ 25°C, IS ~ 12A, VGS ~ OV
IRF533
t" Reverse Recovery Time ALL - 360 - ns T J ~ 150°C, IF - 14A, dlF/dt - 100A/!,s
ORR Reverse Recovered Charge ALL - 2.1 - !,C T J - 150°C, IF = 14A, dlF/dt - 100A/!,s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j)TJ = 25°Cto 150°C. ® Pulse Test: Pulse width .. 300!,s, Duty Cycle .. 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20 20

aL, I--lO",P~LSETE~T /1
10Vya;v
PU iSE TEJT _ - t I
16
I
7V_
- 16
VOS> 10(on) x ROS(,n) max. I(
I J
/I
, VGS=6V=

I
=
/h
rJ
'(II
V y- - TJ = +12S'C !JV
~ Ifl
TJ = 2S'C

10 20 30 40
4V-
- so
- TJ = jssoc
~V
10
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

10
100
= IRF530, 1'-
OPERATION IN THIS
AREA IS LIMITED BY ROS(on)
80~sPULSETEST
!OJ ffi V 50
-IRFS32,3

9~~ ~ ~/ /' I I I I, " 10 MS

vr
20
8V~ IRF530,1
~ V '"
w
~:E
10 = IRF532. 3
100 M'

J 'l /'
6\"/
~
z>-
1 ms

.~ ~ /
-
w
c:
c:

~ '/
1
I-- ~ 10 m'
~y ,..... ~5V
z
;;:
c:
c
1.0
100
DC
m,

A~ ./'
E O.S =
=TC- 2SoC
TJ ISO'C MAX.
_ RthJC = 1.67 K/W
~
IA- i GS = 41
0.2 _tiGLj pmEl1

0.1 I I11111 lRFj31(~ IRtsfO' j-

0.4 0.8 2.0 1.0 S 10 20 50 100 200 SOO
VOS. ORAIN-TO·SOURCE VOLTAGE (VOLTS) VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-179
IRF530, IRF531, IRF532, IRF533 Devices

I-
ao:
in
I I
z
<
0:_
1-1- 1.0
I
wz
>:::>
>=0:
0=0.5
0.5 NOTES:
~~ -~.2
wu
oZ
w< 0.2
NO 0.1
_i~~~~~~~~~
-w
~ ...

1~~lj~~~S~I!EPULSE(TRANSIENT ~2-.i
<", 0.1 0.05
"'-
0: ~
0< -0.0
z.~ 0.05 ~0.01
Uw
:<1:>::
",I-

~
-
E
I ---f-+-+--+++++. i,HERMIALI IMP,EoA NICEI) 1II,+--+-I---I-++++-++I---I-+-+-+-!.,-f++++--+-+
0.02 1--+--+--+-++-I-+1I-1I+-
I-+--+-_+-
I
I. DUTY FACTOR, 0 = ttl
•
IH-f-I-H+--+-+---l-+-+++++f-+-+--++-++-H-++--+-+ 2. PER UNIT BASE = RthJC = 1.67 oEG. CIW.
2

j II I I I I I II 3. TJM - TC = PoM ZlhJC(I).

0.Q1
10-5 10-2 1.0 10
II, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to·Case Vs. Pulse Duration

10
I

-
102
iii Tr 25 0 C
~
..,I-- ~ Z-25 b
TJ =-55 0 C
'"
:5
I- ~ I"-TJ = 150 0 C
Z
0 W
0: /'
V ..........
a:
:::>
U
z
~
TJ = 125 0 C ;;:
a: 10 /I
c

II ~. . . V w
'"
~ TJ = 150'C I

'LI vos> 10(on) x ROS(on) rax.

80(' PULjE rEsi
~
0:
<i:
E'
~.
I
I TJ = 25'C
1.0 11 I
10 15 20 25 o
10, DRAIN CURRENT (AMPERESI VSO, SOURCHO·ORAIN VOLTAGE (VOLTS)

Fig_ 6 - Typical Transconductance Vs_ Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25

w 2.2

;'"o 1.15
w

" . i-'
> U
z Z 1.8
~
;0
o ~ /
c
~a 1.05 ~ i3
0:
V
Ww
...w<:::;
O:N ~~ z
Co 1.4 ./
..".. Ww
~~ ~
UN
0: -
~~
V
~~ 0.95
./ 0/'" /'
./
"
c cO:
1.0

.
~
0:
1- 0
Z:~
;;:
0:
,/
C
~ 0.B5
C

~ O.S V VGS= 10V_

10· SA
~

~ ~
0: 1 I
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATURE (DC) TJ, JUNCT! ON TEMPERATU RE(DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance V,. Temperature
0-180
 IRF530, IRF531, IRF532, IRF533 I)evices
20

2000

I ~GS' J
VOS" 20V
I I f" 1 MHl
I I I I I ~
1600 Ciss = Cgo + Cgd. Cd. SHORTED - VOS" 50V

~V
""~
CBS = Cgd I I
VOS" BOV.IRF530. 532
_ Cgo Cgd
-
, Coss - Cd. + ego + Cgd
- V
"'Cd.+ Cgd
A~
~ .I
C1SS
I

\ /
400 :\ ~
\
- - cL
C;"
/
j 10"'BA

T Ii
FOR TEST CIRCUIT

FIGrRE
I--

10 20 30 40 50 16 24 32 40
VOS. DRAIN-TO SOURCE VOLTAGE (VOLTS} Og. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

20
0.6
u; Ros(L~ MEASUIREO WITH I CURREN~
PULSE o~
'"
:t:
8 0.5 f--
2.0!-lS URATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 !-IS PULSE IS MINIMAL.) - 16
.,w
Z
~
U)
........
iiia: 0.4 .........
z VGS = 10V ........ ......... ..... ...........
0
.,w ...... ~RF530.531
0.3
......... ~
::::~
a:

j
=>
0

----
U)
..,.
r'" ~
0

z 0.2
~
c
- _V ~
~c 0.1
VGS -r OV ~.,
a:

o
10 20 30 40 50 60 25 50 75 100 125 150
10' ORAIN CURRENT (AMPERES) Tc. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

80

70
- "'\.
60
"'\.
f!i
~
« '\
~ 50
z
'-
0
>=
O!: 40
'\

,"
tli
c
a:

~
30
'\
.P 20

10 \.
\
20 40 60 60 100 120 140
TC. CASE TEMPERATURE IOC)

Fig. 14 - Power Vs. Temperature Derating Curve

0·181
IRF530, IRF531, IRF532, IRF533 Devices

VARY tp TO OBTAIN
REQUIRED PEAK Il

VGs·R Il_---<~-~.......W\.---I

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

VOO "36V

_ , . -_ _ Vo

TO SCOPE

Fig. 17 - Switching Time Test Circuit

,.---0 +VOS
(ISOLATED
SUPPL YI

SAME TYPE
AS OUT

o~l.5mA - OUT

--'\.fV',,......-'VV\.,---o -VOS
16 10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-182
 PD-9.373

INTERNATIONAL RECTIFIER II~)R I

HEXFET® TRANSISTORS IRF54D
N-CHANNEL
IRF541
POWER MOSFETs IRF542
IRF543
100 Volt, 0.085 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
The H EXFE1'" tech nology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFETtransis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state • No Second Breakdown
resistance combined with high transconductance • Excellent Temperature Stability
and great device ruggedness.
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as volt-
age control, freedom from second breakdown, very Part Number VOS ROS(on) 10
fast switching, ease of paralleling, and temperature IRF540 lOOV O.085D 27A
stability of the electrical parameters. IRF541 60V O.085D 27A
They are well suited for applications such as switch- IRF542 lOOV O.lm 24A
ing power supplies, motor controls, inverters, chop- IRF543 60V O.lm 24A
pers, audio amplifiers, and high energy pulse circuits.

~ 9.ssill3aO)
CASE STYLE AND DIMENSIONS 3.4110.1351
10 66 (o.410)~

t+""
1.5410.1001 4.08 (0.1611

10.66 (0.420)
TERM3-S0URCE
MAX.
16.5110.650)
14.1310.560)

1~OOFIN
+-
T
6.3510.1501
MAX.
5.3310.210)

t
::fj~'
4.8310.190)

14.73 (0.580)
MAX.
.-L 1.14 (0.045)
0.31(0.012)
l!ECTION
II
L....J
x-x

i 1.7710.070) ~
2.9210.115)
tl----l
1.14 (0.045)
0.5110.020)
1.1510.045)
2Mi(j]801

ACTUAL SIZE Case Style TO·220AB

Dimensions in Millimeters and (Inches)

0-183
IRF540, IRF541, IRF542, IRF543 Devices

Absolute Maximum Ratings

Parameter IRF540 IRF541 IRF542 IRF543 Units

VOS Drain - Source Voltage CD 100 60 100 60 V

VOGR Drain - Gate Voltage (RGS = 1 Mll) <D 100 60 100 60 V
10@TC= 25·C Continuous Drain Current 27 27 24 24 A
10@TC = 100·C Continuous Drain Current 17 17 15 15 A
10M Pulsed Drain Current @ 108 108 96 96 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25·C Max. Power Dissipation 125 (See Fig. 14) W
Linear Derating Factor 1.0 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 1OO~H
A
108 I 108 I 96 I 96
TJ Operating Junction and
-55to 150 ·C
Tstg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for 105) ·C

Electrical Characteristics@TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF540
100 - - V VGS = OV
IRF542
IRF541
IRF543
60 - - V 10 = 250~A

VGSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = ·20V
lOSS Zero Gate Voltage Drain Current - - 250 ~A VOS = Max. Rating, VGS = OV
ALL
- - 1000 ~A VOS - Max. RatingxO.8, VGS - OV, TC - 125·C
10(on) On-State Drain Current (2) IRF540
- -
27 A
IRF541
VOS ) 10(on) x ROS(on) max.' V GS - 10V
IRF542
IRF543
24 - - A

ROS(on) Static Drain-Source On-State IRF540

Resistance ® IRF541
- 0.07 0.085 0
VGS= 10V, 10 = 15A
IRF542
IRF543
- 0.09 0.11 0

9fs Forward Transconductance (g) ALL 6.0 10 - S (Ill VOS ) 10(on) x ROS(on) max.' 10 - 15A
Ciss Input Capacitance ALL - 1275 1600 pF
VGS = OV,VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 550 806 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 160 300 pF
td(on) Turn-On Delay Time ALL - 16 30 ns VOO = 30V, 10 = 15A, Zo - 4.70
tr Rise Time ALL - 27 60 ns See Fig. 17
tdloffl Turn·Off Delay Time ALL - 38 80 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 14 30 ns
Qg Total Gate Charge V GS = 10V, 10 = 34A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate·Orain)
ALL - 38 60 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 17 - nC

Ogd Gate·Orain ("Miller") Charge ALL - 21 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in~ I from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
Junction-to-Case
Case-to-Sink Mounting surface flat, smooth, and greased.
Junction-to-Ambient Free Air Operation

0-184
 IRF540, IRF541, IRF542, IRF543 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF540 Modified MOSFET symbol
(Body Diode) IRF541
- - 27 A
showing the integral
reverse pwN junction rectifier.

~
IRFS42
IRFS43
- - 24 A

ISM Pulse Source Current IRFS40

(Body Diode) ® IRF541 - - 108 A

IRF542
IRFS43
- - 96 A

VSD Diode Forward Voltage @ IRFS40

IRF541
- - 2.S V TC = 2S DC,IS = 27A, VGS = OV
IRFS42
IRFS43
- - 2.3 V TC = 2S DC,IS = 24A, VGS = OV

Reverse Recovery Time ALL - SOO - ns T J - 150DC,I F 27A, dlFldt 100AI~s

t"
QRR Reverse Recovered Charge ALL - 2.9 - ~C TJ = I 50 DC, IF - 27A, dlFldt = 100AI~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by lS + LO'
ID TJ = 2S DC to I SODC. @PulseTest: Pulse width'; 300~s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

50 50

V 80", PU LSETEST
",I,PULSE I,TEST /"
40
10V 9V
B~
40
80
VOS> ID(on) x Tr -55°C"
1 1/ /
RDS(on) max.
[if [if TJ = 25 0 C"'-
Z' /
...~ '"
~ T~ = 125bc",-
H/
'"....
~ 30 '"
~ 30

i:'l
'"
7y ...!z
'"
/1/
'"::>
'"
z 20
'"
::>
'"
z 20 //
:;;:
'"
0
VGS = B~ ~
o 'II
E
10
E
10 I
10 20 30
5~
4~
40
VDS, DRAIN·TO.sOURCE VOLTAGE (VOLTS)
50
.i
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
10

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

1000
50
I' /' 500
~
/V ~ OPERATION IN THIS
40 -SOLpUJETEJ
~ 9V
, ..",.".
200
AREA IS LIMITED
BY RDS(on)
[if 'l ,BV '"w
'"w 100
f-IRF540,1

...~ ~~ ~ ~ ~ IRF542, 3

....'"
~ 30 ~ lOps
.... 50

~ ~ ~ ........ ... 7V
~ IRF540,1
IT"'
'"
~V '"
::> ::> 20 f- IRF542, 3
'"z '"
z ~s
:;;:
'"0
20

I~V VGS =BV

;;'\
0

E
10
it
1=
1= 2510 c i
1

E ~~

~
TJ = 150 0 CMAX.

10
~ R1.hJC = 1.0 KIW lOms

5V r- ~INIGL~ P~ISi II 100 ms

IRF541,3
~ 4V
1.0 JU 111 IRF540:2 DC L
1 1.0 10 20 50 100 200 500
VOS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TD-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-185
IRF540, IRF541, IRF542, IRF543 Devices

....
1ii
0;
z

.-
<
:=i=
wz 1.0
>::> D =0.5
;:: 0: 05
NOTES:
~~ .
woo
~ ~ 0.2
!:::!~ 1--0.1
1-6.2

......
....... ~~
FUL
~2~
-'~
~! 0.1 FO.05
0:-'
0< 1-0.02
z~~ 0.05
1. DUTY FACTOR. D = :~
oow
:2" ~0.01 SINGLE PULSE (TRANSIENT
€I- ~
THERMAL IMPEDANCE) 2. PER UNIT BASE =RthJC =1.0 DEG. CIW.
~ 0.02
:2 3. TJM - TC =POM ZthJC(t).
N 0.01 I I II III I
10-5 10-4 10-3 10-2 2 10-1 1.0 10
'1. SQUARE WAVE PULSE OURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

-
~
TJ =-55 0C 50
~ ~

-
~
~
'"0:
A~
W
JJ = 2JC
W

/ !ii
~
20
'l
V~ ~ mic ....

IV ",.
Tj = 1ii
~ 10
1';
/J
z I I
UV ;;:
0:
o I

rl 80 ps PULSE TEST
I I I
W

'"
[:i
~ - TJ =1500C
I
II
Vos> 10(on) x ROS(on) max. 0:
oi:
E TJ =25 0C
I I
1.0
I I
10 20 30 40 50 o 0.4 O.B 1.2 1.6 2.0
10. ORAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w
00
z
~ 2.0

,..",.
.,.., ~
iii0:
W
!<
./
, ~

tia
zw
1.5
,,/ '" ON
w:::; /
/
00<
"':IE
....V ::>", ~
.,.z~~ 1.0
/

~ ~
;;: / VGS = IOV
0: ~ I I
C 10= 16A
C
Q
0.5

~
0.75 o
-40 40 BO 120 160 -40 40 80 120 160
TJ. JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig.8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On·Resistance Vs. Temperature
0·186
 IRF540, IRF541, IRF542, IRF543 Devices
2000

-
Cia' Cgs + Cgd. Cds SHORTED
C", -Cgd _VGS=OV
.l J. 20

Cgs Cgd f = 1 MHz

1600 NCo" - Cds + Cgs + Cgd
"""" "'Cds+Cgd g
'" 15

~~
"'- 2 VOS-30~~
! 1200
\, CiSS
w
'"
"':;
I I
vos = 50V,

~
u I '""'-.,
z vos = 80V,IRF540. 54~ ~
;:!: '">
~ 10
~ 800
\. '":::>
'""I
V//
..; ......... 1'-00..

-
'"
:;:;

\ ~ r-- ~
'",;, / '0 - 34A
FOR TEST CIRCUIT-
400
'" / SjE FlGUt E 18 I

"
>
cL
10 15 20 25 3D 35 40 45 50
I 20 40 60 80
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge V,. Gate-to-Source Voltage
30
0.3

.."
u;

8
w
u
z
ROS(on! MEASU RElo WITH C)RRENT puLSE OF
2.01" DURATION. INITIAL TJ = 25 0 C. (HEATING
,... EFFECT OF 2.0 1" PULSE IS MINIMAL.)
24
I' ,
--.. ......... .......... ~
"
In I
~
....
"'~
0.2 ~
ili
'"z ~ 18 IRF540.541
'"uw
VGS - 10V t-
z
w
.... ~~
'"
:::>
a:
a: IRF542. 543 ""~
:::>
'""I
'">7z
;;: 0.1
V
J u
z 12
;;:
a:
0>
~
~
'"
'"c
.,
0 -~ -k;;::V E
'~
CI
'" \,
20 40 60 80 100 120
o
25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current V,. Case Temperature

140

120
--- -
"' , ~
'\

"', '\
~

20
"''"",
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

D-187
IRF540, IRF541, IRF542, IRF543 Devices

VARY Ip TO OBTAIN
~EQUIRED PEAK IL

VGS'~ DUT

IL_-~()---""JW~

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

30V
ADJUST RL TO OBTAIN 3.0n
SPECIFIED 10
VOS

r;U~ - - o-lr----O----"J-:* O.U.T.

I GENERATOR
I :J~RCE
IMPEDANCE
Il I
L ___ J

Fig. 17 - Switching Time Test Circuit

r---o() +VOS
(ISOLATED
SUPPLY)

SAME TYPE
AS OUT

o~·5mA - IG
OUT

\I"'_-""rv-o -VDS
10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-188
 PD-9.326

INTERNATIONAL RECTIFIER II~)R I

HEXFET® TRANSISTDRS IRF61D

IAF611
N-Channel IRF612
IAF613

200 Volt, 1.5 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
The HEXFETs technology is the key to International
• Fast SWitching
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the • Ease of Paralleling
HEXFET design achieve very low on-state resistance • No Second Breakdown
combined with high transconductance and great
device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Part Number VOS ROS(on) 10
switching, ease of paralleling, and temperature stabil-
ity of the electrical parameters. IRF610 200V 1.50 2.5A
IRF611 150V 1.50 2.5A
They are well suited for applications such as switching IRF612 200V 2.40 2.0A
power supplies, motor controls, inverters, choppers,
audio amplifiers, and high energy pulse Circuits. IRF613 150V 2.40 2.0A

CASE STYLE AND DIMENSIONS TERM 4-

DRAIN
I... 1.39 (0.055)
I 0.51 (0.020)
10.66 (0.420)
MAX.

~I "£.:i~~
u2(0.;;f

2.19(0.110)
~

t
14.73 (0.580)
5.33 (0.210)
4.83 (0.190)

Mr·
~ECTIONX-X
1.14 (0.D45) r-l
DJllm1l T j::::;j
) 1.14 (0.D45)
~ (0.116) DJllQ.D2DI
2.D41D.liIOf
ACTUAL SIZE Case Style T0-220AB
Dimensions in Millimeters and (Inches)

0-189
IRF610, IRF611, IRF612, IRF613 Devices

Absolute Maximum Ratings

Parameter IRF610 IRF611 IRF6i2 IRF613 Units
VOS Drain - Source Voltage <D 200 150 200 150 V
VOGR Orain - Gate Voltage (RGS - 1 Mill G) 200 150 200 150 V
10 @TC - 25°C Continuous Drain Current 2.5 2.5 2.0 2.0 A
10@ TC ~ 100°C Continuous Drain Current 1.5 1.5 1.25 1.25 A
10M Pulsed Drain Current @ 10 10 8.0 8.0 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25°C Max. Power Dissipation 20 (See Fig. ,14) W
Linear Derating Factor 0.16 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = lOOI'H
A
10 I 10 I 8.0 I 8.0
TJ Operating Junction and
-55.to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF610
IRF612
200 - - V VGS = OV
IRF611
IRF613
150 - - V 10 = 25Ol'A
V GS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS = VGS, 10 = 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain C;:urrent.
ALL
- - 250 I'A VOS = Max. Rating, VGS = OV
- - 1000 I'A VOS = Max. RatingxO.8, VGS = OV, TC = 125°C
10(on) On-State Drain Current ® IRF610
2.5 - - A
IRF611
VOS ) 10(on) x ROS(on) max.' V GS = 10V
IRF612
IRF613
2.0 - - A

ROS(on) Static DraIn-Source On-State IRF610

Resistance ® IRF611
- 1.0 1.5 0

IRF612
VGS = 10V, 10 = 1.25A
- 1.5 2.4 0
IRF613
9fs Forward Transconductance ® ALL 0.8 1.3 - S(ll! VOS ) 10(on) x ROS(on) max.' 10 = 1.25A
Ciss Input Capacitance ALL - 135 150 pF
VGS = OV, VOS ~ 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 60 80 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 16 25 pF
td(on) Turn-On Delay Time ALL - 8.0 15 ns VOO ~ 0.5 BVOSS,IO = 1.25A, Zo = 500
tr Rise Time ALL - 15 25 ns See Fig. 17
tdloffl Tu'rn-Off Delay Time ALL - 10 15 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 8.0 15 ns
Qg Total Gate Charge
ALL - 5.0 7.5 nC
V GS = 10V,I 0 = 3.0A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 2.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 3.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
R'hCS Case-to-Sink Mounting surface fl~t, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-190
 IRF610, IRF611, IRF612, IRF613 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF610 Modified MOSFET symbol
IBody Diode! IRF611 - - 2.5 A
showing the integral
IRF612 reverse P-N Junction rectifier.

~
- - 2.0 A
IRF613
ISM Pulse Source Current IRF610
- - 10 A
IBody Diode! ® IRF611
IRF612
- - B.O A
IRF613
VSD Diode Forward Voltage ® IRF610
IRF611
- - 2.0 V TC ~ 25°C, IS ~ 2.5A, VGS ~ OV

IRF612
- - 1.B V TC ~ 25°C, IS ~ 2.0A, VGS ~ OV
IRF613
trr Reverse Recovery Time ALL - 290 - ns T J - 150°C, IF ~ 2.5A,dI F/dt - 100A/I's

QRR Reverse Recovered Charge ALL - 2.0 - !,C T J - 150°C, IF ~ 2.5A, dlF/dt - 100 A/!'s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'
(j) TJ ~ 25°C to 150°C. ® Pulse Test: Pulse width'; 300I'S, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

5.0 5.0 r-...,.-,...-,--r-;-...,.-,..."r-'71"'"--'

4.5
10VI!;
9V
BV tPulSET+
.I,
1--+-+----t--tTJ =11250C+~----t'jHIt-c/f-+---t
I I
r
t--t---t---t---tTJ = 25 0 C+-'H:I--t---t----t

-
4.0 4.0

13
II: 3.5 JGS =7V-
i TJ = -~50C ~ftI
~
:E
~ 3.0
t-
~~ 3.0 t-- 80 f' PU L~ETEST, I
""V j
i:5 ~ VOS> 1010n! x ROSlon! max. IJ
II: 2.5
II:
13
z 2.0
6V-I--
B il
z 2.0 t--t---t---t---t--t---j,+--t--+-+--1
~
c ~ j
P
1.5
!2 /I
1.0 1.0 JWH-+--+--+-f-----I
1---+--+--+---+----11:
5V- ~
0.5

0
4~ _ _ _
O~~--~~~~~--~~--~~--~
L~
0 10 20 30 40 50 o 4 10
VOS, ORAIN·TO·SOURCE VOLTAGE IVOLTS! VGS, GATE·TO·SOURCE VOLTAGE IVOLTS!

Fig. 1 - Typical Output Characteristics Fig.2 - Typical Transfer Characteristics

50
5.0
OPERATION IN THIS,
_ Jo '" pulsETE1T 20 AREA IS lIMITEO
,
10V BY ROSlon!
4.0 9V ~ A 10
IRF610,1
laps
BV
~~ i,.
i
IRF612,3

:E
~ 3.0
~ ~~=7t: ~ IRF610,1 I"-
106 ps
~~
t- V t-
Z
i:5 W

..«
II:

.«
II:
II:
,
J!lF6JP
'" r,
~V "
II: :::>
:::> 1.0
z z 1mt:::
2.0

~ ~ r-
6V- II:
0.5

,
II:
c c
P P "-
~ V"
~
TC = 25 0C
1.0 02 >-- TJ = 1500C MAX.
10~s
I
~ 5V-
r--
RthJC = 6.4 KIW
O. 1 = SINGLE PULSE
IRF611 ,3
"
r-..... l~tb
OC

o~ J_ 0.05
IRF610,2

o 1.0 2.0 3.0 4.0 5.0 1.0 10 20 50 100 200 500

VOS, ORAIN·TO-SOURCE VOLTAGE IVOLTS! VOS, ORAIN·TO-SOURCE VOLTAGE IVOLTS!

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0·191
 IRF610, IRF611, IRF612, IRF613 Devices

iii
~
""
0:_
1.0
wz
t-I-
>::::> 0=0.5
t; ~ 0.5 NOTES:
it~
w,-,
~:i 0.2
!:::!ffi
... ~6.1
0.2 ~ :::;;ijIII
~ lfUL
~2~
~

~~ 0.1

'* .
O:~ t=iJ.05
0""
~ffi 0.05 ~~.02 1. DUTY FACTOR. 0 =
}~ .....-T'
_?01- ~ SIN GLE PULSE (TRANSIENT 2. PER UNIT BASE = R'hJC = 6.4 DEG. CIW.
~ 0.02
V"
Tm~tL I~PE~ANfE)1 1 3. TJM - TC =PDM Z'hJC(')'
j 0.01 lA"
10-5 10-4 10-3 10-2 10-1 1.0 10
'I. SQUARE WAVE PULSE DURATION (SECONDS)
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

4.0 10

3.6 - B~~' pulsE TEll I

"OS> I'D(on) ~ RDS(on) m.~. Hl
II
III
;;; 3.2
2
w ...ffi fl
:IE
w
§
2.8
'"
S
~ 2 1
z
w
'-'
z
2.4 w
'"
1
TJ = -55 0C '"
""t; 2.0
::>
~ 1.0
::>
ro-
..". ~ ~
0
z TJ 1= 250J
o
~ 1.6 ,.....
V 1250~
w
z
""
0: 1.2 1/~ TJ 1= ffi 5 TJ = 1500C

t ~ f..- ~
~
~ if;
i '" TJ =1250C
0.8

1/ '"
.E.'
0.4

o 0.1
o 1.0 2.0 3.0 4.0 5.0 o 1.0 2.0 3.0 4.0 5.0
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.14 2.04

w 1.11
./v 1.89
/
;'" ./
V w
'-' /
o 1.09 z 1.74
> ~ ""
~ 1.06
./
t;
iii0: 1.59
VGS = 10V
r-- -le=1.0A J
o ~ ~
~'ffi 1.04
./ 2
05 1.43
/~
Ww
"'N
"':::i
'-'N
0:- /
w""
~~
1.02
::>~
0"" 1.28
""",
/ /
~~ 0.99 / ~~
2- 1.13
o
~
/ ;;:
/
~ 0.97 '"
Q
0.98
Q
0.94
/ J 0.82
/
0

0.92
~ '" 0.67 L
V

0.89
V
-55 -34.5 -14 6.5 27 47.5 68 88.5 109 129.5 150
0.52
l/
-55 -34.S -14 6.S 27 47.5 68 88.5 109 129.5 150
TJ.JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-192
 IRF610, IRF611, IRF612, IRF613 Devices
500 20
J GS = 0
1

400
I 'i 1 MHI' l I
CiSS • Cgo + Cgd. Cd. SHORTED - in
':; VDS = 40V ....
CIIS = Cgd 0 15
- I _!
~~
2:
Coss=Cds+ ~ +C
w
'"""':;
VDS = 100V ........
~
"-
....z
w 300 "'Cds + Cgd
go gd
- - -VDS = 160V.IRF610. 612
I I
A~
,
0
>
«
.... l ~ 10

~
a:
.I. ~
t:;
~ '"
o
«
......... 200 "?
o
::;;

1\ f'..
Ciss !.;: /
-
'"
.;, 5
100
~ '"
~
10 =3A
\ 1"""--"- >
I FOR TEST CIRCUIT
It
-

10 20
CIIS

30 40 50
V jEE FliuRE

10
VDS. DRAIN·TD-SDURCE VOLTAGE (VOLTS) Gg• TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

3.0
RDS(on) MEASURED WITH CURRENT PULSE OF
on 2.0 ~s DURATION. INITIAL TJ =25 0 C. (HEATING r---
~
:I: EFFECT OF 2.0", PULSE IS MINIMAL.)
8 t-.....
w 2.4
~ 3 o. ........... .......
~
w
a:
ilia:
z
VGS = 10V
w
"-
:IE
~ 1.8
r--... ..... '-... ..... IRF610.611
o .... ...........
w
....
a:
'"
o
z
w
a:
0:
az
I-- -IRF612.61~ "-
.......... r-.....,I..........
"?
..,oz
-
-
1.2
./ ........ ~ ~ ~'I\..
I--" ~
;;:
a: -VGS =20V 0

I2
o 1 ..... ~
.
c 0.6
;;;
a:
o
... _. '\
o
10 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
20

\
_ 15

~
z
o

iii~
i5
a:
~
10
", '~
r'\.
\

"
~
.P

~
o
'1\
o 20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-193
IRF610, IRF611, IRF612, IRF613 Devices

VARY tp TO OBTAIN

VGs.R
REQUIREO PEAK IL

OUT

IL---<>---~~-"

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
GENERATOR O.U.T.
r------,
I
0---. TO SCOPE
I O.Oln
I 50n HIGH FREOUENCY
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

,---0() +VOS
(lSOLATEO
SUPPLY)

SAME TYPE
AS OUT
12V
BATTERY

o~·5mA - OUT

\J'\,..-.........J\Af\r-O -VOS
IG 10
CU RRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-194
 PD-9.317

INTEANATIONAL AECTIFIEAII<)RI

HEXFET® TRANSISTORS IRF620

IRF621
N-Channal IRF622
IRF623
200 Volt, 0.8 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFET«!) technology is the key to International Recti-
fier's advanced line of power MOSFET transistors. The effi-
• Low Drive Current
cient geometry and unique processing of the HEXFET design • Ease of Paralleling
achieve very low on·state resistance combined with high • No Second Breakdown
transconductance and great device ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well estab- Product Summary
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Part Number VDS ROS(on) 10
paralleling, and temperature stability of the electrical param- IRF620 200V o.an 5.0A
eters.
IRF621 150V o.an 5.0A
They are well suited for applications such as switching power IRF622 200V 1.2n 4.0A
supplies, motor controls, inverters, choppers, audio amplifi- IRF623 150V 1.2n 4.0A
ers, and high energy pulse circuits.

~
CASE STYLE AND DIMENSIONS 3.42 (0.135)
10.6B (0'420)~
9.66 (0.360)

10.66 (0.420)
MAX.
T*~~. TERM 3 - SOURCE

~f·51(~.660)
1~!r~IN. T

f 14.73 (0.580) J X
B.35 (0250)

~
MAX. 5.33(0.210)
413 (0.190)

L
14.73 (0.580)

Mr·
.t.:'ECTION ~-x
1.14(0.045) ,--,
i!:3f1O]ffi T j::::;J
1.14 (0JM!i)
1.77 (0.070) -I
212(0.115)
0.51 (0.020)
1.15 (0JM!i)
2.114(0.010)
ACTUAL SIZE Case Style TO-220AB
Dimensions in Millimeters and (Inches)

0-195
IRF620, IRF621, IRF622, IRF623 Devices

Absolute Maximum Ratings

Parameter IRF620 IRF621 IRF622 IRF623 Units
VOS Drain - Source Voltage (j) 200 150 200 150 V
VOGR Drain - Gate Voltage (RGS = 1 Mill (j) 200 150 200 150 V
10@TC-25'C Continuous Drain Current 5.0 5.0 4.0 4.0 A
10@TC = 100'C Continuous Drain Current 3.0 3.0 2.5 2.5 A
10M Pulsed Drain Current @ 20 20 16 16 A
VGS Gate - Source Voltage ±20 V
PO@TC=25'C Max. Power Dissipation 40 (See Fig. 14) W
linear Derating Factor 0.32 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 100!,H
A
20 I 20 I 16 I 16
TJ Operating Junction and
T stg Storage Temperature Range
-55to 150 'c
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) 'c

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF620
IRF622
200 - - V VGS = OV

IRF621
IRF623
150 - - V 10 = 250!,A

VGS thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS' 10 - 250!,A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = ·20V
lOSS Zero Gate Voltage Drain Current - - 250 !'A VOS - Max. Rating, VGS - OV
ALL
- - 1000 !'A VOS = Max. Rating x 0.8, VGS = OV, TC = 125'C
10(on) On-State Drain Current ® IRF620
5.0 - - A
IRF621
VOS ) 10(on) x ROS(on) max.' V GS = 10V
IRF622
4.0 - - A
IRF623
ROSlon) Static Drain-Source On-State IRF620
- 0.5 0.8 !l
Resistance ® IRF621
V GS = 10V, 10 = 2.5A
IRF622
IRF623
- 0.8 1.2 !l

gts Forward Transconductance ® ALL 1.3 2.5 - S Ul) VOS ) 10(on) x ROS(on) max.' 10 - 2.5A
Ciss· Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, t = 1.0 MHz
Coss Output Capacitance ALL - 150 300 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 40 80 pF
td on Turn~On Delay Time ALL - 20 40 ns VOO = 2.5 BV OSS ' 10 = 2.5A, Zo - 501l
tr Rise Time ALL - 30 60 ns See Fig. 17
td(ottl Turn·Off Delay Time ALL - 50 100 ns IMOSFET switching times are essentially
- independent of operating temperature.)
tt Fall Time ALL 30 60 ns
Qg Total Gate Charge V GS = 50V, 10 = 6.0A, VOS ~ 0.8 Max. Rating.
ALL - 11 15 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate~Source Charge ALL - 5.0 - nC

Qgd Gate·Orain ("Miller") Charge ALL - 6.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to·Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-196
 IRF620, IRF621, IRF622, IRF623 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF620 Modified MOSFET symbol
(Body Diode) IRF621
- - 5.0 A
showing the integral
IRF622 reverse P·N junction rectifier.

~
IRF623
- - 4.0 A

ISM Pulse Source Current IRF620

(Body Diode) ® IRF621
- - 20 A

IRF622
- - 16 A
IRF623
VSD Diode Forward Voltage ® IRF620
- - 1.8 V TC ~ 25°C, IS ~ 5.0A, VGS ~ OV
IRF621
IRF622
- - 1.4 V TC ~ 25°C, IS ~ 4.0A, VGS ~ OV
IRF623
trr Reverse Recovery Time ALL - 350 - ns T J - 150°C, IF = 5.0A, dlF/dt - 100A/~s

QRR Reverse Recovered Charge ALL - 2.3 - ~C TJ - 150°C, IF = 5.0A, dlF/dt - 100 A/~s
ton Forward Turn·on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantiallv controlled by lS + La-

(J)TJ = 25°Cto 150°C. ®PulseTest: Pulsewidth';;300~s, Duty Cycle';; 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

10 10
10V 7V
- ,IO",pu["
, ,.
TEJT I
I. '/ .- - .-

1/ 1
-I -JO",PUlSETElr
VOS> 10(on) x ROSlon) max.

- 1/1
6V ~I
j
f
I I
VGS = 5V - TJ = 125 0 C
I -
I ~
-TJ=15 0 C
.J
-
I ~ (jJ
TJ = -550C
Y 1 ~'/
10 40 60 80 100 10
VOS, DRAIN·TO·SOURCE VOLTAGE IVOLTSI VGS, GATE·TO·SOURCE VOLTAGE IVOLTSI

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
AREA IS L1MITEO
50 BY ROS(on)

1}~! V
,
8V IRF620,1
10
//6: on
8o,uslpULSE leST w IRF621,3

W ......
~
,:!;
10
=IRF620,1
1'10!'s

J
V
i--"""VGS = 5V
'1 1
::5
a:
a:
:::>
'-'
_IRF6p,3
'. ,-- _.
100f

I z
;;;:
.-
~ 1 mt
a: 1.0 I\.
/ 0

.!?
0.5
= TC 15 0 C
10 ms
I

~;:8-
- TJ = 150°C MAX.
I. 4V 0.2 _ RthJC = 3.11 K/W

r to
0.1
-

10
SI~G~E ~um III
10 20
IRF621,3

50 100 200
IRF620,2

500
VoS, ORAIN·TO·SOURCE VOLTAGE (VOLTSI Vas, ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-197
IRF620, IRF621, IRF622, IRF623 Devices

0=0.5
NOTES:

-~.2
-0.1 ::iiiII""" lflJL
0:=0.05

~~.02
~"""
~2~
1. DUTY FACTOR. 0 = :~
~k: SINGLE PULSE (TRANSIENT
W1Rl~AL I~P~OAN1CE\ I
2. PER UNIT BASE = RlhJC = 3.12 OEG. CIW.
3. TJM - TC = POM ZlhJC(I).
I IIII j
10-4 10-2 1.0 10
11. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transie~t Thermal Impedance, Junction-to-Case Vs_ Pulse Duration

TJ LJ 55 0 - ~ 10
2

" :tf
TJ - 25 0 C
-
~
:0;:
,..
---.
r- ....,~

/' ~ ./ "... TJ;-150 0 C

'-
I ,/" TJ! 125 0
....-
J a'"z
V/ V ~
'#'
~ C
10

l V/ V w
~

'"w ./
1//' - I-----
~ -TJ= 150 0 C
I
fI vos> IO(on) x ROS(on)
I I
max.
'"
C 71
BO(SPULrTEsIT
I I I
I ~
TJ ~ 25 0 C
1.0 I
10 o
10. DRAIN CURRENT (AMPERESI VSO. SOURCHO·ORAIN,VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance V,. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 22

w
U /
,... .".
z
'"~
~
1.8
/
~
",
'"z
Co 14
/
."". V
Ww
UN V
"'-
~~ ./
c'"

""
,,?:E

./ ,..0
c'"
z~ 1.0
/'"
V <C
'"c ./
0.85 ~
0

0.6
,// VGS = 10V

~ c
10 = 2A
c '" ./ -I
Ii;

0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATU RE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage V,. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-198
 IRF620, IRF621, IRF622, IRF623 Devices
1000 20
J
GS =J
I I f,= 1 M~z I
800 C;SI =Cgs + Cgd. Cd. SHORTED - ~ VOS ~ 40V
C'" =Cgd 0 15
'I ~
VOS =100V

~~
- ?
~
Cgs Cgd w
I I
~

600 l\ Coss =Cds + Cgs + Cgd

-
'"!:;"" -VOS =160V, IRF620, 622

~ 'f'
w

-
"'Cd. + Cgd
u
z
« \\ i'.. I
0
>
w
>- u 10
c'ss
1 i--
l.ar
U
;t '"=>0
;3 400 "?
u- \ 0
>-;-
w

/
-t:t:::
>-
;;
200
\ "' r-.... .,;
>'"
10 =6A
\ J
-- r-.. Crss
/ T Ii
FOR TEST CIRCUIT I - -
FIG1URE

10 20 30 40 50 12 16 20
VOS. ORAIN·TO·SOU RGE VOLTAGE IVOLTS) Qg' TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

1.5 ............
........
'"x
8'"
w
'z"' VGS =10V
.......... ...........
"r-... .......
~ IRF620.621
~ ..........
iii
'"z
1.0
- -IRF622,~ .......... "-
0
w ) ~"
-- -.....-1'"
'"'=>

" "",\
'" V
~~
---
0

~ VGS =20V
>-;-
z 0.5
<[
'"c '\ ~
c

'"c
'"
0

ROS(on) MEASURED WITH CURRENT PULSE OF

2.01" DURATION. INITIAL TJ =25 0 C, (HEATING
'\
EFFECT OF 2.01" PULSE IS MINIMAL.)
o
10 15 20 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)

Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

35 '\
'">->-
"
~
z
0
~
;t
1ii
30

25

20
'" 'I\.
'\
I\.
;:;

3!'" 15
\
~
~
10
,'\
~
"'\
20 40 60 80 100 120 140
Tc. CASE TEMPERATURE IOC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-199
IRF620, IRF621, IRF622, IRF623 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGS-R

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

PULSE
GENERATOR O.U.T.
r-----.,
I
I
50U I 0---. TO SCOPE
O.OW
I I 50ll HIGH FREQUENCY
L_ ___ ..J SHUNT

Fig. 17 - Switching Time Test Circuit

.---0 +VDS
(ISOLATED
SUPPLY)

o~1.5mA - IG
___-v-.",,_[)
ID
-VDS

CURRENT ":'" CURRENT

SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-200
 PO-9.309

INTERNATIONAL RECTIFIER I IC)R I

HEXFET® TRANSISTORS IRF63D

IRF631
N·Channal IRF632
IRF633

200 Volt, 0.4 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFETe technology is the key to International RectWier's ad- • Low Drive Current
vanced nne of power MOSFET transistors. The efficient geometry
and unique processing of the HEXFET design achieve very low on-
• Ease of Paralleling
state resistance combined with high transconductance and great de· • No Second Breakdown
vice ruggedness.
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well established ad- Product Summary
vantages of MOSFETs such as voltage control, freedom from sec-
ond breakdOwn, very fast switching, ease of paralleling, and temper- Part Number VOS ROS(on) 10
ature stability of the electrical parameters.
IRF630 200V O.4n 9.0A
They are well suited for applications such as switching power sup- IRF631 150V O.4n 9.0A
plies, motor controls, inverters, choppers, audio amplifiers, and high
energy pulse circuits. IRF632 200V O.6n 8.0A
IRF633 150V O.6n 8.0A

~9.BilOliol
IO.8l1042O)~ TEAM<-
CASE STYLE AND DIMENSIONS 3.42 10.135) ORAl.

10.66 (0.420)
MAX. T*~'"
"oY 10IO::;
."~~~!}~
+-
14

I~!r~I •. T 4.8210.;;r
3.5810.1~1
2.7910.1101
6.3510.260) 2.2910.0901
IIAX. 5.33102101
t
'2L
".~3m= ~ 4.8310.1901
x
14.73 (0.580) .t!ECTlON x-x
D
Mr· -I
1.1410.045)
o:ma:mi T i----I
l·l4m.om
O. 1 .0
IJ7(11.o7Ql 2.9210.115)
f.lIlOJi45j
~

ACTUAL SIZE C_ Style TO-220AB

Dimensions in Millimeters and (Inches) .

0-201
IRF630, IRF631, IRF632, IRF633 Devices

Absolute Maximum Ratings

Parameter' IRF630 IFiF63!. IRF632 IRF633 Units
VOS Drain - Source Voltage <D 200 150 200 150 V
VOGR Orain - Gate Voltage (RGS - 1 Mil) (j) 200 150 200 150 V
10@ TC ~ 25°C Continuous Drain Current 9.0 9.0 8.0 8.0 A
10@ TC ~ 100°C Continuous Drain Current 6.0 6.0 5.0 5.0 A
10M Pulsed Drain Current @ 36 36 32 32 A
VGS Gate - Source Voltage ±20 V
PO@TC~25°C Max. Power Dissipatibn ..15 (See Fig. 141 W
Linear Derating Factor 0.6 (See Fig. 141 W/K
ILM Inductive Current. Clamped (See Fig. 15 and 161 L - 100~H
A
36 I 36 I 32 I 32
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063·in. (1.6mmHrom case for 10s1 °C

Electrical Characteristics @TC := 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions

BVOSS Drain- Source Breakdown Voltage IRF630

200 - - V VGS ~ OV
IRF632
IRF631
150 - - V 10 ~ 250~A
IRF633
VGS(thl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS ~ VGS, 10 ~ 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current - - 250 ~A VOS ~ Max. Rating, VGS ~ OV
ALL
- - 1000 ~A VOS ~ Max. Rating x 0.8, VGS ~ OV, TC ~ 125°C
10(onl On-State Drain Current @ IRF630
IRF631
9.0 - - A
V OS ) 10(onl x ROS(onl max.' V GS ~ 10V
IRF632
8.0 - - A
IRF633
ROS(on) Static Drain-Source On-State IRF630
- 0.25 0.4 11
ReSIstance ® IRF631
VGS ~ 10V, 10 ~ 5.0A
IRF632
IRF633
- 0.4 0.6 0

9fs Forward Transconductance ® ALL 3.0 4.8 - 5 (01 VOS ) 10(onl x ROS(onl max.' 10 ~ 5.0A
Ciss Input Capacitance ALL - 600 800 pF
VGS ~ OV, VOS ~ 25V, f ~ 1.0 MHz
Coss Output CapaCitance ALL - 250 450 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 80 150 pF
td(onl Turn-On Delay Time ALL - - 30 ns V OO ~ 90V, 10 ~ 5.0A, Zo ~ 150
tr Rise Time ALL - - 50 ns See Fig. 17
td(offi Turn-Off Delay Time ALL - -- 50 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 40 ns
Qg Total Gate Charge V GS = 10V, 10 ~ 12A, VOS ~ 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 19 30 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 10 _ - nC

Qgd Gate-Drain ("Miller") Charge ALL - 9.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25

$
in.) from package to
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.1 from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-ta-Ambient Free Air Operation

0-202
 IRF630, IRF631, IRF632, IRF633 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF630 Modified MOSFET symbol
- - 9.0 A
(Body Diode) IRF631 showing the integral
IRF632 reverse P-N junction rectifier.

~
IRF633
- - 8.0 A

ISM Pulse Source Current IRF630

- - 36 A
(Body Diode) ® IRF631
IRF632
IRF633 - - 32 A

VSD Diode Forward Voltage ® IRF630

- - 2.0 V TC = 25°C, IS = 9.0A, VGS = OV
IRF631
IRF632
IRF633
- - 1.8 V TC = 25°C, IS = B.OA, VGS = OV
trr Reverse Recovery Time ALL - 450 - ns TJ - 150°C, (F = 9.0A, dlFldt - 100AI~s
QRR Reverse Recovered Charge ALL - 3.0 - ~C T J - 150°C, IF - 9.0A, dlFldt = I 00 AI~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

{j)TJ = 25°C to 150°C. @PulseTest: Pulse width'; 300~s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

20
t 10

,
80~sPUlSE TEST
1O, I
80J.lsPUlSE TEST

f-VOS'> 10(on) ~ ROS(on) max.

1)1
16 7V II
i"
:! 12 I
>-

~ VGS = 6V
TJ=+125 0 C
i
~ I
TJ = 25 0 C ~ ~
'"~
~ NIl
I
Q
TJ = -SSoC
E SV ~ flI)
ill
4V ~ '/
20 40 60 80 100
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100m~~. OPERATION IN THIS

10

.J. ~ L..-t: - SO f-IRF630, 1

1/ AREA IS LIMITED
.- BY ~~(on

20~+I_RrF6_3~2,~3~~~~~"~'~rN+A~~~~~++H
~ ~ ~1°V
r-- JO"' pulSE T,JT
~ rr:
~
9V_ -

~+7V- - i 10 i=-_IRF630, 1
1'-
'.
~"
1\ 10~s,=

~ f= I RF632, 3 100 ~s
Jr/ ~~V >-
~
I
J ~
VGS-5V- - '"
'"
i3
~
0'-.

~P 1.0§:~=1 R~1
10Jms
~
I~
f=TC=2S0C
O.S ~ TJ = lS0 0 C MAX.
• •
lOOms
I; t
r- R,hJC = 1.67 KIW f+-~+-+-+++++++--f-+-=O,CT+++++H
~" 0.2 r- f'1 GL f pmEIIft-+-+-+++H-H+-iI-+-+t

1£ r- - 0.1
1.0
I I II II
10
IRF631,3
Illlil
20 50
IRF6302
I Ti I
100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE {VOLTSI VOS, ORAINTO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-203
IRF630, IRF631, IRF632, IRF633 Devices

I-
2
W
v.;
z:
<
a:_
I-!: 1.0
wz
>::>
i=a: D.= 0.5
<Ow 0.5 NOTES:
tt~ ~b.2
w<o
cZ:
w< 0.2
~::a
-'<>.
0.1
<:IE 0.1 f-- 0.05
:IE-
lTUL
a:-' -~.O
0<
":.~ 0.05 ~0.D1
<Ow SINGLE PULSE (TRANSIENT 1. DUTY FACTOR, D = :21
:<!:z: po-
~I- t--t-t--t-t-++++_itERiAjIMPIEDtICj)I II' -t---t--t--t-+--l---t-t-t+l-t--t-t-t--H-t+tt--t--+ 2. PER UNIT BASE = RthJC =1.67 DEG. CIW.
E<.> 0.02
:2 jH11j+--++---+-+-If--+-H+I---+-+-+--H+++++-H 3. TJM - TC=POM ZlhJCItI.
f-+--+-+--+-+-+--f+-Hllj-Hlj'-H-J--j++
N 0.D1
10-5 10-2 10-1 1.0 10
11, SQUARE WAVE PULSE OURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

10 j

--
10 2
f3 TJ - 25 0 C
~
'"'
:!
I- ", i"TJ = 150oC_
TJ = -55°C
.,..,. -;]=25 0 &
~
a:
a:
. L

-
./ 13
....V V ...- TJ = 125 0 b
z
;;:
g; 10 //
VL ~ f.- w
'"ffi TJ =150 0 C I
hV ~
0:: '"1
III VDS> 10(on) x RDS(on) max. E'" I
I
r 80/JSPULSETEST
1.0 I I
TJ = 250 C
j
10 o
10. DRAIN CURRENT (AMPERES) VSD, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

1.25 2.2

~o 1.15
~
z:
< 1.8 1/
>
~
o ~
- ' i-' ~
~
1/
o a:
/
~c l05
Ww
a:N
"'::::;
~i ~
./
", " 2
0 6 1.4
Ww
<'>N
0::-
::>-'
0<
V
~~ 0.95
./
,,/'"'
oa:
z
0
1-' 2
- 1.0
./ ""
:=z
:'~ 0.85
" ;;:
a:
c
c
0
0.6 ./
V
V
V~S =10lV
'"c
a: ,/
o ID I=3.5~
>
"'
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On·Resistance Vs. Temperature
0-204
 IRF630, IRF631, IRF632, IRF633 Devices
2000 20
V~S=O
I 1=,1 MHz, ,l .J
Ciss = Cgs + Cgd, Cds SHORTED _ VOSI. 40V
1600
~

,
C'" = Cgd I
VoS' 100V
-
~
Cgs Cgd
~
Coss = Cds + Cgs + Cgd I ~
VOS' 160V.IRF630, 632
-
;: 1200
'-'
z
~
"'Cds + Cgd
)
~r
~ ~
l\ --
::: 800 Ciss

'I
400
\
'\ "- .I
.........
~ / 10 = 12A

w
--
.......
C'SS

w ~
VDS. DRAIN-TO-SOURCE VOLTAGE (VOLTS)
~ ~
V 16
Qg' TOTAL GATE CHARGE (nCI
FOR TEST CI RCUIT

TFIGtElj

24 32
-

40

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
0.8 10
lii
::E
:r
ew I
VGS = 10V .........
..'"
"" IRF63~
'-'
I-
~
w
0.6
13 1""'--"' . . . .'" ~·RF630, 631
~

,''"
II:
Z
Q
W ~ 6
I
........
'-'
II: I-
::> ;:'i
Q 0.4
~
.......
.,."I ~
Q

V
-
::>
'-'
Z ...-1-' z 4
« «
II:
Q

i
~
0.2
-~ ~ VGS = 20V

I
II:
Q

ci '"~ '\~
\,
II:

RDS(onl MEASURED WITH CURRENT PUJE OF

2.0~sDURATION. INITIAL TJ=25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.)
o
10 20 30 40 25 50 75 100 125 150
ID' DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
80

-
lii
60
70

"" '\
I\.
~
~ 50
z "I\.
'" '\I'\.
Q
;::
~ ~
ili
i5
II:
W
!O 30
Ii?
~ 20

10

20 40 60 80 100
TC, CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

120 " '\~
140

0-205
IRF630, IRF631, IRF632, IRF633 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

Vo
-.,.---~ TO SCOPE

Fig. 17 - Switching Time Test Circuit

.----0 +VOS
(lSOLATEO
SUPPLY)

SAME TYPE
AS OUT
12V
BATTERY

o~1.5mA - IG
OUT

10
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-206
 PD-9.374

INTERNATIONAL RECTIFIER I I\iR I

HEXFET® TRANSISTORS IRFB4D

N-CHANNEL
IRFB41
POWER MOSFETa IRFB42
IRFB43
200 Volt, 0.2 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
The HEXFE"f® technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFET transis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state • No Second Breakdown
resistance combined with high transconductance • Excellent Temperature Stability
and great device ruggedness.
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as volt-
age control, freedom from second breakdown, very Part Number VOS ROS(on) 10
fast switching, ease of paralleling, and temperature IRF640 200V O.lsn lSA
stability of the electrical parameters.
IRF641 150V O.lSn lSA
They are well su ited for applications such as switch- IRF642 200V 0.22n 16A
ing power supplies, motor controls, inverters, chop-
IRF643 150V 0.22n 16A
pers, audio amplifiers, and high energy pulse circuits.

'0.66 (0.4201~
CASE STYLE AND DIMENSIONS 3.42 (0.1351
~'.iiifiD.3sOi
t'";"
2.54 (0.1001 4.0S (0.161)

10.66 (0.420) TERM 3 - SOURCE

MAX.
16.51 (0.6501
14.23(0.5601

t- ~OOF'N' T
6.35 (0.2501
MAX. 5.33 (0.210)

:tT= d~' ,L
4.S3 (0.1901

t l:'ECTION X-x
D
14.7~l~~80) " I1 1.14(0.0451

I' ,
0.31 (0.012)

I
TJ--...!
1.14(00451
..L.'_ _ , ( [ 1.77 (0.0701 ---I
292(01151
0.51 (0.020)
115 (0.0451
104'iQOSOj

ACTUAL SIZE Case Style TO·220AB

Dimensions in Millimeters and (Inches)

D-207
IRF640, IRF641, IRF642, IRF643 Devices

Absolute Maximum Ratings

Parameter IRF640 IRF641 IRF642 IRF643 Units

VOS Drain· Source Voltage <D 200 150 200 150 V

VOGR Oraln - Gate Voltage (RGS ~ 1 M(J) (j) 200 150 200 150 V
10@TC-25°C Continuous Drain Current 18 18 16 16 A
10@ TC ~ 100°C Continuous Drain Current 11 11 10 10 A
10M Pulsed Drain Current @ 72 72 64 64 A
VGS Gate· Source Voltage ±20 V
PO@TC ~'25°C Max, Power Dissipation 125 (See Fig. 14) W
Linear Derating Factor 1.0 (See Fig. 14) W/K
ILM Inductive Current, Clamped " (See Fig. 15 and 16) L ~ 100~H
A
72 I 72 I 64 I 64
TJ Operating Junction and
-55 to 100 °c
T stg Storage Temperature Range
Lead Temperature 300 (0.064 in. (1.6mm) from case for lOs) °c

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF640
200 - - V VGS ~ OV
IRF642
IRF641
150 - - V 10 ~ 25Ol'A
IRF643
VGS(th) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS ~ VGS' 10 ~ 25Ol'A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS ~ -20V
lOSS Zero Gate Voltage Drain Current - - 250 ~A VOS ~ Max. Rating, VGS ~ OV
ALL
- - 1000 ~A VOS ~ Max. Rating x 0.8, VGS ~ OV, TC ~ 125°C
1010n) On-State Drain Current ® IRF640
18 - - A
IRF641
V OS ) 10(on) x ROS(on) max.' V GS ~ 10V
IRF642
16 - - A
IRF643
ROS(on) Static Drain-Source On-State IRF640
- 0.14 0.l8 0
Resistance ® IRF641
VGS ~ 10V, 10 ~ ·10A
IRF642
IRF643
- 0.20 0.22 0

9fs Forward Transconductance @ ALL 6.0 10 - S(lIl VOS ) 10(on) x ROS(on) max.' 10 lOA

Ciss Input Capacitance ALL - 1275 1600 pF

VGS ~ OV, VOS ~ 25V, f ~ 1.0 MHz
Coss Output Capacitance ALL - 500 750 pF
See Fig. 10
C rss Reverse Transfer Ci3pacitance ALL - 160 300 pF
td(on) Turn-On Delay Time ALL - 16 30 ns VOO ~ 75V, 10 ~ lOA, Zo ~ 4.70
tr Rise Time ALL - 27 60 ns See Fig. 17
td(offl Turn-Off Oelay Time ALL - 40 80 ns (MOSFET switching times are essentially
Fall Time - ns independent of operating temperature.)
if ALL 31 60
Qg Total Gate Charge V GS ~ 10V, 10 • 22A, VOS • 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 43 60 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 16 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 27 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junctlon-to-Case
RthCS Case-to-Sink Mounting surface flat. smooth, and greased.
RthJA Junction-,to-Ambient Free Air Operation

0-208
 IRF640, IRF641, IRF642, IRF643 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF640 Modified MOSFET symbol
- - 18 A
180dy Diodel IRF641 showing the integral
IRF642 reverse P-N junction rectifier.

~
IRF643
- - 16 A

ISM Pulse Source Current IRF640

- - 72 A
IBody Diodel ® IRF641
IRF642
- - 64 A
IRF643
VSD Diode Forward Voltage ® IRF640
IRF641
- - 2.0 V TC = 25°C, IS = 18A, VGS = OV
IRF642
IRF643
- - 1.9 V TC = 25°C, IS = 16A, VGS = OV
trr Reverse Recovery Time ALL - 650 - ns TJ = 150°C, IF - 18A,dlF/dt - 100A/!,s
QRR Reverse Recovered Charge ALL - 4.1 - !,C T J = 150·C,I F = 18A,dlF/dt - 100Al!,s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j) T J = 25°C to 150·C. ® Pulse Test: Pulse width ... 300!,s, Duty Cycle'" 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

40 40

rl AI If

32
10V

r-- ~9V
BV)
.lplpuLETEL- r--- 32
Ti = -55~C,,---
h/
1a ~J = 25~C,,---
1I11
"---
VI
II:
W -.......
"- 7V l125jC,,---
:IE
:; 24
....
ill f---'O 1" PULSE TEST J(
,I
II:
II: , , , .1 I
:::> VOs> 1010ni x ROS(onl max.
'"
z 16
;;: VGS = 6V
II:
C I
E
J
5~ ~,
4~ .,~
10 20 3D 40 50 10
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTS) VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
IRFB4U, OPERATION IN THI AREA IS LlMITEO
40
BY ROSlo"1
-.L,PulsETEh 50 _IRF642,3,_ ~ "'. - tf

f.~ " ..
,1>-0 lO~Sr
32
~r~BV
~
20

10
IR~64d, II,
IRF642,3 ." 1001'S
I
~ ~ _Jv-
~
::;; lms
:;
~~
~ >-
~
'"
~V
II: lOms
1:l
z

~
100 ms
VGS=jV-
~ 1.0
c

~~
P 0.5 =
=TC~250C
TJ = 1500C MAX.
-- . OC-

~
_ R,hJC = 1.0 KIW
51V _
f
0.2 _lSI ~G L pnSIEl1 IRF641,3 IR~640,2
~ lv_ 0.1 LI Ii 1 JJII 111
1 2 3 4 1.0 10 20 50 100 200 SOD
Vas, ORAIN·TO·SOURCE VOLTAGE IVOLTS) VOS, ORAIN·TO.sOURCE VOLTAGE IVOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-209
IRF640, IRF641, IRF642, IRF643 Devices

I-
a'i
0;
z
<
e:wi'
i=' 1.0
>::::>
§~
u. -
~~
~:i 0.2
~~
.......
0.5

r-~.2
r-O.l
~:!!! 0.1 EO.05
"' ....
0<
0=0.5

- .... ~ iii
""'" ...
- NOTES:

lJL.fL
~2~
z.~ 0.05 r-0.02
Uw
:<!:c ~0.D1- SINGLE PULSE (TRANSIENT
I. OUTY FACTOR. 0 = :~
,:1-
0.02 --r-r
THERMAL IMPEDANCE)
~ 2. PER UNIT BASE = R'hJC = 1.0 DEG. CIW.
U
3. TJM - TC = POM Z'hJC(t)·
j 0.01 I I IIIIII
10-5 10-3 5 10-2 10-1 1.0 10
il. SQUARE WAVE PULSE DURATION (SECONDS)
Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

19.0 50 ,
~
0;
15.2
TJ = -55°C
'"w
~ 20 A If'"
a'i
:0;;
~ ~
w
~
iii
w 11.4
U
z
/'
,....,...
T\ = 25JC
I-
ffi
'" 10
1//
<
I-
U
::::>
/ ~
T~= 12JoC- -
'"
B
z
0
z
0 7.6
"/ ~
o
I
~ w
r-- -TJ=150 0 cl
z
«
'"
IIV '"
'"w 1 TJ = 25 0 C
I-

~ 3.8 II (;;
'"<i:
r 80 ps PU lSE TEST
I I I
VOS> 10(on) x RDS(on) max.
E

1.0
I J
16 24 32 40 o 0.4 0.8 1.2 1.6 2.0
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig.6 - Typical Transconductance Vs. Drain Current Fig.7 - Typical Source·Drain Diode Forward Voltage

1.25 2.5

w
U
Z

~ 2.0 IL
. /V Hi
'" V
w
. /V , . . .V
:;:
~s 1.5
./
/ zw
ON
w:::l ./
U<
..,/ "':IE
::::>",
00 ./
/'
1.0
..,z
CI,lz
0-
V
V ;;: ./
'"o ~ VGS= 10V
c 0.5
a Y9A
i!l 1
'"
0.75
-40 40 80 120 160 0-40 40 80 120 160
TJ.JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On·Resistance Vs. Temperature
D-210
 IRF640, IRF641, IRF642, IRF643 Devices
2000
C: .. = + C~ Cg~. Cds S~O RTE6 20
JGS=ot_ r--C", = Cgd -
t= 1 MHz
1600 \ Cgs Cgd
Coss = Cds + Cgs + Cgd -
~~ '" Cds + Cgd

r-- I-- ~Ci" VOS=40V~

...
! 1200
\ I I
Vos = 100V ~ #
~
'" I I "-..
z
~ ~ Vos = 160V. IRF640. 642"",

~'" 800
\ .~'Y
" \ I" ......
~ /
400
'I\..
"""~ t--- C~
-r-
- V
/
10 = 22A
FOR TEST CIRCUIT
SEE FIGiRE 18 -
1
-

10 15 20 25 30 35 40 45 50 20 40 60 80
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) Oy. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

20
0.5

.'"'"
8 16
......... ........
...........
.......... ........... r-....
0.4

..'"
w
Z

.......
~l'-.I'o..
~
VGS = 10V
iZa: IRF640 641
z
0
0.3
...... ~,.
w
IRF642. 643 ,~
'"
a:
::>
0 j

,,
.,.'z" 0.2

"~"'I
0

«a:
.,./ .-" Vv;;=20V
0
~
".e'"
~
0.1
RDS(on) MEASURED WITH CURRENTlpULSJ OF
2.0 ps DURATION. INITIAL TJ = 25 0 C. (HEATING
Pl
EFjECT Of 2.0 PULSIIS M~NIMA\I
I
40 80 100
o
20 60 25 50 75 100 125 150
'0. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATU RE (UC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

- -"
140

120

\..
z
o "\
~ 80
I\..
~ "\
""\
i5
a: 60
~
~
,p 40
I\..
20 ""
20 40 60 80 100
TC. CASE TEMPERATURE (DC)
" 120
~
140

Fig. 14 - Power Vs. Temperature Derating Curve

0-211
IRF640, IRF641, IRF642, IRF643 Devices

VARY tp TO OBTAIN

rF=L
REQUIRED PEAK IL

VGS = _D_UT--.....-y

I L _ - _ o - - -....-'W'Io-.J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

75V
ADJUST RL TO OBTAIN
a.5f!
SPECIFIED 10
VOS

r;U-; - - -1 D.U.T.
I GENERATOR O--r---_O---"'~~

I ~J~RCE
IMPEDANCE
n I
L ___ J

Fig. 17 - Switching Time Test Circuit

r - - - o ( ) +VOS
{ISOLATED
SUPPLY}

SAME TYPE
AS DUT

o..r=JIt· 5mA
- IG
OUT

ID
CURRENT ~ CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0·212
 PD-9.327

INTERNATIONAL REC:TIFIERIIC)RI

HEXFET® TRANSISTORS IRF71D

IRF711
N-Channel IRF712
IRF713

400 Volt, 3.6 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
The HEXFET~ technology is the key to International
• Fast Switching
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the • Ease of Paralleling
HEXFET design achieve very low on-state resistance • No Second Breakdown
combined with high transconductance and great
device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Part Number VOS ROS(on) 10
switching, ease of paralleling, and temperature stabil- IRF710 400V 3.6n 1.5A
ity of the electrical parameters.
IRF711 350V 3.6n 1.5A
They are well suited for applications such as switching IRF712 400V 5.0n 1.3A
power supplies, motor controls, inverters, choppers,
audio amplifiers, and high energy pulse circuits. IRF713 350V 5.0n 1.3A

CASE STYLE AND DIMENSIONS 3.42 (0.1351

~10'66 (0'4201~
9.66 (0.3801

.
2.54(0.1001 ~DIA

10.66 (0.420)
MAX.
T*"'~ TERM 3 - SOURCE

16.51 (0.6501

+-d
14.23 (0.5601

I~O.O~IN. T
6.35(0.2501

~x ~
5.33 (0.2101

t 14.73 (0.5801
4.83(0.1901

L
.i,!lECTION x-x
14.73 (0.580) 0
Mr·
1.14(0.0451
o:mu:nm
'1----1
1.14 (0.0451
1.77 (0.0701 -I
2.92 (0.1161
0.51 (0.0201
1.15 (0.0451 2.04 (O.oeil)

ACTUAL SIZE Case Style TO-220AB

Dimensions in Millimeters and (Inches)

0-213
IRF710, IRF711, IRF712, IRF713 Devices

Absolute Maximum Ratings

Parameter IRF710 IRF711 IRF712 IRF713 Units
VOS Drain - Source Voltage CD 400 350 400 350 V
VOGR Orain - Gate Voltage IRGS ~ 1 Mill CD 400 350 400 350 V
10@TC~25"C Continuous Drain Current 1.5 1.5 1.3 1.3 A
10@TC - 100"C Continuous Drain Current 1.0 1.0 0.8 0.8 A
10M Pulsed Drain Current @ 6.0 6.0 5.0 5.0 A
VGS Gate - Source Voltage ±20 V
PO@TC ~ 25"C Max. Power Dissipation 20 ISee Fig. 14) W
Linear Derating Factor 0.16 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L ~ 1OO~H
A
6.0 I 6.0 I 5.0 I 5.0
TJ Operating Junction and
-55to150 "C
T8t9 Storage Temperature Range
Lead Temperature 30010.063 in. (1.6mml from case for lOs) "C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF710
400 - - V VGS ~ OV
IRF712
IRF711
350 - - V 10 ~ 250~A
IRF713
V GSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS ~ VGS' 10 ~ 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS ~ 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS ~ -20V
lOSS Zero Gate Voltage Drain Current - - 250 ~A VOS ~ Max. Rating, V GS - OV
ALL
- - 1000 ~A VOS ~ Max. RatingxO.8,VGS ~ OV, TC ~ 125"C
1010ni On-State Drain Current @ IRF710
1.5 - - A
IRF711
VOS >1010ni x ROSlon) max.' V GS = 10V
IRF712
1.3 - - A
IRF713
ROSlon) Static Drain-Source On-State IRF710
- 3.3 3.6 Q
Resistance @ IRF711
VGS ~ 10V.10 ~ 0.8A
IRF712
- 3.6 5.0 Q
IRF713
gfs Forward Transconductance @ ALL 0.5 1.2 - S lUI VOS >1010n) x ROSlon) max.' 10 0.8A
C ISS Input Capacitance ALL - 135 150 pF
VGS = OV, VOS = 25V, f ~ 1.0 MHz
Coss Output Capacitance ALL 35 50 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 8.0 15 pF
tdlon) Turn-On Delay Time ALL - 3.0 10 ns VOO - 0.5 BV OSS ' 10 - 0.8A, Zo - 50Q
tr Rise Time ALL - 10 20 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 5.0 10 ns (MOSFET switching times are essentially
Fall Time ALL 8.0 15 independent of operating temperature.)
tf - ns
Qg Total Gate Charge
ALL - 6.0 7.5 nC
V GS = 10V.10 = 2.0A. VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 3.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 3.0 - nC

LO Internal Drain Inductance - 3.5 - "H Measured from the Modified MOSFET
contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25

4~
in.) from package to
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
10.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

D-214
 IRF710, IRF711, IRF712, IRF713 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF710 Modified MOSFET symbol
(Body Diode) IRF711 - - 1.5 A
showIng the integral
reverse P~N junction rectifier.
IRF712
-

~
1.3 A
IRF713
ISM Pulse Source Current IRF710
(Body Diode) @ IRF711 - - 6.0 A

IRF712
IRF713
- - 5.0 A

VSD Diode Forward Voltage ® IRF710

- - 1.6 V TC = 25°C. IS = 1.5A. VGS = OV
IRF711
IRF712
IRF713 - - 1.5 V TC = 25°C. IS = 1.3A. VGS = OV

t" Reverse Recovery Time All - 380 - ns T J - 150·C.I F - 1.5A. dlF/dt - 100A/~s

QRR Reverse Recovered Charge All - 2.7 - ~C TJ - 150·C.IF 1.5A. dlF/dt 100 A/~s

ton Forward Turn-on Time All Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

<l)TJ = 25°Cto 150·C. tID Pulse Test: Pulse width" 300~s. Duty Cycle" 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

2.20 2.20 r--r-....,..-.---r-....,..-.,..,~--r-.,....--,

1.98 -7~ aJ", PULlE TES~ 1.98 r- S~"' PU~SE TEJ ---11 !-HII~+--f---I--I
--+-
VOS> 1010n) x ROS(on) max.
1.76 VGS = 6V 1.76 I--t----t-c.:....:.--t-----'-t-'--r---+I-+-+-t----l
iii I.S4
iii
'" I.S4 I--f---I--+----t--+-......-+---t--t-------i
~:E ~
~ 1.32 ~ 1.32 I--f---t--+----t--+-t.._--t----t--t-------i
I-
::'i 1.10
'"
'"
B
z 0.88
«
'"c 0.66
E
SV
0.44

0.22

o 4~
o 20 40 60 80 100 10
VOS. ORAIN·TO-SOU RCE VOLTAGE (VOLTS) VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

2.20

~~
10V
1.98 - -SL,PULlETEJ :::::~V
~~
8V

1.76

~~
,VGS=6V - -! ~71 J. +-+-t.rt++--!''''
R 1 !
"--'I,.---+,,+-+--F'H-tI-- +--+'-----'*It---.lt--t.l-++tl

illliilliiiiiiir~iiii~lriT~1i
1
iii I.S4 1.0 IRF712.3 "
'"'"
~
~ 1.32
~"
I O.S

"
I-
z , OPERATION IN THIS '_0
~H---I-+AREA IS LIMITED
'"::>'"'" 1.10 H-N'I'/;t-"""d-+-+ItWr
HH--++~YI ~?s(on) ~ ~.
...z V 0_2

§r!:I~IIIIIIII'I~~IHflMlo++L~~I,tH
0.88
«
'"c
E
0.66 L 0.1
=TC - 2SoC 100 ms
0.44 / SV 0_05 =TJ = lS00C MAX. DC'

j~ -RthJC = 6.4 K/W -tt--++-++t--H IRF711 . 3f'"oo<ffi+t-ttH

III I
0.22 0.02 -~17Gl~ Pp WI.*-+-+---H-ttl l RF710. 2'::--+1++++++1
......

o
/ 4l 0_01 L-I-J--J....II......1u...L11J.J......J....J......L....J...J..U......
IIlI--'--'---U.L...........
o 10 1.0 10 20 50 100 200 SOD
VOS. ORAIN·TO-SOURCE VOLTAGE (VOLTS) VOS' ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-215
IRF710, IRF711, IRF712, IRF713 Devices

0=0.5
NOTES:

f--~.1
0.2 ~ :::iiijlllll
~ lfUL
EO.05
f--:
~ ~2~ 11
f--~ 1. DUTY FACTOR. 0 = Iz .
_om'" 10- SINGLE PULSE (TRANSIENT 2. PER UNIT BASE' RthJC = 6.4 oEG. CIW.
.J.ooo'"
/f' ~H~f~~L I~PEIOAN~E)I I 3. TJM - TC = PoM ZthJC(t/.

10-4 10-3 10"2 10-1 1.0 10

11. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

3.0 10

2.1 f--8~~'PUJSETEJT I I
vos> lo(on) x ROS(onl max. ifi 5.0
JL
in 2.4
/I
a:
f:il it! fl
~ 2. 1 ~
§
~ 1.8
TJ = -550C 5 2.0
a:
~
~ ~50C
a:
./ ~
=>

--
=> 1.5 TJ = I-- ~ 1.0
o
z
/
V ~
;(
a:
~ 1.2 TJ = \25 0C I-- o
V W
z
~ 0.9 / i/ ~
W
0.5
1;;
~V
~
a:
-= TJ = 1500C
~ 0.& ri: V' I

0.3
I E
0.2
I¥
TJ = 25 0C
J.
a
'I
O. 1
a 0.22 0.44 0.66 0.88 1.1 1.32 1.54 1.7& 1.98 2.2 1.0 2.0 3.0 4.0 5.0
10. DRAIN CURRENT (AMPERES) VSO. SoURCE·TO·oRAIN VOLTAGE (VOLTS)
Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.10 2.21

W 1.08 / 2.04 lL
'"~ / W
U
z L
o 1.07 < 1.86
> V
!o 1.05 / ~
iiia: 1.69 ..L
~S 1.03 / z
oS 1.52
/
Ww Ww
a:N
~~ 1.0 1 / UN
a:-
=> ....
0< 1.34
V
""",
a:'"
=>a:
~~ 0.99
/ oa:
'"="~
z - 1.17
V
~ /V ;(
V
..
~
Q
0.9 7

0.9 5
V
a:
o.

i
1.00

0.82
V
VGS =10V
10 =O.&A

~ V a: ~
~ 0.94 0.65 .L
0.92 /
-55 -34.5 -14 6.5 27 47.5 68 88.5 109 129.5 150
0.47
,,/
-55 -34.5 -14 6.5 27 47.5 68 88.5 109 129.5 150
TJ.JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage V,. Temperature Fig_ 9 - Normalized On-Resistance Vs_ Temperature
0-216
 IRF710, IRF711, IRF712, IRF713 Devices

20

VoS 80VJ
Vas = 200V
" ~~
I
Vos = 320V
I

~~ '"
A~
II
/ 10 =2A

V SjE FIGr E Ii
FOR TEST CIRCUIT_ I--

10 20 30 40 50 4 6 10
VoS. oRAIN·To-SoURCE VOLTAGE (VOLTS) 1Ig. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
10 2. 0

in - f-- -_. - -- ---

'"
(j.
VGs=l/
8" 9

'00'." """"'" ~"'"""'"'

w 1.6
'z"' PULSE OF 2.0 ~s DURATION. ---, VGS = 20V _ ..........
~ 8
ili
'"z
INITIAL TJ = 25 0 C. (HEATING
~s
EFFECT OF 2.0 PULSE IS MINIMAL.)
I I
h '"w
~
~ 1.2
......... .........
......
, I
-.....!RF710.711
o ....
......... , ' -
w
'"''"
::>
~ 6
.,.z
o
II ~
'"'"
::>
'"'z 0.8
- HRF712.713 .......... " '
r--..... ........

~ I <1
'"
Q

" ~
~
5
o / E
-_.
c
/ 0.4

,
-
o

"
~4
'" /'
3 o
o 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)
Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
20

_ 15

i
z
o
~
"" "\.
'\f\.
~ 10
i5
'"
~
\

"
~
.P
~
o 1\
o 20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-217
IRF710, IRF711, IRF712, IRF713 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

TO
VGS~trtp·L
OUT

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST Rl
TO OBTAIN
SPECIFIED 10 Rl

PULSE
GENERATOR O.U.T.
r-----'l
I
o - - - T O SCOPE
I O.OIn
I HIGH FREQUENCY
L_ SHUNT

Fig. 17 - Switching Time Test Circuit

.----0 +Vos
(ISOLATEO
SUPPl YI

SAME TYPE
AS OUT
12V
BATTERY

o~1.5mA - IG
OUT

____--"tJVv--o -Vas
10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-218
 PD-9.315

INTERNATIONAL RECTIFIER IIC)R I

HEXFET® TRANSISTORS IRF720
IRF721
N-Channel IRF722
IRF723
400 Volt, 1.8 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
The HEXFETe technology is the key to International Recti-
• Fast Switching
fier's advanced line of power MOSFET transistors. The effi- • Low Drive Current
cient geometry and unique processing of the HEXFET design • Ease of Paralleling
achieve very low on-state resistance combined with high • No Second Breakdown
transconductance and great device ruggedness,
• Excellent Temperature Stability
The HEXFET transistors also feature all of the well estab- Product Summary
lished advantages of MOSFETs such as voltage control, free-
dom from second breakdown, very fast switching, ease of Part Number VDS RDS(on) ID
paralleling, and temperature stability of the electrical param-
IRF720 400V 1.Sn 3.0A
eters.
IRF721 350V 1.Sn 3.0A
They are well suited for applications such as switching power
supplies, motor controls, inverters, choppers, audio amplifi- IRF722 400V 2.5n 2.5A
ers, and high energy pulse circuits. IRF723 350V 2.5n 2.5A

CASE STYLE AND DIMENSIONS

~
3.42 (0.135)
10.BB (0'420)~
TBB (0.380)
2.54(0.100) ~OIA

10.66 (0.420)
MAX. t~'±· TERM 3 - SOURCE

lB.61 (0.B50)

+-
14.23 (0.5BO)

l~:rFIN. T
B.35 (0.250)
MAX. 5.33(0.210)
f
:mr= d~ . .--L
4.83 (0.190)

14.73 (0.580) J...!lECTION X-X

MAX. 1.14(0.045)
0.31 (0.012)
0
i 1.77 (0.070) -l
TI--1
1.14(0.045)
051(0.020)
2.92 (0.115)
1.15 (0.045)
2.04 (0]8ii1

ACTUAL SIZE
Case Style TO·220AB
Dimensions in Millimeters and (Inches)

0-219
IRF720, IRF721, IRF722, IRF723 Devices

Absolute Maximum Ratings

Parameter IRF720 IRF721 IRF722 IRF723 Units
VOS Orain - Source Voltage CD 400 360 400 350 V
VOGR Orain - Gate Voltage (RGS = 1 Mil) CD 400 350 400 350 V
10@TC - 25°C Continuous Drain Current 3.0 3.0 2.5 2.5 A
10@TC = 100°C Continuous Drain Current 2.0 2.0 1.5 1.5 A
10M Pulsed Orain Current @ 12 12 10 10 A
VGS Gate - Source Voltage ±20 V
PO@TC·25°C Max. Power Dissipation 40 (See Fig. 14) W
Linear Derating Factor 0.32 (See Fig. 14) W/K
ILM Inductive Current. Clamped (See Fig. 15 and 16) L = lool'H A
12 I 12 I 10 I 10
TJ Operating Junction and
-55to 150 °C
Tstg Storage Temperature Range
Lead Temperature 300 (0.063.in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage" IRF720
IRF722
400 - - V VGS = OV
IRF721
IRF723
350 - - V 10 = 250"A
VGSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS, 10 = 250"A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS - 20V
IGSS Gate-Source Leakage Reverse ALL - - -600 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - - 250 "A VOS = Max. Rating, VGS = OV
ALL
- - 1000 I'A VOS - Max. RatingxO.8,VGS - OV, TC - 125°C
10(on) On-State Drain Current <ID IRF720
3.0 - - A
IRF721
VOS >10(on) x ROS(on) max.' VGS - 10V
IRF722
IRF723
2.5 - - A

ROS(on) Static Drain-Source On-State IRF720

Resistance <ID IRF721 - 1.5 1.8 II
VGS = 10V,I0 = 1.5A
IRF722
IRF723 - 1.8 2.5 11

gts Forward Transconductance ® ALL 1.0 2.0 - S (0) VOS >10(on) x ROS(on) max.' 10 - 1.5A
Ciss Input Capacitance ALL - 450 600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 100 200 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 20 40 pF
tdlonl Turn-On Oelay Time ALL - 20 40 ns VOO ~ 0.5 BV OSS ' 10 = 1.5A, Zo .. 5011
tr Rise Time ALL - 25 50 - ns See Fig. 17
td(off) Turn-Off Oelay Time ALL - 50 100 ns (MOSFET switching times are essentially
tf Fall Time ALL - 25 50 ns independent of operating temperature.)

Total Gate Charge V GS = 10V, 10 .. 4.0A, VOS - 0.8 Max. Rating.

Og
(Gate-Source Plus Gate-Orain)
ALL - 12 15 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Ogs Gate-Source Charge ALL - 6.0 - nC

°.l1.d Gate-Orain ("Miller") Charge ALL - 6.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 nH Measured from the
drain lead, 6mm (0.25
in.) from package to

.$
center of die.

LS Internal Source Inauctance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
Junction-to-Case
Case-ta-Sink Mounting surface flat, smooth, and greased.
Junction-to-Ambient Free Air Operation

0·220
 IRF720, IRF721, IRF722, IRF723 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF720 Modified MOSFET symbol
- - 3.0 A
(Body Diode) IRF721 showing the integral
reverse P-N junction rectifier.

~
IRF722
- - 2.5 A
IRF723
ISM Pulse Source Current IRF720
- - 12 A
(Body Diode) ® IRF721
IRF722
IRF723
- - 10 A

VSD Diode Forward Voltage ® IRF720

- - 1.6 V TC = 25'C, IS = 3.0A, VGS = OV
IRF721
IRF722
IRF723
- - 1.5 V TC = 25'C, IS = 2.5A, VGS = OV
trr Reverse Recovery Time ALL - 450 - ns T J - 150°C, IF - 3.0A, dlFldt - 100 AI~s

QRR Reverse Recovered Charge ALL - 3.1 - ~C TJ 150'C, IF = 3.0A, dlFldt 100 A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j)TJ = 25°C to 150°C. ® Pulse Test: Pulse width'; 300~s, Duty Cycle'; 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

6.0V
10V'
80J. pUlfETEJT f-- 80 {.lIs PUJE TESIT /I
I
I--
I I I I I
VDS> lO(on) x ROS(on) max. rtl
5.L V
l
U
VGS= 5 f
A
4.5V
Tj = moc,

Tj ~25ot
Tj=-55 0 C,
~
~ IJI
{I"
100 200 +
VOS, ORAIN·TO.sOURCE VOLTAGE (VOLTSI
300 1 4
~
~ Vj
r.. V
VGS, GATE·TO·SOURGE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

50

OPERATION IN THIS
II

-
/ AREA IS LIMITED
,~?' 20
IR'do,j
1/ BY RDS(on)

~l.5V- 10

I'
IRF722,3
~
10!"
80 {.IS PULSE rEST - ~ I~Fi20, \
'"
~
J'-
i"'"
VGS = 5.0V
!>
>-
il"i
0:
0:
IRF722,3
',1"1
'\.. '. , rr
110

I I
::J
'-'
1.0 "
J z
;;: 1m,

IL
0: 0.5
Q
4.5V
Eo , "
f
V 0.2
= TC = 25°C
TJ = 150 0 C MAX.
RthJC = 3.12 K/W IRF721'B " 10'm,
IIII

lJO~
II
r ov
0.1
== S'il.§!,E PULSE IRF720,2:- DC

'r 12 16 10
00.5
1.0 10 20 50 100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE (vOLTSI VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

D-221
IRF720, IRF721, IRF722, IRF723 Devices

I-
ffi
0;
z
<
"'_
I- I- 1.0
wz
>:::> o 0.5
;::'"
~~ 0.5
NOTES:

~ ~ 0.2
!:::!fa
.... "-
f-h.2

f--O.l
~
~ !fiIIIII JrUl..
~2~
1..-","
~:!!! 0.1 FO.05
"'0<....
z~~ 0.05 1--0.02
Uw 1. DUTY FACTOR. 0 = :~
~i=
~
~f-' SINGLE PULSE (TRANSIENT
2. PER UNIT BASE = RthJC = 3.12 OEG. CIW.
0.02 WIRI~AL I~P~OANICE\ I
U
3. TJM - TC = POM ZthJc(tl.
:2
N 0.01 1 I1111 I I
10-5 10-3 10-2 10-1 1.0 10
tl. SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

- soL,uJ"TE!T I
-
I I I I
- vos > 10(on) x ROS(on) max.
I
i 10
2

TJ 25 0C
'"
!! ....-
TJ= -55 0C- f--- I-
ffi
=-
_1--1" ~I ' TJ;-150 0C _

- '"

--
,..I--'"" a'"z
TJ = 25 0 C

~
TJ~ 125lc- -
V f-
~ 10

II V
V
V..... ~ ~ - w
'"ffi
a:;
'"
!-TJ = 150 0 C

~II
I
I

"'"
I' I
TJ~250C
1.0 I
o
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25
/
w
to
<
~ 115
w
~ 1.8
/
o
>
z ./
.... ~ /
~
.", iii
o
c
~a 1.05
~ '"
~s 1.4
/
.
Ww
"'N
::;
w< . /~
ww
UN
g~ /
~~ ~ ;gil!! /
~~ 0.95 ./ ~~ 1.0
o
'7
z
V <1
'"
'"§
l/
<1
'"o
~
V VG~= 10V_
I--
~ 0.85 0.6
V
.
>
'" /
\1.5A
I

0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ. JUNCTION TEMPERATURE (OC) TJ,JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-222
 IRF720, IRF721, IRF722, IRF723 Devices
1000

V~S = 0 I
20

1 1 ~ 1 MH~ .1f
Ci.. = Cgs. CUd. Cd. SHORTED ~
800 -
Cros = CUd ~
\ 0 15
VOS = 80V
v-
~OOV ~
~
Cgs CUd ~-
~
cgs+Cgd
~
~

w 600
1\ Co.. = Cd••

"'Cd•• CUd ~r---

w
to
«
~
VOS =

VOS = nov
I'---

~
u
\ ......
-- I 0
z >
«
.... w .J'!
<3 Ciss u 10
a:
«
"-
;3 400
u-
\
\
::>
0
~
..,
0 A W
\,
w 11'//
....
'",;,
to 5 1/
200
>'" lo=4A
\ .......... Coss / r-
...... to-- ""-
FOR TEST CIRCUIT

C'SS
/ jEE FI1URE It
10 20 30 40 50 8 12 16 20
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

/
ROS(on) MEASURED WITH CURRENT PULSE OF
2.01" DURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 1" PULSE IS MINIMAL.)

Jf/
----
VGS=I~
......... r--....
--
VGS = 20V

........ r-.. r---...r-..,

V -"r---...L"'--
IRF720.721

---
./
723..... ~
... ~ IRF722.

o
......
~,
10 12 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERESI Tc. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

40

35 '\
....
'"
....
«
~
z
0
>=
~
~
i5
'"
~
30

25

20

15
" '\.
'\
"\

"
~
ci
"-
10

\.
"
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power V,. Temperature Derating Curve

0-223
IRF720, IRF721, IRF722, IRF723 Devices

VARY tp TO OBTAIN Vas

REQUIRED PEAK IL

VGs:n EI

IL+----()----<~""""--'

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
GENERATOR O.U.T.
r------,
I
501l I 0 - - - TO SCOPE
I 0.011l
I I 50n HIGH FREUUENCY
L_ _ _ _ ...J
SHUNT

Fig. 17 - Switching Time Test Circuit

,...---0() +VOS
(ISOLA TEO
SUPPLY)

0~·5mA - --'.'''·' _ _-''<I"V"...--o -VOS

IG 10
CURRENT "::"' CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-224
 PD-9.306

INTERNATIONAL RECTIFIER II~~R I

HEXFET® TRANSISTORS IRF73D
IRF731
N-Channel IRF732
IRF733

400 Volt, 1.0 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFET® technology is the key to International Rectifier"s • Low Drive Current
advanced line of power MOSFET transistors. The efficient
geometry and unique processing of the HEXFET design achieve • Ease of Paralleling
very low on-state resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well established Product Summary
advantages of MOSFETs such as voltage control, freedom from
second breakdown, very fast switching, ease of paralleling, and Part Number VOS ROS(on) 10
temperature stability of the electrical parameters. IRF730 400V 1.0n 5.5A

They are well suited for applications such as switching power IRF731 350V 1.0n 5.5A
supplies, motor controls, inverters, choppers, audio amplifiers, IRF732 400V 1.5n 4.5A
and high energy pulse circuits. 4.5A
IRF733 350V 1.5n

~
CASE STYLE AND DIMENSIONS 3.4210.135)
10.6610.420)~
9.6610.380)
2.S410.100) 4.0810.1611 OIA

10.66 (0.420)
MAX. t"';
16.5110.650)
TERM 3 - SOURCE

+-
14.2310.560)

I~O'OFtN T
6.3510.250}
MAX.

d
5.3310.210)

t :~~t;: ~'
4.8310.190)

14.73 (0.580)
MAX.
,l- 1.1410.045)
~ECT10NX-X
0
0.3110.012)

i 1.1710.070) ---l
2.9210.115)
T~
1.1410.045}
0.5110.020}
1.1510.045)
2.0410.0801

ACTUAL SIZE Case Style TO-220AB

Dimensions in Millimeters and (Inches)

D-225
IRF730, IRF731, IRF732, IRF733 Devices

Absolute Maximum Ratings

Parameter IRF730 IRF731 IRF732 IRF733 Units

VOS Drain ~ Source Voltage <D 400 350 400 350 V

VOGR Drain - Gate Voltage (RGS = 1 M!lI <D 400 350 400 350 V
lO@TC-25°C Continuous Drain Current 5.5 5.5 4.5 4.5 A
lO@TC - 100°C Continuous Drain Current 3.5 3.5 3.0 3.0 A
10M Pulsed Drain Current @ 22 22 18 18 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25°C Max. Power Dissipation 75 (See Fig. 141 W
Linear Derating Factor 0.6 (See Fig. 141 W/K
ILM Inductive Current, Clamped (See Fig. 15 and 161 L = 1OO~H A
22 I 22 I 18 I 18
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mml from case for 10s1 °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF730
IRF732
400 - - V VGS = OV
IRF731
IRF733
350 - - V 10 = 250~A
VGSlthl Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS' 10 - 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - - 250 ~A VOS - Max. Raling, VGS - OV
ALL
- - 1000 ~A VOS = Max. Rating x 0.8. VGS - OV, TC - 125°C
lO(onl On-State Drain Current ~ IRF730
IRF731
5.5 - - A
V OS ) lO(onl x ROS(onl max.' V GS = 10V
IRF732
IRF733
4.5 - - A

ROS(an) Static Drain-Source On-State IRF730

- 0.8 1.0 Il
Resistance ® IRF731
IRF732
VGS = 10V,I0 = 3.0A
IRF733
- 1.0 1.5 Il

gfs Forward Transconductance ® ALL 3.0 4.0 - S (01 VOS ) 10(onl x ROS(onl max.' 10 - 3.0A
Ciss Input Capacitance ALL - 600 800 pF
VGS = OV, Vas = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 150 300 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 40 80 pF
tdlonl TurnMOn Delay Time ALL - - 30 ns VOO = 175V, 10 = 3.0A, Zo - 150
Ir Rise Time ALL - - 35 ns See Fig. 17
Idloff) Turn-Off Oelay Time ALL - - 55 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 35 ns
Qg Total Gate Charge
ALL - 18 30 nC
V GS = 10V, 10 • 7.0A, Vas = 0.8 Max. Rating.
IGate·Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 11 - nC

Qgd Gate-Orain ("Miller"l Charge ALL - 7.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

LS Internal Source Inductance ALL - 7.5 - nH

center of die.

Measured from the

source lead, 6mm
(0.25 in.1 from
package to source
bonding pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-Io-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-226
 IRF730, IRF731, IRF732, tRF733 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF730 Modified MOSFET symbol
- - 5.5 A
IBody Diode) IRF731 showing the integral
reverse pwN junction rectifier.
IRF732
- -

~
4.5 A
IRF733
ISM Pulse Source Current IRF730
IBody Diode) @ IRF731 - - 22 A

IRF732
IRF733
- - 18 A

VSD Diode Forward Voltage ® IRF730

- - 1.6 V TC = 25°C, IS = 5.5A, VGS = OV
IRF731
IRF732
IRF733
- - 1.5 V TC = 25°C, IS = 4.5A, VGS = OV

trr Reverse Recovery Time ALL - 600 - ns T J - 150°C, IF - 5.5A, dlF/dt - 100A/~s
QRR Reverse Recovered Charge ALL - 4.0 - ~C T J - 150°C, IF - 5.5A,dI F/dt - 100A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j) TJ = 25°C to 150°C. ® Pulse Test: Pulse width .. 300~s, Duty Cycle" 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

M 80/lS PULSE TEST

VG~: 5.L 80" Ipu lSE TEJT

VDS> IDlon) x RDSlon) max.

,
5.0V
TJ: +12S 0 C"

TJ: 2S 0 C,,--- ------r-.

TJ:-SSDC~
4.5V

I I
1
LfL
4.,V
.. .LI)I
50 100 ISO 200 250 300
VDS, DRAIN·TO·SOURCE VOLTAGE IVOLTS) VGS, GATE·TO·SOURCE VOLTAGE IVOLTS)

Fig. 1 - Typical Output Characteristics Fig, 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
50 AREA IS LIMITED
.I .l J lOfffv BY ROSlan)
I- 80 p' PU lSE TEST) L.. r- ~VGS-S.OV-
- -iRF73~, I -

-n
20

1/ :;;'"
w
10
732I'\1
, " 1\
J ~
....
-IRF730, I

IRF732,.3
1'- , 1O~,

If ~ , 111'
-
1
, I'
I 4.SV- a'" II~,L
~ :z
~ 1.0
,,- I

J
I' co

'" 0.5
=T C -2S DC
=TJ 150°C MAX.
.."
IiiI'
- RthJC : 1.67 K/W
'- 4.0V- r-- 0.2 _fI1GL~ PPWII IRF73I,3
IIII I ~
I?~tt
OC
1/ O. I
I I IIIII IRF730,2 r- IIII
10 1.0 10 20 50 100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE IVOLTS) V DS ' DRAIN·TO·SOURCE VOLTAGE IVOLTS)

Fig. 3 - Typical Saturation Characteristics Fig, 4 - Maximum Safe Operating Area

0-227
IRF730, IRF731, IRF732, IRF733 Devices
.
z
w

~
"'-
:; ~ 1.0
>::>
0=0.5
tiwa..ffi 0.5
- NOTES:

Iii;a Iii~·
....

Hl..JL
.... w -h.2
w",

~
fa:i
NO
0.2
0.1
~~
~:!!! 0.1 _0.05
"'-'
0< ,~,
~2~
z.~ 0.05
"'w
2:<:
';:"
~, 0.02
-
~0.01 SINGLE PULSE (TRANSIENT
rIIHERiAiIMPIEOjNICj) I II
1. OUTY FACTOR. 0 = :!
2. PER UNIT BASE = RthJC' 1.61 OEG. CIW.
3. TJM - TC' POM ZthJC(t).
~ 0.01 III I I IIII
10-5 10-2 10-1 1.0 10
tl.SQUARE WAVE PULSE OURATION (SECONOS) .

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

10
I
10 2
~ TJ = 25 0C
~
.'"as
~
~
~

---
I'-TJ = IS0 0C
TJ -5SOC -
a: /'
TJ = 2S OC
a:
B ...
/ . t::::-
z
:;;: //

t/- ---
T;' 12SJc_ 10
:5
.,.,~ /' w
'"
::i TJ = IS0 0 C I
/; 1;:
a: "I
tr vos> 10(on) x ROS(on) max.
180 "' pr lSE TEST
<i:
E I
I I "TJ = 25 0 C
1.0
I I I
10 o
10. ORAIN CURRENT (AMPERES) VSO.SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25

22
w
'"
<
~
>
~
1.15
..,. ",..
w
"'<z
l;;
1.8
V
/
o ~ 0;
o
:l! Q ~ ~
V
."'N
ww
:::;
w<
1.05

./
~~
z
os
Ww
"'N
a:-
14

/
./
~~ ."... ::>-'
0<
::>0
./ "I'"

..
~ ~ 0.95
o
Z
V
0'"
.. 0
z~ 10
:;;:
a:
- V
/
~ c
Cl 0.85 c
c /' VGS'10V

~ <n 0'6
~ 10 ' 2.0A
1;; a: '" ./ 1 I

0.75 0.2
-40 40 BO 120 160 -40 40 80 120
TJ. JUNCTION TEMPeRATURE 10C) TJ• JUNCT10N TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On·Resistance Vs. Temperature
0-228
 IRF730, IRF731, IRF732, IRF733 Devices
20
1000

"'~
1600
_I
Ciss
C",

COIS
=Cgd
•
~
~GS' J
1'1 MHz

Cga Cgd
Cd. + Cga + Cgd
--
=Cga+Cgd,CdSSHORTEO - -
J-
-
~
~ 15
w
c.:>
;o
.+- .L
Vos = SOV",

VOS' 320V, IRF730, 732 "- ~

vps = 2~OV "-

~
,
.,.A
1200 "'Cd.+ Cgd - >
w
'-' 10
;0 0:
U
~
~
=>
o
4
:'">-
:5 800 c'ss o
..olii ."
U
\ «

~- ~
c.:> 5

/
oj,
Coss c.:>
400 > 10 =7A

M2- I
FOR TEST CIRCUIT
SIEE FliuRE Ii -

10 20 30 40 50 16 24 32 40
VOS, DRAIN TO SOURC[ VOLTAGE (VOLTSI ago TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

10

VGS= 10v.

/v /VGS"20V-

r- I'--
V~ r-- r-- -r-. r--...
-
IRF730.731

I
,..,- -r-.~",
IRF732.733 .................

~
ROS(on) MEASURED WITH CURRENT PULSE OF
2.0 ~s OURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 I" PULSE IS MINIMAL.)
" ~,
.........

o
10 15 20 25 30 25 50 75 100 125 150
10. ORAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs_ Case Temperature

SO

70
- ~
'\
60 r\.
.
~
>-
~ 50
'\
'-
z
0
>=
~ 40
'\
@
0

'"~ 30
'\
'"
~
~ 20

10
I'\.
1"\
20 40 60 ~ 100 lW MO
Te. CASE TEMPERATURE (OC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-229
IRF730, IRF731, IRF732, IRF733 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

VGs:R
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

_...-----..Vo
TO SCOPE

Fig. 17 - Switching Time Test Circuit

r -_ _O'VOS
(ISOLATED
SUPPL VI

SAME TYPE
AS OUT
12V
BATTERY

oI=n.s -
mA
OUT

\I\,'\I"-_~"''v--o -VOS
IG 10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-230
 PD-9.375

INTERNATIONAL RECTIFIER II~~R I

HEXFET® TRANSISTORS IRF74D
N-CHANNEL
IRF741
PDWER MDBFETs IRF742
IRF743
400 Volt, 0.55 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
The HEXFE"f'!' technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFETtransis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state • No Second Breakdown
resistance combined with high transconductance • Excellent Temperature Stability
and great device ruggedness.
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as volt-
age control, freedom from second breakdown, very Part Number VOS ROS(on) 10
fast switching, ease of paralleling, and temperature IRF740 400V O.55n lOA
stability of the electrical parameters. IRF741 350V O.55n lOA
They are well suited for applications such as switch- IRF742 400V O.BOn B.OA
ing power supplies, motor controls, inverters, chop- IRF743 350V O.BOn 8.0A
pers, audio amplifiers, and high energy pulse circuits.

CASE STYLE AND DIMENSIONS 3.4210.1351

~ '0.6610'4201~
9.6610.38Di
2.5410.1001 4.0810.1611 DIA

10.66 (0.420)
MAX. T*'±
16.5110.6501
TERM 3 - SOURCE

+-d
14.2310.5601

1~:rFIN. T
6.35102601

t
14.73 (0.580)
MAX.
t I' I,
12L
14.7310.5801 ~ x ~X MAX.

1.1410.0451
0.3110.0121
5.3310.2101
4.8310.1901

l..!lECTION X-X
"
L.....J
TI-----l
~t ___ l (
1.7110.0701 ---1 1.1410.0451
0.5110.0201
1.1510.0451 2.9210.1151
2.0410.080)

ACTUAL SIZE Case Style TO·220AB

Dimensions in Millimeters and (Inches)

0-231
IRF740, IRF741, IRF742, IRF743 Devices

Absolute Maximum Ratings

Parameter IRF740 IRF741 IRF742 IRF743 Units
VOS Drain - Source Voltage <D 400 350 400 350 V
VOGR Drain - Gate Voltage IRGS = 1 Mill <D 400 350 400 350 V
10@TC- 25·C Continuous Drain Current 10 10 8.0 8.0 A
10@TC= 100·C Continuous Drain Current 6.0 6.0 5.0 5.0 A
10M Pulsed Drain Current @ 40 40 32 32 A
VGS Gate - Source Voltage ±20 V
Po @TC - 25·C Max. Power Dissipation 125 ISee Fig. 14) W
Linear Derating Factor 1.0 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = 1OO~H
A
40 I 40 I 32 I 32
TJ Operating Junction and
-55to 150 ·C
T stg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm) from case for 10s) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain· Source Breakdown Voltage IRF740
400 - - V VGS = OV
IRF742
IRF741
IRF743
350 - - V 10 = 250~A

V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - V GS' 10 - 250~A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 ,..A VOS - Max. Rating, VGS - OV
- - 1000 p.A VOS - Max. Rating x 0.8, VGS - OV, T C - 125·C
1010n) On-State Drain Current ® IRF740
10 - - A
IRF741
IRF742
VOS ) 1010n) xBOSlon) max.' V GS = 10V
IRF743
8.0 - - A

ROS(on) Static Drain-Source On-State IRF740

- 0.47 0.55 !l
Resistance ® IRF741
VGS = 10V, 10 = 5.0A
IRF742
IRF743
- .68 .80 !l

gfs Forward Transconductance ® ALL 4.0 7.0 - S 1m VOS ) 1010n) x ROSlon) max.' 10 - 5.0A
Ciss Input Capacitance ALL - 1250 1600 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 300 450 pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - BO 150 pF
tdlon) Turn~On Delay Time ALL - 17 35 ns VOO = 175V, 10 = 5.0A, Zo = 4.711
tr Rise Time ALL - 5.0 15 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 45 90 ns IMOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 16 35 ns
Qg Total Gate Charge
ALL - 41 60 nC V GS = 10V, 10 = 12A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 18 - nC

Qgd Gate-Drain I"Miller") Charge ALL - 23 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm 10.25

.$
in.) from package to
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
10.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-232
 IRF740, IRF741, IRF742, IRF743 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF740 Modified MOSFET symbol
(Body Diode) IRF741 - - 10 A
showing the integral
reverse P~N junction rectifier.
IRF742
- - B.O A

~~
IRF743
ISM Pulse Source Current IRF740
(Body Diode) @ IRF741
- - 40 A

IRF742
IRF743
- - 32 A

VSD Diode Forward Voltage @ IRF740

IRF741 - - 2.0 V TC = 25°C. IS = lOA. VGS = OV
IRF742
IRF743
- - 1.9 V TC = 25°C. IS = S.OA. VGS = OV
t" Reverse Recovery Time ALL - SOO - ns TJ = 150°C. IF - lOA. dlF/dt & 100A/~s

ORR Reverse Recovered Charge ALL - 5.7 - ~C TJ = 150°C. IF • 10A.dlF/dt = 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j) TJ = 25°C to 150°C. @PulseTest:Pulsewidth" 300~s. Duty Cycle .. 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 51.

25 25
1°il'PV
80 '" PULSETEST
TJ' !550 C
UI
j
i'-- VI
, I
7'V
••

,,
20 20 TJ -25 0 C
iii
oc
II iii
or:
I
TJ·125 0C
.........
'I
...w
:E
~
:Ii J
~ 15 ~ 15
~
z
w
oc
oc
::0
<>
, J
VGS' 6V
~
z
w
or:
or:
:::>
<>
_1O",PlJLSETEST
"OS > I~(on) ~ ROS(on) ma•.

,
z 10 z 10
;;:
oc
'"
p
I ;;:
or:
'"
p
J
II
5~ J.
4~ ~
20 40 60 80 100 4 W
VOS. ORAIN·TO.sOURCE VOLTAGE (VOLTS) VGS. GATE-TO.sOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100 OPERATION IN THIS

25
AREA IS LIMITED
_l"'PIJ~ETE~ SO r-IRF740. I BY ROS(on)
.L
IRF742.3
20 20 .~
I' " I,
~
iii
oc
w
~
10V
9V- f---
BV,
...... ~ 10
IRF740. I
'. I' 10~.

100~.

~ 15 ""....
~
~IRF742.3

z
~
~ i5 ,.
...0IIII
, 1 ms

---
w
or: or:
III
~~ ~6V- I--
or: or:
::0
<>
z 10
:>
<>
z
,
;;: ;;:
~ IP'"
10m.
or: oc 1.0
'" '" =TC=2SoC
p
~
p
= lOOms
, ~
'I
O.S TJ -IS0a C MAX.
- RthJC = 1.0 KIW
~
GS =5,V- I--
0.2
- SINGLE PULSE IRF741.3 .... ~~
./ 4~ 0.1 I 111I1 JU 1'17 II
6 10 1.0 10 20 50 100 200 500
VOS. ORAIN·TO.sOURCE VOLTAGE (VOLTS) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-233
IRF740, IRF741, IRF742, IRF743 Devices

...
z
w
0;
z
<
e:wz j::" 1.0

--
>=> 0=0.5
tiwo..ffi

----i~
0.5 NOTES:
'-~2
mIL
tt:~

-
w<.>
ffi ~ 0.2
NO '-0.1
:ne
~:!! 0.1 t====0.05
"'0<....
":il1 0.05
'-0.02 ;! ~ ~2~
<'>w
;;00.01- SINGLE PULSE (TRANSIENT
1. DUTY FACTOR. 0 = :~
}~
E<.> 0.02
--r-r THERMAL IMPEDANCE) 2. PER UNIT BASE' RthJC = 1.0 DEG. CIW.
3. TJM - TC = PDM ZthJc(t)·
j 0.01 I I I II III
10-5 10-4 10-3 10-2 5 10-1 1.0 10
'1. SQUARE WAVE PULSE DURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

15
f
r-J",puJSETEJ 20
v'os > I~(on) ~ RDS(on) ma~. 0;
w I
a:

f
w
0..
TJ' -55 0 C :;;

/
~
.....
~ 10

w
a:
a:
TJ = 25 0 C
/ .
=>
<.>

~ T~' 1ZJoC
;(
a:
0 TJ = 1500 C
VI
!J 1/ w

,
'"
a:
w
>
/I w
a:

'" r-- TJ = 25.1C

E
i I
1.0
I
10 15 20 25 o
10. DRAIN CURRENT (AMPERES) VSD. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

1.25 2.5

w w
~
c..>
~ z
~ 1.15 ~ 2.0
./
>
."
,.",. illa: /~
~
~
,."
o
~E 1.05
"".",. /
Ww
a:N
"':::; .,..~ ;ga
ow
w!::!
1.5
/'
~i
<.>-'
",/ a:<
=>::I! ~ .,
=>0
~~ 0.95 ./ 00:
6~ 1.0
./
.,.oz V ...Z - . . . 1/" vGs= 10V
;( ID=5.5A - -
~ 0:
",/
~ 0.85 '"i 0.5
o
&; i?l
0:

0.75
-40 40 80 120 160 0-40 0 40 80 120 160
Tj. JUNCTION TEMPERATURE (DC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-234
 IRF740, IRF741, IRF742, IRF743 Devices
2000

_
Ci,,·Cgr+Cgd.Cd,SHORTEO.l
Cns =Cgd _VGS=OV
J 20
CCgrCgd t= 1 MHz
1600
~ C.. = Cds + gr+ Cgd
.. Cd, + Cgd

\ "
I
........"'-
A~
... C!..
VDS=80~~
I I
~ 1200 VOS·200V
<.)
z
\ I I~

W
~

~ , VOS=320V~

~
,
_ 800 \.
\ "- ....... I -
'- /
10 = 12A

~
400

"" --
FOR TEST CIRCUIT

w ~
~ ",,-Cns
~ ~ ~ ~ 40 ~
-~
I
20 40
SEE FIGr E 18

60
-
1

80
VOS. ORAIN·TO.sOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage

1.6 10
<n
:IE
"
S
w
<.)
z
«
ROS(on) MEASURED WITH CURRENT PULSE OF
2.0 ~s DURATION. INITIAL TJ = 250 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.) V
VGS~lOV/ /
"
..........
~

~
........
In 1.2
I"-
iii0:
Z
~=2DV i". ... "-. "'""",
",-
0 IRF740.741 _ -
~
0:
:::>
0 0.8 / IRF742.743
'">:-z V ........
' t\,.\
-
0
......
. ..,- ~
0:

'"
~ 0.4
,...,."
."
,~
0:'"
'\,
10 20 30 40
o
25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

140

io-- ~
120

~
~ 100 '" "
z
o
~
iii
c0:
80

60
'" "r\.
r\..

"' "
w
;t
~
...640
20 "'"
20 40 60 80 100
Tc. CASE TEMPERATURE (DC)
"'t\
120 140

Fig. 14 - Power Vs. Temperature Derating Curve

0-235
IRF740, IRF741, IRF742, IRF743 Devices

VARY tp TO OBTAIN
REQUIRED PEAK Il

V~=~ _OU_T~_r-r
I L _ - _ o -_ _ _....,.........

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

175V
ADJUST RL TO OBTAIN 3m
SPECIFIED 10
Vos

r;U-; - - -1 D.n
I GENERATOR C>-i-------<=>----'''-t-~

I :~~RCE Jl I
LIMPEDANCE
___ J

Fig. 17 - Switching Time Test Circuit

. - - - - 0 +VDS
(ISOLATED
SUPPLY)

or=[1.5mA - 16 10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-236
 PD·9.324

INTERNATIONAL RECTIFIER II'~R I

HEXFET® TRANSISTORS IRFS2a

IRFB21
N·Channal IRFse2
IRFS23

500 Volt, 3.0 Ohm HEXFET Features:

TO·220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFET e technology is the key to International
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the • Ease of Paralleli ng
HEXFET design achieve very low on-state resistance • No Second Breakdown
combined with high transconductance and great • Excellent Temperature Stability
device ruggedness.
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as voltage
Part Number VOS ROS(on) 10
control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature IRF820 SOOV 3.0n 2.SA
stability of the electrical parameters.
IRF821 4S0V 3.0n 2.SA
They are well suited for applications such as switching IRF822 SOOV 4.0n 2.0A
power supplies, motor controls, inverters, choppers,
IRF823 4S0V 4.0n 2.0A
audio amplifiers, and high energy pulse circuits.

CASE STYLE AND DIMENSIONS

3.42 (0.1351
~'B66!D:mI~
:as (0 TERM4-
DRAIN

T*~'"
10.66 (0.420)
MAX.

'~~'~~t~
161}~=

+-
14. (

1~:rFIN. T W(o.,;r
~I
6.35 (02501 r 1°UllI
299 0

t
LX
MAX. 5.33 (02101
14.73 (0.580)
14.13 (D.5801 X --1. 4.8310.1901

Mr· o:momJ, D
1.14 (0.D451
J-.--I
~ECTIONX-X

1.17 0.0701 -l
2.92(0.1151
~::;~::I
1.15 0.D45
~
ACTUAL SIZE
Case Style T().220AB
Dimensions in Millimeters and (Inches)

0·237
IRF820, IRF821, IRF822, IRF823 Devices

Absolute tJlaximum Ratings

Parameter' IRF820 IRF821 IRF822 IRF823 Units
VOS Orain - Source Voltage <D 500 450 500 450 V
VOGR Orain - Gate Voltage (RGS = 1 Mill CD 500 450 500 450 V
10@TC= 25°C Continuous Drain Current 2.5 2.5 2.0 2.0 A
10@TC = 100°C Continuous Drain Current 1.5 1.5 1.0 1.0 A
10M Pulsed Orain Current ® 10 10 8.0 8.0 A
VGS Gate - Source Voltage ±20 V
PO@TC=25OC Max. Power Dissipation 40 (See Fig. 141 W
linear Derating Factor 0.32 (See Fig. 141 W/K
ILM Inductive Current, Clamped (See Fig, 15 and lSI L = 100!,H
A
10 I 10 I 8.0 I 8.0
TJ Operating Junction and
-55to 150 °C
TS!ll Storage Temperature Range
Lead Temperature 300 (0.OS3 in. (l.Smml from ca.e for 10.1 °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF820
500 - - V VGS = OV
IRF822
IRFB21
IRFB23
450 - - V 10 = 250!,A

V GSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VOS - VGS, 10 - 250!,A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current - - 250 !'A VOS = Max. Rating, VGS = OV
ALL
- - 1000 !,A VOS - Max. Rating x 0.8, VGS - OV, T C - 125°C
)O(onl On-State Drain Current ® IRF820
2.5 - - A
IRF821
VOS ) 10(oni x ROS(oni max.' VGS = 10V
IRF822
IRF823
2.0 - - A

ROSton) Static Drain-Source On-State IRF820

- 2.5 3.0 Il
Resistance ® IRF821
VGS = 10V,I0 = 1.0A
IRF822
IRF823 - 3.0 4.0 Il

9fs Forward Transconductance ® ALL 1.0 1.75 - S (01 VOS ) 10(oni x ROS(oni max.' 10 = LOA
Ciss Input Capacitance ALL - 300 400 pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 75 150 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 20 40 pF
td(on) Turn~On Delay Time ALL - 30 60 ns VOO = 0.5 BV OSS ' 10 = 1.0A, Zo - 501l
tr Rise Time ALL - 25 50 ns See Fig. 17
td19ffl Turn-Off Oelay Time ALL - 30 SO ns (MOSFET switching times are essentially
Fall Time - independent of operating temperature.)
tf ALL 15 30 ns
Qg Total Gate Charge
ALL - 11 15 nC
V GS = 10V,I 0 = 3.0A, VOS = 0.8 Max. Rating.
(Gate~Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 5.0 - nC

Qgd Gate-Orain ("Millar") Charge ALL - 6.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, Smm (0.25
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-238
 IRF820, IRF821, IRF822, IRF823 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF820 Modified MOSFET symbol
(Body Diode) IRF821
- - 2.5 A
showing the integral
reverse P-N junction rectifier.
IRF822
- - 2.0 A

~
IRF823
ISM Pulse Source Current IRF820
- - 10 A
(Body Diode) @ IRF821
IRF822
IRF823
- - 8.0 A

VSD Diode Forward Voltage @ IRF820

IRF821
- - 1.6 V TC = 25°C, IS = 2.5A, VGS = OV
IRF822
IRF823
- - 1.5 V TC = 25°C, IS = 2.0A, VGS = OV
t" Reverse Recovery Time ALL - 600 - ns T J - 150°C, IF - 2.5A,dl F/dt - 100A/~s
ORR Reverse Recovered Charge ALL - 3.5 - ~C TJ 150°C, IF 2.5A, dlF/dt 100 A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'

<D TJ = 25°Cto 150°C. @PulseTest: Pulse width" 300~s, Duty Cycle" 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

5
7.5V 7.0V ,I L
VGS = 6.5V -sL. PU!SETEJ
I
I
~
I I I I

~ r- so l, PU JE TEST
Vas> 10(on) x ROS(on) max.

, 6.0V

- _TJ= 125 0 C I

T I I
TJ=25 0 C

TJ = -55 0 C'-..
~ IJ
~I
1.
T 1; Y
~~
4.5V
I
4.0V
50 100 150 200 250 10
Vas, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

50
p7.0V J
- sl", PulSE TEJ ~,- 6.V'!!!!!!!! ~ 20
OPERATION IN THIS
AREA IS LlMITEO
BY ROS(on)
IRF820,1
10
1/ i,. IRF822,3

~ 6.0V- ~
:! IRF820,1
10!"

I', I"- III

",
I-

"V' :ii

/
'"'":::>
<.>
z
1.0
IRF822,3
-' ",- lru"
,,- 5 y = F= <1
J '"c 0.5 .11 "l'r
If _ 1.
E - TC:25 D C I'
,-, III
Y= F=
•
0.2 -TJ= 150D CMAX. tOms
Vi S - 5 "-
I - RthJC = 3.12 K/W
0.1 =,SINGLE PULSE IRf8~I,~~
4.~V_
r-- IRF820, 2,'"
DC
4.0V=== 0.5
12 16 20 1.0 10 20 50 100 200 500
VOS, ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area
0-239
IRF820, IRF821, IRF822, IRF823 Devices

0=0.5
NOTES:
iii
-h.2

-0.1
~ t:;;j fiiPI
:ioII lJLfL.
f:=iJ.05
F--iJ.02
-~
~2~
r- 1. DUTY FACTOR. 0 = :~
~~ SINGLE PULSE (TRANSIENT
2. PER UNIT BASE = R.hJC· 3.12 OEG. CIW.
WIRI~AL I~P~OANICE\J
3. TJM - TC= POM Z.hJC(')·
I 11111 I I I
10-4 10-3 10-2 10-1 1.0 10
'1. SQUARE WAVE PULSE DURATION (SECONDSI

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

80 ~s PULSE TEST
I I I
I _I
10 2
I--VDS> 10(on) x ROS(on) max.
~ '"w
« TJ;~ ~
i'li J
§
J.....--" ~ ~~I
TJ=25~ '"...
~

n
w
~
U
z V TJ=250S
«
G V i..-" ~ II:
=> ......
=>
VV ~
~ 1250 t U

- .-.
c TJ Z
z
~ 10 TJ = 1500C ~TJ=1500C=
~ 2 =
z
«
...'"
l;j ~ 0
w
'"~ 1

I. ~ > I
~ w
11 L::::-TJ = 25 0C
'"
I .9 '" II I
lLL ~
I
If 1.0 I
o
10. DRAIN CURRENT (AMPERES) VSO. SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.2 5 2.6
V~s = lov
r- 1-10·2.5A lL
w
~
;'"o w
U 2.2

>
1.1 5

....". I-'
Z

~ lL
z
~
o i-""'"
iii
'"z 1.8 L
~s 1.05 ~ 0
ww
0 V
Ww
"'N
"'::l ..... ,/ UN
g~ 1.4
/
~i 6~ I'
=>0
5;!:. 0.9
. /V ~~
..,.o 5t1"" :;;: V'
z '"
o 1.0 ",
:;;: c L
II: o
o
.;
gj
O.B 5
~ o. 6 ./
I'"
i1i ~
0.7 5 o. 2
-40 40 80 120 160 -40 40 80 120 160
TJ. JUNCTION TEMPERATURE (OC) TJ.JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-240
 IRF820, IRF821, IRF822, IRF823 Devices
1000
20
I
I VGS = 0
J J f=l 1MH, 1 J. - ;;; VDS = 100V
~
800 Ciss =Cgo+Cgd,Cd.SHORTED- :; I I
C", = Cgd 0 15 VDS = 250V

~~
Cgo Cgd - - ~
w
I I
~
..: c"" = Cd. + Cgo + Cgd
'":;<!
Vos = 400V.IRF820.822
oS
600 - -

"
w "'Cd.+ Cgd

~
<> 0
z >
;:!: I
c::;
~
<> 400
I ~ V
U
\ '- Ciss
If
'U

200 \' I
.J
\ ................ ~~ .1 10=3A

Ii -
Co.. FOR TEST CIRCUIT

t-- C,;-
/ SjE FIG,URE

10 20 30 40 50 12 16 20
VOS. DRAIN·TO·SOURCE VOLTAGE IVOL TS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to·Source Voltage
3.0
I
VGS=10V/.

Iv, S=20V
'"w
2.4 1'00..
..........
r-.....
If ~::E
!'i. 1.8
r-.... ....... l""- I'-.... ~20,821

r-- -I::;~ .......

....

I
e:
LU
a::
a:

i'-- ........
' .....
,
::>
<>
'I e: 1.2

/
«
a:
0 ~
~
E
/
/ 0.6
3
V' ROS(on) MEASURED WITH CURRENT PULSE OF '\.,
2 " 2.0", DURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 '" PULSE IS MINIMAL.)
10 12 14
o
25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE.IOC)
Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain CUrrent V,. Case Temperature
40

35
'\
~
30
r'\
...
!z 25
\.
.....
0
;:: \
20
I\..
ilj
Ci
a:
~ 15
\
...
'\
0

~
10

'\.
20 40 60 80 100
TC, CASE TEMPERATURE (DC)

Fig. 14 - Power V,. Temperature Derating Curve

120
"
140

0-241
IRF820, IRF821, IRF822, IRF823 Devices

VARY tp TO OBTAIN
REQUIRED PEAK IL

Tn
VGS;r,r-'"L OUT

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r------,
I
50n I - <>--_TO SCOPE
I O.Oln
I I 50n HIGH FREo.uENCY
L_ ___ .J SHUNT

Fig. 17 - Switching Time Test Circuit

...---0 +VOS
(ISOLATED
SUPPLY)

0~1.5mA - IG
\r'_~''''''r-O -VOS
10
CURRENT ":" CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-242
 PD-9.311

INTERNATIONAL RECTIFIER I ICiR I

HEXFET® TRANSISTORS IRFB3D

IRFB31
N-Channel IRFB32
IRFB33

500 Volt, 1.5 Ohm HEXFET Features:

TO-220AB Plastic Package • Compact Plastic Package
• Fast Switching
The HEXFET8l technology is the key to International Rectifier's
advanced line of power MOSFET transistors. The efficient
• Low Drive Current
geometry and unique processing of the HEXFET design achieve • Ease of Paralleling
very low on-state resistance combined with high transconductance • No Second Breakdown
and great device ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well established Product Summary
advantages of MOSFETs such as voltage control, freedom from
second breakdown, very fast switching, ease of paralleling, and Part Number VOS ROS(on) '0
temperature stability of the electrical parameters. IRF830 500V 1.5n 4.5A
IRF831 450V 1.5H 4.5A
They are well suited for applications such as switching power
supplies, motor controls, inverters, choppers, audio amplifiers, IRF832 500V 2.0n 4.0A
and high energy pulse circuits. IRF833 450V 2.0n 4.0A

TERM 4-
CASE STYLE AND DIMENSIONS DRAIN
1-1.39 10.066)
I 0.51 10.020)

10.66 (0.420)
MAX.
T:~~M2 ~~-D~:~:CE
TERM I-GATE

4J210.;;r
~I
2.7910.110)
f.29i[iiiOj
5.3310.210)

t
14.73 (0.580)
4.8310.190)

~ECTlONX-X
D
Mr·
1.1410.045)
ffi1D.mj
Tl----.j
1.1410,045)
-l
2S210.115)
0.51 10.020)
2.04 10.090)

ACTUAL SIZE Case Style TO-220AB

Dimensions in Millimeters and (Inches)

0-243
IRF830, IRF831, IRF832, IRF833 Devices

Absolute Maximum Ratings

Parameter IRF830 IRF831 IRF832 IRF833 Units
VOS Drain - Source Voltage <D 500 450 500 450 V
VOGR Drain - Gate Voltage (RGS = 1 Mil) <D 500 450 500 450 V
10@TC = 25°C Continuous Drain Current 4.5 4.5 4.0 4.0 A
10@TC = 100°C Continuous Drain Current 3.0 3.0 2.5 2.5 A
10M Pulsed Drain Current ® 18 18 16 16 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25°C Max. Power Dissipation 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 14) WIK
ILM Inductive Current, Clamped (See Fig. 15 and 16) ~ = 100!,H
A
18 I lB I 16 I 16
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRFB30
IRF832
500 - - V VGS = OV

IRF831
IRF833
450 - - V 10 - 250!,A

VGSlthl Gate Threshold Voltaga ALL 2.0 - 4.0 V VOS - V GS ' 10 = 250!,A
IGSS Gate-Source Leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS = -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 p.A VOS - Max. Rating, VGS - OV
- - 1000 I'A VOS = Max. Rating xO.B, VGS = OV, TC = 125°C
10(on) On-State Drain Current CID IRF830
IRF831
4.5 - - A

IRFB32
VOS ) 10(on) x ROS(on) max.' V GS = 10V
IRF833
4.0 - - A

ROS(on) Static Orain-Sourca On-State IRFB30

Resistence @ IRF831
- 1.3 1.5 11
IRFS32
VGS = 10V, 10 = 2.5A
IRFS33 - 1.5 2.0 11

9fs Forward Transconductance <ID ALL 2.5 3.25 - sun VOS ) 10(on) x ROS(on) max.' 10 - 2.5A
Ciss Input Capacnance ALL - 600 SOO pF
VGS = OV, VOS = 25V, f = 1.0 MHz
Coss Output Capacitance ALL - 100 200' pF
See Fig. 10
Crss Reverse Transfer Capacitance ALL - 30 60 pF
tdlonl , Turn-On Delay Time ALL '- - 30 ns VOO = 225V,I 0 = 2.5A, Zo • 1511
tr Rise Time ALL - - 30 ns See Fig. 17
tdloffl Turn-Off Delay Time ALL - - 55 ns IMOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - - 30 ns
Qg Total Gate Charge V GS - 10V,1 0 • 6.0A, VOS • O.S Max. Rating.
IGate-Source Plus Gate-Drainl
ALL - 22 30 nC
See Fig. 18 for test circuit. IGate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 11 - nC

Ogd Gate·Orain ("Miller") Charge ALL - 11 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.26
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case·to-Sink Mounting surface flat. smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-244
 IRF830, IRF831, IRF832, IRF833 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF830 Modified MOSFET symbol
(Body Diode) IRF831
- - 4.5 A
showing the integral
IRF832 reverse PMN junction rectifier.
- - 4.0 A

~
IRF833
ISM Pulse Source Current IRF830
(Body Diode)@ IRF831
- - 18 A

IRF832
IRF833
- - 16 A

VSD Diode Forward Voltage tID IRF830

- - 1.6 V TC = 25°C, IS = 4.5A, VGS = OV
IRF831
IRF832
IRF833 - - 1.5 V TC = 25°C, IS = 4.0A, VGS = OV
trr Reverse Recovery Time ALL - 800 - ns TJ - 150°C, IF - 4.5A, dlF/dt = 100A/~s
ORR Reverse Recovered Charge ALL - 4.6 - ~C TJ - 150°C,I F = 4.5A,dI F/dt - 100A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

<DTJ = 25°C to 150°C. tID Pulse Test: Pulse width'; 300~s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

10V 5.5V
I
r-lso •• LLSEITEST
so " ~U LSETEST
VOS > 10(on) x RDS(on) max.
r
VGS = 5.0V

- r-TJ=~125OC,

TJ ~ 25 OC,
TJ=-550C,
~
T 1"--...'" I;L
rJ./
1 / 1/,
100 200
T 300
~
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

100
OPERATION IN THIS
50 AREA IS LIMITED

- sO~'PUJE TESJ 10~y

V.~.51_ ( - -
BY RDS(on)

lJ' 20
~p'
~
~. r'
IRF832,3
i.' ~
/ I-""'
5.u!= ::::: '"
,.
~
10

/, / ~
I-
i=iRF830,1
lOps
)~ ~ r-IRF832,3 IIII
'"
'":::> ,.
, I' \. lOOps

V '-'
:z:
,
? I-'""
VGS = 4.5\/=
= ~
c
.P
1.0

f:=T C = 25°C
I, Ims

I
) 0.5
t::TJ = 150°C MAX. 10ms
' - RthJC = 1.67 K/W
lOOms
1 4.01"'= i"""'" 0.2 r-FINGL~ PIUWII IRF831,3
::::::::p
~~tti
)11 I
iI' 10
O. 1
1.0
IIIII
10 20 50 100 200
IRF830,2
500
VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VDS' DRAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-245
IRF830, IRF831, IRF832, IRF833 Devices

I-
:5
0;
z
<
"'-
I-I::
wz
1.0
>::::> D = 0.5
;::'" 0.5
uw NOTES:
~~
wu
oZ 0.2
w<
NO
.......
-w
<:;
: ; - 0.1 ,-=0.05
r-0.2

0.1 illJL
"' ....
0< -~.

Zj~ 0.05 ~0.01 SINGLE PULSE (TRANSIENT _ '1

Uw
:2:>: ~ THERMAL IMPEDANCE) 1. DUTY FACTOR. D - 12 .
",I-
0; 0.02
t--+-t---'1r-t-++++'UII I T I 1111,t--t-+--+-++++t-tt--+-t--+-H+t+t+-t-t 2. PER UNIT BASE = RlhJC = 1.67 OEG. CIW.
-r. 1--++-++++++ttlll-HI-H-jt-tt-11Hll+-++++H-Htt-+-t-+H-t+-Ht-H 3. TJM - TC = POM flhJC(t)·
N
il 0.01
10-5 10-2 10-1 1.0 10
I,. SQUARE WAVE PULSE OU RATION (SECONDS)
Fig. 5 - Maximum Effective Transient Thermal Impedance. Junction·to·Case Vs. Pulse Duration

./ ~
TJ I= -55 0 t:.--
- I-

iii
102
I

TJ = 25°C

,/ Tr~ ...::;;~ ~

tJ125 L-
--- -
~
1/ ./ I-
Z
w
/'
.J1If' "TJ = 150°C_

...
0
'"
/ V '"
B
/ V . /V Z
~ 10 //
o

II ,/ w
'"
'"
w TJ - 150°C I

// ~
'"co: "t
lib'I Vos> 10(on) x ROS(on) max. E'
I
I
fo.-. TJ = 250C
f 10 pi PU~SE TE1'
1.0
I I I
o
10. DRAIN CURRENT IAMPERESI VSO.SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w
/
'"~
1.15
w
U
Z
<
1.8
/
<>
>
Z
;: ~ i-'"
In
iii /
,.",.. ~
o '"Z
o
:::! 00 1.4 /
..
Ww
"'N
0
:::;
1.06
..,~ Ww
UN
"'-
::::> ....
0<
/
~i ",.. "/:&

~~ 0.95 ./
0'"
'"="~
z - 1.0
/
..,<>
Z
", ;;:
'"0 /
:
o
c
0
V VGS = 10V
r--
~ 0.85 '"
0 0.6
10=I.SA -

,V
'" -I I
~

0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE laC) TJ.JUNCTION TEMPERATURE 1°C)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-246
 IRF830, IRF831, IRF832, IRF833 Devices
2000
20
)GS' 01
_I f ' l MHz 1
Cjss • Cgs + Cgd. Cd. SHORTEO _
J
1600
C'" • Cgd ~o 15
Cgs Cgd VOS =100V

~~
-
Coss • Cd. + Cgs + Cgd
~
w
I V
~
VOS',250V
1200 "'Cd. + Cgd - '"~
«

~V
w Vos - 400V
u o
z
« >
t-
~ 10
~
U

~
~
«
::J
o
'/
u 800 _C'SS "?
u- o
\ '" /I '/
400
l'"- ........
~
~
'".;,
>'"
5

/ 10 =6A
FOR TEST CI RCUIT- -
~~ 1"-00.. / SEi FIGiRE 18
1

10 20 30 40 50 16 24 32 40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTSI Qg. TOTAL GATE CHARGE (nCI

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
ROS(onl MEASUREO WITH CURRENT PULSE OF
2.0 ~s OURATION. INITIAL TJ' 25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMALII ............
i"...
VGSI'10V~
r--
......... i"... .... ,
........ , ~F830.831

'-
V
VGS = 20V I-- 1--1 RF832. 833
........ ,"-
/ I"--. ~
~
,
.......
/ ~
~
,,/
V
,"
1 o
o 10 15 20 25 25 50 75 100 125 150
10. ORAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
80

~
f---
70
'\
60
'\.
~
t-
«
i!; 50
'\ '\.
z
0
;:::
~
;;; 40
'\
'"
Q
'"
~ 30
'\
'"
~
~
20

10 I\. '\
r\
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (OCI

Fig. 14 - Power Vs. Temperature Derating Curve

0-247
IRF830, IRF831, IRF832, IRF833 Devices

VARY tp TO OBTAIN
REQUIRED PEAK 'L

VGS-R 'L_---<)----4~w.-J

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

_ _---..Vo
TO SCOPE

Fig. 17 - Switching Time Test Circuit

. . . - - - 0 +VOS
(ISOLATED
SUPPLY)

D~·5mA - IG 10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-248
 PD-9.378

INTERNATIONAL RECTIFIERII~~RI

HEXFET® TRANSISTORS IRFB4D

N-CHANNEL
IRFB41
POWER MOSFETs IRFB42
IRFB43
500 Volt, 0.85 Ohm HEXFET Features:
TO-220AB Plastic Package • Compact Plastic Package
The HEXFE~ technology is the key to International • Fast Switching
Rectifier's advanced line of power MOSFETtransis- • Low Drive Current
tors. The efficient geometry and unique processing • Ease of Paralleling
of the HEXFET design achieve very low on-state • No Second Breakdown
resistance combined with high transconductance • Excellent Temperature Stability
and great device ruggedness.
The HEXFET transistors also feature all of the well Product Summary
established advantages of MOSFETs such as volt-
Part Number VOS ROS(on) 10
age control, freedom from second breakdown, very
fast switching, ease of paralleling, and temperature IRF840 SOOV O.8Sn 8.0A
stability of the electrical parameters. IRF841 4S0V O.8Sn 8.0A
They are well suited for applications such as switch- IRF842 SOOV 1.10n 7.0A
ing power supplies, motor controls, inverters, chop- IRF843 4S0V 1.10n 7.0A
pers, audio amplifiers, and high energy pulse circuits.

~
CASE STYLE AND DIMENSIONS 10.6610.4201~
3.42 (0.135) 9.66 (0.3i10)
2.5410.1001 4.0810.1611 0 A

10.66 (0.420)
MAX.
T*'"±'
16.5110.6501
14.2310.5601
TERM 3 - SOURCE

t l~OF1NT 4.8210. ;;;r

3.5610·~i
2.7910.11014 -+-+-....1
6.3510.2501 2.2910.0901
MAX.

d
5.33101101

t ::~r=: ~. ,l-
4.8310.1901

.i3ECTION x-x
14.73 (0.580)
MAX.
1.1410D451
0,3110.0121
0
i i l
1.7710.0701 ~
2.9210.1151
'1--1
1.1410.0451
0.5110.0201
1.1510.0451
2:0410.080)

ACTUAL SIZE Case Style TO·220AB

Dimensions in Millimeters and (Inches)

0-249
IRF840, IRF841, IRF842, IRF843 Devices

Absolute Maximum Ratings

Parameter IRF840 IRF841 IRF842 IRF843 Units
VoS Drain - Source Voltage <D 500 450 500 450 V
VoGR Drain - Gate Voltage IRGS = 1 Mill <D 500 450 500 450 V
10@TC= 25°C Continuous Drain Current 8.0 8.0 7.0 7.0 A
10@TC - 100·C Continuous Drain Current 5.0 5.0 4.0 4.0 A
10M Pulsed Drain Current @ 32 32 28 28 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 125 ISee Fig. 141 W
Linear Derating Factor 1.0 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = 100~H
A
32 J 32 I 28 J 28
TJ Operating Junction and
-55to150 °C
T stg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm) Irom case lor lOs) ·C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVoSS Drain - Source Breakdown Voltage IRF840
IRF842
500 - - V VGS = OV
IRF841
IRF843
450 - - V 10 = 250~A

VGSlth) Gate Threshold Voltage ALL 2.0 - 4.0 V VoS = VGS' 10 = 25Ol'A
IGSS Gate-Source leakage Forward ALL - - 500 nA VGS = 20V
IGSS Gate-Source Leakage Reverse ALL - - -500 nA VGS - -20V
lOSS Zero Gate Voltage Drain Current
ALL
- - 250 I'A VoS = Max. Rating, VGS = OV
- - 1000 ~A VoS = Max. RatingxO.8, VGS = OV, TC = 125°C
On-State Drain Current @ IRF840
lolon)
IRF841
8.0 - - A
VoS >lolon) x RoSlon) max.' V GS = 10V
IRF842
IRF843
7.0 - - A

RoSlon) Static Drain-Source On-State IRF840

Resistance @ IRF841 - 0.1 1.0 II

IRF842
VGS = 10V, 10 = 4.0A
IRF843 - 0.2 4.0 II

gls Forward Transconductance ® ALL 4.0 6.5 - S UJ) V oS >101on) x RoSlon) max.' 10 = 4.0A
Ciss Input Capacitance ALL - 1225 1600 pF
VGS = OV, VoS = 25V, I = 1.0 MHz
Coss Output Capacitance ALL - 200 350 pF See Fig. 10
Cr• s Reverse Transfer Capacitance ALL - 85 150 pF
tdlon) Turn-On Delay Time ALL - 17 35 ns Voo = 200V, 10 = 4.0A, Zo - 4.711
tr Rise Time ALL - 5 15 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 42 90 ns (MOSFET switching times are essentially
independent of operating temperature.)
tl FaUTime ALL - 14 30 ns
Og Total Gate Charge
ALL - 42 60 nC V GS = 10V, 10 = lOA, VOS = 0.8 Max. Rating.
(GatewSource Plus Gate-Drainl See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Oas Gate-Source Charge ALL - 20 - nC

Ogd Gat... orain I"Miller") Charge ALL - 22 - nC

Lo Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm 10.25
in.) from pack'age to

-$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
10.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-ta-Case

RthCS Case-to-Sink Mounting surface flat, smooth, and greased.

RthJA Junctiun-ta-Ambient Free Air Operation

0-250
 IRF840, IRF841, IRF842, IRF843 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF840 Modified MOSFET symbol
- - 8.0 A
(Body Diode) IRF841 showing the integral
IRF842 reverse P-N junction rectifier.
- - 7.0 A
IRF843
ISM Pulse Source Current
(Body Diode) ®
IRF840
IRF841
IRF842
IRF843
-

-
-

-
32

28
A

A
JiEl
VSD Diode Forward Voltage ® IRF840
- - 2.0 V TC = 25°C, IS = 8.0A, VGS = 100A/~s
IRF841
IRF842
- - 1.9 V TC = 25°C, IS = 7.0A, VGS = 100A/~s
IRF843
trr Reverse Recovery Time ALL - 1100 - ns T J - 150°C, IF - 8.0A,dI F/dt - 100A/~s

ORR Reverse Recovered Charge ALL - 6.4 - ~C T J - 150°C, IF - 8.0A, dlF/dt - 1 00 A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time IS negligible. Turn-on speed is substantially controlled by LS + LO'

(j)T J = 25°C to 150°C. ® Pulse Test: Pulse width .. 300~s, Duty Cycle .. 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.

,,
See Transient Thermal Impedance Curve (Fig. 5).
20
10
LI{v sf~'
20

-S~~'PU~SETE~T l If
PulSETEJT - I I
15 16
VOS> 1010n) x RDS(on) max. I /
VGs=J IV
J 1/
I I
j 0
I !J V T~=250t- r--
TJ =-55 0C

Jr 5V
,r, ~TJ'= 1250C
II ~V
f 4V
~~
20 40 50 BO 100 10
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TD-SDURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

10

~~
100m~:mI OPERATION IN THIS

80~!PULSEITEST
AREA IS LIMITED
10V 50 1/ BY RDS(on)
t-~FB40, 1 r- ....

"
9V
BV ~
7V~ III"'"
~w I) I I 10 ms

l/ 5V
~
~
10 I=I=IRFB40, 1

r--- IRFB42,3
100m

~ VGS = 5V

~~
~

,
, ~,.

y 111J....J-L..-L-l-U~':-1R... I
" VOS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
0.1 L.....J-L..-l....J..1!-J11u.1.u
1.0 10 20 50
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS)
100
FB_40,:-'2....I...J.LU,.I.W
200 500

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-251
IRF840, IRF841, IRF842, IRF843 Devices

I-
15
u;
z
;L
I- I- 1.0
wz

-
>=> D = 0.5
t; ffi 0.5 NOTES:

~~
ffi ~
......
~fa
~!
",...
0'"
z,~ 0.05
'-'w
}~
0.2

0.1 =0.05

-0.02

% 0.02 """"l
-&.2

-0.1

:':;0.D1 ~
~

SINGLE PULSE (TRANSIENT

THERMAL IMPEDANCE)
- ~~ ~ii
""'"
HUL
~2~
1. DUTY FACTOR, D = :~
2. PER UNIT BASE = RthJC = 1.0 DEG. CIW.
3. TJM - TC = PDM ZthJC(t).
j 0.01 I I II III
10-5 10-3 2 10-2 10-1 1.0 10
il, SQUARE WAVE PULSE DURATIDN (SECDNDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to·Case Vs. Pulse Duration

16.0

1---8~ '" pulsE TElT

I I I I I
20
,
VDS> 10(on) x ROS(on) max. /
~ 12.8
w
'"
w
i'"
~
10

§ I-
~ 9.6 TJ = -55 0 C 15
z
'"t;=> ., I I
'"
'"
a TJ=150 0 C
c i-""'" TJ = 25 0 C Z
z
~ 6.4
/ ~
z

'"I-'".;,
r Tj = 125lc
0
w
'"
'"w
1.0

== TJ 25 0 C

L~
0.5

= 3.2
~
<i:

If .E'
0.2

0.1
B 12 16 20 o
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO-ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w ~
'-'
z
'"
t; 2.0 L
V ~ /
..,.'" ~ w
~
~s 1.5 /
/
", Zw
ON
w:::;
'-''''
V
./
", "''''
=>",
./
V
~~ 1.0
V >:-
z ,;/ VGS = 10V
I---
~ ~~ 10=4.5A -
o
C
Q
0.5

'"
~

0.75 o
-40 40 80 120 160 -40 40 80 120 160
TJ, JUNCTION TEMPERATURE (OC) TJ, JUNCTION TEMPERATURE (OC)

Fig,8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-252
 IRF840, IRF841, IRF842, IRF843 Devices
2000
Ciss = Cgs + Cgd. Cds SHORTED
r-- Crss = Cgd _ VGS = OV
.! J 20
C Cd f = 1 MHz
1600 ~ Coss = Cds+ C;.t9d
"'Cds+Cgd
~ 15
0
~OS = I~OV--......

! 1200 """""" ""'-

C,I"
?
w
'"
«
,vos = 2;oV--......
~ W
z
«
>-
\ ~
0
>
w
Vos = 400V " "

~
U
~
;3 800
\ '-' 10
II:
=>
0
~
d
\ I\. "I
0
>-
w ~~
\ ',,-
>-
«
'"u; 5 r 10 = lOA
-
400

f' ......." ......... ~ Coss

>'"
/ FOR TEST CIRCUIT
SEE FIGURE 18

""'- C,ss
V
10 15 20 25 30 35 40 45 50 w w ~ M
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) ago TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate·to-Source Voltage
10
3.5

RDS(O~) MEASUIREO WIT~ CURRE~T PULSE1DF

"'
e'"'" 3.0
I-~'O~s DURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.) J ..........

- r--...
w
'-'
z
«
t; 2.5
~ r---.... r--....
'"
VGS = lOV
Bi
'"z
0 2.0
~ ........... ~841
w 'VGS=20V
'-'

/ IRl~ ~
'"=>
0
"I 1.5

r" ~
0
>-
z
~ ./
/
~
1.0
~-
0

,
c
c

~
iii
0.5
\
o
10 15 20 25 30 35 25 50 75 100 125 150
10. DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature

140

~~
120

~
'\
~ 100
~
z
o
'\
~ 80
\..
gj '\
C
II: 60
'\.
iO '\
~
rP 40
~
'\
20 \..
'\
I\.
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-253
IRF840, IRF841, IRF842, IRF843 Devices

VARY tp TO OBTAIN

VGS='R
REQUI RED PEAK I L

OUT

IL+----o---_......,.",.--'
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

200V
AOJUST RL TO OBTAIN 4511
SPECIFIEO 10
VOS

i;ULSE ---1 O.U.T.

I GENERATOR O - - , - - - - - O - - -......... t-~

I ~6~RCE
IMPEDANCE
Sl I
L ___ J

Fig. 17 - Switching Time Test Circuit

r - - - < l +VOS
(ISOLATED
SUPPLY)

12V
BATTERY

o~·5mA - IG
~ __-V'I.''''"-U -VOS
10
CURRENT -=- CURRENT
SHUNT SHUNT

Fig. 18 - Gate Charge Test Circuit

0-254
 PD-9.348

INTERNATIONAL RECTIFIERII~)RI

HEXFET® TRANSISTORS IRF5522

MOSFET
IRF5523
COMPLEMENTARY
PAIRS

N-Channel P-Channel

100 Volt Complementary HEXFETs Features:

TO-220AB Plastic Package • Compact Plastic Package
The HEXFET® technology is the key to International • No Storage Time
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the
HEXFET design achieve very low on-state resistance • Ease of Paralleling
combined with high transconductance and great device • No Second Breakdown
ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and temperature stability of
the electrical parameters. Part Number VOS 10M Po

This complementary pair is particularly well suited for IRF5522 ±100V ±12A 40W
audio applications but can be also used in power supplies,
motor controls, inverters, choppers, and high energy pulse IRF5523 ±60V ±12A 40W
circuits.

* DESIGNATOR N '" N·CHANNEl DEVICE

DESIGNATOR P" P·CHANNEL DEVICE

~
3.42(0.135)
'0.66 (0.420)~
9.66(0:380]

T*+.'
254 (0.100) 4.08 (0 161) DI

TERM 3 - SOURCE

16.51 (0.650)
1423(0560) *N F5522

+-~.~'" 5.33 (0.210)

4.83 (0.190)

::::j d~' 11410.045)

0.31 (0.012)
D
i!ECTION x-x

Ti--I
1.14(0.045)
1.77 (0.070)
--..j 0.51 (0.020)
2.92 (0.115)
1.15 (0.045)
2.04 (0.0801

Case Style TO·220AB

Dimensions in Millimeters and (Inches)

0-255
Absolute Maximum Ratings
IRF5522 IRF5523
Parameter N-CHANNEL P-CHANNEL N-CHANNEL P-CHANNEL Units
VDS Drain - Source Voltage 100 -100 60 -60 V
VDGR Drain - Gate Voltage IRGS = 1 Mn) 100 -100 60 -60 V
ID @TC= 1000 C Continuous Drain Current 4.0 -3.5 4.0 -3.5 A
ID@TC=25 0 C Continuous Drain Current 7.0 -5.0 7.0 -5.0 A
IDM Pulsed Drain Current 12 -12 12 -12 A
VGS Gate - Source Voltage ±20 V
PD Max. Power Dissipation 40 W
Linear Derating Factor 0.32 W/K
TJ Operating and
-55 to 150 oC
T stg Storage Temperature Range

Electrical Characteristics @ TC = 25 DC{Uniess Otherwise Specified)

Parameter Device Type Min. Typ. Max. Units Test Conditions
BVDSS Orain - Source Breakdown
IRF5522
N-CHANNEL 100 - - VGS -OV
Voltage P-CHANNEL -100 - - V 10 = 250 jJ.A (N-CHANNEL)
IRF5523
N-CHANNEL -60 - -
P-CHANNEL -60 - - 10 = -250 jJ.A (P-CHANNEL)
VGSlth) Gate Threshold Voltage
ALL
N-CHANNEL 2.0 - 4.0
V VOS = VGS, 10 = ±250 jJ.A
P-CHANNEL -2.0 - -4.0
IGSS Gate - Source Leakage
ALL
N-CHANNEL - - 500
nA
VGS = 20V
P-CHANNEL - - -500 VGS --20V
lOSS Zero Gate Voltage Orain - - 250 VOS = Max. Rating, VGS = OV
Current N-CHANNEL
VDS = Max. Rating x 0.8,
- - 1000
VGS = OV, TJ = 1250 C
ALL jJ.A
- - -250 VOS - Max. Rating, VGS - OV
P·CHANNEL
VDS = Max. Rating x 0.8,
- - -1000
VGS = OV, TJ = 1250 C
RDS(on) Static Orain-Source On-State N-CHANNEL - 0.3 0.4 VGS = 10V, 10 = 3A
Resistance ALL n
P-CHANNEL - 0.6 0.8 VGS - -10V, ID - -2A
gfs Forward Transconductance
ALL
N-CHANNEL 1.5 2.5 - S(U)
VDS = 25V, 10 = 3A
P-CHANNEL 0.9 I.B - VOS = -25V, 10 = -2A
Ciss Input Capacitance
ALL
N-CHANNEL - 450 600 VGS=OV,f-l MHz
P-CHANNEL - 300 450
pF
VOS = 25V (N-CHANNEL)
Coss Output Capacitance ALL ALL - 200 400 VOS = -25V (P-CHANNEL)
Crss Reverse Transfer Capacitance ALL ALL - 50 100 See Figs. 11 and 12

Thermal Resistance
RthJC Junction-to-Case ALL ALL - - 3.12 KIW
RthCS Case-to-Sink ALL ALL 1.0 K/W Mounting surface flat, smooth, and
greased.
RthJA Junction-to-Ambient ALL ALL - - 80 K/W Free Air Operation

20
/1OJ
II .
J/
laops P~lSE T~ST

9Y-
--
-10

-a
,
-10V
i/ I I
80 ",I PULSE TEST
-9~-

I
-

~
16

I ~
-a~- -
'"
W
Q.
~
ay- ~ ,.ffi
Q.
J I
'>-"
~ 12 ~ -6
z>-
~
'"
I
r--
w
'" 'I
VGs=-7l=
==
'"
i3
z
VGS"7V-
I
'"
i3
z
;;:
-4 I
~
0

E
6l-
"I'
r--
a:
c
E
+-J r--
-2
5Y- r-- -5V= ~
I
40- r-- -4V- ~
10 20 30 40 50 -10 -20 -30 -40 -50
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) VDS. DRAIN·TO·SDURCE VOLTAGE (VOLTS)
Fig. 1 - Typical Output Characteristics (N-Channel Device) Fig. 2 - Typical Output Characteristics (P-Channel Device)
0-256
 IRF5522, IRF5523 Devices
-10
20.

/1 J. . PU LlE TEsJ . 1/ 1 'j

r-J", PUJSE TEJ f---
I I
J / /If
I
Vos = 25V
I

:/1 j -8
Vos = -25V
TJ = 125°C,
if/
I ~J
16
TJ =11250CI~
AI V 13
ffi TJ = 25°C
Ty2501~
J7 rY ~
::> -6
I
TJ = -55°C
~ "J;
TJ - -55°1 "'Y rlJ I-
~ 11,(J
'"'"
II. V 13
z -4 liD
/1' ~
co //
,A'
E
/I -2 J
~'"
~~ ....",.;!
10 -2 -4 -6 -8 -10
VGS. GATE-TO-SOURCE VOLTAGE (VOLTS) VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)
Fig. 3 - Typical Transfer Characteristics IN-Channel Device) Fig. 4 - Typical Transfer Characteristics IP-Channel Device)

I J

-
TJ=-55 0C _ r=

~ -T]=250~- f - -
/'
./ ~ r-
/ /"
/' TJ ~ 125 06
t-- TJ --55°C
// ",. V

IJ
II ./ /'"
V-
V
~
~ -
--- t--

t--
Tr 25 OC-

TJ = 125°C
r---

I Vos = 25V //" VDS = J5V

BOT PULsi TEST
J 1" PU \SETESi
If
12 16 20. -2 -4 -6 -8 -10.
10. DRAIN CURRENT (AMPERES) ID. DRAIN CURRENT (AMPERES)
Fig. 5 - Typical Transconductance Vs. Drain Current Fig. 6 - Typical Transconductance Vs. Drain Current
IN-Channel Device) IP-Channel Device)
20. -20.

10.
r- ~ - -- -. - ~
10,us
-10
,- 1-- .... 10p:s

t ---- f--
....
u;
~
,.
5 -, , " 100.:, i,. -5 I,
~

, -, lOD~'
::> I'\.. "- ::> I"" I'

'-', " '\r-. 1',

I- f-
z
~
~ 2 ~ ~2
'"
13
z
'\. 1 m,
13
z
'" r'\ -, 1 m,

~
co
ci
1

0._5
TJ -15DoC MAX_
SINGLE PULSE
" lOms

1DDT'- ~-- - ' -

~
co
ci
-1

-D.S
TJ 15DoC MAX.
SINGLE PULSE
10 ms

lOOms
DC
DC

IRr5r
I RF~522 IRrSr
IRFS;S22

0..2 -02
5_0. 10. 20. 50. 10.0. 20.0. -S 0. -10 -20. -so. -100. -20.0.
VOS. ORAIN-TO-SOU RCE VOLTAGE (VOLTS) VDS. DRAIN-TD-SDURCE VDLTAGE (VDLTS)

Fig. 7 - Maximum Safe Operating Area Fig. 8 - Maximum Safe Operating Area
IN-Channel Device) IP-Channel Device)
D-257
IRF5522, IRF5523 Devices

2.2 2.2
w w
u u
z
~ 1.8
V ~
Z

.I
1.8
iii
0:
z
0
Ww
0
/
./ '" iii0:
Z
Co
ww V
/
~~ 1.4 ~!::::! 1.4
0"
'?'"
V g~ ./
V
~~
00:
1- 0
z-
:
. z
1.0
V
/ '" ~- 1.0
./ V
C

'"
~
c
o

0.6 , .,,- v-
VGS = 10V
10 =3A
C

~
0:
c
o
0.6
,V
.."
" VGS = -10V
10 =-4A

0.2 0.2
-40 40 80 120 160 -40 40 80 120 160
TJ.JUNCTION TEMPERATURE (DC) TJ.JUNCTION TEMPERATURE (DC)

Fig. 9 - Normalized On·Resistance Vs. Fig. 10 - Normalized On·Resistance Vs.

Temperature (N·Channel Devicel Temperature (P·Channel Devicel

500
1000
J

~r\-
Ciss = Cgs + Cud. Cd. SHORTEO.l
J
.I.vGS = 0 c'" = Cgd _ VGS=O

800
I 1,=1 MH,'
Cin = Cgs+ Cgd. Cd,SHORTEO
J - 400
CgsCgd
Coss = Cd.+ Cgs+ CUd
l=lMH'

Crss = Cgd ~ "Cd,+ Cgd

Cgs Cud -

~ \
c... = Cd, + Cg, + CUd ...
~ r-- c}ss
600 ., Cd, + Cgd - w 300

-
w
u
...
z \ ....... I
u
z
« f'....

-
I- CISS I-
;:;
\ '""'- ;:;
;;: \ ......... ~COSS
,I
~u- 400 ;3 200
r--....
!\.. U
\
200
\ r---.... ""- Coss
100
~
............
\ i
crss r- r-.-C,ss

10 20 30 40 50 -10 -20 -30 -40 -50

VOS' ORAIN·TO·SOURCE VOLTAGE (VOLTS)
VOS. ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 11 - Typical Capacitance Vs. Drain·to-Source Voltage Fig. 12 - Typical Capacitance Vs. Drain·to·Source Voltage
(N·Channel Devicel (P·Channel Devicel

0-258
 PD-9.347

HEXFET® TRANSISTORS IRF5532

MOSFET
IRF5533
COMPLEMENTARY
PAIRS

N-Channel P-Channel

100 Volt Complementary HEXFETs Features:

TO-220AB Plastic Package • Compact Plastic Package
The HEXFETG!) technology is the key to International • No Storage Time
Rectifier's advanced line of power MOSFET transistors. • Low Drive Current
The efficient geometry and unique processing of the
HEXFET design achieve very low on-state resistance • Ease of Paralleling
combined with high transconductance and great device • No Second Breakdown
ruggedness. • Excellent Temperature Stability
The HEXFET transistors also feature all of the well
established advantages of MOSFETs such as voltage
control, freedom from second breakdown, very fast
Product Summary
switching, ease of paralleling, and temperature stability of
the electrical parameters. Part Number VOS 10M Po

This complementary pair is particularly well suited for IRF5532 ±100V ±25A 75W
audio applications but can be also used in power supplies,
motor controls, inverters, choppers, and high energy pulse IRF5533 ±60V ±25A 75W
circuits.

* DESIGNATOR N '" N·CHANNEL DEVICE

DESIGNATOR P" P CHANNEL DEVICE

~
1O'6610'(20)~
3.42 10.135) 9.66 10.380)

t'+'·
2.5410.100) 4.0810.1611

TERM 3 - SOURCE

+- ~'F'"
16.5110.650)
1423(0560) *N F5532

5.3310.210)
4.83 10.190)

:tfj~' 1.1410.0(5)
0.31(0.012)
.i!ECTION

T~
0 x-x

1.1410.045)
1.7710.070)
--j 0.5110.020)
2.9210.115)
1.1510.045)
2.0410.080)

Case Style TO-220AB

Dimensions in Millimeters and (Inches)

0-259
Absolute Maximum Ratings
IRF5532 IRF5533
Parameter N-CHANNEL P-CHANNEL N-CHANNEL P-CHANNEL Units
VDS Drain - Source Voltage 100 -100 60 -60 V
VDGR Drain - Gate Voltage (RGS = 1 MO.) 100 -100 60 -60 V
ID@TC- 1000 C Continuous Drain Current 8.0 -6.5 8.0 -6.5 A
ID@TC-25\)C Continuous Drain Current 12 -10 12 -10 A
10M Pulsed Drain Current 25 -25 25 -25 A
VGS Gate - Source Voltage ±20 V
Po Max. Power Dissipation 75 W
linear Derating Factor 0.6 W/K
TJ Operating and
T stg -55 to 150 °C
Storage Temperature Range

Electrical Characteristics @ TC = 25°C(Unless Otherwise Specified)

ALL

Gate - Source Leakage

ALL

lOSS Zero Gate Voltage Drain

Current N-CHANNEL

ALL
P·CHANNEL

RDS(on)
ALL

Forward Transconductance
ALL

Ciss Input Capacitance VGS = OV, f = 1.0 MHz

VDS = 25V (N-CHANNEL)
pF
VDS = -25V (P-CHANNEL)
See Figs. 11 and 12

Thermal Resistance
RthJC Junction-to-Case ALL ALL - - 1.67 K/W
RthCS Case-to-5ink ALL ALL - 1.0 - K/W Mounting surface flat. smooth. and
greased.
RthJA Junction-to-Ambient ALL ALL - - 80 K/W Free Air Operation

20
IOV~V
-20
-IV Js PU LS~ TEST
-y- -
sL, PU iSE TEJT _ -
f
80

I
7V_
- I
'"w
16
1/ ~ 1-
-8 ~

'"
w
'"
'"5 12
I
I-
r--
~
::i
~
I'
VGS~6V=
= VGS-)V-

I
z
~ -6~- -
'"53
I' y- ~
-4 I
-5~- -
4~- ~ -4~- -
10 20 30 40 50 -10 -20 -30 -40 -50
Vas. ORA1N·TO·SOURCE VOLTAGE (VO LTS) VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics IN-Channel Device) Fig. 2 - Typical Output Characteristics IP-Channel Device)
0-260
 IRF5532 and IRF5533 Devices

,
-20
20

I-- ~O"' P~LSE

TElT
// -aol I
pULsl TEST
Vos = -25V
I
1/fjI 1//
VOS = 15V I -16 TJ = 125 0C
J

'"w
16

J 13 I I0 '--- ~ /J
TJ = 25 C,---
'I
..
~
:; /I
~
".
:>. -12
ITJ=-55I0C........ ~ lh If
~'I
~
....
12 ....z
~ rJ ~

G
ex:
ex:

z 8
lh '"
::>
'-'
z
:;;:
-8 /h
:;;:
ex:
c '1/ ex:
c
.9
II
.9 TJ = +125 0C Ii I -4 I
~ VII ~'
TJ = 25 0C
~ TJ = ~550C

I ~V ~ ~
4 10 -2 -4 -6 -8 -10
VGS. GATE·TO·SOURCE VOLTAGE (VOLTS) VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Transfer Characteristics IN-Channel Device)

10

V
TJ=-~

~J=i50:"" ,...--
--
Fig. 4 - Typical Transfer Characteristics IP-Channel Device)

V
,..
I---
- TJ =-55 0C

~ = 25O~
:/ . /~11250C
'/ . /V
/
-
~~ TJ = 1250C

J} ./V
'/V V~s = 15V vos = 25V

T
I
ST - -
I BOt' PU LiE TES, 80 .. I"LSE

10 15 20 25 -4 -8 -12 -16 -20

10. DRAIN CURRENT (AMPERES) 10. DRAIN CURRENT (AMPERES)
Fig. 5 - Typical Transconductance Vs. Drain Current Fig. 6 - Typical Transconductance Vs. Drain Current
IN-Channel Device) IP-Channel Device)
50 -50

20
- , .-
-,
- ,,- lO"t -20 , ~
-, r--
"
~I- 10"1
13 , ~ ' ... "
~:;
:>.
10
" " 1001. ;l; -10
~
100J.

....z ....
~ , ," ,
I' •
~ 5 " I"- " a:
a:
-5
"
::>
'-'
z
:;;: "- " 1 ms
G
z
~, I-'!I. 1 ms
~, ~ "'~ r.
ex:
c
.9
TJ = 150.C MAX.
SINGLE PULSE
" "-
I
10ms
c
Eo
-2 TJ = 1500C MAX.
SINGLE PULSE " i'
10ms
I
100m. -1 lOOms
OC DC
IRF5533 IRF5532 IRF5533 IRF5532
0.5 -0.5
5.0 10 20 50 100 200 -5.0 -10 -20 -50 -100 -200
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) VOS. DRAIN·TO·SOU RCE VOLTAGE (VOLTS)
Fig. 7 - Maximum Safe Operating Area Fig. 8 - Maximum'Safe Operating Area
IN-Channel Device) IP-Channel Device)
D-261
IRF5532 and IRF5533 Devices

2.2 2.2
w
u
z
;'
~ 1.8 .I

/ ~ /
z
./
V °5
ww
~~ 1.4
Y
/ V
/ ~~
~~ ..,-V
/
"
~- 1.0
V VGS = 10V c ". V VGS=-10V
c
o

~ 0.6
V
10 =9A

~
c
o
0.6
,..." 10 =-4A

'"

0.1 0.2
-40 o 40 80 120 160 -40 40 80 120 160
TJ.JUNCTION TEMPERATURE (OC) TJ. JUNCTION TEMPERATURE (OC)

Fig. 9 - Normalized On-Resistance Vs. Fig. 10 - Normalized On-Resistance Vs.

Temperature (N-Channel Device) Temperature (P·Channel Device)

1000
2000

I tGS = ~ \ I
1
tGs=d
t= 1 MHz .!
1600
I 1= IM r'.l J
Ciss = Cgs+Cgd.CdsSHORTEO-
800
\ Ciss = Cgs+Cgd.CdsSHORTEO
Cess = Cgd I--
crss = Cgd Cgs Cgd
Co.. = Cds + Cus + Cgd I--
~\
Cgs Cgd - "-
Coss = Cds + Cgs + Cgd .s OIoICds+Cgd

-
~
600 I--
~ - w

~ "--
1200 u
"'Cds + Cgd z C!IS
z
«
.... 1 ...G
«

I
"-\ - '"
G
~ 800 J ~
u 400
u·
c,ss u'
\ ,I
........... ........COIS

r- r-
400 \ i'..
- - J
Coss 200
~
......
......... """'- C~
~

" 10 20
"I
Crss

30 40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 11 - Typical Capacitance Vs. Drain-to-Source Voltage

50 -10 -20 -30
I
-40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS)

Fig. 12 - Typical Capacitance Vs. Drain-to-Source Voltage

-50

(N-Channel Device) (P-Channel Device)

0-262
 PD-9.318

INTERNATIONAL RECTIFIER II'~R I

HEXFET® TRANSISTORS IRF5I~ 3D
IRF5I~ 3~

P-Channel IRF5I~ 32
IRF5I~ 33

-100 Volt, 0.3 Ohm HEXFET Features:

The HEXFET® technology is the key to International Rectifier's • P-Channel Versatility
advanced line of power MOSFET transistors. The efficient geometry
and unique processing of the HEXFET design achieve very low
• Fast Switching
on-state resistance combined with high transconductance and • Low Drive Current
extreme device ruggedness. • Ease of Paralleling
The P-Channel HEXFETs are designed for applications which • No Second Breakdown
require the convenience of reverse polarity operation. They retain all • Excellent Temperature Stability
of the features of the more common N-Channel HEXFETs such as
voltage control, freedom from second breakdown, very fast switch-
ing, ease of paralleling, and excellent temperature stability. The Product Summary
P-ChannellRF9130 device is an approximate electrical complement
to the N-ChannellRF120 HEXFET. Part Number VOS ROS(on) 10
I RF9l30 -100V O.30n -12A
P-Channel HEXFETs are intended for use in power stages where
complementary symmetry with N-Channel devices offers circuit IRF9l3l -60V O.30n -12A
simplification. They are also very useful in drive stages because of
the circuit versatility offered by the reverse polarity connection. IRF9l32 -100V O.40n -lOA
Applications include motor control, audio amplifiers, switched IRF9l33 -60V O.40n -lOA
mode converters, control circuits and pulse amplifiers.

22.22(0.875)

' 'i'1==tl:,,,,
CASE STYLE AND DIMENSIONS 342 MAX. OIA 11.43 (0.4om

22.22 (0.875)
MAX.OIA. T~ PLANE

1.09(0.043 DIA
097003 III I 1016(040)MIN
.. .
TWO PLACES TWO PLACES

;.~8 m·;SlJ OIA .

. 4 .51
TWO PLACES

DRAIN
(CASE)

J SOURCE

" ' 1.09 (0.043)

MAX.OIA.
1+-_ _ 39.95 (1.573) :wm::;~!t
MAX. t MEASURED AT SEATING PLANE

ACTUAL SIZE Conforms to JEDEC Outline TO-204AA (TO-3)

Dimensions in Millimeters and (lnchesl

0-263
IRF9130, IRF9131, IRF9132, IRF9133 Devices

Absolute Maximum Ratings

Parameter IRF9130 IRF9131 IRF9132 IRF9133 Units
VOS Drain - Source Voltage <D -100 -60 -100 -60 V
VOGR Orain - Gate Voltage (RGS = 1 MD) (j) -100 -60 -100 -60 V
10@TC = 25°C Continuous Drain Current -12 -12 -10 -10 A
10@TC = 100°C Continuous Drain Current -7.5 -7.5 -6.5 -6.5 A
10M Pulsed Drain Current ® -48 -48 -40 -40 A
VGS Gate - Source Voltage ±20 V
PO@TC = 25°C Max. Power Dissipation 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L = 100~H
A
-48 I -48 I -40 I -40
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 In. (1.6mm) from case for 10s) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF9130
IRF9132
-100 - - V VGS = OV
IRF9131 10 = -250~A
-60 - - V
IRF9133
V GS(th) Gate Threshold Voltage ALL -2.0 - -4.0 V VOS - V GS ' 10 - 250~A

IGSS Gate-Source Leakage Forward ALL - - -100 nA VGS = -20V

IGSS Gate-Source Leakage Reverse ALL - - 100 nA VGS = 20V
lOSS Zero Gate Voltage Drain Current - - -250 ~A VOS - Max. Rating, VGS - OV
ALL
- - -1000 ~A VOS = Max. RatingxO.8, VGS = OV, TC = 125°C
10(on) On-State Drain Current @ IRF9130
- -
-12 A
IRF9131
V OS } 10(on) x ROS(on) max.' V GS = -10V
IRF9132
-10 - - A
IRF9133
ROS(on) Static Drain-Source On-State IRF9130
- 0.25 0.30 11
ReSIstance @ IRF9131
IRF9132
VGS = -10V, 10 = -6.5A
- 0.30 0.40 11
IRF9133
9fs Forward Transconductance ® ALL 2.0 3.7 - S(Ui VOS } 10(on) x ROS(on) max.' 10 6.5A

Ciss Input Capacitance ALL - 500 700 pF

VGS = OV, VOS = -25V, f = 1.0 MHz
Coss Output Capacitance ALL - 300 450 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 100 200 pF
td(on) Turn~On Delay Time ALL - 30 60 ns VOO ~ 0.5 BV OSS ' 10 = -6.5A, Zo = 5011
tr Rise Time ALL - 70 140 ns See Fig. 17
tdloff) Turn~Off Delay Time ALL - 70 140 ns (MOSFET switching times are essentially
- independent of operating temperature.)
tf Fall Time ALL 70 140 ns
Qg Total Gate Charge
ALL - 25 45 nC
V GS = -15V, 10 = -15A, VOS ~ 0.8 Max. Rating.
(Gate~Source Plus Gate~Draln) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate~Source Charge ALL - 13 - nC

Qgd Gate~Drain ("Miller") Charge ALL - 12 - nC

LO Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that is closer to internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 in.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction~to~Case

RthCS Case-to-Slnk Mounting surface flat, smooth, and greased.

RthJA Junction~to~Ambient Free Air Operation

0-264
 IRF9130, IRF9131, IRF9132, IRF9133 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9130 Modified MOSFET symbol
(Body Oiode) IRF9131 - - ·12 A
showing the integral
reverse P·N junction rectifier.
IRF9132

~
IRF9133
- - ·10 A

ISM Pulse Source Current IRF9130

- - ·48 A
(Body Diode) @ IRF9131
IRF9132
IRF9133
- - -40 A

VSD Diode Forward Voltage ® IRF9130

- - ·6_3 V TC ~ 25°C, IS ~ -12A, V GS ~ OV
IRF9131
IRF9132
IRF9133
- - ·6.0 V TC ~ 25°C, IS ~ -lOA, V GS ~ OV

trr Reverse Recovery Time ALL - 300 - ns T J - 150°C,I F - 12A, dlF/dt - 100 AIMS
ORR Reverse Recovered Charge ALL - 1.8 - MC T J - 150oC,I F - 12A, dlF/dt - 100 AIMS
ton Forward Turn-on Time ALL Intrinsic turn-on time IS negligible. Turn-on speed is substantially controlled by LS + LO'

CDTJ ~ 25°Cto 150°C. ® Pulse Test: Pulse width ::s;; 300,us, Duty Cycle ::s;; 2 %. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

·20
.I
V 80 ~s PUlsJ TEST -r-- -20

)--80lpULSLEST II /

, //
VOS> 1010n) x RDS(on) max.
I
·16
.8r--
I -16 Tj,'25OC ,
ITj'25I C , ~ /, 'j
~
/'
I
i" I I ~
0

1h
">- -12
~ ~ -12 Tj"-55 C, 0

z
w
~
VGS')V- -
>-
~ N '/
~

"uz ·8 I
~

"z
u
-8
//;
~ .L-- ~
0

Eo
~
Eo
·4 I -4
I
.5IV_

.L--
-
~ W
,J
"
·10 ·20 ·30 ·40 ·50 ·2 -4 ·6 -8 ·'0
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-100
OPERATION IN THIS
-10 f-IRF9130, I AREA)S LIMITED BY RDS(on)

r- 80 J,ULSJTEST lYv ~ ./
V" -50

//-8~ . V
f-IT'Y'i
-20 I\. tOjlS
-8 I"-
~ IRF9130, I
h
-
'i/7VI w 100 jls
~ -10
i"
5 -6 'I/~ V VGS,t- ~ f-- '"
5 -5
F==; ~;RF9132,
, I ms
~
~ IIV /? cc
~

G I
VIi '/
~
-2
"uz -4
z 10ms
I I
~
~ 1-~ o
-1.0

r- TC - 25°C
100 ms

Eo
·2 1// r- ~
_-5V '"
- -0.5
~TJ 150°C MAX.
DC

~V
)-- R,hJC" 1.67 K/W
I
r
-02 )-- SINGLE PULSE

V..
-1 -2
-L
-3 -5
-0.1
-1.0 -2
IIIIIII
-5 -10 -20
9 '3
1 1',
-50
) Rf 9 13O

-tOO -200
',2
-500
-4
VOS. ORAIN·TO-SOURCE VOLTAGE IVOLTS)
VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-265
IRF9130, IRF9131, IRF9132, IRF9133 Devices

0-0.5
NOTES:

r-h.2

r-O.l lrLJL
0.05
r-0.02- ~2~
~~1=- ~ SINGLE PULSE (TRANSIENT 1. OUTY FACTOR, 0 - 'I
'2
mRMA~ I~PEOfNfE\ I I 2. PER UNIT BASE = R,hJC = 1.67 OEG. CIW.
3. TJM - TC = POM Z'hJC(')'
1111 I I II
10-3 10-2 10-1 1.0 10
'I, SQUARE WAVE PULSE OU RATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to-Case Vs. Pulse Duration

TJ="7

, /~J-i50;""
-
_i'""'"
-100

-50
/'J

V . /~25~
'/ / 'V - r-
~
,.~
:'S
...
~
-20

-10

-5
/.
'/
V

'L '"'"
'-'
z f-- TJ = 1500 C
I
I

~
c:J
-2
w
~
-1 III
~
i;;
vos> 10(on) x ROS(on) max. -0.5
'"
80 "'IU lSE lEST - r-- E'" TJ 25 0 C

-0.2 I
I
-0.1 II
-4 -8 -12 -16 -20 o -2 -4 -6 -8 -10
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w
to

..
w
~ '-'
z
1.8
o
>
z
1.15

,,-
.,."" In
~
/
;:
o
o
'"~s 1.05 / z
00'
ww
1.4
,/
V
"'~ / '-'N
"'- ./
"'::; ". "'0 ".....
~i / "I'"
0'" V
~~ 0.95 Y ... 0
. z
z - 1.0
./
..,z V
o

;;:
'"
o
" ~
c:J

§
Ui ..".,
..".,
./

VGS = -10V
~ 0.85 ~
0.6 -
l-4A[ -
iii;

0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE (OC) TJ, JUNCTION TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-266
 IRF9130, IRF9131, IRF9132, IRF9133 Devices

,
1000

1\ 1I tGs=J
I)
800 \ \= 1 M~zl
Ciss = Cgs + Cgd. Cds SHORTED -
~ 10 = -15A
1

FOR TEST CIRCUIT- f---

\ Crss = Cgd
Cgs Cgd -
SEE FIGURE 18

~
Coss = Cds+ Cgs+Cgd
~ 1\\
- ,
BOO ~Cds+ Cgd -
..
w

~ r- ,~
u
z Ciss
I--
;:;
"it
j 400 \ "- 1 ........
"""- ~
u'
\ I'-. ,I
...... Coss

200 ~ 1-r-- r--

Vas -80V.IRF9130.9132/
,
Vos = -50V
'./ ~
.......
r-..... """- ,Irss
__ C Va~=-2tiV/

I -20
-10 -20 -30 -40 -50 o 16 24 32 40
Vas. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE InC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
1.0 ·12.0

0;- VG1S =-lOl

i""'-- ~
;:"
S
~
z
~
~
o. 8

0.6
-9.B
r-....
"
.........
r--......
IRF9132.91~
......~
......... ~9130.9131

z
o
w
u
f'''......

"
'"
=>
o
'? 0.4
o
/ ~
--
>:-
z
..... --;;;;;-
~
o
0.2
- VGS =-20V-

-2.4 ~
ROS(on) MEASURED WITH CURRENT PULSE1OF
2.0JIs DURATION. INITIAL TJ = 25 0 C. (HEATING
\
EFFECT OF 2.0JIs PULSE IS MINIMAL.)
o
·10 ·20 ·30 ·40 ·50 25 50 75 100 125 150
' 0 , DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current V,. Case Temperature
80
I--
70 I'\.
'\
60
r\.
..
0;-
I--
I--

~
z
50 "r-...
0
>=
"it 40
'\
iii
c
'"~ 30
'\
~
,p
20 '\.
10

20 40 60 80 100
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

'" "
120
'\

140

0-267
IRF9130, IRF9131, IRF9132, IRF9133 Devices
r---
, I
VARY tp TO OBTAIN " , II

I IL~' "
REQUIRED PEAK IL

VGS· H ILvD:U_T-_~.~--cY>- _ _ _""",--,

~tp----j
I
"

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL
TD DBTAIN
SPECIFIED ID RL

PULSE
GENERATOR D.U.T.
r------,
I
50f! I 0 - - - - TO SCOPE
I O.Off!
I I 50f! HIGH FREaUENCY
L_ _ __ .J SHUNT

- Switching Time Test Circuit

ID
CURRENT
SHUNT
--'\'IV"v-~_'V'''''-O +VDS

O-,---rr.
L........I.e mA
DUT

-VDS
'------t_--..... _---~~--_o (ISOLATED
SUPPL VI

Fig. 18 - Gate Charge Test Circuit

D·268
 PD-9.349

INTERNATIONAL. RECTIFIER II~~R I

HEXFET@TRANSISTORS IRF9230
P-CHANNEL IRF923~
200 VOLT IRF9232
POWER MOSFETs
IRF9233
-200 Volt, 0.8 Ohm HEXFET Features:
The HEXFET technology is the key to International Rectifier's • P-Channel Versatility
advanced line of power MOSFET transistors. The efficient geom-
etry and unique processing of the HEXFET design achieve very low • Fast Switching
on-state resistance combined with high transconductance and • Low Drive Current
extreme device ruggedness.
• Ease of Paralleling
The P-Channel HEXFETs are designed for applications which re- • No Second Breakdown
quire the convenience of reverse polarity operation, They retain all
of the features of the more common N-Channel HEXFETs such as
• Excellent Temperature Stability
voltage control, freedom from second breakdown, very fast switch-
ing, ease of paralleling, and excellent temperature stability. The Product Summary
P-Channel IRF9230 device is an approximate electrical comple-
ment to the N-Channel IRF220 HEXFET. Part Number VOS ROS(on) 10

P-Channel HEXFETs are intended for use in power stages where IRF9230 -200V O.8n -6.5A
complementary symmetry with N-Channel devices offers circuit IRF9231 -150V O.8n -6.5A
simplification. They are also very useful in drive stages because of
the circuit versatility offered by the reverse polarity connection. IRF9232 -200V 1.2n -5.5A
Applications include motor control, audio amplifiers, switched
mode converters, control circuits and pulse amplifiers. IRF9233 -150V 1.2n -5.5A

22.22 (O.875)
CASE STYLE AND DIMENSIONS

'Hr:,'",
342 MAX, DIA. 11.43 (0.450)

22.23 (0.875)
'"''JTTT
..
r::l
'."'0...
1.09 (0.043 OIA
097(00
TWO PLACES

4.08 (0,161 DIA

' III I ...
TWO PLACES
PLANE

1016(0401 MIN

.840.151 .
o PLACES

'~
DRAIN
(CASEI

J"1.09 (0.043)
MAX.DIA.
39.96 (1.573)
MAX. 11.17 (0.440)t
fII:ST"[iilll!j
t MEASURED AT SEATING PLANE

Conforms to JEDEC Outline TO·204AA (TO-3)

ACTUAL SIZE All Dimensions in Millimeters and (Inches)

D-269
IRF9230, IRF9231, IRF9232, IRF9233 Devices

Absolute Maximum Ratings

Parameter IRF9230 IRF9231 IRF9232 IRF9233 Units

VDS Dram - Source Voltage CD -200 -150 -200 -150 V

VDGR Drain - Gate Voltage (RGS ~ 1 M{J) CD -200 -150 -200 -150 V
ID@ TC ~ 25°C Continuous Drain Current -6.5 -6.5 -5.5 -5.5 A
ID@ TC ~ 100°C Continuous Drain Current -4.0 -4.0 -3.5 -3_5 A
IDM Pulsed Drain Current @ -26 -26 -22 -22 A
VGS Gate - Source Voltage ±20 V
PD@TC~25°C Max. Power Dissipation 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L ~ 100MH
A
-26 I -26 I -22 I -22
TJ Operating Junction and
-55to150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 In. (1.6mm) from case for 10s) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage IRF9230
-200 - - V VGS ~ OV
IRF9232
IRF9231 ~
-150 - - V ID -250MA
IRF9233
VGS th Gate Threshold Voltage ALL -2.0 - -4.0 V V DS - V GS ' ID - 250MA
IGSS Gate-Source Leakage Forward ALL - - -100 nA V GS - -20V
IGSS Gate-Source Leakage Reverse ALL - - 100 nA V GS - 20V

IDSS Zero Gate Voltage Drain Current - - -250 MA VDS ~ Max. Rating, VGS ~ OV
ALL
- - -1000 MA VDS ~ Max. RatingxO.S, VGS ~ OV, TC ~ 125°C
ID(on) On-State Drain Current @ IRF9230
-6.5 - - A
IRF9231
VDS >ID(on) x RDS(on) max.' V GS ~ -10V
IRF9232
-5.5 - - A
IRF9233
ROS(on) Static Drain-Source On-State IRF9230
- 0.5 O.S 0
Resistance ® IRF9231
VGS ~ -10V, ID ~ -3.5A
IRF9232
- O.S 1.2 0
IRF9233
9fs Forward Transconductance ® ALL 2.2 3.5 - S(m VDS >ID(on) x RDS(on) max.' 'D - 3.5A
Ciss Input Capacitance ALL - 550 650 pF
VGS ~ OV, VDS ~ -25V, f ~ 1.0 MHz
Coss Output Capacitance ALL - 170 300 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 50 90 pF
td(on Turn~On Delay Time ALL - 30 50 ns V DD ~ 0.5 BV DSS ' ID ~ -3.5A, Zo ~ 500
tr Rise Time ALL - 50 100 ns See Fig. 17
td(offl Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
Fall Time - 40 Independent of operating temperature.)
tf ALL SO ns
Qg Total Gate Charge V GS ~ -15V, 'D ~ -S.OA, V DS ~ O.S Max. Rating.
ALL - 31 45 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
Independent of operating temperature.)
Q gs Gate-Source Charge ALL - 1S - nC

Qgd Gate-Drain ("Miller") Charge ALL - 13 - nC

LD Internal Drain Inductance ALL - 5.0 - nH Measured between Modified MOSFET

the contact screw on symbol showing the
header that IS closer to Internal device
source and gate pins inductances.
and center of die.

LS Internal Source Inductance ALL - 12.5 - nH Measured from the

source pin, 6 mm
(0.25 In.) from header
and source bonding
pad.
$
Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junctlon-to-Ambient Free Air Operation

0-270
 IRF9230, IRF9231, IRF9232, IRF9233 Devices

Source-Drain Diode Ratings and Characteristics

IS ContinUOUS Source Current IRF9230 Modified MOSFET symbol
- - -6.5 A
(Body Diode) IRF9231 showing the Integral
IRF9232 reverse P-N Junction rectifier.
- - -5.5 A

~
IRF9233
ISM Pulse Source Current IRF9230 - - -26 A
(Body Diode) @ IRF9231
IRF9232
-- - -22 A
IRF9233
VSD DIode Forward Voltage ® IRF9230
- - -6.5 V Te ~ 25°e, IS ~ -6.5A, VGS ~ OV
IRF9231
IRF9232 - - -6.3 V Te ~ 25°e, IS = -5.5A, VGS ~ OV
IRF9233
trr Reverse Recovery Time ALL - 400 - ns T J - 150 o e, IF - -6.5A, dlF/dt - 100A/~s

ORR Reverse Recovered Charge ALL - 2.6 - ~e TJ 150 o e, )F 6.5A, dlF/dt 100 A/~s
ton Forward Turn-on Time ALL IntrinsIc turn-on time IS negligible. Turn-on speed IS substantially controlled by LS + LO'

<DTJ ~ 25°e to 150 o e. ®Pulse Test: Pulse width" 300/is, Duty Cycle ~ 2%. @ Repetitive Rating: Pulse width limited
by max. Junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-15
-lo;V
-9V lJ--Jv- - -15

lL I
-12
,.lib j..-""
80.l PU Lsl TEST -12 t-- 80., !PU LSE ~EST J.1 L
IV
i'"
5 -9 IV ~
-7V
~w
~

'" -9
::;
VOS> 10(on) x ROS(on) max.

J
Tr 55 0 C III /
~
~
III ~
I
TJ' 25°C I"'l [II
Y 100--
~
)

~ rL
~
~
=>
'-' => TJ' 125°C
z -6 '-'
VGS'-SV -6
l~
~
"=
" I ;;'i
" , 1111
E
-3 f -5V
E
-3
V
It·
IT
i-""" 1 I
.lv ~"
-10 -20 -30 -40 -50 -2 -4 -S -8 -10
VoS, oRAIN-To-SoURCE VOLTAGE (VOLTS) VGS. GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-15
_100.~:::mI
OPERATION IN THIS
AREA IS LIMITED
t - - t- 80 .! I
PU LSE TEST -50 8Y ROS(on)

1::::::,1 RF9230, 1.~m~=t~;{;~~m;J=t=llnnn

-12
-20~~H~ I-

~
~
'"w
~ -9V
w
-10 t=IRF9230, (
"-
:;; -8V ~
5 -9 ::;

~~
I- I I- -5 IRF9232,3
tii _~7V-
~
'" .-
~~
'"~ '"'-'=>
z
:;;:
'"
"E
-6

.. .-~ ~
VGS' :SV_
z

~ ~~~~~Z-~g~llml~l~o~~ms,::gll
E

~
f=TC - 25°C 100 ms
-3
f= -1.0
-0.5 TJ 150°C MAX.
I- RthJC 1.S7 K/W DC:-t
~ }5V_ I- S) NGLE PU LSE t-H--+-++t1ft1t----f-+-t-
1j+-+-t+1-H
-0.2 I-H-+-+ttiitt-+-+-+-t-:I:±±1f±+--:+r:±:Il:--t-lttH
~~ I, t-++-t-I~IIKIBII~It-t-++IIRriill·3
-4V_ 1111
I RF9 23 0 2
-0.1 ................L...L..I..U.J.I.I......L...L....L...L.J..L.I.Ju.L........L-.l...Ju..u..u.I
-2 -4 -S -8 -10 -1.0 -2 -5 -10 -20 -50 -100 -200 -500
VOS. ORAIN-TO·SOURCE VOLTAGE (VOLTS) VOS, ORAIN-TO-SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig.4 - Maximum Safe Operating Area

0-271
IRF9230, IRF9231, IRF9232, IRF9233 Devices

D = 0.5
NDTES:

C-b.2
1--0.1
..- FUL
0.05
~2~
~ ~~
r--0.02-

SINGLE PULSE (TRANSIENT 1 DUTY FACTOR, D - :;

mRMA~ I~PEOtNfE)1 I I 2. PER UNIT BASE = RthJC = 1.67 DEG. C/W.
3. TJM - TC = PDM ZthJC(t).
III I II
10-4 10-3 10-2 10-1 1.0 10
t" SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

7.00
8~ '" pu iSE TEJT
VDS> ID(on) x ROS(on) rna!,
-20

-10 /..
, h

5.60
"'1:5 TJ = -55°C f f
i'll
§
~ I--"
w
u
z
«
4.20
TJ = 25°C / 1/
t; / r- TJ=1500C
::::I
C
Z
c "l T~ = 125~C / ~J 25°C
2.80
l;l

,"
V
w
z
« '"
'"~
'"
>- -0.5 I I
~
1.40 II c2
c
V V
-0. 2 I I
1 I
-0. 11L lL
-3 -6 -9 -12 -15 -2.0 -3.2 -4.4 -5.6 -6.B -8.0
ID' DRAIN CURRENT (AMPERES) VSD, SOURCE·TO·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w
to

~
o 1.15
>
z
;0 - ' I-' L
o
V"
c
'"
~~ 1.05
~ LV
"':::; .... .",. ~
~

~i .",. V
::::10
~~ 0.9
./ L
.., 5~
c ,./
z
;;:
...... vGS = -1OV
'"c c
~ o. 5
V I
10 = -2.5A
I

~ 0,8 5 c
~ '"

OJ 5 o
-40 40 BO 120 160 -40 40 80 120 160
TJ, JUNCTlON TEMPERATURE (OC) TJ, JUNCTION TEMPERATU RE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-272
 IRF9230, IRF9231, IRF9232, IRF9233 Devices
2000

J I GS = 0
1 f = 1 MHz 1 _I
1600 CIS' = Cg, + Cgd. Cds SHORTEO _
C,,' = Cgd
1\ I I I _I--
Cgs Cgd -
'"'"'=' 10 = -SA

~ 1200
z
Coss = Cds + Cgs +. Cgd
~ Cds + Cgd
-
2:
~
«
-5
\, FOR TEST CIRCUIT
SEE FIGURE IS

;:: ::;
<3
«
~ ~
'">
co
<.> 1'-...... ,
- ~
800
......... '"=>
<..i
\ CISS ~

~
-10
~~
\\ I-
;;
40
0, .......
.......... ~ssI Vi
>'" -15
VOS = -160V.IRF9230.9132/
'[ I v~s = -1'OOV/
P ~~
..... ..... erss ~OS = ~40V/
I I
-10 -20 -30 -40 -50 16 24 32 40
VOS. ORAIN·TO·SOURCE VOLTAGE (VOLTS) Qg. TOTAL GATE CHARGE (nC)

Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
2.0 -10

"'"~
=
ROS(on) MEASUREO WITH CURRENT PULSE OF
2.0 ~s OURATION. INITIAL TJ 25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.)

co 1.6
I -S
<.>
z
«
In
/
/ r-.... I--
~
z
'"co
<.>
'"
=>
1.2

V GS =-¥ -
- to-- . . . . r-..... . . .
-r-....
92~
~9230.9231

......

-
'""? O.S I RF9232.
................. ~
'">:-
z
~
'"§
V
I---- "" ---
VGS 20V ........
~.
·2

t\,
0.4
in
",'"
o
·5 ·10 ·15 ·20 ·25 25 50 75 100 125 150
10 , DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
SO

70 ------""\.
60
"i\.
~«
~ 50
'\ \.
z
'"
;::
~ 40
'\
iii
c;
'"~ 30
'\
'""
~
.P
20

10

"i\
20 40 60 SO 100 120 140
TC. CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-273
IRF9230, IRF9231, IRF9232, IRF9233 Devices

r---
, I
VARY tp TO OBTAIN " , II
REQUIREO PEAK IL

IL r , " El

VGS'~ IL:'~~=~=:~--~~~~~ I
~tp~
" I

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

AOJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r------,
I
50n I <>---TO SCOPE
I
I
L_ ___ .J
I 50n
10
tI O.Oln
HIGH FREQUENCY
SHUNT

Fig. 17 - Switching Time Test Circuit

IG 10
CURRENT CURRENT
SHUNT ":" SHUNT
--'\/\J\~_~JV\/\'--"" +VOS

O...,---rr.
L......J~5mA
OUT

12V
BATTERY
-VOS
'--------~~ .....------------_o (ISOLATEO
SUPPLY)

Fig. 18 - Gate Charge Test Circuit

0-274
 PD-9.319

INTERNATIONAL. RECTIFIERII'!RI

HEXFET® TRANSISTORS IRF952D

IRF9521
P-Channel
IRF9522
IRF9523

-100 Volt, 0.6 Ohm HEXFET Features:

TO-220AB Plastic Package • P-Channel Versatility
• Compact Plastic Package
The HEXFET® technology is the key to International Rectifier's • Fast Switching
advanced line of power MOSFET transistors. The efficient geometry
and unique processing of the HEXFET design achieve very low • Low Drive Current
on-state resistance combined with high transconductance and • Ease of Paralleling
extreme device ruggedness. • No Second Breakdown
The P-Channel HEXFETs are designed for applications which • Excellent Temperature Stability
require the convenience of reverse polarity operation. They retain all
of the features of the more common N-Channel HEXFETs such as
Product Summary
voltage control, freedom from second breakdown, very fast switch-
Part Number VOS ROS(on) 10
ing, ease of paralleling, and excellent temperature stability.
IRF9520 -l00V O.60n -6.0A
P-Channel HEXFETs are intended for use in power stages where
complementary symmetry with N-Channel devices offers circuit IRF9521 -60V O.60n -6.0A
simplification. They are also very useful in drive stages because of IRF9522 -100V o.aon -5.0A
the circuit versatility offered by the reverse polarity connection.
Applications include motor control, audio amplifiers, switched IRF9523 -60V o.aon -5.0A
mode converters, control circuits and pulse amplifiers.

CASE STYLE AND DIMENSIONS

~
10'6610'(20)~
3.4210.135) 9.6610.380)
2.5410.100) ~DIA

10.66 (0.420)
MAX. T*~± TERM 3 - SOURCE

+-
16.5110.650)
14.2310.560)

"!iF"
t
5.3310.210)
U310.190)
14.73 (0.580)

Mr· ::~j j~' 1.1410.0(5)

o:mmll
D
.i.!lECTION x-x

T~
1.1410.045)
1.1710.070) -I
2.9210.11S)
0.5110.020)
1.1510.0(5)
2.0410.080)
ACTUAL SIZE
Case Style TO-220AB
Dimensions in Millimeters and (Inches)

0-275
IRF9520, IRF9521, IRF9522, IRF9523 Devices

Absolute Maximum Ratings

Parameter IRF9520 IRF9521 IRF9522 IRF9523 Units

VDS Drain - Source Voltage CD -100 -60 -100 -60 V

VDGR Drain - Gate Voltage IRGS ~ 1 Mill (j) -100 -60 -100 -60 V
ID@ TC ~ 25°C Continuous Drain Current -6.0 -6.0 -5.0 -5.0 A
ID@ TC ~ 100°C Continuous Drain Current -4.0 -4.0 -3.5 -3.5 A
IDM Pulsed Drain Current ® -24 -24 -20 -20 A
VGS Gate - Source Voltage ±20 V
PD@ TC ~ 25°C Max. Power Dissipation 40 ISee Fig. 14} W
Linear Derating Factor 0.32 ISee Fig. 14} W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16} L - 1 OO~H
A
-24 I -24 I -20 I -20
TJ Operating Junction and
-55 to 150 °C
T stg Storage Temperature Range
Lead Temperature 30010.063 in. 11.6mm} from case for 10s} °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage }RF9520
·100 - - V VGS ~ OV
IRF9522
IRF9521
-60 - - V ID ~ ·250~A
IRF9523
VGSlth} Gate Threshold Voltage ALL -2.0 - -4.0 V VDS ~ VGS' ID ~ -250~A
IGSS Gate-Source leakage Forward ALL - - -500 nA VGS ~ -20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA VGS ~ 20V
IDSS Zero Gate Voltage Drain Current - - -250 ~A VDS ~ Max. Rating, VGS ~ OV
ALL
- - -1000 ~A VDS ~ Max. RatingxO.B, VGS ~ OV, TC ~ 125°C
IDlon} On-State Drain Current ® IRF9520
-6.0 - - A
IRF9521
V DS ) I Dlon } x RDSlon} max.' V GS ~ -10V
IRF9522
IRF9523
-5.0 - - A

ROS(on) Static Drain-Source On-State IRF9520

- 0.5 0.6 {l
Resistance ® IRF9521
VGS ~ -10V, ID ~ -3.5A
IRF9522
- 0.6 O.B {l
IRF9523
9fs Forward Transconductance ® ALL 0.9 2.0 - SIUl V DS ) I Dlon } x RDSlon} max.' ID - -3.5A
Ciss Input Capacitance ALL - 300 450 pF
VGS ~ OV, Ves ~ -25V, f ~ 1.0 MHz
Coss Output Capacitance ALL - 200 350 pF
See Fig. 10
erss Reverse Transfer Capacitance ALL - 50 100 pF
tdlon} Turn-On Delay Time ALL - 25 50 ns V eD ~ 0.5 BV DSS ' ID - -3.5A, Zo - 50n
tr Rise Time ALL - 50 100 ns See Fig. 17
tdloff} Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
Fall Time - independent of operating temperature.)
tf ALL 50 100 ns
Qg Total Gate Charge V GS ~ -15V, ID ~ -S.OA, VDS ~ O.B Max. Rating.
ALL - 16 22 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 9.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 7.0 - nC

LD Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol shOWing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm 10.25

$
in.) from package to
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
10.25 In.} from
package to source
bonding pad.

Thermal Resistance
RthJC Junctlon-to-Case
RthCS Case-to-Slnk Mounting surface flat, smooth, and greased.
RthJA Junctlon-to-Ambient Free Air Operation

0-216
 IRF9520, IRF9521, IRF9522, IRF9523 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9520 Modified MOSFET symbol
- - -6.0 A
(Body Diode) IRF9521 showing the integral
reverse P-N junctIon rectifier.
IRF9522
- - -5.0 A

~
IRF9523
ISM Pulse Source Current IRF9520
- - -24 A
(Body Diode) Q) IRF9521
IRF9522
- - -20 A
IRF9523
VSD Diode Forward Voltage ® IRF9520
- - -6.3 V TC ~ 25'e, IS ~ -6.0A, VGS ~ OV
IRF9521
IRF9522
- - -6.0 V Te ~ 25'e, IS ~ -5.0A, VGS ~ OV
IRF9523
trr Reverse Recovery Time ALL - 230 - ns TJ - 150'e, IF - -6.0A, dlF/dt - 100 AIl's
ORR Reverse Recovered Charge ALL - 1.3 - I'e T J - 150'e, IF 6.0A, dlF/dt - 100 AIl's
ton Forward Turn-on Time ALL Intrinsic turn-on time IS negligible. Turn-on speed is substantially controlled by LS + LD'

ill TJ = 25°C to 150°C. ® Pulse Test: Pulse width.:s;; 300ttS, Duty Cycle ~ 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-10
-10
-1,0/

r
-y- f-- r-- 8~" PUl~E TES~ '/
/ /,
'j
80 "s PULSE TEST
I -8
VOS> 10(on) x
f--- ROS(on) max. r---- TJ' J5 0 C
-8
_8 IV_ f-- 1il I ~j '/
~
TJ ~ 25°C
'lJ
~

J I
~
I ~
"
!> -6 "
!> -6 TJ '" -55 C 0

VGS'-7~= F= 11 (j
§
~
=>
u
z -4
'I ~
z -4 I/!J
~
c
-L- f--
~
c
E
rt
E
-2
V
l -2
j
-5l=
I F=
-4V- f - - ~ ~
A'
-10 -20 -30 -40 -50 -2 -4 -6 -8 -10
VOS, ORAIN·TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-
-100

-5 OPERATION IN THIS
-50

~r/
AREA IS LIMITED
-SOj'PUlJTEST t--
,'- BY ROS(on)

I/~!. /'
IRF9520,1
-8V -20
'""'::I
-4

1il t LI£ V7V ~

w
~ -10
IYTY r" ...
lOr

~
w
~

".... -3
W) 'f' '">--
:'<:
-5
IRF9520,1

IRF9522,3
lOOps

~
!>
IIV V~-6V- '\.
1'\',

,--
'" 1 ms

J -2 lYi V ~
z
~
-2
'\.

"
z
~ J. 'I' Q ~1.0 101s
c
'"
-
100 ms
E -05 ~'TC 25°C
f---5V I-- TJ ~ 150°C MAX. DC
-1

J. ,/' I-- RthJC. 3.12 K/W

IR~9~20, f
r
~0.2 I-- SI NG LE PU LSE f-- t-IIRF15211'13

_41V
-0 1 I II III II I
-1 -2 -3 -4 -5 ~1.0 -2 -5 -10 -20 ~50 -100 -200 500
VOS, ORAIN·TO-SOURCE VOLTAGE (VOLTS) VOS, ORAIN-TO-SOU RCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig.4 - Maximum Safe Operating Area

0-277
IRF9520, IRF9521, IRF9522, IRF9523 Devices

D = 0.5

1-~.2
1-0.1
io-
-;;;",
,..... ... NOTES:

msL
~2~
_I-"
FO.05

=0.02 _ tl
I-
1. DUTY FACTOR, 0 - "i2 .
~~ SINGLE PULSE (TRANSIENT
~HIEIRWL I~P~OANICE~ I 2. PER UNIT BASE = RthJC = 3.12 OEG. CIW.
3. TJM - TC = POM ZthJC(t)·
I IIIII I I
10-4 10-3 2 5 10-2 2 10-1 1.0 10
tl, SQUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

-100

-50
....-:
ie /. V
~ -20
/
'"
:": -10
>-
/./
iIi
TJ- -55'C '"=>
'"
-5
,
...-
--
'-'
Tr 25'C- - z
/
V t-- TJ - 125'C ~ -2 - TJ= 150 0 CI
I
r- = '" I
V ...-r- ~ -1

1
/r _I
VOS> 10(,n) x RDS(on) max.
~
'"
to
-0.5 TJ = 25 0 C

8t
/ ",$ PUiSE TESr E'
-0.2 LI
I
V -0.1 I
-2 -4 -6 -8 -10 o -2 -4 -6 -8 -10
10, DRAIN CURRENT (AMPERES) VSD, SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w
w
'"~ U
z 1.8
Q
>
~
1.15

,,-
,... :"
<
t;
~
/
Q

~s ~
z
08 1.4
Ww
V
1.05 UN /'
~~
w< ".
".,. "'-
=>~
0< /'
~~
. /~
CI?~
00
':"z ./
:/
..,~~ 0.95 "",
z - 1.0
Q ;;;: /
Z
'"
Q /'
;;;:
cr:
Q ~ ./
V VGS = -10V
~ 0.85 ~ 0.6 10=-4A - r--
iii "I 1
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ, JUNCTION TEMPERATURE (OC) TJ,JUNCTION TEMPERATURE (OC)

Fig.8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-278
 IRF9520, IRF9521, IRF9522, IRF9523 Devices
500
J

~rt
C;ss=C9S+Cgd.CdSSHORTE0,l.
C", = Cgd
CgsCgd
Coss = Cds+ Cgs+Cgd
_ VGS = 0
t= 1 MHz
1\ I=J
1 +--
400
1\ ~Cds+Cgd
in
'=' \ FOR TEST CIRCUIT
SEE FIGURE 18

,
~ -5

~ 300
1--.... C.'ss w
co
<t 1\
-
w
u
'o='
z
<t
>-
1'.. >
w
u
1\ I'-- ,I

--
~ -10
tc ~
~~
........ Coss =>
;3 200 o
oS
\ I-- .... 6 - ---
-
S
>-
<t
Vos = -BOV, IRF~520, 9~22/
r:> ~ ~

'"
~-15
100
...........
r- ~rss >
co
Vos = -50V
vloS = Jov/
V
-20
-10 -20 -30 -40 -50 o 12 16 20
VOS, ORAIN-TO-SOU RCE VOLTAGE IVOLTS) Qg' TOTAL GATE CHARGE InC)

Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
2.0 -6_0

in
ROSlon) MEASUREO WITH CURRENT PULSE OF
2.0 ~s OURATION. INITIAL TJ = 25 0 C. (HEATING
f'..~
EFFECT OF 2.0 ~s PULSE1IS MINIMAL.)
'"
:J::
8 1.6 -4.8
"",-
~
w

'"f---IRF95:,~
u
z I
<t
t;;
ffi
a: 1.2
VGS =-10V
i'"
:'! -3.6 -
""RF9520.9521

"-
z >- .........
o
w
u
~
go "- ........
/
"'" " ~
a:
=> ~
~ 0.8 z -2.4
6 / ~-
~

-
t-;-
z ./ 0
;;;: _I"'"
-'
a:
'" ~
T r-
o
1 0.4 f--- -1.2

'\,
~

o
-5 -10 -15 -20 -25 25 50 75 100 125 150
10 , ORAIN CURRENT IAMPERES) TC. CASE TEMPERATURE IOC)

Fig. 12 - Typical On·Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
4U

35
'\
~
30
1'\
"
>-
<t
~ 25
z
0
>= \
tc 20 I\.
gj
0
a:
~ 15
\
~
~
10
'\
20 40 60 80 100
TC, CASE TEMPERATURE IOC)

Fig. 14 - Power Vs. Temperature Derating Curve

'"
120
'\
1\
140

D-279
IRF9520, IRF9521, IRF9522, IRF9523 Devices

,,
VARY Ip TO OBTAIN ,,
REQUIRED PEAK lL

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

AOJUST RL El
TO OBTAIN
SPECIFIEO 10 RL
Vi
PULSE
GENERATOR O.U.T.
r------,
I
I 50n I o - - - - T O SCOPE

I
L _ ___ ...J
I 50n
10
tI O.Oln
HIGH FREQUENCY
SHUNT

Fig. 17 - Switching Time Test Circuit

10
CURRENT
SHUNT
_ _....JVV,,--___ +V DS

°L:.lI:5mA OUT

12V
BATTERY
-VOS
'-------4t-----<____- - - _ > - - - - - Q (lSOLATEO
SUPPL YI

Fig. 18 - Gate Charge Test Circuit

D-280
 PD-9.320

INTERNATIONAL RECTIFIER II'iR I

HEXFET® TRANSISTORS IRF9S30
IRF9S31
P-Channel
IRF9S32
IRF9S33
-100 Volt, 0.3 Ohm HEXFET Features:
TO-220AB Plastic Package • P-Channel Versatility
The HEXFET® technology is the key to International Rectifier's • Compact Plastic Package
advanced line of power MOSFET transistors. The efficient geometry
and unique processing of the HEXFET design achieve very low • Fast Switching
on-state resistance combined with high transconductance and • Low Drive Current
extreme device ruggedness. • Ease of Paralleling
The P-Channel HEXFETs are designed for applications which • No Second Breakdown
require the convenience of reverse polarity operation. They retain all • Excellent Temperature Stability
of the features of the more common N-Channel HEXFETs such as
voltage control, freedom from second breakdown, very fast switch- Product Summary
ing, ease of paralleling, and excellent temperature stability. The
P-ChannellRF9530 device is an approximate electrical complement Part Number VOS ROS(on) 10
to the N-Channel IRF520 HEXFET.
IRF9530 -lOOV O.30n -12A
P-Channel HEXFETs are intended for use in power stages where IRF9531 -12A
-60V O.30n
complementary symmetry with N-Channel devices offers circuit
simplification. They are also very useful in drive stages because of IRF9532 -lOOV O.40n -lOA
the circuit versatility offered by the reverse polarity connection.
Applications include motor control, audio amplifiers, switched IRF9533 -60V O.40n -lOA
mode converters, control circuits and pulse amplifiers.

CASE STYLE AND DIMENSIONS TERM 4-

DRAIN

TERM3-SDURCE
10.66 (0.420)
MAX.

5.33(02101
4.83 (0.1901

f
14.73 (0.580) o:mo.om
D
.i!ECTIDN
1.14(0.0451
x-x

MAX. Ti--I
1.14(0.0451
i -J
2.92(0.1151
2.04(0.0801
0.51 (0.0201

Case Stvle TO·220AB

ACTUAL SIZE Dimensions in Millimeters and (Inches)

D-281
IRF9530, IRF9531, IRF9532, IRF9533 Devices

Absolute Maximum Ratings

Parameter IRF9530 IRF9531 IRF9532 IRF9533 Units
VDS Drain - Source Voltage <D -100 -60 -100 -60 V
VDGR Drain - Gate Voltage (RGS ~ 1 M{}) G) -100 -60 -100 -60 V
10@TC~25°C Continuous Drain Current -12 -12 -10 -10 A
10@ TC ~ 100°C Continuous Drain Current -7.5 -7.5 -6.5 -6.5 A
IDM Pulsed Drain Current ® -48 -48 -40 -40 A
VGS Gate - Source Voltage ±20 V
PD@ TC ~ 25°C Max. Power Dissipation 75 (See Fig. 14) W
Linear Derating Factor 0.6 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L ~ 1OO~H
A
-48 I -48 I -40 I -40
TJ Operating Junction and
-55to150 °C
T stg Storage Temperature Range
lead Temperature 30010.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVDSS Drain - Source Breakdown Voltage IRF9530
-100 - - V VGS ~ OV
IRF9532
IRF9531
-60 - - V ID ~ -250~A
IRF9533
VGSlth) Gate Threshold Voltage ALL -2.0 - -4.0 V VDS ~ VGS, ID ~ -250~A
IGSS Gate-Source Leakage Forward ALL - - -500 nA VGS - -20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA VGS ~ 20V
lOSS Zero Gate Voltage Drain Current - - -250 ~A VDS ~ Max. Rating, V GS ~ OV
ALL
- - -1000 ~A VDS - Max. RatingxO.a, VGS - OV, TC - 125°C
ID(on) On-State Drain Current ® IRF9530
-12 - - A
IRF9531
VDS } ID(on) x RDS(on) max.' V GS ~ -10V
IRF9532
-10 - - A
IRF9533
ROSlon) Static Drain-Source On-State IRF9530
Resistance ® IRF9531
- 0.25 0.30 {)
VGS ~ -10V.ID ~ -6.5A
IRF9532
- 0.30 0.40 0
IRF9533
9fs Forward Transconductance ® ALL 2.0 3.8 - Sill) VDS } 10(on) x RDS(on) max.' ID - -6.5A
Ciss Input Capacitance ALL - 500 700 pF
VGS ~ OV. VDS ~ -25V. f ~ 1.0 MHz
Coss Output Capacitance ALL - 300 450 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 100 200 pF
td(onl Turn-On Delay Time ALL - 30 60 ns V DD ~ 0.5 BV DSS ' ID - -6.5A, Zo = 500
tr Rise Time ALL - 70 140 ns See Fig. 17
td(off) Turn-Off Delay Time ALL - 70 140 ns (MOSFET switching times are essentially
Fall Time - 140 ns independent of operating temperature.)
tf ALL 70
Qg Total Gate Charge V GS ~ -15V. 10 ~ -15A. V DS ~ 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain)
ALL - 25 45 nC
See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 13 - nC

Qgd Gate-Orain ("Miller") Charge ALL - 12 - nC

LD Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.) from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-282
 IRF9530, IRF9531, IRF9532, IRF9533 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9530 Modified MOSFET symbol
- - -12 A
(Body Diode) IRF9531 showing the integral
reverse P-N Junction rectifier.
IRF9532

~
- - -10 A
IRF9533
ISM Pulse Source Current IRF9530
- - -48 A
(Body Diode) @ IRF9531
IRF9532
IRF9533
- - -40 A

VSD Diode Forward Voltage ® IRF9530

- - -6.3 V Te = 25·e.I S = -12A. V GS = OV
IRF9531
IRF9532
IRF9533
- - -6.0 V T e = 25·C.I S = -IDA. V GS = OV

trr Reverse Recovery Time ALL - 300 - ns T J - 150·C. IF - -12A. dlF/dt - I 00 A/~s
QRR Reverse Recovered Charge ALL - 1.8 - ~C T J - 150·C.I F - -12A.dI F/dt - 100A/~s

ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO-

(j)TJ = 25·e to 150·C. ® Pulse Test: Pulse width .. 300~s. Duty Cycle .. 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-20
-IV
80 ~ PU LSJ TEST
-i V- r---

If I -16
-16

V -8r- r---
i,.
i'"
5 -12 I 5 -12
VGS--7~- ~
I-

~
=>
~
[l
"z -8
I z -8

~ -~V_ ~ ~
E
E
-4 I -4
I
-5~- ~
-4~- f--
-10 -20 -30 -40 -50 -2 -6 -8 -10
VDS. DRAIN·TO·SOURCE VOLTAGE (VOLTSI VGS. GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-100
OPERATION IN THIS
-IRF9530.1 AREA IS LIMITED
-10 -50
-tt~ / ' V'
BY RDSlon)
-801 PUlSJ TEST

/1-8~.V '- 10~

-iRTY';
-20 "
-8 -:RF~53bS I"-

--
@
h';':,/1 ..
~ -10
100 ~s

i'"
5 -6 WJ v VGs.l-
~ ~
I- -5
--=!RF9532.3
1 ms
~
~ IIV /~ a:
a:
az IO~s

, //iV
~
=>
-2
"z «
~
-4

J. r,- ~ -1.0
100 ms

-
E =TC 25 0 C OC
E o
-0.5 ==TJ -150 C MAX.
f--- 5V
J ;....---..-
-2 - RthJC • 1.67 K/W
-SINGLE PULSE
I
lv
-0.2

-t t U i
'-- -I -2 -3 -4 -5
-0.1
-1.0
I
-2
1111111
-5 -10 -20
F9 3

-50 -100 -200

I Ri9j30.

-500
VOS. DRAIN·TO-SOURCE VOLTAGE (VOLTS) VDS. DRAIN-TO·SOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig, 4 - Maximum Safe Operating Area

0-283
IRF9530, IRF9531, IRF9532, IRF9533 Devices

....
ii'j
~
<
"'-
........
wz 1.0
>::::0 0=0.5
~ffi 0.5
w,,- NOTES:
:t;:; -~.2
w",

ffi~ 0.2
!:::!ffi 0.1
~
Iii;;; III"" lTUL
~2~
-'''-

~E
~:!l 0.1 0.05
"'-'
0< -0.02
"'_il!! 0.05 ..... 0.01
"'w PULSE (TRANSIENT
1. DUTY FACTO R, 0 = :~
~~ ! itERjAi IMPIEOnCj) I II
.!!"
~ 0.02
2. PER UNIT BASE = RthJC = 1.67 OEG. crw.
3. TJM - TC = POM ZthJC(t)·
~ 0.01 III I I I IIII
10-5 10-4 10-3 10-2 10-1 1.0 10
tl, SQUARE WAVE PULSE OURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs, Pulse Duration

-100

TJ=~ ~
-50

V ~-2150~ ~- A

/ /" ~11250C
'/ . /
...... ~
.,....... - ~
!!l;
~
....
~
-20

-10 r/
/L
//

r/ '"~
z
~
-5

-2
-TJ= 150 0 C
I
II

I
'"
w
0> III
-1
'"
w

vos> lo(on) x RoS(on) max. ~

'" -0.5
TJ 25 0 C
80"'1"'8'I'8T- -
'"
E' I
I I
-0.2
L
-0.1
I J
-4 -8 -12 -16 -20 o -2 -4 -6 -8 -10
10, DRAIN CURRENT (AMPERES) VSO, SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

2.2
1.25

w
w
'"~ '"<z 1.B
o
>
1.15 ....
0> /
z
~ ,.."
~
'" ~
z V
'" ~ 1.4
~ffi
05

"
1.05 Ww
"'N
:;~
".
~ "'-
g~
/"
~~
::::0'"
""",.. "1'"
0'"
.... 0 . /V
~~0.95 ,.." ". ' z-
z 1.0 - r--
'"~
;;:
'" ./ V
'"c .,.......
:i 0 .,....... VGS = -IOV
'"~
<;)
-
i;
0.85 ~
0,6
IO=-4A -
-, ,
0.75 0.2
-40 40 80 120 160 -40 40 80 120
TJ,JUNCTIDN TEMPERATURE (DC) TJ,JUNCTIDN TEMPERATURE (OC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-284
 IRF9530, IRF9531, IRF9532, IRF9533 Devices

,
1000
1\
II ~Gs=J I. ,I I
800
\
f= 1 MHz .1
Ciss = Cgs + Cgd. Cds SHORTED
r--
r\ la= -15A
FOR TEST CIRCUIT- r--
\
,--
c"s = Cgd SEE FIGURE 18
'"
~
Cgs Cgd
Coss = Cds + CgS + Cgd I-- ~ -5
~
~
600 l\\ ::::::Cds + Cgd
I--
w
co
« \
......
w

~ '""'-
~
CI~S
u
z
\ "
>
u ~
:;
;3 400 "- "'- I =>
""I
-10
r--. ~
u'
\ .1
........Coss "~ 953~~
r\...... I r-- f-- !;;:
C!:I -15
Vas = -80V.1 RF9530.
I I
VDS = -50V ~
200
I"- ~
.1
...... Crss
co
> '" Va~=·2tiV/

I -20
-10 -20 ,3D -40 -50 o 16 24 32 40
Vas. aRAINTO·SOURCE VOLTAGE (VOLTS) Og. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
1.0 ·12.0
..........
VG1S =-lOl r--....
"'£~ r-..... i'-
0.8 -9.6
........... r--...... ...... ,
..
w
u
Z

t;; '"
W
Ir ~9530.9531
W ..........
~ Q.

Ir
0.6 '"....
:;. -7.2 IRF9532. 95~
z
"'-'w ~ ........... '"
~
Ir Ir
=>
.........
=> U
"I " 0.4 z -4.8

/ ~
;;(
"z
"'~ Ir

"E
"c 0.2
- ...... VGS =-20V-
1_~
~
-2.4
'~
'"
Ir"
0
RDS(on) MEASUREa WITH CURRENT PULSE OF
2.0 ~s DURATION. INITIAL TJ = 25 0 C. (HEATING
1
\
EFFECT OF 2.0 ~s PULSE IS MINIMAl.)
o
·10 ·20 ·30 40 ·50 25 50 75 100 125 150
I D• DRAIN CURRENT (AMPERES) TC. CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs_ Case Temperature
80

70
- "-
'\
60 '\.
g '\
~
z
50 '-
";::
:; 40
'\
iii
i5
Ir

~ 30
"\
It
.E 20 I'\.
10 '\.
'~
20 40 60 80 100 120 140
TC. CASE TEMPERATURE (DC)

Fig, 14 - Power Vs. Temperature Derating Curve

0-285
IRF9530, IRF9531, IRF9532, IRF9533 Devices
r---
I
VARY tp TO OBTAIN I
REQUIRED PEAK IL
I
I
I

Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r-----...,
I
50n I < ) - - _ TO SCOPE
I o.ow
I I 50n HIGH FREUUENCY
L_ _ __ -l SHUNT

Fig. 17 - Switching Time Test Circuit

IG 10
CURRENT CURRENT
SHUNT ":" SHUNT
--'\.I\F\~_<lI__'V\J\,.-n +Vos
o-,---rr.
L.....J~5mA
OUT

-VOS
' - - - - - ' - - - - - - - - - < 1 1 - - - - - 0 (ISOLATED
SUPPLY)

Fig. 18 - Gate Charge Test Circuit

0-286
 PD-9.350

INTERNATIONAL RECTIFIER II\~R I

HEXFET®TRANSISTORS IRF961D
P-CHANNEL IRF9611
2DD VDLT DEVICES IRF9612
IRF9613
-200 Volt, 3.0 Ohm HEXFET Features:
TO-220AB Plastic Package • P-Channel Versatility
The HEXFET technology is the key to International Rectifier's • Compact Plastic Package
advanced line of power MOSFET transistors. The efficient geom- • Fast Switching
etry and unique processing of the HEXFET design achieve very
low on-state resistance combined with high transconductance • Low Drive Current
and extreme device ruggedness. • Ease of Paralleling
The P-Channel HEXFETs are designed for applications which • No Second Breakdown
require the convenience of reverse polarity operation. They reo • Excellent Temperature Stability
tain all of the features of the more common N-Channel H EXFETs
such as voltage control, freedom from second breakdown, very
fast switching, ease of paralleling, and excellent temperature Product Summary
stability. The P-Channel IRF9610 device is an approximate
electrical complement to the N-ChannellRF61 0 H EXFET for lin· Part Number VOS ROS(on) 10
ear applications.
IRF9610 -200V 3.0n -1.7SA
P-Channel H EXFETs are intended for use in power stages where
complementary symmetry with N-Channel devices offers circuit IRF9611 -lS0V 3.0n -1.7 SA
simplification. They are also very useful in drive stages because IRF9612 -200V 4.Sn -l.SA
of the circuit versatility offered by the reverse polarity con·
nection. Applications include motor control, audio amplifiers, IRF9613 -lS0V 4.Sn -l.SA
switched mode converters, control circuits and pulse amplifiers.

CASE STYLE AND DIMENSIONS '0.66 (0.'20)~

3.42 (0.135)
2.54 (0.100) ~ 9.66 (0.3800
4.08 (0.161)

10.66 (0.420)
MAX. -G'±""
16.51 (0.650)
14.23 (0.580)
TERM 3 - SOURCE

t
+-"!fF" 5.33 (0.210)
4.83 (0.190)

14.73 (0.580)
MAX.

i
:~IJ~' 1.14(0.0451
0.31 (0.012)
~ECTlONX-X
D
TI------I
1.14(0.045)
1.77 (0.070) -I
2.92 (0.115)
0.51 (0.020)
1.15 (0.045)
2.04 (0.0801

ACTUAL SIZE Case Style TO·220AB

All Dimensions in Millimeters and (Inches)

0-287
IRF9610, IRF9611, IRF9612, IRF9613 Devices

Absolute Maximum Ratings

Parameter IRF9610 IRF9611 IRF9612 IRF9613 Units
VOS Drain - Source Voltage <D -200 -150 -200 -150 V
VOGR Orain - Gate Voltage (RGS = 1 MOl <D -200 -150 -200 -150 V
10@TC - 25°C Continuous Drain Current -1.75 -1.75 -1.5 -1.5 A
10@TC-100oC Continuous Drain Current -1.0 -1.0 -0.9 -0.9 A
10M Pulsed Drain Current ® -7.0 -7.0 -6.0 -6.0 A
VGS Gate - Source Voltage ±20 V
PO@TC - 25°C Max. Power Dissipation 20 (See Fig. 141 W
Linear Derating Factor 0.16 (See Fig. 141 W/K
ILM Inductive Current, Clamped (See Fig. 15 and 161 L = 1OO~H
A
-7.0 I -7.0 I -6.0 I -6.0
TJ Operating Junction and
-55to 150 °C
Ts.tlJ.. Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mml from case for 10s1 °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF9610
IRF9612
-200 - - V VGS = OV
IRF9611
IRF9613
-150 - - V 10 = -250~A
V GS..nh) Gate Threshold Voltage ALL -2.0 - -4.0 V VOS - VGS' 10 - -250~A
IGSS Gate-Source Leakage Forward ALL - - -500 nA VGS = -20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA VGS = 20V
lOSS Zero Gate Voltage Drain Current - - -250 ~A VOS - Max. Rating, V GS - OV
ALL
- - -1000 ~A VOS = Max. Rating x 0.8, VGS = OV, T C = 125°C
10(onl On-State Drain Current ® IRF9610
-1.75 - - A
IRF9611
V OS ) 10(onl x ROS(onl max.' V GS = -10V
IRF9612
-1.5 - - A
IRF9613
ROSlon) Static Drain-Source On-State IRF9610
- 2.3 3.0 !J
Resistance ® IRF9611
IRF9612
VGS = -10V, 10 = -0.9A
- 3.5 4.5 II
IRF9613
gfs Forward Transconductance ® ALL 0.9 1.3 - S!llI VOS ) 10(onl x ROS(onl max.' 10 -0.9A

Ciss Input Capacitance ALL - 170 300 pF

VGS = OV, VOS = -25V, f = 1.0 MHz
Coss Output Capacitance ALL - 50 100 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 15 35 pF
td(onl Turn-On Delay Time ALL - 8.0 15 ns VOO = 0.5 BV OSS ' 10 - -0.9A, Zo = 5011
tr Rise Time ALL - 15 25 ns See Fig. 17
tdloff) Turn-Off Delay Time ALL - 10 15 ns (MOSFET switching times are essentially
- independent of operating temperature.)
tf Fall Time ALL 8.0 15 ns
Qg Total Gate Charge
ALL - 8.0 11 nC
V GS = -15V, 10 = -3.5A, VOS = 0.8 Max. Rating.
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - 5.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 3.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25
in.J from package to

$
center of die.

LS Internal Source Inductance ALL - 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.1 from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-288
 IRF9610, IRF9611, IRF9612, IRF9613 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9610 Modified MOSFET symbol
(Body Diode) IRF9611
- - -1.75 A
showing the integral
IRF9612 reverse P-N junction rectifier.
- - -1.5

~
A
IRF9613
ISM Pulse Source Current IRF9610
- - -7.0 A
(Body Diode)@ IRF9611
IRF9612
- - -6.0 A
IRF9613
VSD Diode Forward Voltage@ IRF9610
IRF961 I
- - -5.8 V TC = 25·C, IS = -1.75A, VGS = OV

IRF9612
IRF9613 - - -5.5 V TC = 25·C, IS = -1.5A, VGS = OV

trr Reverse Recovery Time ALL - 240 - ns T J - 150·C, IF - -I .75A, dlF/dt = 100 A/~s
QRR Reverse Recovered Charge ALL - 1.7 - ~C T J - 150·C, IF - -1.75A, dlF/dt = 100A/~s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + lO'

(j) T J = 25·C to 150·C. @Pulse Test: Pulse width'; 300~s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-2.40 -2.40
-lOV '1-8V
-9V
-7V
I 'I
-1.92
'I tJsETElT -1.92
I.
TJ = -55 0C II
TJ = ~50C "-., 'I,
.'"~
~ -1.44
iii
.'"
15
~ -1.44
TJ = 125 0C
" ""'r-J'I
I-
VGS = -6V
>- IJ.I
IJ
~ i'ii
I '" I[
'"
::> '"
::>
'"'z
:;;:
-0.96 '"'z
:;;:
-0.96

'"
c '"c rJ Bl!",PU~SETEST-
E E VDS> ID(on) x RDS(on) max.
-0.48 -0.48
-51
J
-4~ V
-10 -20 -30 -40 -50 -2 -4 -6 -8 -10
VDS, DRAIN·TD-SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-50
-2.40
80 PI PU LSE TEST -1~ -8~ J,...-
-20 OPERATION IN THIS

V V~7V""
AREA IS LIMITED
-9y~ <J>
W
a: 8Y RDS(on)
-1.92 -10
~
~V
t:::JRF9610, I
10l's
iii 'z>-"
~
-5 -IRF9612,3
~,.
~ -1.44
~V w
a:
a:
_:R~96110, \
.<
1'.. ~.
10~I'S
>-
i'ii J~ ~VGS=-6V 13
z
-2
"-
a:
a:
::>
II /
:;;:
a:
c
-1.0
IRF9612,3
~' ~ .. "

~ -0.96 E 1 ms
~
c
j V -0.5
-,
E
-0.48 I' -0.2 -
,LTC=25 0C
TJ = IS0 0C MAX.
~
10 Ims
I I

J V- -5, - RthJC = 6.4 K/W

-0. 1 :::::::;SINGLEPULSE
... 100 ms
oc~:i
ii' -4~ -0.05
IRF9611,3 I RF9610, 2

-2 -4 -6 -8 -10 -1.0 -2 -5 -10 -20 -50 -100 -200 -500

VOS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VOS, ORAIN-TO.sOURCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-289
 IRF9610, IRF9611, IRF9612, IRF9613 Devices

....
i:i:i
0;
z
«
"'-
........ 1.0
wz
>::>
0=0.5
~e:i 0.5
~~
w,-,
~ ~ 0.2
0.2 -- !II
NOTES:

msL
~ffi ~6.1 ::oil

~2~
~"-
;)!~ 0.1
"'~ EO.05
0«
z_~ 0.05 f-~ _ 11
Uw
:;1:r f-~ 1. OUTY FACTOR, 0 -12 .
~ ....
...0.Q1~ 2. PER UNIT BASE = RlhJC = 6.4 OEG. CIW.
~ 0.02 SINGLE PULSE (TRANSIENT
~ ........,.. j..o"" jH~~~~L I~PEIOANfE)1 I 3. TJM - TC = POM ZlhJC(I) .
J 0.01
10-5 10-3 10-2 10-1 1.0 10
11, SQUARE WAVE PULSE OURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction·to·Case Vs. Pulse Duration

2.0 -10

r- 8L,PUJSETEJ I I
I I I -5
I
1.6 r-- VOS > 10(on) x ROS(on) max.
~ iii /1
~
§ TJ = -550 C ~::;; -2
'/
/
, ~ .......
w 1.2
U :!
z ....
«
t; TJ = 2150 C f:l /
~ ....-
'" -1.0
::>
c
z
~z
0.8
V TJ = l25 0 C
'"~
z

~
....
~~~ ~
c
-0.5 - TJ = 150 0 C
/TJ= 25 0 C
j
0.4 !J.V E
1I II
l
V -0.2

-0.1
-2.0
I I
-3.2 -4.4 -5.6 -6.8 -S.O
-0.4S -0.96 -1.44 -1.92 -2.4
10, ORAIN CU RRENT (AMPERES) VSO,SOURCE·TO·ORAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source·Drain Diode Forward Voltage

1.25 2.5

w
U
:::: 2.0
~

'"
t;;
ffi ./
,,-
".,
"., '"
z
°31.5
V
,~ Ww
UN

~~ V '"
./ ",::;;
V
./ ~~- 10.
z
./
~ «
0: .... / vGS = -10V
'" 10 = -0.6A

~
~ V
0.85 ~ 0.5
c
ii;

0.15
-40 40 80 120 160
o
-40 40 SO 120 160
TJ, JUNCTION TEMPERATURE (DC) TJ,JUNCTION TEMPERATURE (DC)

Fig, 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On·Resistance Vs. Temperature
0-290
 IRF9610, IRF9611, IRF9612, IRF9613 Devices
500

JGS = 0 I

400
J f= 1 MHz J J
C;ss = Cgs + Cgd, Cds SHORTED \ tJ5A I r--
Crss = Cgd
Cgs Cgd
CO" = Cds + Cgs+Cgd
-

-
"'
~
~ -5
\ FOR TEST CIRCUIT
SEE FIGURE 18

~
~Cds + Cgd w
'"
« ~
-
w
300
~
'-'
z
«
f-
o
>
w \
~
U ~ -10

~ ~~
::J
200 o
'-'-
\ """- C1SS
'"o~
100 ~ I\..
~
~ -15
VOS = -100V, IRF9610, 9612--;
VD~" -60Y
~~
I >'"
\
-
~~
VOr=-40l'/

......... Gns

-20
-10 -20 -30 -40 -50 o 4 10
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) 1Ig, TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
2.0

"0••••
2.0 ~""'"
"'" '""""'""'"'
~s DURATION. INITIAL TJ = 25 0 C. (HEATING
EFFECT OF 2.0 ~s PULSE IS MINIMAL.)
f 1.6
r--....
r--....
~
...... ~
I i,. ......... .....
VGS=-17-

/
5
f-

~
1.2
~
........
IRF9612,9~ " ~F9610, 9611

......
,
--
/ '" ..........
.,/' 13
z 0.8
i'...
.......-:::: VGS =-20V ~
0 ~ \..
E
0.4
'\ ~
'\
-1 ·2 ·3 -4 ·5 ·6 ·7 o
25 50 75 100 125 150
ID' DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
20

'\
~
~
~
z
0
1=
~ 10
iii
c
'"~
15

" '[\.
'\
I\.
'\
~
~
~

20 40 60 80 100
TC, CASE TEMPERATURE (DC)

Fig. 14 - Power Vs. Temperature Derating Curve

0-291
"
120
'\
140
IRF9610, IRF9611, IRF9612, IRF9613 Devices

, I
r---
VARY tp TO OBTAIN " , II
REQUIRED PEAK IL

IL./" "
VGS=fr] OUT I " I
...L IL+---C~--_\110-"'" ~tp~
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

ADJUST RL El
TO OBTAIN
SPECIFIED 10 RL
Vi
PULSE
O.U.T.
r-----...,
GENERATOR

I
500 I 0---- TO SCOPE
I 10 I o.om
I I 500
L_ _ __ ...1 • HIGH FREQUENCY
SHUNT

Fig. 17 - Switching Time Test Circuit

10
CURRENT
SHUNT

o-,---rr.
L..-.J~5mA
OUT

12V
BATTERY
-Vas
'-----41---_____- - -.....- - - - ( ) (ISOLATED
SUPPLY)

Fig. 18 - Gate Charge Test Circuit

0-292
 PD-9.351

INTERNATIONAL RECTIFIER II\~R I

HEXFET@TRANSISTORS IRF9620
P-CHANNEL IRF9621
aDDVDLT IRF9622
POWER MDBFETs
IRF9623
-200 Volt, 1.5 Ohm HEXFET Features:
TO-220AB Plastic Package • P-Channel Versatility
The HEXFET technology is the key to International Rectifier's • Compact Plastic Package
advanced line of power MOSFET transistors. The efficient geome- • Fast Switching
try and unique processing of the HEXFET design achieve very low
on-state resistance combined with high transconductance and
• Low Drive Current
extreme device ruggedness. • Ease of Paralleling
• No Second Breakdown
The P-Channel HEXFETs are designed for applications which
require the convenience of reverse polarity operation. They retain
• Excellent Temperature Stability
all of the features of the more common N-Channel HEXFETs such
as voltage control, freedom from second breakdown, very fast Product Summary
switching, ease of paralleling, and excellent temperature stability.
The P-ChanneIIRF9620 device is an approximate electrical com-
plement to the N-Channel IRF610 HEXFET. Part Number VOS ROS(on) 10
IRF9620 -200V 1.5n -3.5A
P-Channel HEXFETs are intended for use in power stages where
complementary symmetry with N-Channel devices offers circuit IRF9621 -150V 1.5n -3.5A
simplification. They are also very useful in drive stages because of
the circuit versatility offered by the reverse polarity connection. IRF9622 -200V 2.4n -3.0A
Applications include motor control, audio amplifiers, switched IRF9623 -150V 2.4n -3.0A
mode converters, control circuits and pulse amplifiers.

~ '0.6610'4201~
CASE STYLE AND DIMENSIONS 3.4210.1351 9.6610.3801
2.5410.1001 4.0810.161) IA

10.66 (0.420)
MAX. T*~' TERM 3 - SOURCE

+- ~'F'"
16.61 (0.650)
14.2310.5601

5.3310.2101

t 4.83101901

14.73 (0.580)

Mr· It
:Ij~' 1.1410.0451
0.3110.0121
.i.:ECTION
0
TI--I
1.1410.0451
x-x

1.7710.0701 -I
2E210.1151
0.5110.0201
1.1510.0451
2.0410.080)

ACTUAL SIZE Case Style TO-220AB

All Dimensions in Millimeters and (Inches)
IRF9620, IRF9621, IRF9622, IRF9623 Devices

Absolute Maximum Ratings

Parameter IRF9620 IRF9621 IRF9622 IRF9623 Units

VOS Drain - Source Voltage <D -200 -150 -200 -150 V

VOGR Orain - Gate Voltage (RGS - 1 MOl <D -200 -150 -200 -150 V
10@TC-25°C Continuous Drain Current -3.5 -3.5 -3.0 -3.0 A
10@ TC ~ 100°C Continuous Drain Current -2.0 -2.0 -1.5 -1.5 A
10M Pulsed Drain Current ® -14 -14 -12 -12 A
VGS Gate - Source Voltage ±20 V
PO@ TC ~ 25°C Max. Power Dissipation 40 (See Fig. 14) W
Unear Derating Factor 0.32 (See Fig. 14) W/K
ILM Inductive Current, Clamped (See Fig. 15 and 16) L - 100/LH
A
-14 I -14 I -12 I -12
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 (0.063 in. (1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF9620
-200 - - V VGS ~ OV
IRF9622
IRF9621
-150 - - V 10 ~ -250/LA
IRF9623
VGS(th) Gate Threshold Voltage ALL -2.0 - -4.0 V VOS ~ VGS' 10 ~ -250/LA
IGSS Gate-Source Leakage Forward ALL - - -500 nA V GS - -20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA V GS - 20V
lOSS Zero Gate Voltage Drain Current - - -250 /LA VOS - Max. Rating, VGS - OV
ALL
- - -1000 /LA VOS ~ Max. RatingxO.8, VGS ~ OV, TC ~ 125°C
10(on) On-State Drain Current @ IRF9620
IRF9621
-3.5 - - A
V OS } 10(on) x ROS(on) max.' V GS ~ -10V
IRF9622
IRF9623
-3.0 - - A

ROS(on) Static Drain-Source On-State IRF9620

- 1.0' 1.5 0
Resistance ® IRF9621
VGS ~ -10V, 10 ~ -1.5A
IRF9622
IRF9623 - 1.5 2.4 0

9fs Forward Transconductance ® ALL 1.0 1.8 - S((J) VOS } 10(on) x "OS(on) max.' 10 - 1.5A

Ciss Input Capacitance ALL - 350 400 pF

VGS ~ OV, VDS ~ -25V, f ~ 1.0 MHz
Coss Output Capacitance ALL - 100 125 pF
See Fig. 10
erss Reverse Transfer Capacitance ALL - 30 45 pF
td(on) Turn-On Delay Time ALL - 15 40 ns VOO ~ 0.5 BV OSS ' 10 ~ 1.5A, Zo ~ 500
tr Rise Time ALL - 25 50 ns See Fig. 17
tdJoffl Turn-Off Oelay Time ALL - 20 50 ns (MOSFET switching times are essentially
- independent of operating temperature.)
tf Fall Time ALL 15 40 ns
Qg Total Gate Charge V GS ~ 15V, 10 ~ -4.0A, VOS ~ 0.8 Max. Rating.
ALL - 16 22 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Q gs Gate-Source Charge ALL - 9.0 - nC

Qgd Gate-Drain ("Miller") Charge ALL - 7.0 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm (0.25

.$
in.) from package to
center of die.

LS Internal Source Inductance ALL 7.5 - nH Measured from the

source lead, 6mm
(0.25 in.) from
package to source
bonding pad.

Thermal Resistance
RthJC Junction-to-Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-294
 IRF9620, IRF9621, IRF9622, IRF9623 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9620 Modified MOSFET symbol
- - -3.5 A
(Body Diode) IRF9621 showing the Integral
reverse P-N junction rectifier.
IRF9622
- -

~
-3.0 A
IRF9623
ISM Pulse Source Current IRF9620
- - -14 A
(Body Diode) @ IRF9621
IRF9622
- - -12 A
IRF9623
VSD Diode Forward Voltage ® IRF9620
- - -7.0 V TC ~ 25°C, IS ~ -3.5A, VGS ~ OV
IRF9621
IRF9622
- - -6.8 V TC ~ 25°C, IS = -3.0A, VGS ~ OV
IRF9623
trr Reverse Recovery Time ALL - 300 - ns TJ - 150°C, IF - 3.5A, dlF/dt - 100 Ai"s
ORR Reverse Recovered Charge ALL - 1.9 - "C T J - 150°C, IF - -3.5A, dlF/dt - 100 Ai"s
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LO'

(j)TJ ~ 25°C to 150°C. ® Pulse Test: Pulse width'; 300"s, Duty Cycle'; 2%. @ Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-5 -5
-10V
-9V ~ -8V
-7V 80 ~S, PUlSE ,TEST
VOS> 10(on) x II /
-4
'/
aoJpULSE:TEST -4
ROS(on) max. ITJ = -J50C"
II /
'-..1/
TJ=25 0 C"
iii iii
::;
0-
'"~ TJ = 125 0 C"
1/
'"....
5- -3 J
GS = -6V '"....
5- -3
.........

~
'"'"
r ~ 1
'"'"
::>
<..>
z -2
a
z -2
«
'"
Q
;::
Q

!? , -5V
'"
-1

-10 -20 -30

Jv
-40 -50
-1

-2 -4
~
,J -6 -8 -10
Ves, ORAIN·TO-SOURCE VOLTAGE (VOLTS) VGS, GATE·TO·SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-100
-5

r-l", PU!SE TEJT -50

OPERATION IN THIS
AREA IS LIMITED
BY ROS(on)
-4
-1~V;:::::: r-- -20
~RF9620, 1
iii
::;
-9V ~ ~w "';:I.~-
-10 =IRF9622,3
~ 1-
10,",,=
0-
-~~ 0-

'...."
5- -3 -7V_
'...."
5- -5
=IRF9620,1 1O~ ,",'
~ L,[;=-6'V:::::::: ~ ....
r-..I"'\, 1'.
'"
::>
<..>
z -2
~V a'"
z
-2 _TRF9~2, 3
~
« ,'[ 1 .... 1iS

~
« V -1.0
'"
Q '"
Q

~ TC 25 0 C
~~
!? !? -0.5 = TJ = 150 0 C MAX.
-5V- 10 ms
-1 ~
--.-r
m,
~~
I-""" _ RthJC - 3.12 K/W 100
-0.2 _ISINIGL~ p~~s~( oc;~± I
~~ -4~- IRF9621,3 I RF9620, 2
-0.1 II II
-1 -2 -3 -4 -5 -1.0 -2 -5 -10 -20 -50 -100 -200 -500
VOS, ORAIN·TO-SOURCE VOLTAGE (VOLTS) VOS, ORAIN·TO·SOU RCE VOLTAGE (VO LTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-295
IRF9620, IRF9621, IRF9622, IRF9623 Devices

...
1:5
u;
z
<
"'-
......
wz 1.0
>:::>
o 0.5
;:: '" 0
~~
::a ~ 0.2
~Ea -0.1
.5
-~.2 -- i
NOTES:

3:fUL
~2~
~Q.
_i-"~
~~ 0.1 =0.05
"'~
0<
-0.02
z.~ 0.05
Uw
- _ '1
1. DUTY FACTOR, 0 - t2 .
}~ ~~ SINGLE PULSE (TRANSIENT
=:: 0.02 1WI~AL Irp~OANICE: I
2. PER UNIT BASE = R'hJC = 3.12 OEG. C/W.
u 3. TJM - TC = PaM Z,hJC(I)·
j 0.01 I IIIII I I I
10-5 10-4 10-3 10-2 10-1 1.0 10
q, saUARE WAVE PULSE OURATION (SECONOS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case V,. Pulse Duration

4.0 -20
r
r--8~"'PU~SETE~T I I -10 A
Vas> 10(on) x ROS(on) max.
in
1:5
3.2
i,. -5
,.
i'li
§
TJ = -55 DC ~
... "
'f
w
U
z
2.4
~ TJ = 25 0 C
1:5
~ -2 /J
...<
U
/ :::>
U
'/
z
/,1
/ ./ ~
:::>
c
z T} - 1251c ~ -1.0
c 1.6 c f= TJ -150 0 C

,
~
z
...<'"
'/ . / i-""'"
w
'"
'"w
G;
-0.5 ,
TJ = 25 0 C

£ 0.8 /I '/ '"<i: /

E'
-0.2 / I
J
-0.1
/ I
-1 -2 -3 -4 -5 -2.0 -3.2 -4.4 -5.6 -6.8 -8.0
10, ORAIN CURRENT (AMPERES) VSO,SOURCE·TO-DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance V,. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w
'"~ w
./
,.,
U
c 1.15 z 2.0
>
~ /'
~
Q
"..",.
...- ../
ffi
'"z /
",
~E 1.05 061.5
ww
:;~ "..",.
~~
~
UN

g~ /"
:::>'"
"..",. 6~ /'
5) ~ 0.95
./ I-;-~ 1.0 ./ VGS=-10V
,.,.c ~ z-
z
;;:
;;:
'"c ....V I I
10 = -1.0A

'"c c
o
",
~ 0.85 '"
c 0.5
il:; '"

0.75 o
-40 40 80 120 160 -40 40 BO 120 160
TJ, JUNCTION TEMPERATURE (DC) TJ, JUNCTION TEMPERATURE (DC)

Fig. 8 - Breakdown Voltage V,. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
D-296
 IRF9620, IRF9621, IRF9622, IRF9623 Devices
500

~
\
t·J ~
I~'
I
400
......
'1'1 MHz

~ \ -4A

c~"
FOR TEST CIRCUIT
\ r--..... '"- 0 ·5 -

~
2: SEE FIGURE 18

...
~ \, I ..'"
w

:;
'"
z
300 Ciss • Cos + Cgd. Cds SHORTEO
Crss • Cgd
0
>
w \ ~

..
;!:
U
!it 200 \ \ Cgs Cgd
CO" • Cds + Cgs + Cgd
'"'"=>
0
"?
..,
0
-10

~~
'"
\ "'Cds+ Cgd
..'" .,/

~&
"...... ........
",'
w VOS' -100V. I RF9620. 9622
I I-

.I I I
/
100
'\. '- Cos,
> '"""
-15
I
VOS' ·60V
I /
"
VOS' ·40V
C'
rss

-20
-10 -20 -30 -40 -50 o 8 12 16 20
VOS. DRAIN·TO·SOURCE VOLTAGE (VOLTS) 1Ig. TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
·5
RDS(.n) MEASURED WITH CURRENT PULSE OF
2.0 ~s DURATION. INITIAL TJ' ~'C. (HEATING
EFFECT OF 2.0 I'S PULSE IS MIN,IMAL.l

-4

ts Jov I
,......""
I ...........

J
/ ..........
.........
'
...... ........... ...... ~:O.9621
IRF9622.9~

- / ./
....... ........ ......... VGS '-20V
·1
'",~
........
~
~ ,
o
·4 ·8 ·12 ·16 ·20 25 50 75 100 125 150
I D• ORAIN CURRENT (AMPERES) TC. CASE TEMPERATURE ('C)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
40

i ::
2:
o
~~
35

"" '~
\~
20
C
'"
w 15
\
~
ci
... 10 i~

20 40 60 80 100
Tc. CASE TEMPERATURE ('C)
Fig. 14 - Power Vs. Temperature Derating Curve
"
120
'1\
140

0-297
IRF9620, IRF9621, IRF9622, IRF9623 Devices

, I
r---
VARY tp TO OBTAIN " , II
REQUIRED PEAK IL
IL r , " El

VGS=~ IL4-----~----~~~~
I " I
~tp----.j
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

AOJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR O.U.T.
r------,
I
50n I 0-----+ TO SCOPE
I O.Oln
I I 50n HIGH FREQUENCY
L_ _ __ ...1 SHUNT

Fig. 17 - Switching Time Test Circuit

IG 10
CURRENT CURRENT
SHUNT -= SHUNT
\ l \ l \ r - -......J\IVI~-n +VOS

O-,---rr.
L.....J.r: 5mA
OUT

12V
BATTERY
-Vas
L------'~--~.........------_4II_----_o (ISO LATEO
SUPPLY)

Fig. 18 - Gate Charge Test Circuit

D-298
 PD-9.352

INTERNATIONAL RECTIFIERII\~RI

HEXFET@TRANSISTORS IRF9S3D
P-CHANNEL IRF9S31
2DDVOLT IRF9S32
POWER MDSFETs
IRF9S33
-200 Volt, 0.8 Ohm HEXFET Features:
TO-220AB Plastic Package • P-Channel Versatility
The HEXFET technology is the key to International Rectifier's • Compact Plastic Package
advanced line of power MOSFET transistors. The efficient geom- • Fast Switching
etry and unique processing of the HEXFET design achieve very low
on-state resistance combined with high transconductance and • Low Drive Current
extreme device ruggedness. • Ease of Paralleling
• No Second Breakdown
The P-Channel HEXFETs are designed for applications which re-
quire the convenience of reverse polarity operation. They retain all • Excellent Temperature Stability
of the features of the more common N-Channel HEXFETs such as
voltage control, freedom from second breakdown, very fast switch-
ing, ease of paralleling, and excellent temperature stability. The
Product Summary
P-Channel IRF9630 device is an approximate electrical comple-
ment to the N-Channel IRF620 HEXFET. Part Number VOS ROS(on) 10
IRF9630 -200V o.an -6.5A
P-Channel HEXFETs are intended for use in power stages where
complementary symmetry with N-Channel devices offers circuit IRF9631 -150V o.an -6.5A
simplification. They are also very useful in drive stages because of
the circuit versatility offered by the reverse polarity connection. IRF9632 -200V 1.2n -5.5A
Applications include motor control, audio amplifiers, switched IRF9633 -150V 1.2n -5.5A
mode converters, control circuits and pulse amplifiers.

~
CASE STYLE AND DIMENSIONS 3.4210.135)
'0'66(0'420)~
9.66(0.3801
2.54(0.100) 4.08(0.161)

10.66 (0.420)
MAX.
T*m~t TERM 3 - SOURCE

16.51(0.650)
14.23 (0.560)

+-~'F'"
)

::r d~'
5.33(0.210)
4.83(0190)
f D
13ECTION x-x
14.73 (0.580)
MAX.
t
Il
;,' 1.14(0.045)
iffi(ifii'f2j
T 1.14
1-------1
(0.045)
1.77(0.070) -l
2.92(0.115)
0.51(0.020)
1.15(0.045)
2.04(0.080)

ACTUAL SIZE Case Style T0-220AB

All Dimensions in Millimeters and (I nchesl

0-299
IRF9630, IRF9631, IRF9632, IRF9633 Devices

Absolute Maximum Ratings

Parameter IRF9630 IRF9631 IRF9632 IRF9633 Units

VOS. Drain - Source Voltage <D -200 -150 -200 -150 V

VOGR Drain - Gate Voltage IRGS = 1 Mill (j) -200 -150 -200 -150 V
10@TC-25°C Continuous Drain Current -6.5 -6.5 -5.5 -5.5 A
10@TC-l00oC Continuous Drain Current -4.0 -4.0 -3.5 -3.5 A
10M Pulsed Drain Current @ -26 -26 -22 -22 A
VGS Gate - Source Voltage ±20 V
PO@TC=25°C Max. Power Dissipation 75 ISee Fig. 14) W
linear Derating Factor 0.6 ISee Fig. 14) W/K
ILM Inductive Current, Clamped ISee Fig. 15 and 16) L = 100"H
A
-26 I -26 I -22 1 -22
TJ Operating Junction and
-55to 150 °C
T stg Storage Temperature Range
Lead Temperature 300 10.063 in. I 1.6mm) from case for lOs) °C

Electrical Characteristics @TC = 25°C (Unless Otherwise Specified)

Parameter Type Min. Typ. Max. Units Test Conditions
BVOSS Drain - Source Breakdown Voltage IRF9630
IRF9632
-200 - - V VGS = OV

IRF9631
IRF9633
-150 - - V 10 = -250"A

VGSlth) Gate Threshold Voltage ALL -2.0 - -4.0 V VOS = VGS' 10 = -250"A
IGSS Gate-Source Leakage Forward ALL - - -500 nA V GS - 20V
IGSS Gate-Source Leakage Reverse ALL - - 500 nA V GS - 20V
lOSS Zero Gate Voltage Drain Current
ALL
- - -250 "A VOS = Max. Rating, VGS = OV
- - -1000 "A VOS = Max. Rating x O.S, VGS = OV, TC = 125°C
1010n) On-State Drain Current ® IRF9630
-6.5 - - A
IRF9631
V OS } 1010n) x ROSlon) max.' V GS = -10V
IRF9632
IRF9633
-5.5 - - A

ROS(on) Static Drain-Source On-State IRF9630

- 0.5 O.S Il
Resistance ® IRF9631
V GS = -10V, 10 = -3.5A
IRF9632
- O.S 1.2 Il
IRF9633
9fs Forward Transconductance ® ALL 2.2 3.5 - Sill) VOS } 1010n) x ROSlon) max.' 10 - 3.5A
Ciss Input Capacitance ALL - 550 650 pF
VGS = OV, VOS = -25V, f = 1.0 MHz
Coss Output Capacitance ALL - 170 300 pF
See Fig. 10
C rss Reverse Transfer Capacitance ALL - 50 90 pF
tdlon) Turn·On Delay Time ALL - 30 50 ns V OO ~ 0.5 BV OSS ' 10 = -3.5A, Zo = 501l
tr Rise Time ALL - 50 100 ns See Fig. 17
tdloff Turn-Off Delay Time ALL - 50 100 ns (MOSFET switching times are essentially
independent of operating temperature.)
tf Fall Time ALL - 40 SO ns
Qg Total Gate Charge V GS = -15V, 10 = -S.OA, VOS = O.S Max. Rating.
ALL - 31 45 nC
(Gate-Source Plus Gate-Drain) See Fig. 18 for test circuit. (Gate charge is essentially
independent of operating temperature.)
Qgs Gate-Source Charge ALL - lS - nC

Qgd Gate-Drain ("Miller") Charge ALL - 13 - nC

LO Internal Drain Inductance - 3.5 - nH Measured from the Modified MOSFET

contact screw on tab symbol showing the
to center of die. internal device
ALL inductances.
- 4.5 - nH Measured from the
drain lead, 6mm 10.25
in.) from package to

LS Internal Source Inductance ALL - 7.5 - nH

center of die.

Measured from the

source lead, 6mm
10.25 in.) from
package to source
bonding pad.
$
Thermal Resistance
RthJC Junction·to·Case
RthCS Case-to-Sink Mounting surface flat, smooth, and greased.
RthJA Junction-to-Ambient Free Air Operation

0-300
 IRF9630, IRF9631, IRF9632, IRF9633 Devices

Source-Drain Diode Ratings and Characteristics

IS Continuous Source Current IRF9630 Modified MOSFET symbol
(Body Diode) IRF9631
- - -6.5 A
showing the integral
reverse pwN junction rectifier.
IRF9632
- - -5.5 A

~
IRF9633
ISM Pulse Source Current IRF9630
(Body Diode) ® IRF9631
- - -26 A

IRF9632
- - -22 A
IRF9633
VSD Diode Forward Voltage ® IRF9630
- - -6.5 V TC ~ 25°C, IS ~ -6.5A, VGS ~ OV
IRF9631
IRF9632
- - -6.3 V TC ~ 25°C, IS ~ -S.5A, VGS ~ OV
IRF9633
t" Reverse Recovery Time ALL - 400 - ns T J - 150°C, IF - -6.5A,dI F/dt - 100AII's
ORR Reverse Recovered Charge ALL - 2.6 - I'C TJ ~ 150°C, IF - 6.5A, dlF/dt - 100 AIl's
ton Forward Turn-on Time ALL Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD'

<DTJ ~ 25°C to 150°C. ® Pulse Test: Pulse width'; 300I'S, Duty Cycle'; 2%. ® Repetitive Rating: Pulse width limited
by max. junction temperature.
See Transient Thermal Impedance Curve (Fig. 5).

-15
-1£ll...-J--Jv- ..... -15

V If
,
-9V
.,.-
-12 lib J, 80 PU LsLEST -12 - 80 .,!PU LSE ~EST JI /
~
~
w
c:
VOS> 10(on) x ROS(on) max_ /II '(

~
~ -9
I ...- -7V w
"-
'">-
~ -9 J
TJ: 55 0 C VI /
>-
~c:
IIJ~ I
"'J 'I,
~ TJ: 25 0 C

~
z -6
V VGS: -6V
'"
=>
'-'
z -6
I
TJ: 125'C
::tJ jI
~
c l~ 10- I ;;:
'"c VI)
C
I C
r
-3

IlL i-"""" -r -3

I
If' L ,J1'1'
-10 -20 -30 -40 -50 -2 -4 -6 -8 -10
VDS, DRAIN·TO·SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics

-15
-100~_~.
= OPERATION IN THIS

~ r- 80 J PU LSE: TEST
AREA IS LIMITED
BY RDS(,n)
-
-
~1J~~~~ii[OJljnt1tJ
~;,F++tttt>"',,'o+--t--t*r+t*l-"""'+++++HfH
-12 _IRF9630'pl
-20

i'" -9
-9V

~ -BV
i,. -10 ~!RJ963~,! ' 101~s
100 ~s
~ ~

~ ",. _!7V-
>- >- -5 _IRF9632, 3
ffi
'" ~
'"
~
z -6 ~ ~ """'"
., '"=>'-'
z

~ ~6V_
~_--' ~~~~::I!~§II~I~10~lm~C;1
;;:
c: VGS:
c
..- =
=
~
E -1.0
TC : 25'C 100 ms
-3
-0.5 Tr 150'C MAX.
~5V_
_ RthJC 1.67 K/W O(-t-
~ -0.2 - SI NG LE PU LSE
II"""
~ 1-
-4V_ -0.1 I I I 1111
-2 -4 -6
-8 -10 -1.0 -2 -5 -10 -20 -50 -100 -200 -500
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS, ORAIN-TO-SOU RCE VOLTAGE (VOLTS)

Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area

0-301
 IRF9630, IRF9631, IRF9632, IRF9633 Devices

'""
15
u;
Z

::- 1.0
'""'""
wz
>=>
;::'" 0 0.5
'-'w 0.5 NOTES:
~~
OZ
w< 0.2
NO
-w
-',,-
<", 0.1
"'-
0.05
1--0.2
0.1 In.JL
'"
0< -' 1--0.02
z~~ 0.05 pO.Ol
'-'w SINGLE PULSE (TRANSIENT 1. DUTY FACTOR. 0 = :~
:;l"
~~ 1-+-+-+-+-+++-+·itERn IM7Dni) 111,+--+-+---+-+-++++1+--+-+--+-+-1-+1++-1--+-+ 2. PER UNIT BASE = R,hJC = 1.67 DEG. C/W.
0.02
""G
I-+-+-+-+-+++++t I +-1+-1H
III-HIIr--H-+- I I+--+-+--+-+-1-+1r-tt-t-+-+-+-+-++++++-H 3. TJM - TC = PDM Z,hJC(')'
~ 0.01
10-5 10-4 10-3 10-2 10-1 1.0 10
'l,saUARE WAVE PULSE DURATION (SECONDS)

Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Vs. Pulse Duration

7.00 -20
8~.' pulsE TEJT .n
VDS> 'O(on) x RDS(on) max. -10 .........: V
.,
15
ill
5.60

Tr-55OC
i'"
~
-5
/ /
§ ~
~ '~""
w
'-'
z
4.20
TJ = 25 0 C -2 / /
<
'""
'-' / '"
=>
'-'
z
-TJ=150 0 C
=>

~ T; = 125~C / ~J
~w
0
z -1.0 25 0 C
.,8 2.80
z
« /I V- '"

,
'" '"w -0.5
~
I I
'"~"
1.40 1/ E'"
I I
-0.2 -'- j
I I
-0.1
II ,/
-3 -6 -9 -12 -15 -2.0 -3.2 -4.4 -5.6 -6.8 -8.0
'0, DRAIN CURRENT (AMPERES) VSD, SOURCE·TD·DRAIN VOLTAGE (VOLTS)

Fig. 6 - Typical Transconductance Vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage

1.25 2.5

w
~ 2.0
«

",
", " In
iii
./
... V '" /'
z
°31.5
ww ,.
........ V ./
'-'N

~~
V V .,'" ,/
~~ 10 ./
", z~ .

~
o
,.,V vGS = -10V
g ", I
10 = -2.0A
I

~ 0.85 en
o
O. 5
o
i:; '"

0.75 o
-40 40 80 120 160 -40 40 80 120 160
TJ, JUNCTION TEMPERATURE (DC) TJ, JUNCTION TEMPERATU RE (DC)

Fig. 8 - Breakdown Voltage Vs. Temperature Fig. 9 - Normalized On-Resistance Vs. Temperature
0-302
 IRF9630, IRF9631, IRF9632, IRF9633 Devices
2000

J
GS = 0 I
j= 1 MHz
I I
1600 -
CIS' = Cgs + Cgd, Cd, SHO RTEO
Crss = Cgd

CO" = Cd, + Cgs Cgd

- ~
~ I
10= -8A
I I _r--
~
z
1200
Cgs + Cgd
~Cd,+Cgd -
'"
~
~ -5
\, FOR TEST CI RCUIT
SEE FIGURE 18

~
5 '">
~
;3 800 t-... ""
'"
'"=>
'- ~~
..........
",'

\ CtSS ~ -10
'"J; "\ ~
\\ ~

~~~
400 to VDS = -160V, IRF9630, 9632
\. .......
" .......... I <i>
vI I V~S=-l'OOV'/

--
~o" to
> -15
Crss ~DS = 40V'/
I I
-10 -20 -30 -40 -50 16 24 32 40
VOS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Qg' TOTAL GATE CHARGE (nC)
Fig. 10 - Typical Capacitance Vs. Drain·to·Source Voltage Fig. 11 - Typical Gate Charge Vs. Gate-to-Source Voltage
2_0 -10
RDS(on) MEASUREO WITH CURRENT PULSE OF
~ 2_0~, DURATION. INITIAL TJ = 25 0 C_ (HEATING
~ EFFECT OF 2.0 P' PU LSE IS MINIMALl
S
1.6 I -8
'"""«'" /
to
8l
'"
:3
""
'"
'"=>
1.2

VGS = - ¥ -
/
~
~
::;;
~

~
>--

'"=>
-6
r-
r- -- ..... r--...
l"-
--~ ~F9630, 9631

-"" -
'"6
~ 0_8 '"z -4 I RF9632, 963t;-..... t'-... -
>c-
z ,/ ...- ~
'"
-....i'-~
~
'"
VGS 20V
'" -2 "~
,
0.4

~
0

",''""
o
-5 -10 -15 -20 -25 25 50 75 100 125 150
ID' DRAIN CURRENT (AMPERES) TC, CASE TEMPERATURE (DC)

Fig. 12 - Typical On-Resistance Vs. Drain Current Fig. 13 - Maximum Drain Current Vs. Case Temperature
80

..
~
>--
70

60
"' '\i\.
'\r\.
~ 50
'"'">=
~ 40
iii
'\
c
!!!'"
~
30 '\
.P
20

10

20 40 60 80 100
TC, CASE TEMPERATURE (DC)
" 120
~
"\
140

Fig. 14 - Power Vs. Temperature Derating Curve

0-303
IRF9630, IRF9631, IRF9632, IRF9633 Devices

VARY tp TO OBTAIN
REOUIREO PEAK IL

VGS=~ ..,O_UT-..,c'-y

JL IL+----o----~~~
Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms

AOJUST RL
TO OBTAIN
SPECIFIED 10 RL

PULSE
GENERATOR
r------,
I
I
50U I o-----TO SCOPE
I 10 I 0.010
I 50U ~ HIGH FREOUENCY
L _ ___ .J SHUNT

Fig. 17 - Switching Time Test Circuit

IG 10
CURRENT CURRENT
SHUNT ":' SHUNT

O-,---rr.
L......-J~5mA
OUT

-V DS
'----'-------------0 SUPPLY)
(ISOLATED

Fig. 18 - Gate Charge Test Circuit

INTERNATIONAL RECTIFIER
WORLD HEADQUARTERS UNITED STATES. 233 KANSAS ST ., EL SEGUNDO, CA 90245. (213) 772-2000
I~iR
EUROPEAN HEADQUARTERS ENGLAND. HURST GREEN , OXTED , SURREY RH8 9BB . (08833) 3215 /4321
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