count.

vhd Tue Jun 26 10:38:47 2018

1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:32:27 06/26/2018
6 -- Design Name:
7 -- Module Name: count - RTL
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity count is
33 Port ( x : in STD_LOGIC;
34 clk : in STD_LOGIC;
35 y0 : out STD_LOGIC;
36 y1 : out STD_LOGIC);
37 end count;
38
39 architecture RTL of count is
40 TYPE states IS (A,B,C,D);
41 SIGNAL estado : states;
42
43 begin
44 process(clk)
45 begin
46 if rising_edge(clk) then
47 case estado is
48 when A =>
49 if x='1' then
50 estado <= B;
51 else
52 estado <= D;
53 end if;
54 when B =>
55 if x='1' then
56 estado <= C;
57 else

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count.vhd Tue Jun 26 10:38:48 2018
58 estado <= A;
59 end if;
60 when C =>
61 if x='1' then
62 estado <= D;
63 else
64 estado <= B;
65 end if;
66 when D =>
67 if x='1' then
68 estado <= A;
69 else
70 estado <= C;
71 end if;
72 when others =>
73 estado <= A;
74 end case;
75 end if;
76 end process;
77
78 y0 <= '0' when (estado=A or estado=C) else '1';
79 y1 <= '0' when (estado=A or estado=B) else '1';
80
81 end RTL;
82
83

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