Aa00003286 00001

ACCELERATING DETAILED SIMULATIONS OF AN HVDC SYSTEM
BASED ON MODULAR MULTILEVEL CONVERTERS IN A MULTI-CORE
ENVIRONMENT
by
XIAODAN WANG
B.S., Beijing Technology and Business University, 2010
A thesis submitted to the
Faculty of the Graduate School of the
University of Colorado in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2015
This thesis for the Master of Science degree by
Xiaodan Wang
has been approved for the
Electrical Engineering Program
by
Fernando Mancilla-David, Chair
Titsa Papantoni
Dan Connors
June 18, 2015
ii
Wang, Xiaodan (Electrical Engineering)
Accelerating Detailed Simulations of an HVDC System Based on Modular Mul-
tilevel Converters in a Multi-core Environment
Thesis directed by Professor Fernando Mancilla-David
ABSTRACT
The topology of the Modular Multilevel Converter (MMC) was introduced
in 2001. The MMC topology is well suited for the High Voltage Direct Current
(HVDC) system. The MMC-HVDC topology has several advantages over other
topologies: (i) it is based on simple converter cells, (ii) it has easy voltage
and current scaling, (iii) it features distributed capacitive energy storage, (iv) it
offers straightforward protection schemes, (v) it has low switching frequency and
losses. However, the simulation speed of a detailed MMC model in an HVDC
system is slow due to the computational burden.
In this thesis, with the help of PSCAD/EMTDC, a new approach in a
multi-core CPU environment has been implemented to speed up the simulations
of the HVDC system based on the MMC topology. This approach is evaluated
by comparing results with a single-core average model, a single-core detailed
model and a eight-core detailed model. This thesis also includes an analysis
selecting the best sorting algorithm.
iii
The form and content of this abstract are approved. I recommend its publication.
Approved: Fernando Mancilla-David
iv
DEDICATION
This thesis is dedicated to my family and my girlfriend who have supported me

all the way since the beginning of my studies. They provide me with a great
source of motivation and inspiration. Finally, this thesis is dedicated to all those
who believe that knowledge is power.
v
ACKNOWLEDGMENT
I would like to express my deepest gratitude to my advisor, Professor Fer-

nando Mancilla-David, for his excellent guidance, care, patience, and for pro-
viding me with an excellent environment for doing research.
I greatly appreciate Professors Titsa Papantoni, and Professor Dan Con-

nors for forming part of my dissertation defense committee. Finally, I would
like to thank my family; they were always there cheering me up and stood by
me through the good and bad times.
I also want to thank Phd student Miguel Carrasco for his tips on my simu-
lation modeling and thesis arrangement.
vi
CONTENTS
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Chapter
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Average model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Detailed model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Rectifier and inverter control . . . . . . . . . . . . . . . . . . . . . 14
3.2 Leg energy control . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 Control of the average model . . . . . . . . . . . . . . . . . . . . 18
3.3.2 Control of the detailed model . . . . . . . . . . . . . . . . . . . . 19
4. Sorting algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 Insertion sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Quick sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Merge sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4 Performance test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4.1 MATLAB based tests . . . . . . . . . . . . . . . . . . . . . . . . 27
vii
4.4.2 PSCAD/EMTDC based tests . . . . . . . . . . . . . . . . . . . . 28
5. Implementation of the detailed model in a multi-core environment . . 34
6. Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1 Test case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.1 Average model test in the one-core CPU environment . . . . . . . 40
6.1.2 Detailed model test in the one-core CPU environment . . . . . . 42
6.1.3 Detailed model test in the eight-core CPU environment . . . . . . 44
6.2 Test case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2.1 Average model test in the one-core CPU environment . . . . . . . 46
6.2.2 Detailed model test in the one-core CPU environment . . . . . . 48
6.2.3 Detailed model test in the eight-core CPU environment . . . . . . 50
6.3 Test case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4 Comparative evaluation . . . . . . . . . . . . . . . . . . . . . . . . 52
6.5 Simulation speed versus SMs number . . . . . . . . . . . . . . . . . 53
7. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8. Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Appendix
A. FORTRAN codes for the detailed model . . . . . . . . . . . . . . . . 60
viii
FIGURES
Figure
2.1 Schematic of the HVDC back–to–back system. . . . . . . . . . . . . 3
2.2 (a) Structure of a SM; (b) series connection of a number of SMs
constituting an arm; (c) converter composed of three legs – one for
each phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Overview of the HVDC system in PSCAD. . . . . . . . . . . . . . . 6
2.4 Average model arm. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Detailed model arm. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Submodule at on-state or off-state. . . . . . . . . . . . . . . . . . . 11
2.7 The MMC with average or detailed arm. . . . . . . . . . . . . . . . 12
3.1 PSCAD control panel. . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Overview of the control strategy. . . . . . . . . . . . . . . . . . . . 14
3.3 Current controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Leg energy controller for each phase. . . . . . . . . . . . . . . . . . 16
3.5 Per-phase modulation index computation. . . . . . . . . . . . . . . 17
3.6 Arm in the average model. . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Arm in the detailed model. . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Different stairs-V comparison with sinusoidal-V. . . . . . . . . . . . 21
3.9 Flowchart of the voltage balancing algorithm. . . . . . . . . . . . . 23
4.1 PSCAD based algorithms validation test input plot. . . . . . . . . . 29
4.2 PSCAD based algorithms validation test output. . . . . . . . . . . 29
ix
4.3 PSCAD based algorithms validation test switching array. . . . . . . 30
4.4 PSCAD based algorithms validation test trigger. . . . . . . . . . . 30
4.5 PSCAD based algorithms validation test output with N–check. . . 31
4.6 PSCAD based algorithms validation test switching array. . . . . . . 31
5.1 CPU monitor in task manager for ENI. . . . . . . . . . . . . . . . . 34
5.2 CPU monitor in task manager for single core. . . . . . . . . . . . . 35
5.3 ENI detailed model. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 ENI circuit in Part1. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 ENI circuit in Part2. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 WEST MMC active power and reactive power. . . . . . . . . . . . 41
6.2 EAST MMC active power and reactive power. . . . . . . . . . . . . 41
6.3 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4 Synthesized voltage Va Vb Vc. . . . . . . . . . . . . . . . . . . . . 42
6.7 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.11 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.12 Synthesized voltages Va Vb Vc. . . . . . . . . . . . . . . . . . . . . 45
6.13 Voltage of 12 SMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
x
6.16 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.20 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.24 DC link Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.25 Synthesized voltages Va Vb Vc. . . . . . . . . . . . . . . . . . . . . 51
6.26 Synthesized voltages Va Vb Vc(Nsm=36). . . . . . . . . . . . . . . 52
6.27 Synthesized voltages Va Vb Vc(Nsm=108). . . . . . . . . . . . . . 52
6.28 Transmission line and π-structure. . . . . . . . . . . . . . . . . . . 53
6.29 Simulation time curve. . . . . . . . . . . . . . . . . . . . . . . . . . 55
xi
TABLES
Table
2.1 Design parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Phase voltage in terms of N. . . . . . . . . . . . . . . . . . . . . . . 22
4.1 MATLAB based algorithms speed test results. . . . . . . . . . . . . 28
4.2 PSCAD based algorithms validation test input. . . . . . . . . . . . 28
4.3 PSCAD based algorithms speed tests input arrays. . . . . . . . . . 32
4.4 PSCAD based algorithms speed test results. . . . . . . . . . . . . . 33
6.1 Simulation time versus Submodule number on each arm. . . . . . . 54
xii
1. Introduction
A new High Voltage Direct Current (HVDC) transmission technology based
on the Modular Multilevel Converter (MMC) topology has been introduced in
recent years. In this topology, the converter arm behaves as a controllable
voltage source with a high number of possible discrete voltage steps, which
together can produce close to a true sinusoidal voltage in the AC terminal [1].
MMC topology enables using a smaller switching frequency to reduce converter
losses and eliminates the filter requirements by using a significant number of
levels per arm [2]. Nowadays, there are five MMC-HVDC projects in progress
in Europe [3][4].
In the following thesis, the basics of the MMC-HVDC technology is ex-
plained in Section 1; the power stage design is shown in Section 2; the control
strategies are shown in Section 3; the sorting algorithm is shown in Section 4;
the multi-core simulation approach is shown in Section 5; the simulation results
are shown in Section 6; the conclusions are shown in Section 7; the future work
is shown in Section 8.
The advantages of the MMC-HVDC technology are summarized in [5, 6, 7]:
• AC voltages can be adjusted in very fine increments and a DC voltage with
very little ripple can be achieved, this minimizes the level of generated
harmonics and in most cases completely eliminates the need for AC filters.
• The low switching frequency of the individual semiconductors results in
very low switching losses. Total system losses are therefore relatively low,
1
and the efficiency is consequently higher than existing two– and three–level
solutions.
• Due to the elimination of additional components such as AC filters and
their switchgear, high reliability and availability can be achieved.
• Through a highly modular construction both in the power section and
in control and protection, the system is very scalable, (i.e. conveniently
adaptable to any required power and voltage ratings.)
• With respect to later provision of spare-parts, it is easy to replace existing
components by state-of-the-art ones, since the switching characteristics
of each power module are determined independently of the behavior of
the other power modules. This is an important difference to the direct
series-connection of semiconductors as in the two-level technology where
nearly identical switching characteristics of the individual semiconductors
are mandatory.
• Independent control of active and reactive power. As a consequence, no
reactive power compensation equipment is needed at the station.
• Possibility to connect the system to a “weak” ac network or even to one
where no generation source is available and the short-circuit level is very
low.
• It can provide a variety of ancillary services to the interconnected ac sys-
tems, such as harmonic and unbalanced voltage compensation, flicker elim-
ination, etc.
2
2. Power stage
In a back-to-back configuration, two converters are connected by a DC link
capacitor, as shown in Figure 2.1. Each converter can independently synthe-
size a sinusoidal voltage at its terminals. These voltages can be defined by
their amplitudes (V̂1 , V̂2 ) and phase angles (θ1 , θ2 ). Active power injections
depend mainly on phase angles, while reactive power injections depend on the
amplitudes of the synthesized voltages. The MMC topology allows independent
control of the voltage amplitudes V̂1 and V̂2 . Therefore, reactive power injections
on both sides can be controlled independently. However, phase angles (θ1 , θ2 )
need to be controlled in such a way that the active power being transmitted
by one converter equals the active power transmitted by the other converter in
steady state to keep the energy of the DC link constant.
V1 V2
MMC MMC
1 2
AC System 1 AC System 2
θ1 θ2
V̂1 V̂2
Figure 2.1: Schematic of the HVDC back–to–back system.
The basic component of the MMC converter is a simple half bridge with a
capacitor called power submodule (SM), as shown in Figure 2.2(a). With the
two power electronic switches, an SM can generate two output voltages, zero, or
3
the voltage of the capacitor. An SM has bidirectional current capability. The
capacitor can be charged or discharged depending on the direction of the arm
current [8][9]. The series connection of a number of SMs constitutes an arm, as
shown in Figure 2.2(b). In the converter there are three legs, one for each phase.
A converter leg is composed of an upper and a lower arm. Figure 2.2(c) shows
the structure of the converter. The number of the output steps depends on the
number of SMs available in each arm. By connecting enough SMs in series, no
AC filters will be necessary. In the TransBay Cable Project, Siemens used more
than 200 SMs per converter arm. As a result, the synthesized voltage profile is
very close to sinusoidal [1].
Leg
Arm
SM SM Arm Arm Arm
phase a phase b phase c
SM Arm Arm Arm
(a) (b) (c)
Figure 2.2: (a) Structure of a SM; (b) series connection of a number of SMs
constituting an arm; (c) converter composed of three legs – one for each phase.
2.1 Design parameters
Figure 2.3 shows the overview of the HVDC system implemented in PSCAD.
Each converter consists of three legs. In turn, each leg is composed by two arms,
and each arm is electrically connected with a certain number of SMs in series.
Since the MMC topology belongs to the VSC family, a DC link capacitor is
4
needed. Both converters are connected to the grid through a circuit breaker.
The initial state of both breakers are open, and they will close after all SMs are
fully charged. The nominal power is 110 MW. The selected DC voltage is ±200
kV. The number of SMs per arm was chosen to be 36 by heuristics because there
is a trade of between the computational complexity and the harmonics content
on the synthesized voltage.
5
bus2
Ibus Main : C... Main : C...
East AC System
Voltage west Voltage east
West AC System 1.5 1.5
A A
BRK
0.1132 [H] V V 0.2598 [H]
V F Ph Ph F V
R=0
V
200.0
0.0
0.0
60.0
60.0
10 [uF]
0.1 0.1
1 1
DC Link
Timed
umec West MMC DC_1 Breaker DC_1
East MMC umec Voltage east
6
Vdc Logic
#1 #2
AC BRK #2
AC #1
* Closed@t0 *
DC_2 DC_2
Voltage west
BRK
Q_ref P_ref P_ref Q_ref
R=0
230.0
230.0
V
West Transformer 200.0 East Transformer

Qref_West Pref_West Pref_East Qref_East
10 [uF]
Figure 2.3: Overview of the HVDC system in PSCAD.

The primary side of the transformer is rated at 230 kV with a grounded Wye
connection and the secondary side is rated at 180 kV with a delta connection,
considering the DC link voltage ±200 kV. A leakage reactance of 10% is selected
as a typical value of this rated power.
The insulated-gate bipolar transistors (IGBTs) in each SM are selected ac-
cording to their voltage blocking and maximal current conduction capabilities.
The voltage blocking capability needs to reach Vb=400/36=11.1 kV and a max-
imum forward current of 1.2 kA. The resistance of the selected IGBT is 1 mΩ,
therefore, the total resistance of each arm is 36 mΩ. The capacitance of each
SM may be obtained by the following equation [10]:
2SEMMC
C=
6Narm VC2
where S is the nominal power of the converter, EMMC is the capacitor’s storage
energy in [KJ/MVA], Narm is the number of the SMs in each arm, and VC is the
SM nominal voltage.
kJ
With a storage energy of 331 MVA [5], combining all the known parameters
in the equation, the capacitance is found to be 16.4 mF. The arm inductance,
LS , has been selected as 15% of the system’s base impedance, as shown in the
following equation [10].

Vac2
Zs =
S
Ls = 0.15Zs = 0.1172H
All system parameters are summarized in the Table 2.1.
7
Table 2.1: Design parameters.
West AC System
Bus Voltage East (kV) 230
Thevenin Equivalent Impedance (H) 0.1132
West Transformer
Primary Voltage (kV) 230 (Y)
Secondary Voltage (kV) 180 (∆)
Power Rating (MVA) 133
Leakage Reactance (pu) 0.1
West MMC
Number of SMs per arm 36
Number of IGBTs per SM 2
IGBT blocking capability (kV) 15
IGBT maximal forward current (kA) 3
IGBT resistance (mΩ) 1
SM Capacitor (mF) 14.6
Arm inductance (H) 0.1172
DC Link Capacitor
Capacitance (µF) 0.5
Rated voltage (kV) 400
East MMC
Number of SMs per arm 36
Number of IGBTs per SM 2
IGBT blocking capability (kV) 15
IGBT maximal forward current (kA) 3
IGBT resistance (mΩ) 1
SM Capacitor (mF) 14.6
Arm inductance (H) 0.1172
East Transformer
Primary Voltage (kV) 230 (Y)
Secondary Voltage (kV) 180 (∆)
Power Rating (MVA) 133
Leakage Reactance (pu) 0.1
East AC System
Bus Voltage West (kV) 230
Thevenin Equivalent Impedance (H) 0.2598
2.2 Average model
To validate the detailed model simulations, the average model is imple-
mented first. In the average model, each arm is presented by an equivalent
8
voltage source, and the calculation is shown in Section 3. The series resistance
and inductance in each average arm is 36 mΩ and 0.117 H, respectively. One
arm in the average model is shown in Figure 2.4.
Average Vout
R
Arm V-calculated
Nin
Figure 2.4: Average model arm.
2.3 Detailed model
In the detailed model, each arm has a series connection of a certain number
of SMs. The control on the SMs will be explained in Section 3. One arm in the
detailed model is shown in Figure 2.5.
9
L
Detailed Vout SM
SM Controls
Arm
Nin
Figure 2.5: Detailed model arm.
It is worth noting that the arm inductance and resistance of both models
are same. In the detailed model, the diodes and the IGBTs have the same
resistance. As shown in Figure 2.6, in both on and off states of the SMs, the
arm resistance remains constant, (i.e. the total resistance is a constant 36 mΩ).
10
Capacitor off-state Capacitor on-state
C C
C C
Figure 2.6: Submodule at on-state or off-state.
Finally, the WEST and EAST MMC are modified with either average or
detailed arm, as shown in Figure 2.7.
11
DC_1
Vout Vout Vout
MMC MMC MMC
Vap_eq Vbp_eq Vcp_eq
average average average
or or or
Nin Nin Nin
detailed detailed detailed
Np_a Np_b Np_c
arm arm arm
P = 0.0001059
Q = -0.001344
BRK
A
AC V
Vout Vout Vout

MMC MMC MMC
Van_eq Vbn_eq Vcn_eq
average average average
or or or
Nin Nin Nin
detailed detailed detailed
Nn_a Nn_b Nn_c
arm arm arm
DC_2
Figure 2.7: The MMC with average or detailed arm.
12
3. Control scheme
The overall operation of the converters is directed by the control panel as in
Figure 3.1. The references can be set in this control panel, including the active
and reactive power of the rectifier side, the reactive power of the inverter side
and the active power flow direction.
Figure 3.1: PSCAD control panel.
Depending on the active power flow direction, one of the converter stations
will act as a rectifier and the other one will act as an inverter. For instance, if
power is flowing from the WEST MMC to the EAST MMC, the east converter
will act as the inverter and the west converter will act as the rectifier [11].
13
Rectifier control Wi
i = a, b, c
Leg energy controller
udiff i 1
Reactive power i = a, b, c
Qrect Qref rect Iq ref
reference generator
Power–to–current
transformation Current controller Modulation
Control panel
Active power Pref Ei Np i

P P Id ref
reference generator i = a, b, c Nn i
i = a, b, c
Vdc Active power Pref V

400 kV
ref Id ref
reference generator
Power–to–current
transformation Current controller Modulation
Reactive power Qref inv Ei Np i
Qinv Iq ref
reference generator i = a, b, c Nn i
udiff i 1
i = a, b, c
Leg energy controller i = a, b, c
Wi
Inverter control i = a, b, c
Figure 3.2: Overview of the control strategy.
Figure 3.2 shows the overall control strategy. Through the ABC-to-DQ
transformation, the active and reactive power references are transformed to DQ
current references an fed to the current controller. The current and energy
controllers then work together to generate the modulation index, N , for each
arm in both converters [12] [13].
3.1 Rectifier and inverter control
The difference between the rectifier and the inverter is the active power
reference generator. In the rectifier, the active power reference and the reactive
power reference are coming directly from the control panel. In the inverter, the
reactive power reference is coming from the control panel, however, the active
power reference is generated by the DC link voltage control.
Following the active and reactive power generators, the power references are
transferred to current references with the ABC-to-DQ transfer. The ABC-to-DQ
14
transformation is based on the following equations:
3
P = (vd id + vq iq ),
2
3
Q = (−vd iq + vq id ).
2
The Phase Lock Loop(PLL) forces vq = 0, which will simplify the above
equation set to be:

3
Pref = vd Id ref ,
2
3
Qref = − vd Iq ref .
2
Following the power-to-current transformation, reference current and actual
current are compared to generate an error, and the error is driven to zero with
the help of two decoupled compensators. Aiagram of this process is shown in
Figure 3.3. The output signals of the current controller, Ea, Eb and Ec, will be
used as input signal in the modulation in Section 3.3.

wL
Iq
*
P
Idref Ed
Pref Ea
DQ
I
1.5 Vd Id Vd Eb
to
Vq
P
Iqref Eq ABC Ec
Pref
I
-1.5 Vd Iq Id
*
wL
Figure 3.3: Current controller.
15
3.2 Leg energy control
The leg energy control is built to balance the three phase voltages and reduce
the circulating current. The energy on each leg is a function of the upper and
lower arm voltages. In other words, the leg energy will be stable if the leg voltage
is fixed, and the three phases will be balanced.
1
Dif fi = (Wi ref − Wi )(Ki + Kp ) i = a, b, c,
s
where Wi = Vip2 eq + Vin2 eq i = a, b, c.
The leg energy controller is shown in Figure 3.4.
P
Diff
320000
Vup 2
X I
Vlow W
2
X
Figure 3.4: Leg energy controller for each phase.
3.3 Modulation
The instantaneous voltage of each arm is determined by the modulation
index N. In the average model, N is in the range of 0 to 1. When N equals 0,
16
all SMs are disconnected, and when N equals 1, all SMs are connected. For the
upper and lower arm in each leg, the modulation indexes are computed as:

Vdc 1
Niup = − Ei − Udiff i i = a, b, c
2 Viu eq

Vdc 1
Nilow = + Ei − Udiff i i = a, b, c
2 Vil eq
where Vdc is the DC link voltage, Ei is AC terminal voltage to be synthesized
which is determined by the current controller, and Udiff i is the output of the
leg energy controller. At any point in time the sum of the upper and lower
modulation indexes in an arm is one:
Nup + Nlow = 1
A diagram of the modulation index computation for one leg is shown in
Figure 3.5.
Diff-a
Vdc
* Na-up
2 Ea Va-up N N
Diff-a Quantizer
Vdc
* Na-low
2 Ea Va-low N N
Figure 3.5: Per-phase modulation index computation.
17
3.3.1 Control of the average model
The arm equivalent capacitance is:
CSM
Ceq =
n
and the arm voltages are:
Viup = Varm iup Nup i i = a, b, c
Vilow = Varm ilow Nlow i i = a, b, c
where Varm iup and Varm ilow are the equivalent voltages of the upper arm and the
lower arm. Combining the three equations above, the Varm iup and Varm ilow are:
Iiup
Z
Varm iup = Ceq
dt i = a, b, c
Nupi
Iilow
Z
Varm ilow = Ceq
dt i = a, b, c
Nlowi
Based on these equations, the average arm can be modeled as shown in Figure
3.6.
18
Nin * I-equiv
L
I
Average Vout R I-equiv Vout

1/sT
Varm C
V-equiv
Arm
Nin
* Vout
I
Nin
Figure 3.6: Arm in the average model.
3.3.2 Control of the detailed model
The detailed model arm is shown in Figure 3.7.
19
Nin
L
Delay
T(1)
Detailed Vout SM V(1)
T(2)
SM V(2) Sorting
T(3) Varray Algorithm
SM V(3)
Arm and
Nin T(N)
SM V(N) Switching
Tarry
I
Vout
Figure 3.7: Arm in the detailed model.
In the detailed model, the modulation index needs to be multiplied by the
number of the SMs in each arm. As a result, the modulation index of the detailed
model is an integer in the range of 0 to 36. In general, the number of the levels
is equal to one plus the number of the SMs. It is also worth noting that the
number of SMs has to be even, otherwise the 0 kV level cannot be achieved.
20
Figure 3.8: Different stairs-V comparison with sinusoidal-V.
Three voltage curves with different number of SMs (N) per arm (N=4, N=8,
N=12) are generated as shown in Figure 3.8. It is apparent that as the number
increases, the voltage profile becomes closer to sinusoidal. In the detailed model
simulations, the magnitude of the stepwise curve equals the number of the SMs
in each arm [14].
Assuming there are N SMs in each arm, to satisfy Kirchhoff’s Voltage Law
(KVL), the synthesized voltage on phase A needs to fit both upper arm’s and
lower arm’s voltage drop, as in the following equations:
Va = Vdc /2 − Nupperarm Vsm
Va = −Vdc /2 + Nlowerarm Vsm
N = Nupperarm + Nlowerarm
Solving the above equations set, Vsm equals Vdc/N. Assuming four SMs, Va
would take values as shown in Table 3.1.
21
Table 3.1: Phase voltage in terms of N.
N(upper) N(lower) Va(upper KVL) Va(lower KVL)
4 0 Vdc /2 − 4Vsm = −Vdc /2 −Vdc /2 + 0Vsm = −Vdc /2
3 1 Vdc /2 − 3Vsm = −Vdc /4 −Vdc /2 + 1Vsm = −Vdc /4
2 2 Vdc /2 − 2Vsm = 0 −Vdc /2 + 2Vsm = 0
1 3 Vdc /2 − 1Vsm = Vdc /4 −Vdc /2 + 3Vsm = Vdc /4
0 4 Vdc /2 − 0Vsm = Vdc /2 −Vdc /2 + 4Vsm = Vdc /2
Va is in the range of -Vdc/2 to +Vdc/2 by steps of Vdc/4. However, the
size of every step may be different without control. To equalize all the steps,
the SMs voltage balancing algorithm is introduced.
In the following discussion, the term ”ON” signifies that one SM gives the
Capacitor voltage (Vc) as the output voltage, and ”OFF” signifies that a sub-
module gives 0 kV as the output voltage. The number of SMs on and off is in
the range of 0 to 36. Also, N(t) refers to the number of the submodules in the
”ON” state in the upper arm of one phase leg at time ”t”.
The SMs voltages are balanced by turning ON or OFF SMs depending on the
current flow directions. N(t) SMs with lower capacitor voltages will be turned
ON when the arm current flow is charging the capacitors, and OFF when the
arm current flow is discharging them. A flowchart of SMs voltage balancing is
shown in Figure 3.9 [15] [16].
22
Voltage Array Indices Array
Voltages and Indices Matrix
Sorting with a
selected algorithm Sorting process
Sorted Matrix, ascending order
Current .GE. 0 ?
Yes No
Select N count SMs Select N count SMs
with low voltage with low voltage
Switching Array Switching process
Figure 3.9: Flowchart of the voltage balancing algorithm.
There are three inputs: (i) N(t), (ii) Id(current direction) and (iii) V(array,
for all SMs). The voltage balancing controller will receive data from all the
inputs during the simulations, then, the data of V(array) will be listed in a table
along with their labels VLB(array). Next, the table of V(array) and VLB(array)
will be sorted into ascending sequence, and finally, the switching signals T(array)
will be generated based on N(t), I, and the sorted table generated in step three
of Figure 3.9. Combined with the voltage balancing control, the detailed arm is
built as shown in Figure 3.7.
23
Also, to accelerate the simulation, the sorting process will only be triggered
when N(t) changes [15]. This will reduce the sorting process’ frequency and the
results will be acceptable if the SMs number is high enough to avoid using filters.
The process of checking whether N(t) changes in the processing time interval
will be notified as ”N-check” in this thesis.
24
4. Sorting algorithm
The sorting algorithm has been selected from three candidates in order to
improve the simulation speed. Three sorting algorithms are evaluated both in
MATLAB and PSCAD. The computing time is matching the computational
complexity (big O notation) in terms of the size of the list(N). The candidate
sorting algorithms are:
• Insertion Sort
• Quick Sort
• Merge Sort.
4.1 Insertion sort
Insertion sort is an iterative algorithm which removes one element from the
input data each iteration and adds it to the correct lovation in a sorted output
list. This process repeats until no input elements remain [17].
The best case input is an array that is already sorted. In this case insertion
sort has a linear running time O(n). During each iteration, the first remaining
element of the input is only compared with the right-most element of the sorted
subsection of the array.
The simplest worst case input is an array sorted in reverse order. The set of
all worst case inputs consists of all arrays where each element is the smallest or
second-smallest of the elements before it. In these cases every iteration of the
25
inner loop will scan and shift the entire sorted subsection of the array before
inserting the next element. This gives insertion sort a quadratic running time
O(n2 ).
The average case is also quadratic, which makes insertion sort impractical
for sorting large arrays. However, insertion sort is one of the fastest algorithms
for sorting very small arrays, even faster than quick sort. In fact, good quick
sort implementations use insertion sort for arrays smaller than a certain thresh-
old, also when arising as subproblems; the exact threshold must be determined
experimentally and depends on the machine, but is commonly around ten [18].
4.2 Quick sort
Quick sort is a divide and conquer algorithm. Quick sort first divides a
large array into two smaller sub-arrays: the low elements and the high elements.
Quick sort then recursively sorts the sub-arrays [19] [20].
The steps of quick sort are:
1. Pick an element as a pivot from the array. 2. Reorder the array so that
all elements with values less than the pivot are placed before the pivot, while all
elements with values greater than the pivot are placed after it (equal values can
go either way). After this partitioning, the pivot is in its final position, which
is called the partition operation. 3. Recursively apply the above steps to the
sub-array of elements until the sub-array contains one element.
Quick sort’s divide-and-conquer formulation makes it amenable to paral-
lelization using task parallelism. The partitioning step is accomplished through
the use of a parallel prefix sum algorithm to compute an index for each array
element in its section of the partitioned array. Given an array of size n, the
26
partitioning step performs O(n) work in O(logn) time and requires O(n) addi-
tional scratch space. After the array has been partitioned, the two partitions
can be sorted recursively in parallel. Assuming an ideal choice of pivots, parallel
quick sort sorts an array of size n in O(nlogn) work in O(log 2 n) time using O(n)
additional space.
4.3 Merge sort
Merge sort is an O(nlogn) comparison-based sorting algorithm. Merge sort
is also a divide and conquer algorithm used in computer science [19] [20].
The steps of merge sort are:
1. Divide the unsorted list into n sublists halfway, until each list containing
1 element (a list of 1 element is considered sorted). 2. Repeatedly merge sublists
to produce new sorted sublists until there is only 1 sublist remaining. This will
be the sorted list.
4.4 Performance test
The sorting algorithms are tested both in MATLAB and PSCAD/EMTDC.
Since the tic-toc function is available in MATLAB, a small arbitrarily time
scale is enough for the MATLAB based tests. However, the tic-toc function is
not available in PSCAD, so a longer period of time is necessary to make the
stopwatch reliable for the PSCAD based tests.
4.4.1 MATLAB based tests

Using tic-toc function in MATLAB, these three algorithms computing time
are compared with same input array as shown in Table 4.1.
27
Table 4.1: MATLAB based algorithms speed test results.
Algorithms time1(s) time2(s) time3(s) time4(s) time5(s)

Insertion Sort 0.0531 0.0541 0.0553 0.0562 0.0555
Quick Sort 0.0209 0.0216 0.0213 0.0204 0.0212
Merge Sort 0.0327 0.0351 0.0345 0.0361 0.0342
The quick sort approach is the optimal choice. MATLAB also gives hints
for the sorting algorithm choice in SIMULINK. When the number of elements
in an array is less than or equal to 32, MATLAB recommends the insertion sort,
and when it is greater than 32, quick sort is recommended.
4.4.2 PSCAD/EMTDC based tests

In this section, the three sorting algorithms are tested in PSCAD. The first
test shows how these sorting algorithms work to speed up the voltage balancing
control. To make the sorting process occur frequently, all the six elements of the
input array (to represent a voltage array) are defined to be different from each
other at all times as shown in Table 4.2.
Table 4.2: PSCAD based algorithms validation test input.
Elements Name Elements(Voltage)

V(1) V = 3 sin(2ωt + 60) + 10
V(2) V = 3.5 sin(2ωt + 75) + 10
V(3) V = 2 sin(2ωt + 40) + 10
V(4) V = sin(2ωt + 70) + 10
V(5) V = sin(2ωt + 20) + 10
V(6) V = 2.2 sin(2ωt + 118) + 10
Selecting time interval between 0s and 0.035s, the input Voltage array is
shown in Figure 4.1.
28
Figure 4.1: PSCAD based algorithms validation test input plot.
As mentioned in Section 3, without the N-check, the sorted indices will be
as shown in Figure 4.2. Combined with the direction of the arm current flow,
the switching signal T(6) will be as shown in Figure 4.3. In this test, the current
direction, Id, is set to be constantly positive. From T(1) to T(6), again, they
are only switched when N changes. N also decides the number of the SMs to be
ON or OFF. For a positive Id in this test, the SMs with lower voltage will be
switched ON.
Figure 4.2: PSCAD based algorithms validation test output.
29
Figure 4.3: PSCAD based algorithms validation test switching array.
The N-check is realized by delaying N for one simulation time step, and then
comparing N with Ndelay. The sorting process will only be triggered if they are
different, as in Figure 4.4. The sorted indices with N-check will be as shown in
Figure 4.5. The switching signals with N-check will be as shown in Figure 4.6.
Figure 4.4: PSCAD based algorithms validation test trigger.
30
Figure 4.5: PSCAD based algorithms validation test output with N–check.
Figure 4.6: PSCAD based algorithms validation test switching array.
Both the quick sort and the merge sort are divide-and-conquer algorithms
and therefore need to be programmed with recursive subroutines. However, the
FORTRAN compiler inside of PSCAD cannot accept recursive subroutines in
programmed blocks. The solution of the recursive programming is to use the
”Additional Source files” and link the files to simulations. In a source file, the
quick sort and the merge sort subroutines can be programmed recursively. The
quick sort and the merge sort subroutines can be ”called” by the programmed
block in PSCAD, which introduces additional communication time. Therefore,
31
a PSCAD based algorithm speed test is necessary.
Table 4.3: PSCAD based algorithms speed tests input arrays.
Index Array1 Array2 Array3

1 3 sin(2ωt + 60) + 10 3 sin(2ωt + 60) + 10 36
2 3.5 sin(2ωt + 75) + 10 3.5 sin(2ωt + 75) + 10 35
3 2 sin(2ωt + 40) + 10 2 sin(2ωt + 40) + 10 34
4 sin(2ωt + 70) + 10 sin(2ωt + 70) + 10 33
5 sin(2ωt + 20) + 10 sin(2ωt + 20) + 10 32
6 2.2 sin(2ωt + 118) + 10 2.2 sin(2ωt + 118) + 10 31
7 7 30 30
8 8 29 29
9 9 28 28
. . . .
. . . .
. . . .
36 36 1 1
Three sorting algorithms are tested with three different input arrays as in
Table 4.3. Array1 requires least effort to sort (because most of the array is
already in ascending order), and Array3 requires most effort to sort (because it
is in opposite order). Setting the time step to 50 µs, and plot step to 250 µs, the
time to complete a 100 s simulation for three sorting algorithms is summarized
in Table 4.4.
32
Table 4.4: PSCAD based algorithms speed test results.
Algorithms Simulation Simulation Simulation
time(s) for time(s) for time(s) for
Array1 Array2 Array3

Insertion Sort 53.94 54.17 66.66
Merge Sort 55.69 52.40 54.14
Quick Sort 64.41 54.38 64.41
Regarding 36 elements, Table 4.4 shows that: (i) the insertion sort is the
best for a less-effort sorting situation, (ii) the quick sort speed is not stable,
because it is influenced by the pivot selection too much. In this test, the first
element is selected as the pivot, (iii) the merge sort has good speed in all three
situations.
Therefore, the merge sort is the optimal selection when the communication
time is considered.
33
5. Implementation of the detailed model in a multi-core
environment
Other than the selection of the sorting algorithm, a new approach is imple-
mented to accelerate the simulation on the software side. The new approach is
called Electrical-Network-Interface(ENI) and it’s from PSCAD/EMTDC.
The concept of the ENI approach splits the project into pieces, and the
computational burden from every piece is assigned to each CPU core of the
computer. As a result, the overall CPU usage can reach 100%, as shown in
Figure 5.1. For a typical simulation, only two cores will do the processing,
so the CPU usage normally acts as shown in Figure 5.2 on a eight-core CPU
computer. There are two requirements for ENI: 64-bit operation system and a
multi-core CPU.
Figure 5.1: CPU monitor in task manager for ENI.
34
Figure 5.2: CPU monitor in task manager for single core.
In order to fully use the CPU, the number of the splitting pieces has to be
one less than the number of the CPU cores, since one core has to be left for
the PSCAD software and windows operations. For example, in a computer with
eight cores, the original project is better to be split into seven pieces. These
seven pieces will be computed in parallel. Therefore, giving each piece an equal
portion of the total work is preferred, so that the cores who finish their tasks
will not have to wait for other cores who have not finished.
The bridge between different pieces for the ENI approach is the transmission
line as shown in Figure 5.3. The original project is split into a simulation set of
seven project pieces, since the computer running the simulation has eight cores.
35
Main Piece
Arm Arm Arm Arm Arm Arm

PHAwest PHAeast
PHBwest PHBeast
PHCwest PHCeast
Arm Arm Arm Arm Arm Arm
Arm Arm Arm
Arm Arm Arm
Piece No.2 Piece No.3 Piece No. 4 Piece No. 7
Transmission Line
Figure 5.3: ENI detailed model.
After splitting, the main project piece consists of the whole system control,
the grid and the DC link. The other six project pieces comprise two arms,
36
the sorting process, the switching process and all the SMs. In Figure 5.3 all
transmission lines are represented by black solid squares.
The main project piece (Part1) is built as shown in Figure 5.4, and other
pieces (Part2-Part7) are shown as in Figure 5.5. The transmission lines are also
useful for sending and receiving data in between different project pieces. As
seen in Figure 5.4 and 5.5, Part1 sends modulation indices to Part2, and Part2
sends arm voltages back to Part1 for both upper and lower arms.
P P P
ar ar ar
t2 t3 t4
:T :T :T
lin lin lin
Nanw 2 1 Napw e3 e5 e7
Va1w Vb1w Vc1w

Tline0
2 1 Timed
Nbnw Nbpw Breaker
BRKdc Logic Edc
Closed@t0
Tline1
Va2w Vb2w Vc2w

Ncnw 2 1 Ncpw
Tline2
4e 6e 8e
nli nli nli
:T :T :T
2t 3t 4t
ra ra ra
P P P
Figure 5.4: ENI circuit in Part1.
37
N d elia t ed
N d elia t ed
4
neli
T
sms 63
sms 63
po te
po te
V mra
mra
t ob e
t ob e
3 enil T
V
0 enil T:1 traP
2 1
Figure 5.5: ENI circuit in Part2.
The ENI approach also raises a new restriction for the simulation step-time.
Since the transmission line is the bridge to connect different pieces, the ”signal
traveling time” needs to be taken into account. PSCAD/EMTDC requires the
simulation step to be equal or smaller than 10% of the ”signal traveling time”.
The capacitive reactance XC of the transmission line can be calculated to avoid
the ”signal traveling time” issue using the following equation:

√
TS = CL
where C and L are the capacitance and the inductance of the transmission line,
TS is the maximum simulation time step.
In PSCAD/EMTDC, the transmission line can be set in the ”Bergeron
Mode” to avoid the soil and the transmission tower configuration. Afterward,
using ”Manual Entry of X, Y”, the R(Ω/m), XL(Ω/m), XC(M Ω ∗ m) param-
eters are set. To make the transmission line equal to an inductor, it requires
R=0 and XC→ ∞. However, according to the equation of the time step, the
38
XC is dependent on the XL. This will influence the simulation results, it will be
shown in Section 6.
39
6. Simulation results
Three test cases are built to evaluate the ENI multi-core approach. The
first two test cases include simulations for the single-core average model, the
single-core detailed model and the eight-core detailed model. The third test
case includes simulations for the eight-core detailed model for different number
of SMs per arm.
The simulation results will include the active and reactive power for both
MMC converters, the DC link voltage and the synthesized voltage. Some SM
voltages will also be shown in the detailed model simulation.
6.1 Test case 1
The first test case uses the references as:
• DC link voltage reference, Vdcref=400 kV,
• WEST MMC active and reactive power reference, PWref=60 MW, QWref=0
MVar,
• EAST MMC reactive power reference, QEref=10 MVar.
6.1.1 Average model test in the one-core CPU environment
Figure 6.1 shows the active and the reactive power of the WEST MMC.
Figure 6.2 shows the active and reactive power of the EAST MMC. Figure 6.3
shows the DC link voltage. Figure 6.4 shows the synthesized voltage.
40
Figure 6.1: WEST MMC active power and reactive power.
Figure 6.2: EAST MMC active power and reactive power.
Figure 6.3: DC link Voltage.
41
Figure 6.4: Synthesized voltage Va Vb Vc.
6.1.2 Detailed model test in the one-core CPU environment
Figure 6.5 shows the active and reactive power of the WEST MMC. Figure
6.6 shows the active and reactive power of the EAST MMC. Figure 6.7 shows
the DC link voltage. Figure 6.8 shows the synthesized voltage.
42
43
6.1.3 Detailed model test in the eight-core CPU environment
44
Figure 6.12: Synthesized voltages Va Vb Vc.
In an arm of the multi-core detailed model, 12 SMs voltage are randomly
selected as shown in Figure 6.13. They are almost overlapping, which shows the
sorting process is working well.
45
Figure 6.13: Voltage of 12 SMs.
6.2 Test case 2
The second test case uses the references as:
• DC link voltage reference, Vdcref=400 kV,
• WEST MMC active and reactive power reference, PWref=40 MW, QWref=-
10 MVar,
• EAST MMC reactive power reference, QEref=20 MVar.
6.2.1 Average model test in the one-core CPU environment
Figure 6.14 shows the active and the reactive power of the WEST MMC.
Figure 6.15 shows the active and reactive power of the EAST MMC. Figure 6.16
shows the DC link voltage. Figure 6.17 shows the synthesized voltage.
46
47
6.2.2 Detailed model test in the one-core CPU environment
48
49
6.2.3 Detailed model test in the eight-core CPU environment
50
Figure 6.25: Synthesized voltages Va Vb Vc.
6.3 Test case 3
In test case 3, only the multi-core models are tested. The simulation result
of the synthesized voltage with different number of SMs, (Nsm=36, Nsm=108)
are as shown in Figure 6.26 and Figure 6.27.
51
Figure 6.26: Synthesized voltages Va Vb Vc(Nsm=36).
Figure 6.27: Synthesized voltages Va Vb Vc(Nsm=108).
It is worth noting that as the number of the SMs per arm increases, the bad
effect from the ENI approach decreases.
6.4 Comparative evaluation
From the simulations, the results show that:
• The active and reactive power of both WEST and EAST MMC in all tests
meet the references at steady state.
52
• The synthesized voltage of the multi-core model contains some noise not
seen in the one-core models.
• The DC voltage in the multi-core model contains noise as well.
• The noise in the multi-core model decreases when the number of SMs per
arm gains.
The source of this noise is the ENI bridge, transmission line. Since trans-
mission line and cable are the only available bridge for the ENI approach, the
best way to split system is replacing inductors by transmission lines. Since the
transmission line can be treated as a series connection of π-structures, as shown
in Figure 6.28, the shorter the length is, the less π-structures will exist. Even
though the length of every transmission line is set as 1 m, the noise still exists.
This is the downside of the ENI approach. This drawback of the ENI approach
is decreased as the number of levels increases.

L R L R
C C C C
Figure 6.28: Transmission line and π-structure.
6.5 Simulation speed versus SMs number

The main contribution of this thesis is speeding up the simulations. Accord-
ing to [10] [16] [21], the typical detailed MMC model simulation with a large
number of SMs is slow. A table of simulation time versus SMs number per arm
53
is summarized in the Table 6.1 in the single-core CPU environment. It shows
how much time it will take to finish 1 s simulation.
Table 6.1: Simulation time versus Submodule number on each arm.
Arm SMs number 14 16 18 20 22 24
Simulation time(s) 232 392 541 710 902 1044
Arm SMs number 26 28 30 32 34 36
Simulation time(s) 1424 1693 2520 2848 3086 4084
A quadratic curve fit for the data in Figure 6.29 is obtained using the ”basic
fitting” tool by MATLAB. The equation of simulation time versus SMs number
per arm is:
T = 6.9N 2 − 180N + 1500
Note that if the number of the SMs per arm is 200, it will take 86400s to
finish 1s duration of run. For the test cases (with 36 SMs per arm), it only takes
94.4 s to simulate one second with the multi-core approach vs. 4048 s reported
in the literature for a single-core architecture. This is a simulation speed gain
of 43 times.
54
Simulation time respect to SMs number per arm
6000
data 1
2 quadratic
y = 6.9*x - 1.8e+02*x + 1.5e+03
5000
Simulation time for 1 sec duration
4000
3000
2000
1000
0
10 15 20 25 30 35 40
SMs number per arm
Figure 6.29: Simulation time curve.
55
7. Conclusions
An HVDC system based on MMC topology has been modeled to one average
and two detailed models and simulated in a single-core and a multi-core environ-
ment. The performance of three sorting algorithms are evaluated by MATLAB
and PSCAD/EMTDC.
The simulation speed has been greatly improved with the help of selected
sorting algorithm and the ENI approach. Compared to the average model,
the detailed model can show more information such as the submodule voltage
profiles. The approach in a multi-core environment makes it possible to simulate
a large system in the detailed model within a reasonable time frame.
In the ENI approach, inductors are replaced by the transmission line models.
This approximation introduces noise on the DC link and synthesized voltage.
This seems to be a huge problem to the detailed model with 36 submodules in
each arm. However, in the real MMC-HVDC technology projects, it usually has
more than 200 submodules in each arm, and the introduced noise will decrease
as the submodules number increases.
Therefore, the ENI approach in a multi-core environment can accelerate the
simulation significantly, and it will be effective for MMC simulations with a high
number of submodules.
56
8. Future work
In the future, the following work may be done:
• More comparisons: The circulating current effects can be analyzed.
• ENI bridge: In the future, it can be improved if the inductor substitution
is better.
• Optimal way of splitting: The original project has been split by assumed
model branch computational equality, there could be better ways to split
the system to maximize the CPU usage. One possible approach to do this
could be to use the software VTune to analyze CPU usage.
57
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59
APPENDIX A. FORTRAN codes for the detailed model
In this chapter, the algorithm of sorting is shown. The codes are pro-
grammed in the FORTRAN language, which can be directly compiled by the
PSCAD. Instead of injecting C file or Matlab file, the FORTRAN approach ap-
pears to be the best choice, as for saving the simulation time. Here is the code
using InsertionSort in PSCAD.
#LOCAL real A
#LOCAL real B
#LOCAL real clmfst(36)
#LOCAL real clmscd(36)
#LOCAL integer tri
!CHECK IF N CHANGE
!---STORAGE MATRIX-----!
!---INITIAL ORIGINAL MATRIX 2ND CLO WITH LABELS---!
DO I=1,36
clmscd(I)=I
END DO
!---INITIAL ORIGINAL MATRIX 1ST CLO WITH VOLTAGES---!
DO J=1,36
clmfst(J)=$IN(J)
60
END DO
!---SORT MATRIX ROWS BASED ON 1ST CLO VALUES IN ASENDING SEQUENCE---!
DO I=1,36
DO J=(I+1),36
IF (clmfst(J).LT.clmfst(I)) THEN
A=clmfst(J)
clmfst(J)=clmfst(I)
clmfst(I)=A
B=clmscd(J)
clmscd(J)=clmscd(I)
clmscd(I)=B
END IF
END DO
END DO
!---GIVE OUT WITH SORTED LABELS---!
DO I=1,36
$OUT(I)=clmscd(I)
END DO
tri=0
!---GIVE T WITH 1/0 BASED ON NUMBER OF ON/OFF CAPS-N AND CURRENT DIRECTION-ID-
if ($ID .gt. 0 .and. tri .eq. 0) then
tri=1
61
do i=1, 36
if (i .le. NT) then
$T(clmscd(i))=0
else
$T(clmscd(i))=1
end if
end do
else if ($ID .le. 0 .and. tri .eq. 0) then
tri=2
do i=1, 36
if (i .le. 36-NT) then
$T(clmscd(i))=1
else
$T(clmscd(i))=0
end if
end do
end if
Here is the code calling MergeSort or QuickSort.
#LOCAL integer num
#LOCAL integer vsarray(36)
#LOCAL integer vlb(36)
#LOCAL integer TT(19)
#LOCAL integer Tlb(19)
if ($N .ne. $Nd) then
62
num=36
do i=1, num
vsarray(i)=$IN(i)*10
vlb(i)=i
end do
!call MergeSort
call MergeSort(vsarray, vlb, num, TT, Tlb)
!call QuickSort
call QuickSort(vsarray, vlb, num)
if ($ID .ge. 0) then
do i=1,$N
$T(vlb(i))=0
end do
do i=$N+1, num
$T(vlb(i))=1
end do
else
do i=1, num-$N
$T(vlb(i))=1
end do
do i=num+1-$N, num
$T(vlb(i))=0
63
end do
endif
endif
Here is the linked FORTRAN file for MergeSort.
subroutine Merge(A,ALB,NA,B,BLB,NB,C,CLB,NC)
integer, intent(in) :: NA,NB,NC
integer, intent(in out) :: A(NA)
integer, intent(in out) :: ALB(NA)
integer, intent(in) :: B(NB)
integer, intent(in) :: BLB(NB)
integer, intent(in out) :: C(NC)
integer, intent(in out) :: CLB(NC)
integer :: I,J,K
I = 1; J = 1; K = 1;
do while(I <= NA .and. J <= NB)
if (A(I) <= B(J)) then
C(K) = A(I)
CLB(K)=ALB(I)
I = I+1
else
C(K) = B(J)
64
CLB(K)=BLB(J)
J = J+1
endif
K = K + 1
enddo
do while (I <= NA)
C(K) = A(I)
CLB(K)=ALB(I)
I = I + 1
K = K + 1
enddo
do while (J <= NB)
C(K) = B(J)
CLB(K)=BLB(J)
J = J + 1
K = K + 1
enddo
return
end subroutine merge
recursive subroutine MergeSort(A,ALB,N,T,TLB)
integer, intent(in out) :: N
65
integer, dimension(N), intent(in out) :: A
integer, dimension(N), intent(in out) :: ALB
integer, dimension((N+1)/2), intent (out) :: T
integer, dimension((N+1)/2), intent (out) :: TLB
integer :: NA,NB,V,VLB
if (N < 2) return
if (N == 2) then
if (A(1) > A(2)) then
V = A(1)
VLB=ALB(1)
A(1) = A(2)
ALB(1)=ALB(2)
A(2) = V
ALB(2)=VLB
endif
return
endif
NA=(N+1)/2
NB=N-NA
call MergeSort(A,ALB,NA,T,TLB)
call MergeSort(A(NA+1),ALB(NA+1),NB,T,TLB)
66
if (A(NA) > A(NA+1)) then
T(1:NA)=A(1:NA)
TLB(1:NA)=ALB(1:NA)
call Merge(T,TLB,NA,A(NA+1),ALB(NA+1),NB,A,ALB,N)
endif
return
end subroutine MergeSort
Here is the linked FORTRAN file for QuickSort.
recursive subroutine QSort(a,alb,na)
integer, intent(in) :: na
integer, dimension(na), intent(in out) :: a
integer, dimension(na), intent(in out) :: alb
integer :: left, right
integer :: pivot
integer :: temp, templb
integer :: marker
if (na > 1) then
pivot = a(1)
67
left = 0
right = na + 1
do while (left < right)
right = right - 1
do while (a(right) > pivot)
right = right - 1
enddo
left = left + 1
do while (a(left) < pivot)
left = left + 1
enddo
if (left < right) then
temp = a(left)
templb = alb(left)
a(left) = a(right)
alb(left) = alb(right)
a(right) = temp
alb(right) = templb
end if
enddo
if (left == right) then
marker = left + 1
68
else
marker = left
end if
call QSort(a(:marker-1),alb(:marker-1),marker-1)
call QSort(a(marker:),alb(marker:),na-marker+1)
end if
end subroutine QSort
69

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ACCELERATING DETAILED SIMULATIONS OF AN HVDC SYSTEM

BASED ON MODULAR MULTILEVEL CONVERTERS IN A MULTI-CORE

B.S., Beijing Technology and Business University, 2010

A thesis submitted to the

Faculty of the Graduate School of the

University of Colorado in partial fulfillment

of the requirements for the degree of

has been approved for the

Electrical Engineering Program

Fernando Mancilla-David, Chair

June 18, 2015

Thesis directed by Professor Fernando Mancilla-David

The topology of the Modular Multilevel Converter (MMC) was introduced

losses. However, the simulation speed of a detailed MMC model in an HVDC

system is slow due to the computational burden.

In this thesis, with the help of PSCAD/EMTDC, a new approach in a

multi-core CPU environment has been implemented to speed up the simulations

by comparing results with a single-core average model, a single-core detailed

selecting the best sorting algorithm.

Approved: Fernando Mancilla-David

This thesis is dedicated to my family and my girlfriend who have supported me

I would like to express my deepest gratitude to my advisor, Professor Fer-

I greatly appreciate Professors Titsa Papantoni, and Professor Dan Con-

2.1 Design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Average model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Detailed model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Rectifier and inverter control . . . . . . . . . . . . . . . . . . . . . 14

3.2 Leg energy control . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 Control of the average model . . . . . . . . . . . . . . . . . . . . 18

3.3.2 Control of the detailed model . . . . . . . . . . . . . . . . . . . . 19

4.1 Insertion sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Quick sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3 Merge sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4 Performance test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.4.1 MATLAB based tests . . . . . . . . . . . . . . . . . . . . . . . . 27

5. Implementation of the detailed model in a multi-core environment . . 34

6.1 Test case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1.1 Average model test in the one-core CPU environment . . . . . . . 40

6.1.2 Detailed model test in the one-core CPU environment . . . . . . 42

6.1.3 Detailed model test in the eight-core CPU environment . . . . . . 44

6.2 Test case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.1 Average model test in the one-core CPU environment . . . . . . . 46

6.2.2 Detailed model test in the one-core CPU environment . . . . . . 48

6.2.3 Detailed model test in the eight-core CPU environment . . . . . . 50

6.3 Test case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.4 Comparative evaluation . . . . . . . . . . . . . . . . . . . . . . . . 52

6.5 Simulation speed versus SMs number . . . . . . . . . . . . . . . . . 53

A. FORTRAN codes for the detailed model . . . . . . . . . . . . . . . . 60

2.1 Schematic of the HVDC back–to–back system. . . . . . . . . . . . . 3

2.2 (a) Structure of a SM; (b) series connection of a number of SMs

constituting an arm; (c) converter composed of three legs – one for

2.3 Overview of the HVDC system in PSCAD. . . . . . . . . . . . . . . 6

2.4 Average model arm. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5 Detailed model arm. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Submodule at on-state or off-state. . . . . . . . . . . . . . . . . . . 11

2.7 The MMC with average or detailed arm. . . . . . . . . . . . . . . . 12

3.1 PSCAD control panel. . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Overview of the control strategy. . . . . . . . . . . . . . . . . . . . 14

3.3 Current controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Leg energy controller for each phase. . . . . . . . . . . . . . . . . . 16

3.5 Per-phase modulation index computation. . . . . . . . . . . . . . . 17

3.6 Arm in the average model. . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Arm in the detailed model. . . . . . . . . . . . . . . . . . . . . . . 20