IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO.

7, JULY 1998 1065

A 15-b Resolution 2-MHz Nyquist Rate

ADC in a 1- m CMOS Technology
Augusto Manuel Marques, Vincenzo Peluso, Michel S. J. Steyaert, Senior Member, IEEE,
and Willy Sansen, Fellow, IEEE

Abstract—A high-resolution high-speed fourth-order cascaded

16 analog-to-digital converter, based on a 2-1-1 topology, is
presented. The converter is implemented with fully differential
switched capacitor circuits in a standard 1-m CMOS technology.
The converter uses two symmetrical reference voltages of 1 V, and
is driven by a single 48-MHz clock signal. With an oversampling
ratio of only 24, the converter achieves a resolution of 91 dB, a
peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist
rate of 2 MHz after comb filtering. The power consumption of
the converter is 230 mW, from a single 5-V supply voltage.
Index Terms— Analog–digital conversion, CMOS analog in-
tegrated circuits, delta–sigma modulation, switched capacitor
circuits.

I. INTRODUCTION

A N EFFICIENT way of trading off speed for resolution

is provided by converters [1], [2]. Nevertheless, the
demands for high-speed and high-resolution converters have
been increasing considerably over the last few years. The
most effective way to satisfy the increasing demands for large
signal bandwidths is to increase the sampling frequency and to
decrease the oversampling ratio, so that the desired bandwidth
is reached. However, the maximum sampling frequency is ulti-
mately restricted by technology limitations, and the minimum
oversampling ratio is restricted by the resolution specification,
together with the type of topology used. On the other hand,
the most effective way to satisfy the increasing demands for
high resolution is to increase the order of the noise shaping.
Depending on the converter topology selected, one has to
either deal with stability problems, in single-loop topologies,
or with matching problems, in cascade-loop topologies [1].
In order to achieve a signal bandwidth of 1 MHz, with
at least 15-b resolution, two different alternatives have been
proposed. In [4], the characteristics of the bipolar transistors
are explored in a BiCMOS technology to achieve a 750-
kHz bandwidth, with 16-b resolution. In [5], a multibit
converter is combined with a pipeline converter in a submicron
CMOS technology to achieve 1.25-MHz bandwidth, with 16-
b resolution. In this paper, the design and measurement of a
classic converter is reported. Although implemented in
Manuscript received October 30, 1997; revised November 24, 1997. The
work of A. M. Marques was supported by a scholarship from the Portuguese
National Research Board (JNICT).
The authors are with the ESAT Laboratory, Katholieke Universiteit Leuven,
3001 Heverlee, Belgium (e-mail: Augusto.Marques@esat.kuleuven.ac.be).
Publisher Item Identifier S 0018-9200(98)03102-3.
0018–9200/98$10.00  1998 IEEE
Fig. 1. Dynamic range versus oversampling ratio. SLi: ith-order single-loop
topology. Cijk : i–j –k cascade-loop topology.
a standard 1- m CMOS technology, the converter achieves a
1-MHz signal bandwidth, with 15-b resolution.
The outline of this paper is as follows. In Section II, the
design of the converter from a system-level perspective is ad-
dressed. In Section II, the specifications for the building blocks
are derived. In Section IV, the design of each building block
is discussed. In Section V, the measurement results of the
fabricated IC are presented. In Section VI, the performance of
the realized converter is compared with other implementations.
Finally, in Section VII, some overall conclusions are drawn.
II. SYSTEM-LEVEL CONSIDERATIONS
A. Topology Selection
Fig. 1 shows the theoretical, i.e., considering all integrators
and comparators ideal—achievable peak SNR, with a brick-
wall filter, as a function of the oversampling ratio, for different
topologies [6], [7]. The fourth-order cascade 2-1-1 topology,
with an oversampling ratio of 24, is the best choice to achieve
15-b resolution. The topology parameters used are the ones
discussed in [6]. Then, to achieve a 1-MHz bandwidth, the
system sampling frequency is 48 MHz.
B. Topology Scaling
A fully differential implementation with a double reference
is selected to implement the converter. A fully differential
1066
implementation offers a net gain of 3 dB in the signal-to-white-
noise ratio, when compared to a single-ended implementation.
Moreover, in a fully differential implementation, the noise
immunity is higher and the charge/clock feedthrough cancels
better than in a single-ended implementation. Finally, in a
differential implementation, the operational transconductance
amplifiers (OTA’s) have better settling characteristics, since
the differential to single-ended conversion is avoided.
A double reference implementation allows the sampling
capacitors to be used for two different purposes: 1) to sample
the input signal and 2) to subtract the signal fed back from the
comparator output. Due to this capacitor sharing, the number
of white noise sources is reduced and, consequently, the
capacitor and OTA sizes can be scaled down by a factor of two,
reducing the power consumption and die area. Furthermore,
due to this sharing, the capacitive feedback factor is increased,
reducing the integrators capacitive load and moving the closed-
loop dominant pole to higher frequencies.
Based on these considerations, the detailed block diagram
of the converter can be derived, as presented in Fig. 2. For a
practical realization, the topology has to be scaled according
to two criteria; first, the output range of each integrator
should lie roughly between the two reference voltages, and
second, all scaling factors should be ratios that facilitate the
implementation of the overall system and, in particular, the
coupling between stages.
Then, the actual capacitor values depend only on white noise
considerations. Designating the total input referred white noise
power of integrator by , the total input referred white
noise power of the overall converter is given by
OSR
OSR OSR
(1)
OSR
where is the product of the scaling coefficients between
the converter input and the input of integrator . Equation (1)
shows that the main contribution to the converter noise comes
from the first integrator, even when an oversampling ratio as
low as 24 is used. Furthermore, it shows that all integrators can
be progressively scaled down, without a negligible increase of
the overall converter noise.
Hence, the sampling capacitors of the first integrator are
chosen to provide a noise floor low enough for 15-b resolution,
with margin for the first OTA noise and the quantization noise
(see Section IV-C2). All subsequent integrators are scaled
down to decrease the load of the integrators and to reduce the
power consumption and die area (the size of the last integrator
is restricted by matching considerations). The relative scaling
of the OTA’s is 1:0.5:0.4:0.4. Table I shows the capacitor
values used (the smallest unit capacitor is 0.15 pF).
Finally, note that, to avoid kickback noise, the input for
every comparator is sampled on a 125-fF capacitor.
III. BUILDING-BLOCKS SPECIFICATIONS
The effects of the finite OTA gain, finite closed-loop pole,
and nonzero switches resistance on the operation of a switched
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
TABLE I
CAPACITOR SIZES IN PICOFARADS
Sampling Capacitors Integration Capacitors
First stage C11 = 2.50
C13 = C14 = C12 = C15 =
1.00 0.50 7.50 2.50
Second
stage
C21 = 0.30 C22 = 0.45 C23 = 0.90
Third
C31 = 0.25 C32 = C33 = C34 = 0.75
stage 0.25 0.25
capacitor network have been studied in literature [8]–[12].
In the context of this work, the transfer functions for an
integrator taking these effects progressively into consideration
were obtained. The structure with the equations for the
nonideal integrator were programmed in MATLAB, and then
the performance of the modulator as a function of each
parameter was derived. The results obtained are presented
next.
A. Effect of the Finite OTA Gain
The finite gain of an integrator introduces simultaneously
a gain and a pole error in the integrator transfer function.
These errors are especially important in the first and second
integrators of the first stage. On the one hand, the gain error
limits the perfect cancellation of the first-stage quantization
noise. On the other hand, the pole error creates noise leakage
at low frequencies that is not canceled by the digital noise
cancellation network and that can degrade significantly the
converter performance. As an example, for a 3-dB reduction in
SNR, the gain and pole error for the first stage integrators have
to be smaller than approximately 2% and 0.2%, respectively.
Fig. 3(a) shows the simulated SNR as a function of the OTA
gain for an input signal amplitude close to overload. To insure
a degradation smaller than 3 dB, the gain has to be higher
than about 1000. The final 3 dB can only be recovered at the
expense of a large increase in gain. Therefore, to have a very
small performance reduction and to provide some margin for
other nonideal effects, the design was made for a significantly
higher gain, by resorting to an OTA structure with a gain of
the order of —at least 80 dB.
B. Effect of the Finite Closed-Loop Pole
The finite closed-loop pole also introduces a gain and a pole
error on the integrator transfer function. Fig. 3(b) presents the
results of the behavioral simulations of the overall converter
as function of the finite closed-loop pole, considering an OTA
gain of 80 dB. Hence, the closed-loop pole has to obey
(2)
Considering that approximately 20% of the clock cycle is
needed to insure nonoverlapping and delayed clock phases,
this means that the closed-loop dominant pole frequency has to
be higher than approximately 200 MHz, for a clock frequency
of 48 MHz.
Again, to provide some margin for other effects, the closed-
loop dominant pole was pushed to higher frequencies. Circuit
level simulations indicate that the closed-loop dominant pole
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC
Fig. 2. Block diagram of the overall 16 converter.
of the first integrator is 320 MHz. Note that the closed-loop
dominant pole of the subsequent integrators is slightly smaller,
due to the progressive scaling. However, this fact does not
impair the system performance, since the requirements for the
last integrators are more relaxed.
C. Effect of the Nonzero Switch Resistance
The nonzero switch resistance combined with the finite
closed-loop pole can introduce a significant degradation in
the overall transfer function of an integrator [12]. Fig. 3(c)
presents the results of the behavioral simulations of the overall
converter as a function of the switch resistance, for an OTA
1067
gain of 80 dB and a closed-loop pole of 320 MHz. Hence, the
total switch resistance has to obey
(3)
This means that the sum of the resistance of the two switches
on both sides of the first integrator sampling capacitor has to
be smaller than 200 .
D. Effect of the Finite OTA Slew Rate
Considering an OTA with finite gain and with a finite closed-
loop dominant pole, the effect of the OTA slew rate can be
1068
(a)
(c)
Fig. 3. (a) SNR as function of the OTA gain. (b) SNR as function of the OTA closed-loop pole. (c) SNR as function of the sampling time constant.
(d) SNR as function of OTA slew-rate.
modeled as described in [13]. Using the nonlinear difference
equations to model the performance of every integrator of the
modulator, the performance of the overall converter as a
function of the normalized OTA slew rate is evaluated through
behavioral simulations. Fig. 3(d) presents the converter perfor-
mance as a function of the normalized OTA slew-rate. Hence,
the slew-rate should obey
(4)
With a 1-V reference, this means that the OTA slew rate
should be higher than approximately 500 V/ s. This slew-
rate specification is quite large and could imply that an
unreasonably large overdrive voltage should be used for the
input transistors.
Therefore, a closer look at the modeling described in [13]
is mandatory. The model assumes that the switch resistance is
zero. Consequently, at the beginning of the integration phase,
there is an instantaneous charge redistribution that immediately
feeds forward the sampled voltage, causing the OTA to slew.
However, at the beginning of the integration phase, since
the switch resistance is not zero, the sampled voltage is
subject to the RC network composed of the switches and the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
(b)
(d)
sampling capacitor. This considerably slows down the initial
“charge redistribution,” reducing the amplitude of the initial
feedforwarded voltage and relaxing the slew-rate specification.
Using a more elaborate model, that accounts for this effect,
and considering the value of the RC time constant used in this
design, the previous slew-rate specification could be relaxed
to approximately 300 V/ s.
IV. BUILDING-BLOCKS DESIGN
Taking into consideration the previously derived specifica-
tions, the design of the building blocks of the converter
are discussed in this section.
A. Design of the Clock Driver
The clock circuit generates two nonoverlapped clock phases,
in normal and delayed versions, in order to avoid signal-
dependent charge injections. Moreover, every clock phase has
to be generated in normal and inverted form, in order to drive
both the NMOS and the PMOS switches. One extra clock
signal is also generated to control all the switching logic.
Traditionally, both the rising and falling edges of the clock
are delayed, in order to generate the delayed clock waveforms
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC
Fig. 4. Schematic diagram of the clock driver.
Fig. 5. Schematic diagram of the comparator and switching logic.
[4], but, in fact, to avoid signal-dependent charge injection,
only the falling clock edges need to be delayed [14]. Hence,
in this design, in order to efficiently use the short clock
period, the falling clock edges are delayed and the rising clock
edges are synchronized. The circuit designed to implement this
clocking scheme is shown in Fig. 4.
B. Design of the Comparator
The specifications of the comparator were not discussed
in the previous section because, in general, they are quite
relaxed. One can find, by behavioral simulations, that the
offset and hysteresis should be smaller than 100 and 40 mV,
respectively. Although both specifications are easy to achieve,
it is interesting to note that the hysteresis is more important
than the offset for the converter operation. The comparator [18]
1069
with the associated switching logic is presented in Fig. 5. One
aspect of the design worth mentioning is the relative scaling of
the top and bottom regeneration loops. For signals below the
resolution of the comparator, the initial imbalance is difficult
to regenerate. Hence, to avoid an eventual improper trigger
of the SR latch, the metastable point at the top regeneration
loop must be made higher than the threshold voltage of the
SR latch.
C. Design of the OTA
Due to its good frequency characteristics, a fully differential
folded cascode OTA is selected [15]. The gain is increased
with a gain-boosting stage [16], with just one transistor, that
can be designed so that neither the frequency nor the settling
characteristics are impaired [17]. The schematic diagram of the
1070
Fig. 6. Schematic diagram of the folded cascode OTA with gain boosting.
OTA and of the dynamic common mode feedback (CMFB) are
presented in Figs. 6 and 7, respectively.
In the following sections, the analysis of OTA frequency
response is presented, and the noise calculations for the first
integrator, as well as the overall converter, are carried out.
1) Frequency Analysis: The folded cascode differential
amplifier with gain boosting is a possible solution to achieve
simultaneously a large gain and a large bandwidth [16], [17].
However, if the gain-boosting stage is not carefully designed,
it can degrade significantly the frequency characteristics and
the settling performance of the OTA [16], [17].
In Fig. 8, a simplified schematic diagram of the OTA with
gain boosting is presented. The transfer function of the OTA
from the input to the output is obtained by the following
procedure. First, the feedback from node to by the gate-
drain capacitance of can always be neglected without
introducing a significant error. Second, the feedback from node
to through is only important for the calculation of the dc
gain and can be neglected for the pole-zero analysis. Third, the
transfer function is then calculated and simplified disregarding
every value that appears summing with a value. Then,
(5) and (6), shown at the bottom of the page, are obtained.
For simplicity of notation, the ratio between the bulk-source
transconductance and gate-source transconductance of is
represented by [15], i.e., . integrator has two different origins, the white noise due to
The sizing of the OTA is discussed next. Consider that
the output swing has to be approximately 2.5 V (differential
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
reference voltage of 2 V) and that the nondominant pole has
to be at about three–four times the closed-loop dominant pole
(for stability). Then, the folded cascode OTA, without gain
boosting, can be designed following the procedure described in
[15]. In the normal design of a folded cascode OTA, the gain-
bandwidth product depends on two independent parameters:
the input stage transconductance and the output load. However,
in this case, the OTA is used in a feedback configuration, i.e.,
a switched capacitor integrator. Consequently, the effective
load capacitance seen in closed loop depends also on the size
of the input transistors, and then, it is not obvious how to
design the OTA in order to maximize the closed-loop dominant
pole. In fact, two degrees of freedom exist; first, the bias
current of the whole OTA can be scaled, and second, the
size of the input transistors can also be independently scaled,
keeping the same current, and changing the overdrive voltage.
Obviously, the OTA slew rate and power consumption depend
also on these degrees of freedom. Fig. 9 shows the closed-
loop dominant pole, slew rate, and power consumption as a
function of the scaling of the bias current and the size of
the input transistors, for the first OTA, during the integration
phase. The unity scaling on the plot corresponds to the imple-
mented design and yields a closed-loop dominant pole of 320
MHz, a slew rate of 320 V/ s, and a power consumption of
90 mW.
The gain-boosting stage of the OTA is now discussed. To
maximize the output swing, the overdrive voltage of transistors
and has to be minimized; in this design, it is 0.15 V.
Consequently, in the design of the gain boosting, only one
degree of freedom is left to explore, i.e., the biasing current
of the gain-boosting transistors. By changing the bias current
of the gain-boosting transistors, several terms of (5) change
simultaneously, and it is not easy to see their effect on
the pole-zero positions. Fig. 10 shows a plot of the high-
frequency poles and zeros introduced by the gain boosting.
The unity scaling represents the scaling used in the first
OTA. It gives two complex poles with a natural frequency
of approximately 860 MHz and a damping factor of
approximately 0.7, and a real zero at 860 MHz (the other
zero is at very high frequency and can be disregarded). With
these values, the OTA exhibits a good settling performance
[17].
2) Noise Analysis: As seen in Section II-C, the circuit
noise of the converter is almost completely determined by the
noise of the first integrator. The circuit noise generated in an
the resistance of the MOS switches and the OTA noise. In
a switched capacitor circuit, these noise sources originate a
(5)
(6)
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC 1071

Fig. 7. Schematic diagram of the OTA dynamic CMFB circuit.

the integration phase, the switches resistance noise is once

more sampled on , and it is directly integrated to the
output. Third, during the integration phase, the noise of the
OTA is sampled on , and it is also directly integrated to
the output.
Fig. 11 shows the three different sampling networks. The
transfer functions from the noise sources to the sampling
capacitor are given by

(7)

and (8) and (9), shown at the bottom of the page. The total
sampled noise power of a white noise source with
Fig. 8. Simplified schematic diagram of the OTA.
an equivalent noise resistance , filtered by the transfer
function , is given by
broad-band and a sampled noise component at the output of
the integrator [19]. The broad-band component is due to the (10)
all noise sources that inject noise at the output in, at least, one
phase. The sampled noise component results from the sampling
Due to the oversampling nature of the converter, only the
on of the broad-band noise. Since the noise bandwidth of
part of this noise that lies in the Nyquist band contributes to
the broad-band noise is always much larger than the sampling
the converter noise power. The inband noise power is just
frequency, the OTA flicker noise is completely “submerged”
by the aliased sampled noise. Hence, the OTA flicker noise is OSR (11)
neglected in this analysis. Moreover, since the sampled noise is
folded, and appears at the output integrated, it is much higher In the case of the switches resistance noise, the equivalent
than the broad-band noise. At high frequencies, the broad- resistance is just the switches resistance . In the case of the
band noise component still contributes somewhat to the noise OTA noise, the equivalent resistance is 2/3 , where is
of the second integrator, but there, it is of lesser importance the OTA excess noise factor [15]. For this OTA structure, the
[see (1)]. Therefore, the broad-band noise component is also excess noise factor is given approximately by
neglected in this analysis.
The sampled noise component due to the switches resistance (12)
and the OTA is now discussed. There are three important
noise contributions to the total sampled noise. First, during which is, in this design, about 2.75.
the sampling phase, the switches resistance noise is sampled The inband sampled noise power for each of the previous
on , and it is integrated on the next phase. Second, during noise sources is then given by

(8)

(9)
1072 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998

(a)

Fig. 10. Plot of the poles and zero versus scaling of the bias current of the
gain-boosting transistors. x: real part of the pole; o: zero frequency; dashed
line: closed-loop dominant pole.

TABLE II
CALCULATED SAMPLED NOISE POWERS
Nrs -102 dBv
Nri -102 dBv
Noi -110 dBv
(b) Nwn -99 dBv

The calculated power for each noise source, as well as their

sum, , is given in Table II.
The preceding calculations are for a single-ended imple-
mentation. In a differential implementation, the circuit noise
power increases by 3 dB, while the signal power increases by
6 dB. Subtracting the maximum signal power (considering a
loss of 1.5 dB due to premature overload) from the sum of
the circuit noise power plus the quantization noise power, the
achievable peak SNR is 88 dB after brick-wall filtering and
92 dB after comb filtering (due to some noise attenuation at
high frequencies).
(c)
Fig. 9. (a) Closed-loop pole versus scaling of the bias current and the input
transistors size. (b) Slew rate versus scaling of the bias current and the input
transistors size. (c) Power consumption versus scaling of the bias current and
V. MEASUREMENT RESULTS
the input transistors size. To measure the performance of a converter that has si-
multaneously a large bandwidth and a high resolution, the
shielding, grounding, and decoupling of the device under test
(13) are of the utmost importance. Therefore, the ADC die is
OSR
mounted on a thick film ceramic substrate. The substrate is
OSR encapsulated in a thick copper–beryllium box to shield the
circuit from external noise coupling. Different power supplies
are used for the analog, digital, and output drivers. All biasing
inputs are locally decoupled with SMD capacitors. Finally, the
(14) differential input signal is obtained from a single-ended signal
source with a transformer. A photograph of the measurement
setup is shown in Fig. 12. A chip microphotograph is shown
OSR in Fig. 13.
To evaluate the converter performance, 65 536 points of the
three bitstream outputs are acquired with a logic analyzer, and
(15) subsequently processed with MATLAB.
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC 1073

(a) (b) (c)

Fig. 11. Noise sampling networks of (a) switches noise during the sampling phase, (b) switches noise during the integration phase, and (c) OTA noise
during the integration phase.

Fig. 12. Photograph of the measurement setup.

Fig. 14. Plot illustrating the converter noise floor with the inputs short
circuited.

TABLE III
CONVERTER PERFORMANCE

DR 91 dB
SNR 90 dB
SNDR 85 dB
Oversampling Ratio 24
Sampling Rate 48 MHz
Signal Bandwidth 1 MHz
Supply Voltage 5V
Power Consumption 230 mW
Technology 1 m CMOS DMDP
Die Area 2
2.5 2.1 mm2

Then, the SNR and SNDR of the converter are calculated

Fig. 13. Microphotograph of the ADC die.
Fig. 14 shows the power spectral density of the output with
the two inputs short circuited. The top line on the graph is the
cumulative power spectral density of output. It clearly shows
that the converter is white-noise limited up to 1 MHz (slope of
10 dB/decade), and, thereafter, it becomes quantization-noise
limited with a fourth-order noise-shaping characteristic (slope
of 90 dB/decade). Fig. 15 presents the same data, but now for
a sinusoidal input signal applied, where it can be seen that the
converter noise floor remains the same.
as functions of the amplitude of the sinusoidal input signal,
for an oversampling ratio of 24 and using a comb filter. The
measurement results are presented in Fig. 16. The converter
achieves a DR of 91 dB, a peak SNR of 90 dB, and a peak
SNDR of 85 dB.
The measured digital power consumption is 20 mW and is
mainly consumed by the clock driver circuit. The measured
analog power consumption is 210 mW. The die area of the
converter, including bondpads, is 2.5 2.1 mm .
Table III presents a summary of the most important charac-
teristics of the converter.
1074
Fig. 15. Spectrum of the converter output for a sinusoidal input signal.
Fig. 16. SNR and SNDR versus the normalized signal amplitude.
VI. PERFORMANCE COMPARISON
A. Figure of Merit
The power efficiency of different analog-to-digital convert-
ers can be compared using the following figure of merit [20]:
Fig. 17 presents the figure of merit for several
as a function of the signal bandwidth.
B. Comparison
The first interesting point to note is that the figure of merit
varies almost two orders of magnitude. This is caused by
several reasons; different topologies are implemented (single-
loop, cascaded, multibit, etc.), different types of technolo-
gies are used (CMOS, BiCMOS, etc.), as well as different
technology generations (different channel lengths, etc.), and,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998
Fig. 17. Figure of merit for several published 16 converters.
finally, different emphasis has been devoted to the system
optimization.
It can be seen that, in the region of high speed (bandwidth
of roughly 1 MHz), and with more than 12-b resolution, there
have been three other implementations proposed until now
[3]–[5].
In [3], a resolution of 12 b is obtained using a 1- m
CMOS technology. In a similar technology, the converter
being presented achieves a higher resolution, at the cost of
a larger power consumption.
In [4], a resolution of 16 b and a bandwidth of 750 kHz is
achieved in a BiCMOS technology. Due to the exploitation of
the superior transconductance efficiency, , of the bipolar
transistors, a slightly higher figure of merit is achieved.
In [5], a resolution of 16 b and a bandwidth of 1.25 MHz is
achieved using a 0.6- m CMOS technology. The converter is
based on a combination of a multibit converter, where the
feedback DAC uses dynamic element matching, and a pipeline
converter.
In summary, considering that only a 1- m CMOS tech-
nology is used, the overall performance of this converter
compares well, both with the best reported BiCMOS converter
and with the best reported CMOS converter implemented in
a submicron technology.
(16) VII. CONCLUSION
A cascade 2-1-1 converter with 15-b resolution, for a
converters
signal bandwidth of 1 MHz, has been presented. The converter,
implemented in a standard 1- m CMOS technology, achieves
a performance comparable to the best existent high-speed high-
resolution converters fabricated in more expensive and more
advanced technologies.
The obtained performance has been achieved through a
proper system design which entails optimizing the topology
parameters, modeling the circuit nonidealities, scaling properly
the overall system, and, finally, optimizing for speed all
building blocks.
MARQUES et al.: A 15-b RESOLUTION 2-MHz NYQUIST RATE ADC
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Augusto Manuel Marques was born in Tomar,
Portugal, in 1967. He received the B.Sc. degree
in computer engineering and the M.S. degree in
technological physics from the Faculty of Science
and Technology, University of Coimbra, Coimbra,
Portugal, in 1990 and 1992, respectively. He is
currently working towards the Ph.D. degree at the
Katholieke University Leuven, Heverlee, Belgium.
In 1992, he joined the Physics Department, Uni-
versity of Coimbra, Coimbra, Portugal, as a Re-
search Assistant. His current research interests are
the design and testing of high-speed and high-resolution analog-to-digital and
digital-to-analog data converters.
1075
Vincenzo Peluso, photograph and biography not available at the time of
publication.
Michel S. J. Steyaert (S’85–A’89–SM’92) was
born in Aalst, Belgium, in 1959. He received the
Master’s degree in electrical–mechanical engineer-
ing and the Ph.D. degree in electronics from the
Katholieke Universiteit Leuven, Heverlee, Belgium,
in 1983 and 1987, respectively.
From 1983 to 1986, an IWNOL Fellowship (Bel-
gian National Foundation for Industrial Research)
allowed him to work as a Research Assistant at the
ESAT Laboratory, Katholieke Universiteit Leuven.
In 1987, he was responsible for several industrial
projects in the field of analog micropower circuits at the ESAT Laboratory,
as an IWONL Project Researcher. In 1988, he was a Visiting Assistant
Professor at the University of California, Los Angeles. In 1989, he was
appointed a Research Associate by the National Fund of Scientific Research
(Belgium) at the ESAT Laboratory, where he was appointed a Senior Research
Associate in 1992 and a Research Director in 1996. Between 1989–1996,
he was also a Part-Time Associate Professor and, since 1997, he has been
an Associate Professor at the Katholieke Universiteit Leuven. His current
research interests are high-performance and high-frequency analog integrated
circuits for telecommunication systems and analog signal processing.
Prof. Steyaert received the 1990 European Solid-State Circuits Conference
Best Paper Award, the 1995 ISSCC Evening Session Award, and the 1991
NFWO Alcatel–Bell Telephone Award for innovative work in integrated
circuits for telecommunications.
Willy Sansen (S’66–M’72–SM’86–F’95) was born
in Poperinge, Belgium, in 1943. He received the
Master’s degree in electrical engineering from the
Katholieke Universiteit Leuven, Heverlee, Belgium,
in 1967 and the Ph.D. degree in electronics from the
University of California, Berkeley, in 1972.
In 1968, he joined the Katholieke Universiteit
Leuven as a Research Assistant. During 1971, he
was a Teaching Fellow at the University of Califor-
nia, Berkeley. In 1972, he was appointed a Research
Associate by the National Fund of Scientific Re-
search (Belgium) at the ESAT Laboratory, Katholieke Universiteit Leuven,
where he has been a Full Professor since 1981. During 1984–1990, he was
also the Head of the Electrical Engineering Department. In 1978, he spent the
winter quarter at Stanford University, Stanford, CA, as a Visiting Assistant
Professor. He was a Visiting Professor at the Federal Technical University,
Lausanne, Switzerland, at the University of Pennsylvania, Philadelphia, and
at the Technical University, Ulm, Germany, in 1981, 1985, and 1994,
respectively. He is a member of the editorial committees of several journals,
including Sensors and Actuators and High Speed Electronics. He has been
involved in design automation and in numerous analog integrated circuit
designs for telecom, consumer electronics, medical applications, and sensors.
He has supervised 30 Ph.D. theses. He has authored or coauthored 300
papers in international journals and conference proceedings and six books,
including the textbook (with K. Laker) Design of Analog Integrated Circuits
and Systems.
Prof. Sansen is a Member of the Editorial Committee of the IEEE
JOURNAL OF SOLID-STATE CIRCUITS. He serves regularly on the program
committees of various conferences, including ISSCC, ESSCIRC, ASICTT,
EUROSENSORS, TRANSDUCERS, and EDAC.