IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO.
3, MAY/JUNE 2017
Fast and Easily Implementable Detection Circuits for
Short Circuits of Power Semiconductors
Tobias Krone, Student Member, IEEE, Chengzhi Xu, and Axel Mertens, Member, IEEE
Abstract—Short-circuit detection is a fundamental function of
most inverters. In this paper, two new fast and easily implementable
short-circuit detection approaches are presented. The first one of-
fers a significantly accelerated desaturation detection. The second
one allows a full inverter to be protected by only one short-circuit
detection circuit. Both approaches are verified by simulations and
hardware tests.
Index Terms—Desaturation detection, fault analysis, insulated-
gate bipolar transistor (IGBT), short circuit.
I. INTRODUCTION
HORT-CIRCUIT fault detection circuits are used in many
S power electronics applications to detect dc-link short cir-
cuits caused by device failure. They are necessary to prevent fur-
ther damage to the inverter. Furthermore, in redundant systems
a short circuit can affect other redundant parts of the system.
Therefore, the fault must be detected and cleared. The main de-
tection circuit requirement is a fast and reliable fault detection.
Moreover, the circuit should be easily implementable at a low
price.
The short-circuit fault can be divided into two different types
of faults. The first one is the hard switching fault (HSF). It
appears when a device is turned ON while the other device of
the half-bridge has already been shorted by a fault. The other
one—namely fault under load (FUL)—appears when a device
is shorted by a fault while the other device of the half-bridge
has already been turned ON. Both types must be detected. The
most common detection circuit is the desaturation detection cir-
cuit. But there are also other possibilities known. An overview
is given in [1] and [2]. The disadvantage of the desaturation de-
tection is the blanking time which is necessary after turn-on to
avoid false detections. This paper focuses on silicon (Si)-based
Manuscript received May 20, 2016; revised August 10, 2016; accepted Oc-
tober 3, 2016. Date of publication October 19, 2016; date of current version
May 18, 2017. Paper 2016-PEDCC-0451.R1, presented at the 2015 IEEE En-
ergy Conversion Congress and Exposition, Montreal, QC, Canada, Sep. 20–24,
and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLI-
CATIONS by the Power Electronic Devices and Components Committee of the
IEEE Industry Applications Society. This work was supported by the German
Federal Ministry for Economic Affairs and Energy under Project FuSy (FKZ:
01MY12007A).
The authors are with the Institute for Drive Systems and Power Elec-
tronics, Leibniz Universität Hannover, Hannover 30167, Germany (e-mail:
tobias.krone@ial.uni-hannover.de; xuchengzhi3@126.com; mertens@ial.
uni-hannover.de).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2016.2618785
0093-9994 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
2871
IGBTs. Thus, the minimum detection delay is limited to about
1 µs (depending on the turn-on time of the device). The short-
circuit withstand time of most commercial Si-based IGBTs is
between 5 and 10 µs. Therefore, the common desaturation de-
tection is suitable. However, the short-circuit withstand time is
a design parameter for power semiconductors. It depends on the
chip volume and the desaturation current. The progress in chip
design and chip manufacturing leads to thinner chips. Further-
more, the desaturation current depends on the gate channel. An
optimized gate channel for reduced conducting losses in new
chip technologies leads to a higher desaturation current as well.
Due to the smaller chip volume and the increased desaturation
current, short-circuit robustness becomes more critical and the
acquired withstand time limits a further reduction of conduction
losses for new chips. Thus, shorter response time could enable
shorter withstand time and therefore further reduction of the
conduction losses [3].
In [4], a fast desaturation detection is presented. The paper
focuses on the design issues for desaturation detection at fast
switching SiC devices and presents a concept for solving them.
The fact that in the suggested paper a faster short-circuit detec-
tion is realized results from the devices used. Due to the faster
switching of the SiC devices in comparison to Si devices, a
shorter blanking time is possible but it must still be longer than
the maximum fall time of the blocking voltage. Therefore, the
approach cannot be used to accelerate the desaturation detection
for Si devices.
Faster short-circuit detection for Si devices can be realized
by monitoring the gate–emitter voltage vGE . HSF can be de-
tected by identifying the missing Miller plateau [5]–[7]. In ad-
dition, a FUL causes a gate voltage peak which can be detected
[8], [9]. Another possibility for fast fault detection is to detect
the current transient under short-circuit conditions (di/dt). For
this purpose, the voltage at the parasitic inductor between power
emitter and auxiliary emitter can be used [10], [11]. A combi-
nation of these approaches is given in [3]. Both approaches are
suited to detect a short circuit in a few hundred nanoseconds, but
both systems can only detect the fault in the small time period
during which the fault appears. If this period is missed, e.g., by
an error in the detection system, the fault cannot be detected
anymore. Furthermore, slow rising fault currents cannot be de-
tected. To avoid this, the first proposed approach combines the
missing Miller plateau detection and the desaturation detection.
In this way, no additional blanking time is necessary and the
desaturation detection can be accelerated [12].
2872 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017
Fig. 1. Comparison of the common desaturation detection circuit and the
accelerated detection circuit.
Another possibility to detect short circuits in inverters is to
analyze the dc-link current [13]. One advantage is that just one
detecting circuit for all half-bridges in parallel is necessary, but
there are two main disadvantages of this system. The fault lo-
cation cannot be detected and for the detection a current sensor
inside the dc link is needed. To get around the first disadvantage,
the fault location detection can be realized in the software. How-
ever, the additional current sensor still influences the switching
behavior and the system losses due to the additional inductance
and resistance in the dc link. Therefore, the second proposed
detection circuit identifies a dc-link overcurrent without an ad-
ditional current sensor. Instead of the current, the resulting dc-
link voltage transient is analyzed. It is proportional to the current
and this approach does not affect the switching behavior or the
power losses [12].
In this paper, the accelerated desaturation detection circuit
and the dc-link voltage transient detection circuit are presented.
Moreover, the results of time-based circuit simulations and hard-
ware tests of these circuits are given.
II. ACCELERATED DESATURATION DETECTION
The first proposed approach combines a common desaturation
detection circuit with monitoring system for the gate–emitter
voltage. For this purpose, a feedback path to the gate–emitter
voltage is used to accelerate the fault detection. A comparison
of these circuits is given in Fig. 1. As in common desatura-
tion detection circuits, the diode D1 is used to block the high
collector–emitter voltage during off-state condition of the IGBT.
Instead of a resistor to the supply voltage of the gate driver (see
R4 in Fig. 1) or a current source, the blocking diode is driven
by the feedback path from the gate voltage vGE during the
on-state. This is realized by the resistor R3 . Under normal con-
dition, due to the Miller plateau the gate voltage stays at a certain
lower level (see Fig. 3 upper graph) until the collector–emitter
voltage becomes low and the blocking diode D1 is turned ON.
If the resistors are selected appropriately, the voltage at the
comparator v1 stays below the compared voltage Vcom p dur-
ing turn-on without the need for an additional capacitor for a
blanking time. The given capacitor C1 is used to prevent false
detection due to noise and induced voltages from high di/dt
stages only. It is very small compared to the capacitor needed in
common desaturation detection circuits. Thus, the fault detec-
tion is hardly delayed by this capacitor. Under HSF conditions,
the gate–emitter voltage rises very fast up to the supply voltage
VCC because of the missing Miller plateau (see Fig. 3 upper
graph). Therefore, the voltage at the comparator exceeds the
compared voltage without additional delay, and the fault can be
detected. If the IGBT is turned ON, the circuit behavior is close
to the common desaturation detection. Nevertheless, the FUL
detection is accelerated due to the smaller time constant.
The hardware demand of this circuit is comparable to a com-
mon desaturation detection. For this circuit, no additional pull-
down transistor (see T1 in Fig. 1) during off-state is necessary. In
common desaturation detection circuits, this transistor is needed
to maintain v1 below the comparator threshold voltage. Further-
more, the blanking capacitor is discharged via this transistor
during off-state to ensure the blanking time for the next turn-on.
For the approach in this paper, v1 remains below the comparator
threshold voltage due to the resistor to the gate. An additional
discharge transistor is not necessary because the time constant
of the detection circuit (R2  R3 · C1 ) is much smaller than the
minimum off-state period. Instead of the transistor, just the ad-
ditional resistor to the gate is needed. Therefore, the detection
circuit can be implemented easily.
A. Circuit Design
In this section, an overview of the detection circuit design is
given. To identify the exact resistance values in the first step,
the transfer function of V1 (s) is identified
 
Rp123 1 1
V1 (s) = VGE (s) + VCED (s) . (1)
1 + C1 Rp123 s R3 R1
The equivalent resistance Rp123 is the equivalent resistor of
all resistors in parallel (Rp123 = R1 R2 R3 ), and the voltage
vCED is the sum of the collector–emitter voltage and the forward
voltage of D1 . Due to its small size, the capacitor C1 can be
neglected for the calculations. In this way, a stationary analysis
is possible.
During switching ON, the diode is blocking (VCED = V1 ).
The voltage V1 depends on the gate–emitter voltage only
R2
V1, sw = VGE. (2)
R2 + R3
Under normal condition, the gate–emitter voltage stays on the
Miller plateau until the collector–emitter voltage is reduced.
The Miller plateau voltage depends on the current and the
junction temperature. For the maximum Miller plateau voltage
VGE = VM iller, m ax , the voltage V1, norm al (3) must be below
the compared voltage Vcom p . Under the short-circuit condition,
KRONE et al.: FAST AND EASILY IMPLEMENTABLE DETECTION CIRCUITS FOR SHORT CIRCUITS OF POWER SEMICONDUCTORS 2873

Fig. 2. Accelerated desaturation detection circuit.

the gate–emitter voltage directly rises to the gate driver supply VCED, m ax ), V1 must be lower or equal to the highest voltage
voltage (VGE = VCC ). Under this condition, V1, HSF (4) must under normal condition during switching [V1, norm al (3)]. From
exceed the compared voltage. Therefore, the compared voltage this, the maximum R1 can be identified
must be chosen between the lowest voltage under fault con-
dition V1, HSF and the highest voltage under normal condition VM iller, m ax VCED, desat − VCED, m ax VCC
R1 ≤ R3 . (8)
V1, norm al VCC2 −V
M iller, m ax VCC

R2 The optimum resistor R3 can be identified by considering

V1, norm al = VM iller, m ax (3)
R2 + R3 two boundary conditions. The resistance must not be too small
R2 because of its negative effect on the gate voltage. On the other
V1, HSF = VCC. (4) side, a large resistance in combination with parasitic capacitors
R2 + R3
can cause long delays.
Thus, the ratio of V1, norm al and V1, HSF depends on the ratio of
Although for this approach C1 is not needed to blank the
the maximum Miller plateau voltage and the gate driver supply
turning-on period, a small capacitor is still reasonable to prevent
voltage
false detections. For example, due to parasitic inductances in the
V1, norm al VM iller, m ax power module, collector current transients lead to gate voltage
= . (5)
V1, HSF VCC peaks. Without a small capacitor, these over voltages could cause
If the short circuit occurs while the semiconductor is al- false detections, but it must be considered that the capacitor
ready turned ON (FUL), the conditions are: VGE = VCC and causes an additional short-circuit detection delay. Therefore, an
VCED = VCED, desat . VCED, desat is the minimum collector– optimum has to be found. For the devices used for testing, a
emitter voltage during desaturation VCE, desat plus the diode’s time constant (R2  R3 ) · C1 of less than 100 ns is sufficient to
forward voltage drop VD . The resulting voltage V1, FUL is prevent false detections.
A disadvantage of the system is that an error in the gate
Rp123 Rp123 circuit resulting in a smaller gate voltage would influence the
V1, FUL = VCC + VCED, desat . (6)
R3 R1 detecting circuit. The resulting desaturation of the IGBT cannot
For a reliable detection during switching and during the on- be detected. This does not affect the short-circuit detection, but
state in both cases, the voltage V1 should be equal (V1, SC = it is a disadvantage in comparison to the common desaturation
V1, FUL = V1, HSF ). Consequently, the ratio of the resistors R2 detection. The problem can be solved by adding an additional
and R3 can be calculated from the combination of (4) and (6) pull-up current to the detection circuit after the IGBT turn-
on. This can be realized by an additional resistor R4 and a
VCED, desat
R2 = R3 . (7) transistor (see Fig. 2, optional extension circuit). The transistor
VCC − VCED, desat is turned ON after IGBT turn-on and adds a current through the
Using this ratio, V1, SC equals VCED, desat . Under this condition, resistor to the circuit. The resulting components’ values for the
the resistance R1 does not affect V1, SC . Therefore, R1 can extended detection circuit can be calculated similar to the given
be selected independently. Under normal conditions (VCED = calculations for the normal detection circuit.
2874 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017

TABLE I
DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE ACCELERATED
DESATURATION DETECTION (T 1 AND R 4 NOT APPLIED)

VC C 15 V VC E D , d esa t 71.5 V Vco m p 6.5 V

VM ille r, m ax 12 V VC E D , m a x 4V R1 6.67 kΩ
R2 10 kΩ R3 10 kΩ C1 16.6 pF

Fig. 4. Comparison of the desaturation detection circuits’ detection delays.

TABLE II
DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE EXTENDED
ACCELERATED DESATURATION DETECTION (T 1 AND R 4 APPLIED)

VC C 15 V VC E D , d esa t 8V Vco m p 7V
VM ille r, m ax 12 V VC E D , m a x 4V R1 740 Ω
R2 11.42 kΩ R3 10 kΩ R4 2.9 kΩ
C1 10 pF td e la y 1 µs
Fig. 3. Simulation results of the accelerated desaturation detection circuit (T 1
and R 4 not applied).

selected. For the proposed accelerated detection circuit, the volt-

B. Simulation Results
For simulations and tests of the circuits, a H-bridge
600 V/100 A Trench-IGBT power module is used. A choke
is used as a load. The choke is connected between the out-
puts, so that the load current can be controlled by this setup.
The short circuit is realized by turning ON both IGBTs by one
half-bridge. Regarding the order of the turn-on, FUL or HSF
can be tested easily. The circuits are investigated by time-based
circuit simulations. In the simulation, IGBT models, the gate
drivers, and the dc-link connection as well as parasitic elements
of the interconnections inside and outside the power modules
are implemented. The design parameters and the resulting com-
ponents’ values of the accelerated desaturation detection circuit
are given in Table I.
The simulation results are given in Fig. 3. During the normal
operation, the fault signal is not triggered. If the FUL or the
HSF occurs, the input signal of the comparator v1 exceeds the
compared voltage.
A comparison of the detection speed of the proposed detec-
tion circuit to the common desaturation detection circuit is given
in Fig. 4. The common desaturation detection needs a delay time
of about 1 µs (depending on the turn-on time of the device) to
avoid false detections. This is why for the circuit given in Fig. 1,
the resistance R4 = 15 kΩ and the capacitance C1 = 120 p are
age limit is exceeded at about 200 ns. Thus, the detection delay
can be reduced by 800 ns. For the FUL detection, no delay is
necessary. Therefore, the detection period is much smaller. Nev-
ertheless, the detection speed can be increased by the proposed
circuit as well.
Furthermore, the extended detection circuit is also evaluated
by simulations. The parameters and the components values for
the extended detection circuit are given in Table II. The simu-
lations investigate the circuit behavior at desaturation due to a
reduced gate voltage and at an open-circuit fault due to a gate
circuit failure. The simulation results are presented in Fig. 5.
They prove that both faults can be detected by the extended
circuit.
C. Test Setup
The schematic of the test setup is given in Fig. 6, and a
photograph of it is presented in Fig. 7. For the tests of the
accelerated desaturation detection, the H-bridge on the right-
hand side is used only. The additional H-bridge on the other
side is needed for the tests of the second proposed detection
circuit. As already described, the circuit behavior in case of
normal switching, FUL or HSF, can be tested with this setup.
The collector current through the test device is measured by
a Rogowski coil. It is realized on a printed circuit board (PCB)
KRONE et al.: FAST AND EASILY IMPLEMENTABLE DETECTION CIRCUITS FOR SHORT CIRCUITS OF POWER SEMICONDUCTORS 2875

Fig. 7. Test setup.

Fig. 5. Simulation results of the extended accelerated desaturation detection
circuit (T 1 and R 4 applied).

Fig. 8. PCB Rogowski coil.

Fig. 6. Schematic of the test circuit.

which is located around the pins of the dc-link capacitors (see

Fig. 8). The simulated magnetic field resulting from the dc- Fig. 9. Simulated magnetic field inside the Rogowski coil resulting from the
dc-link current (ID C = 100 A).
link current inside the Rogowski coil is presented in Fig. 9.
During the tests, the voltage of the Rogowski coil is measured.
The resulting current is calculated in MATLAB afterward. This
setup is calibrated with a commercial Rogowski probe before it
is used for the measurements. The calibration results are given
in Fig. 10.
The voltages at the high-side IGBT are measured by com-
mercial differential high-voltage probes.

D. Test Results
The test results for the accelerated desaturation detection at a
low-side IGBT are given in Fig. 13. The results for vGE and v1
are close to the simulation results. vout is the output signal of the
comparator. It shows that both faults are detected (blue and red
circles) and no false detection occurs under normal switching Fig. 10. Result of the PCB Rogowski coil calibration.
2876 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017
Fig. 11. DC-link voltage transient detection circuit.
Fig. 12. General idea of dc-link voltage transient detection.
conditions. Furthermore, for the HSF the compared voltage is
exceeded in less than 250 ns and the fault is detected by the
comparator in about 340 ns.
In the simulation, the compared voltage is exceeded in 200 ns.
The 50 ns difference between simulation and experimental test
results from the input capacitance of the comparator, which
is not included in the simulated circuit. Instead, an optimized
capacitance C1 is used. In the test setup, the input capacitance of
the comparator is slightly higher than the simulated capacitance
C1 . Consequently, the delays in simulation and experimental
tests are not equal. Although the detection time is slightly longer
than that stated by the simulations, it is still a factor four faster
than with a common desaturation detection.
The test results at a high-side IGBT are presented in Fig. 14.
They verify that the proposed circuit can be used for high-side
IGBTs as well and that both faults are detected (red circles). The
detection delays are close to the delays at the low-side IGBT.
III. DC-LINK VOLTAGE TRANSIENT DETECTION
To detect a short-circuit current in the dc link, the change
of the dc-link voltage can be analyzed. This can be realized by
adding a smaller capacitor and a resistor in parallel to the dc-
link capacitor (see Fig. 12). The capacitor voltage follows the
dc-link voltage. Assuming that the current from the dc source
changes slowly compared to the capacitor current and the short-
circuit current is mainly fed from the dc-link capacitor in the first
microseconds, the voltage across the resistor is nearly propor-
tional to the dc-link current. Therefore, all half-bridges in par-
allel can be monitored without a significant influence on the
switching behavior or the inverter power losses.
A. Circuit Design
For the design of the dc-link voltage transient detection cir-
cuit, it is assumed that CDC  C1 . Thus, the current through
the detection circuit can be neglected. In this way, the current
through the dc-link capacitor is approximately the difference
between input and output currents of the dc-link capacitor
iDC = iDC, out − iDC, in . (9)
First measurements showed that the parasitic inductance and
parasitic resistance of the dc-link capacitors (see Fig. 11) cannot
be neglected for the circuit consideration. For this reason, they
must be considered in the transfer function of the dc-link voltage
VDC (s) with the capacitor current as the input state
 
1
VDC (s) = − + RDC + LDC s IDC (s). (10)
CDC s
Due to its high forward voltage drop, the diode D1 (see Fig. 11)
does not influence the circuit behavior in the relevant voltage
range around the comparator threshold voltage and can therefore
be neglected. The objective of this diode is discussed later in
this paper. The resulting transfer function of the voltage v1 is
1
CD C + RDC s + LDC s2
V1 (s) = −τ1 IDC (s) (11)
1 + τ1 s
where τ1 is the time constant τ1 = C1 R1 .
V1 (s) shows that beside the current iDC , the voltage v1 is
affected by the derivative of the current and the second derivative
of the current. For the components’ selection, it must also be
considered that the time constant and the gain of the detection
circuit are linked by the time constant τ1 .
The influence of the derivative and the second derivative to
the dc-link voltage and to v1 are illustrated in Fig. 16. For this
investigation, the component values in Table III are used. In the
KRONE et al.: FAST AND EASILY IMPLEMENTABLE DETECTION CIRCUITS FOR SHORT CIRCUITS OF POWER SEMICONDUCTORS 2877

Fig. 13. Test results of the accelerated desaturation detection circuit (LOW side, T 1 and R 4 not applied).

Fig. 14. Test results of the accelerated desaturation detection circuit (HIGH side, T 1 and R 4 not applied).

Fig. 15. Test results of the dc-link voltage transient detection circuit.
2878 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 53, NO. 3, MAY/JUNE 2017

first step, the voltage drop due to the measured capacitor cur-
rent behavior is calculated separately for the capacitor and the
parasitic inductor and resistor (b). This calculation is validated
by comparing the sum of these voltage drops to the measured
one (c). Next, the voltages v1 resulting from these voltage drops
are calculated (d), and again the sum is compared to the mea-
sured voltage (e). The results show that especially the second
derivative combined with the parasitic inductance leads to high-
voltage peaks. This must be considered for the detection circuit
design.
The voltage peaks due to the capacitor current transient can
be reduced by the additional low-pass filter (R1, PT1 , C1, PT1 ),
but as shown in Fig. 16(f), this does not block the high-voltage
peaks effectively. Therefore, the voltage v1 is additionally cut
by a diode D1 at its forward voltage drop (here Vf , D1 = 1.8 V).
The voltage level should be selected slightly above the compared
voltage level Vcom p . Depending on the compared voltage level,
either the reverse voltage drop of a zener diode or the forward
voltage drop of a normal diode can thus be used. With this circuit,
voltage overshoots of v1, PT1 and resulting false detections can
be prevented [see Fig. 16 graph (f)].
For the selection of the compared voltage, the maximum cur-
rent of the dc-link capacitor under normal condition and the
minimum current under short-circuit condition must be identi-
fied (“worst case consideration”). The capacitor current under
normal condition is maximum in case of a maximum recupera-
tion current to the dc source and a maximum phase current. The
minimum current is the minimum short-circuit current which
shall be detected reduced by the maximum input current from
the dc source
IDC, norm , m ax = Iload, m ax − IDC, in, m in (12)
IDC, short, m in = Ishort, m in − IDC, in, m ax . (13) Fig. 16. Transient behavior of dc-link voltage transient detection circuit:
(a) dc-link capacitor current iD C (measured); (b) resulting dc-link voltage drops
Therefore, a gap between these currents is necessary to detect the (calculated separately for capacitor and parasitic inductance and resistance);
short circuit. The optimum compared voltage can be chosen in (c) comparison of calculated and measured overall voltage drop; (d) v 1 result-
the middle of the resulting voltages in case of IDC, norm , m ax and ing from voltage drops (calculated separately); (e) comparison of calculated and
measured overall voltage v 1 ; and (f) effects of the voltage transient suppression
IDC, short, m in . Assuming that the maximum dc source current (calculated).
is the same in both directions (IDC, in, m ax = −IDC, in, m in ), the
optimum compared voltage can be calculated as
TABLE III
τ1 Iload, m ax + Ishort, m in DESIGN PARAMETER AND COMPONENTS’ VALUES OF THE DC-LINK VOLTAGE
Vcom p =− . (14)
CDC 2 TRANSIENT DETECTION

In the considered inverter system, the maximum load current is

Il o a d , m a x 120 A ID C , i n , m a x 100 A Vco m p −1 V
100 A and the maximum input dc current is 85 A. To ensure a Is h o r t , m i n 317 A CD C 50 µF
safety margin, Iload, m ax = 120 A and IDC, in, m ax = 100 A are C1 230 pF R1 1 kΩ Vf , D1 1.8 V
used for the circuit design and for the tests. The selected voltage C1, P T 1 47 pF R1, P T 1 10 kΩ

level for the comparator Vcom p = −1 V leads to a detectable

minimum short-circuit current of 317 A
CDC
Ishort, m in = − Vcom p + IDC, in, m ax = 317 A. (15)
τ1
B. Test Results
The test results of the dc-link voltage transient detection cir-
cuit are given in Fig. 15. In the first step, the circuit behavior
without an additional input current is investigated under nor-
mal switching condition and under short-circuit condition. In
the next step, an input current is added. In this case, the in-
put and output currents are selected regarding the “worst case
consideration” given in (12) and (13) with the parameters from
Table III. The negative voltage peak in v1 due to the second
derivative of the current is cut by the diode D1 in the time pe-
riod 0–200 ns. This verifies the simulation results from Fig. 16,
graph (f). Under normal switching conditions, v1, PT1 does not
exceed the compared voltage level. Under short-circuit con-
ditions, the compared voltage level is exceeded (blue circle)
KRONE et al.: FAST AND EASILY IMPLEMENTABLE DETECTION CIRCUITS FOR SHORT CIRCUITS OF POWER SEMICONDUCTORS
and the error is detected by the comparator (red circles). Besides
the circuit design, the delay depends on the time period until the
capacitor current exceeds the minimum detection current. If the
resulting short-circuit current inside the dc-link capacitors is
reduced, e.g., by an additional dc source current, the short cir-
cuit is delayed. Therefore, a slower increase in the short-circuit
currents leads to a longer detection time period and to higher
thermal stress to the devices.
Summing up, the tests showed that under the given condi-
tions, short-circuit faults can be detected by the proposed circuit
and that under normal switching conditions, no false detection
occurs.
IV. CONCLUSION
In this paper, two approaches for fast accelerated short-circuit
fault detection are presented. The first one is an accelerated
desaturation detection. It is shown that by combining the desat-
uration detection and the feedback of the gate–emitter voltage,
the fault detection can be accelerated significantly. Furthermore,
the hardware effort is comparable to the common desaturation
detection circuit. The concept is verified by simulations and
tests.
The second proposed approach is suitable for monitoring all
half-bridges of an inverter at the same time regarding short-
circuit faults. This is realized by detecting dc-link voltage tran-
sients. For this purpose, a detection circuit is presented in this
paper. It is verified by simulations and tests as well.
In summary, the first approach is a good possibility to use
the well-known desaturation detection in applications requiring
the fast fault detection. The second approach is a convenient
short-circuit detection for space- or cost-critical applications.
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Tobias Krone (S’13) received the Dipl.-Ing. degree
in electrical engineering from the Leibniz Universität
Hannover, Hannover, Germany, in 2012.
Since 2012, he has been a Research Associate in
the Institute for Drives Systems and Power Electron-
ics, Leibniz Universität. His research interests include
gate drivers for power semiconductors and converter
topologies for fault tolerant drive systems in automo-
tive applications.
Chengzhi Xu received the B.Sc. degree in inte-
grated circuit design and integration system from the
Xidian University, Xi’an, China, in 2010 and the
M.Sc. degree in electrical engineering and infor-
mation technology from the Leibniz Universität
Hannover, Hannover, Germany, in 2014.
In 2014 and 2015, he was a Student Assistant in
the Institute for Drive Systems and Power Electron-
ics, Leibniz Universität. His main research interests
include gate drivers for power semiconductors.
Axel Mertens (S’89–M’92) received the Dipl.-
Ing. and Dr.-Ing. (Ph.D.) degrees from Rheinisch-
Westfaelische Technische Hochschule (RWTH)
Aachen University, Aachen, Germany, in 1987 and
1992, respectively.
In 1989, he was a Research Associate in the
Wisconsin Electric Machines and Power Electronics
Consortium, University of Wisconsin, Madison, WI,
USA. From 1993 to 2004, he was with Siemens Drive
Technologies, Germany, where he was responsible
for the control of large drives ranging from three-level
high-voltage insulated-gate bipolar transistor inverters to cycloconverters and
load-commutated inverters. In 2004, he was appointed as a Professor of power
electronics and drives, Leibniz Universität Hannover, Hannover, Germany. Since
2012, he has been the Head of the Department Converter Technology within the
Fraunhofer Institute for Wind Energy and Energy System Technology. His re-
search interests include application of wide bandgap semiconductors, condition
monitoring of power semiconductor devices, design of power electronic circuits,
modular multilevel converters, and control of electronic power converters and
drives. His preferred fields of application are industrial drives, electric vehicles,
and grid connected inverters such as in wind power systems.
Prof. Mertens published more than 100 technical papers and holds a number
of patents. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS and served as the Chairman of the IEEE Joint German Chapter
of the IEEE INDUSTRY APPLICATIONS, IEEE POWER ELECTRONICS, and IEEE
INDUSTRIAL ELECTRONICS SOCIETIES.