Introduction to CMOS

MICROELECTRONIC ENGINEERING
ROCHESTER INSTITUTE OF TECHNOLOGY

Introduction to CMOS

Dr. Lynn Fuller

Webpage: http://people.rit.edu/lffeee
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Fax (585) 475-5041
Email: Lynn.Fuller@rit.edu
Department webpage: http://www.microe.rit.edu

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12-8-2009 LEC_CMOS.ppt

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 Introduction to CMOS

OUTLINE

Transistor Terminology
n-Type MOSFETs
p-Type MOSFETs
Transistor Characteristics
Sub Threshold Characteristics
Channel Length Modulation
Effective Channel Length
Short Channel Effect on Vt
CMOS Digital Building Blocks
p-well CMOS
N-well CMOS
Dual Well / Quad Well
Latch-Up
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 Introduction to CMOS

TRANSISTOR TERMINOLOGY

FET - Field Effect Transistor

IGFET - Insulated Gate FET
MOSFET - Metal Oxide Semiconductor FET
MNOSFET - Metal Nitride Oxide Semiconductor
SAGFET - Self Aligned Gate FET
JFET - Junction FET
MESFET - Metal Epitaxy Semiconductor FET
(Schottky Barrier Junction FET)
NMOSFET - n-type MOSFET
PMOSFET - p-type MOSFET
ENHANCEMENT MODE MOSFET
DEPLETION MODE MOSFET
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 Introduction to CMOS

TRANSISTOR TERMINOLOGY (CONTINUED)

MOSFET Device Parameters:

THRESHLD VOLTAGE, Vt
TRANSCONDUCTANCE, gm
MOSFET SATURATION REGION - larger values of Vds
NON SATURATION REGION - low values of Vds
SUBTHRESHOLD REGION - Vgs lower than Vt

CMOS - Complementary MOS

P-WELL CMOS
N-WELL CMOS
Dual Well, Quad Well

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 Introduction to CMOS

TYPES OF n-type MOSFETS

Drain Drain
n n
Gate Sub Gate Sub
Poly Gate, Enhancement -NMOS
Source Source Self Aligned Gate Technology
Enhancement Depletion n-
NMOS NMOS
n n
Source is the source of electrons, Poly Gate, Depletion-NMOS
Drain is the drain of electrons. Self Aligned Gate Technology

G G
S D D S
n n
n n p p
p-well
PMOS Metal Gate, Enhancement -NMOS
n-substrate NMOS
Overlapping Gate Technology
p-well CMOS n-
n n
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Metal Gate, Depletion -NMOS
Overlapping Gate Technology
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 Introduction to CMOS

TYPES OF p-type MOSFETS

Drain Drain
p p
Gate Sub Gate Sub
Poly Gate, Enhancement -PMOS
Source Source Self Aligned Gate Technology
Enhancement Depletion p-
PMOS PMOS
p p
Source is the source of holes, Poly Gate, Depletion-PMOS
Drain is the drain of holes. Self Aligned Gate Technology

G G
S D D S
p p
p p n n
n-well
NMOS Metal Gate, Enhancement -PMOS
p-substrate PMOS
Overlapping Gate Technology
n-well CMOS p-
p p
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Metal Gate, Depletion -PMOS
Overlapping Gate Technology
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 Introduction to CMOS
MOSFET ID-VDS CHARACTERISTICS
FAMILY OF CURVES

+I -I
+5 +Vg -5 -Vg
+4 -4
NMOS
+3 -3 PMOS
+2 -2
+V Drain Drain
-V
Gate Sub Gate Sub
Enhancement Enhancement
NMOS Source Source
PMOS
+I -I
+2 -2
+1 -1
NMOS
0 0 PMOS
-1 Drain +1
+V Drain
-V
Gate Sub
Depletion Gate Sub
Source Depletion
NMOS Source
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PMOS
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 Introduction to CMOS

NON SATURATION REGION CHARACTERISTICS

+Ids
Vd = 0.1 Volt
+5
Id +4
+ D Non Saturation +Vgs
Region +3
Vgs G +2

- +Vds
S G
Vsub
S D
Vsub = 0 n n
+Id
Body Effect p
-1 Vsub
-2 nMOSFET with Vt=1, since the Drain is at 0.1 volts
-3 volts and the source is at zero. Both drain and source will
+Vg be on at gate voltages greater than 1.1 volt. the
Vto transistor will be in the non saturation region.

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 Introduction to CMOS

SATURATION REGION CHARACTERISTICS

Id IDsat = µW Cox’ (Vg-Vt)2 +Ids Saturation Region

2L +5
+ +4
D NMOS +Vgs
+3
G Vgs=Vds
+2
- +Vds
S Vsub G
S D
Vsub = 0 n n
+Id
Body Effect p
-1 Vsub
-2
-3 volts nMOSFET with Vt=1, Drain end is never on
because Voltage Gate to Drain is Zero. Therefore
+Vg
Vto this transistor is always in Saturation Region if
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the gate voltage is above the threshold voltage.
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 Introduction to CMOS

SUB-THRESHOLD CHARACTERISTICS
Id (Amps)

10-2
Id 10-3

Sub Vt Swing (Amps)

10-4
10-5
+ Lights On Sub Vt Slope
D 10-6
10-7 (mV/dec)
Vgs=Vds
G 10-8
10-9
- 10-10
S 10-11
10-12 Vt
Vgs
The sub-threshold characteristics are important in VLSI circuits
because when the transistors are off they should not carry much
current since there are so many transistors. (typical Sub Vt Slope
value about 100 mV/decade, typical Sub Vt Swing about 6 to 12
decades of current)
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 Introduction to CMOS

SUBTHRESHOLD CHARACTERISTICS

The major parameter that affects the sub-threshold characteristics is the

distance between the gate and the carriers in the channel. The Gate
oxide thickness is one part of this distance. The other part is the
location of the carriers in the silicon. In some devices they are at the
surface (called surface channel devices) making the distance equal to
the oxide thickness only and giving the best sub-threshold
characteristics. In devices that have received an ion implanted Vt
adjust with a dopant of the opposite type from the substrate dopant the
resulting channel has a energy minimum away from the surface where
the carriers move, giving poorer sub-threshold characteristics.
Reducing gate oxide thickness improves sub-threshold characteristics.

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 Introduction to CMOS

SURFACE CHANNEL / BURIED CHANNEL FET

Whether a MOSFET requires an threshold adjust implant depends on

the details of the threshold voltage calculation, including the oxide
thickness, substrate doping, gate material work function, surface state
density, etc.
A buried channel device will result if the threshold adjust implant is the
opposite type from the substrate. The carriers will flow from source to
drain at a low energy region some small distance away from the
surface. The buried channel transistor performance is poorer.
The preference is to design the transistors to be surface channel devices.
One technique is to engineer the gate material work function by using
n+ poly gates on NMOS transistors and p+ poly gates on PMOS
transistors.
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 Introduction to CMOS

SHORT/LONG CHANNEL MOSFET

Long-channel MOSFET is defined as devices with width and

length long enough so that edge effects from the four sides can be
neglected
Channel length L must be much greater than the sum of the drain
and source depletion widths

L L L

Long Channel Device Short Long

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 Introduction to CMOS

WIDTH OF SPACE CHARGE LAYER

Built in Voltage: Ψο = 0.55 + KT/q ln (N /ni)

Width of Space Charge Layer, Wsc= [ (2ε/q) (Ψο +VR) (1/N )]1/2
W on lightly doped side:
Maximum Electric Field: Ε ο = - [(2q/ε) (Ψο +VR) (N )] 1/2

Example: L
Ψο = 0.55 + 0.026 ln (3E16/1.45E10) = 0.928

Wsc = [ (2(11.7)(8.85Ε−14)/1.6E-19) (0.928) (1/3E16 )]1/2 Leff

= 0.20 µm or 0.41µm @ VR=3V Wsc
Long Channel
Eo = - [(2(8.85E-14(11.7))(0.928+3)(3E16)]1/2 Behavior
=-1.92E5 V/cm
ε =Rochester
εo εr Institute
= 8.85E-12
of Technology (11.7) F/m
Note: Eomax = 3E5 V/cm
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8.85E-14 (11.7) F/cm
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 Introduction to CMOS

TERADA-MUTA METHOD FOR EXTRACTING Leff and Rds

Terada-Muta Method for Leff and Rds

Masured Resistance, Rm
Vg = -6
In the linear region (VD is small):
0
ID = µW Cox’ (Vgs-Vt-Vd/2) VD
Leff Vg = -8

1/Rm I D = 1/Rm VD
Leff = Lm - ∆L Vg = -10
where ∆L is correction due to processing
Lm is the mask length Rds
Lm (mask length)
Rm = VD/ID = measured resistance ∆L
= Rds + (Lm - ∆L)/ µW Cox’ (Vgs-Vt)

so measure Rm for different channel length transistors and plot Rm vs Lm

where Rm = intersect find value for ∆L and Rds
Then Leff can be calculated for each different length transistor
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from Leff = Lm - ∆L
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 Introduction to CMOS

TERADA-MUTA METHOD FOR EXTRACTING Leff and Rds

VD 1400

1200
RD 1000
Leff = Lmask – ? L
Rsd (Ohms)

800 RSD = 530 Ω Leff = 0.5 µm – 0.3 µm

600
Leff = 0.2 µm
VG VG-VT=0.5V
400
VG-VT=1.0V

RS
200
? L ~ 0.3 µm
VG-VT=1.5V
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Lmask (µm)

VS Leff & RSD extraction for NMOS Transistors

Linear Region: Rm = Vd = R SD + (Lmask- ? L)

VD= 0.1V Id µCox’W(VGS-Vt)
VG-VT >> IRochester
DR SDInstitute of Technology
At low ID, Microelectronic
VRSD small Engineering
Plot Rm vs. Lmask for different (VGS-Vt)
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 Introduction to CMOS

CHANNEL LENGTH MODULATION

Channel Length
Modulation Parameter λ NMOS
λ = Slope/ Idsat +Ids Saturation Region
Slope
Vg +5
S
Vd +4
Idsat +Vgs
+3
n n +2
p
L - ∆L Vd2 Vd1 Vd2 +Vds
L Vd1

IDsat = µW Cox’ (Vg-Vt)2 (1+ λVds) NMOS Transistor in Saturation Region

2L
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DC Model, λ is the channel length modulation
parameter and is different for each channel
length, L. Typical value might be 0.02

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 Introduction to CMOS

SUBSTRATE (WELL) DOPING

The drain and source form junctions with the substrate. The size of
the space charge layer associated with the junction depends on the
doping of the substrate. The lighter the doping the bigger the space
charge layer. In sub-micron MOSFETs the space charge layer must
be small so the substrate doping must be higher. There are tradeoffs
that make the choice of substrate doping difficult to pick for all
desirable conditions. This leads to the selection of twin well or quad
well CMOS technologies where the substrate doping can be
optimized for each type of transistor. (NMOS, PMOS, NPN, PNP)

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 Introduction to CMOS

SHORT CHANNEL EFFECT ON Vt

A Test Chip is used that includes nMOS and pMOS transistors of various lengths
from 0.1 µm to 5.0 µm and the threshold voltage is plotted versus channel length.
The threshold voltage needs to be high enough so that when the input is zero or
+Vsupply the transistor current is many decades lower than when it is on. Vt , sub-Vt
slope, sub-Vt swing and power supply voltages determine performance of MOSFETs
in CMOS circuits.
THRESHOLD VOLTAGE

NMOS
+1.0
Gate
VOLTS

0.0
PMOS
Source Drain
-1.0
Space
Space
Charge
0.1 0.5 1.0 Charge
GATE LENGTH, µm
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 Introduction to CMOS

PUNCH THROUGH AND SHALLOW JUNCTIONS

Punch-through is a condition where the space charge layers

associated with the drain and source junctions touch. The size of the
space charge layer depends on substrate doping and the value for
junction bias. To increase the drain voltage at which punch through
occurs for a MOSFET we can increase the substrate doping.

Source VD = 3, 5 volts
In addition submicron Gate
MOSFETs have better
punch-through
characteristics when the
drain and source junctions
are shallow. Space Charge
Layer at 3 and 5 volts
Substrate or Well
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 Introduction to CMOS

PUNCHTHROUGH

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 Introduction to CMOS

HOT CARRIERS, LOW DOPED DRAIN (LDD), SIDE

WALL SPACERS
For submicron channel length devices the electric field (drain source
voltage divided by the channel length) approaches 10 million V/m.
At these high electric fields the carriers have lots of energy (called
“hot”) and at these energies they can penetrate into the gate oxide
where they can cause shifts in threshold voltage. By reducing the
doping in the drain of a transistor a series drain resistance can be
created to realize a voltage drop and provide for a lower electric field
across the channel. This structure is called a low doped drain and is
often created using self aligned side wall spacers and a two step ion
implant for the drain and source.
Low Doped Silicide Side wall Spacer
Drain Gate
Field Oxide
Source Drain
Stop
P-type well P-type Punch Through Implant
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 Introduction to CMOS

CMOS INVERTER

Vin Vout Vout

+V +V
Idd Voh

Vin Vout Imax

Idd

VoL Vin
CMOS
0
TRUTH TABLE 0 +V
VIN VOUT ViL Vih
0 1
1 0 ∆ 0 noise margin = ViL - Voh
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∆ 1 noise margin = Voh - Vih
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 Introduction to CMOS

OTHER INVERTER REALIZATIONS

+V +V -V +V +V

0 0 0 0 0
0 +V 0 +V 0 -V 0 +V 0 +V
VOUT VERSUS VIN
-V +V +V
+V
+V

VIN VO VIN VO VO VO VO
VIN VIN VIN

PMOS
SWITCH ENHANCEMENT NMOS NMOS
CMOS
LOAD ENHANCEMENT DEPLETION
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 Introduction to CMOS

NOR GATE

SYMBOL TRUTH TABLE

VA VB VOUT
VA
VOUT 0 0 1
VB 0 1 0
1 0 0
1 1 0
+V V
V +V

R R
VOUT VOUT VOUT
VA VB VOUT
VA VB VA VB
SWITCH RESISTOR PMOS
LOAD LOAD VA VB
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 Introduction to CMOS

NAND GATE

SYMBOL TRUTH TABLE

VA VB VOUT
VA
VOUT 0 0 1
VB 0 1 1
1 0 1
+V V V 1 1 0
+V
R
R
VOUT
VA VOUT VOUT
VA VA
VOUT
VA
VB VB VB
VB
SWITCH RESISTOR PMOS
LOAD LOAD
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 Introduction to CMOS

P-WELL CMOS
Drain Drain

NMOS Gate Sub SYMBOL Gate Sub PMOS

Source Source
G G
S D D S

p+ n n p p n+
p
PMOS
NMOS
n CROSSECTION
+I -I
+Vg -Vg
NMOS
PMOS

+V -V
CHARACTERISTICS
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 Introduction to CMOS

P-WELL CMOS CROSSECTION

6000Å n+ Poly 6000Å CVD Ox

1 µm Aluminum

10,000Å Field Ox p+ p+ n+
p+ n+ n+
field Vt adj 8e13
p-well B11, 100KeV Bare
p+ D/S 4e15, 120 KeV
BF2 into bare silicon
n+ D/S 4e15, 100KeV Vt adj nmos 2e12, 60 KeV
P31 thru gate Oxide B11, 1000Å Kooi Vt adj pmos 5e11, 60 keV
Blanket, 1000Å Kooi
p-well 4e12, 50 keV, B11, 1123 C, 20 hr

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 Introduction to CMOS

N-WELL CMOS
Drain Drain

NMOS Gate Sub SYMBOL Gate Sub PMOS

Source Source
G G
S D D S

p+ n n p p n+
n
p NMOS PMOS
CROSSECTION
+I -I
+Vg -Vg
NMOS
PMOS

+V -V
CHARACTERISTICS
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 Introduction to CMOS

DUAL WELL CMOS

NMOS PMOS
G
S D D G S
p+ n n p p n+
p n p- epi

p substrate

CROSSECTION
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 Introduction to CMOS

BICMOS

NMOS PMOS npn Bipolar

S G D D G S B E C
p+ n n p p n+ p n+ n+
p n n
n+

p- epi
p substrate
CROSSECTION

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 Introduction to CMOS

QUAD WELL CMOS

NMOS PMOS npn Bipolar pnp Bipolar

G G
B E C C E B
S D D S
p p+ n n p p n+ p n+ n+ p p+ n+
n P
n+
n n+

p- epi
p substrate

CROSSECTION

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 Introduction to CMOS

LATCH-UP

NMOS PMOS
Vss Vdd
G G
S D D S
n n p p p n
p
R-well
vertical npn
Lateral pnp

R-Sub
n-Substrate

Sub CROSSECTION
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 Introduction to CMOS

LATCH-UP MODEL / PROTECTION

Vdd Bipolar Beta Spoiling

Increase lateral pnp base width decreasing beta
large well to active distance design rules*
R-Sub deep trench increases base width
Retrograde well reduces vertical transport
Lateral decreasing vertical npn beta
pnp
Bipolar Decoupling
vertical Reduce substrate resistance by using n- on n+ epi
npn Reduce well resistance by using buried layer
R-well Silicon on insulator technology
Guard rings reduce substrate or well resistance

Vss
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 Introduction to CMOS

REFERENCES

1. Introduction to VLSI Systems, Carver Mead and Lynn Conway,

Addison-Wesley Publishing Company, 1980.
2. Analog VLSI Design - nMOS and CMOS Malcomb R. Haskard
and Ian C. May, Prentice Hall Publishing Company.
3. Principles of CMOS VLSI Design - A Systems Perspective, Neil
Weste, and Kaman Eshraghian, Addison-Wesley Publishing
Company, 1985.
4. CMOS Analog Circuit Design, Phillip E. Allen and Douglas R.
Holberg, Holt, Rinehart and Winston Publishers, 1987.

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 Introduction to CMOS

HOMEWORK - INTRO TO CMOS

1. What is the main advantage of MOS technology over Bipolar

technology?
2. What is the main advantage of CMOS technology?
3. What is the significance of the sub threshold slope?
4. What physical parameters control the sub threshold slope?
5. What is the difference between channel length and effective
channel length?
6. Give a brief explanation for latch-up. How is latch-up
avoided in RIT’s p-well CMOS circuits?
7. Give some reasons for the selection of the following
technologies: a) p-well, b) n-well, c) dual well, d) quad well.

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