IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO.

5, MAY 2013 1861

Design of Neutral-Point Voltage Controller

of a Three-Level NPC Inverter With
Small DC-Link Capacitors
Ramkrishan Maheshwari, Member, IEEE, Stig Munk-Nielsen, Member, IEEE, and
Sergio Busquets-Monge, Senior Member, IEEE

Abstract—A neutral-point-clamped three-level inverter with

small dc-link capacitors is presented in this paper. The inverter
requires zero average neutral-point current for stable neutral–
point voltage. The small dc-link capacitors may not maintain
capacitor voltage balance, even with zero neutral-point current.
This may happen due to nonlinearities present in the circuit.
This requires a fast control of the neutral-point voltage. A simple
carrier-based modulation strategy which allows modeling of the
neutral-point voltage dynamics as a continuous function of power
drawn from the inverter is proposed. This continuous model shows
that the neutral-point current is proportional to the power drawn
from the inverter, and it enables the use of a well-established
classical control theory for the neutral-point voltage controller
design. A simple proportional integral controller is designed for
the neutral-point voltage control on the basis of the continuous
model. The design method for optimum performance is discussed.
The implementation of the proposed modulation strategy and Fig. 1. NPC three-level inverter.
the controller is very simple. The controller is implemented in a
7.5-kW induction machine-based drive with only 14 μF dc-link
capacitors. Also, the experimental results show that fast and stable able to use them [4]. These kinds of drives are referred to as
performance of the neutral-point voltage controller are achieved slim dc-link or small dc-link drives [4]. Recently, these drives
and thus verify the validity of the proposed control approach. have become commercially available with two-level inverter
Index Terms—Multilevel inverter, neutral-point-clamped (NPC) topology [5]. If a diode bridge rectifier is used as a front-end
inverter, neutral-point voltage control, pulsewidth modulation converter in the drive, the small dc-link capacitors have an
(PWM). advantage of low input line current total harmonic distortion
(THD) as compared to the THD in case of the large dc-link
I. I NTRODUCTION capacitors. A small dc-link capacitor-based NPC three-level
inverter is presented in this paper.
A NEUTRAL-POINT-CLAMPED (NPC) three-level in-
verter was proposed for high- and medium-voltage drives
[1]. Now, this topology is also used for low-voltage drive appli-
In steady state, with conventional modulation strategies, the
neutral-point current has a fundamental frequency which is
cations [2]. Fig. 1 shows the circuit diagram of the NPC three- three times the output fundamental frequency [6]. This re-
level inverter. The NPC three-level inverter with conventional quires a large dc-link capacitor value for constant neutral-
modulation was seen to require 50% higher dc-link capacitance point voltage. In addition, a neutral-point voltage control
than that of a two-level inverter for a fixed grid frequency opera- is required in order to avoid the output-voltage distor-
tion [3]. A large capacitor value requires the use of electrolytic tion and overvoltage stress on semiconductors. Different
capacitors. The high reliability of film capacitors has been a neutral-point voltage controllers are proposed in the literature
major driving force to reduce the value of capacitance and be [6]–[14], [22]–[26]. The controllers presented in [6], [11]–[14],
[22]–[26] are based on sinusoidal pulse width modulation
(PWM) or space vector PWM methods which cannot eliminate
Manuscript received September 19, 2011; revised March 26, 2012; accepted low-order harmonic component of the neutral-point current
May 9, 2012. Date of publication June 4, 2012; date of current version
January 30, 2013.
for all operating conditions. The controllers described in [6],
R. Maheshwari and S. Munk-Nielsen are with the Department of Energy [11]–[14] use the common mode offset as a control variable
Technology, Aalborg University, 9220 Aalborg, Denmark (e-mail: rkm@et. which is added to the PWM reference signals. However, low-
aau.dk; smn@et.aau.dk).
S. Busquets-Monge is with the Department of Electronic Engineering, frequency oscillations in the neutral-point voltage appear under
Technical University of Catalonia, 08034 Barcelona, Spain (e-mail: sergio. certain operating conditions, and they have to be suppressed by
busquets@upc.edu). large dc-link capacitors. If the frequency of the PWM reference
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. signal is variable, the capacitors should be selected for the
Digital Object Identifier 10.1109/TIE.2012.2202352 lowest frequency of operation. This may require very high value
0278-0046/$31.00 © 2012 IEEE
1862 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
of the dc-link capacitor. The low-frequency component in the
neutral-point current makes these techniques unsuitable for a
small dc-link capacitor-based drive.
A PWM strategy proposed in [15] ensures zero average
neutral-point current in a switching period for any load (linear
or nonlinear) over the full range of inverter output voltage and
for all load power factors, the only requirements being that
the addition of the output three-phase currents equals zero and
that the phase currents are approximately constant during the
switching period. A fast carrier-based implementation for this
PWM strategy is presented in [10]. However, it causes more
switching losses in the inverter. A hybrid PWM strategy which
uses a combination of sinusoidal PWM (SPWM) strategy and
the PWM strategy proposed in [10] is proposed in [9] to reduce
the switching losses, but the neutral-point voltage contains low-
order harmonics. This makes it not suitable for a small dc-link
capacitor-based drive.
The neutral-point voltage controllers presented in [7], [8],
and [10] are based on the modulation strategy producing zero
average neutral-point current in a switching period. The neutral-
point current contains only switching frequency components in
this case. Thus, the required dc-link capacitance is minimal.
The controllers presented in [7], [8], and [10] modify the duty
cycles of the inverter switches. The controller presented in [7]
uses an optimized virtual-vector-based modulation strategy for
low output-voltage distortion. The strategy presented in [7] re-
quires the calculation of the reference voltage vector angle and
the measurement of the inverter dc-link voltages and the output
phase currents for the neutral-point voltage control. However,
the relationship between the control variable (PWM-references
offset) and the neutral-point voltage is discontinuous, and the
criterion to design the controller was not presented.
The carrier-based implementation of the PWM strategy
which ensures zero neutral-point current presented in [10] does
not require the reference voltage vector angle. This makes the
implementation very simple. The neutral-point voltage con-
troller proposed in [10] also modifies the duty cycles. The
modified duty cycle of a phase depends on the sign of the
neutral-point voltage variation times the phase current. This
makes the controller discontinuous and nonlinear. The criterion
for the determination of the controller parameters is also not
discussed. An optimal controller based on the modulation strat-
egy presented in [10] was developed in [8], but it requires the
information of the output currents, the modulation index, the
carrier frequency, the dc-link capacitor values, and the dc-link
voltages. This controller guarantees stability under all operating
conditions, but it requires high computational effort for the
controller.
A small dc-link capacitor-based NPC three-level inverter
needs zero average neutral-point current in a switching period.
A suitable modulation strategy, similar to the PWM strategies
presented in [10] and [15], is selected for meeting this require-
ment. This strategy is discussed in Section II. Since a small
disturbance in the neutral-point current may drift the neutral-
point voltage in a few switching periods because of low energy
stored in the dc-link capacitors, a fast and stable controller for
the neutral-point voltage is required. In Section III, a new first-
order model of the neutral-point voltage dynamics is discussed,
and it is based on a continuous equation. The model was re-
cently presented in [16]. With this new model, classical control
theories can be applied to design the controller for the neutral-
point voltage. As an addition to [16], the controller design
is presented in Section IV. A simple proportional integral
(PI) controller is used in this paper to control the neutral-
point voltage. The considerations required to implement the
PWM strategy for a small dc-link capacitor-based inverter are
discussed in Section V, and they are also addition to [16]. The
implementation of the proposed controller with the modulation
strategy only requires the information of the sensed dc-link
voltages and the PI controller parameters. It does not require
the output phase current information and the reference voltage
vector angle. The controller is tested with a 7.5-kW induction
machine drive. The neutral point is realized by the midpoint
of two series-connected 14 μF capacitors. The experimental
results which verify the fast dynamics of the controller are
presented for this drive in Section VI.
II. C ARRIER -BASED PWM FOR Z ERO
N EUTRAL -P OINT C URRENT
The three-phase normalized per unit reference signals for
SPWM can be given by
vA,ref = m · cos(ωs t)
vB,ref = m · cos(ωs t − 2π/3)
vC,ref = m · cos(ωs t − 4π/3) (1)
for a given modulation index (m) and frequency (ωs ). vdc1 and
vdc2 are the voltages of the top and bottom dc-link capacitors
as shown in Fig. 1. In steady state, vdc1 and vdc2 are equal and
denoted by vdc . The modulation index is defined as
√
vo 2
m=
vdc
where vo is the rms value of the fundamental component of
an inverter output phase voltage. In every switching cycle, the
reference signals can be classified as vmax , vmid , and vmin ,
and they correspond to the reference signals representing the
maximum, middle, and minimum values
vmax = max(vA,ref , vB,ref , vC,ref )
vmid = mid(vA,ref , vB,ref , vC,ref )
vmin = min(vA,ref , vB,ref , vC,ref ). (2)
The carrier-based implementation of SPWM uses two carrier
waves [17]. Fig. 2 shows the relationship between each ref-
erence signal and the duty cycle of the corresponding output
phase voltage. If the reference signal is positive, it is compared
with carrier waveform 1; on the other hand, if the reference
signal is negative, it is compared with carrier waveform 2. Ts
represents the time period of one switching cycle. vAO , vBO ,
and vCO denote the voltages of the output phases A, B, and C
with respect to the neutral point of the NPC three-level inverter.
MAHESHWARI et al.: NEUTRAL-POINT VOLTAGE CONTROLLER OF A NPC INVERTER WITH DC-LINK CAPACITORS 1863

Fig. 3. Modified phase voltage with middle voltage value.

Using (4) and (5), for SPWM, the average neutral-point

current io T s can be given as
Fig. 2. PWM duty cycle generation.
io Ts = −(|vmax | · ivmax +|vmid | · ivmid +|vmin | · ivmin ). (6)
The average values of the output phase voltages in a switching
period can be expressed as The average neutral-point current for SPWM is a function
of the reference signals and the output currents of the NPC
vAO Ts = m · vdc · cos(ωs t) inverter, and it is, in general, different from zero. To achieve
zero average neutral-point current, the duty cycles should be
vBO Ts = m · vdc · cos(ωs t − 2π/3)
modified without affecting the line-to-line output voltages. First
vCO Ts = m · vdc · cos(ωs t − 4π/3) (3) of all, zero average neutral-point current in every Ts can be
obtained for all loading conditions only if the phase having
T s denotes the average value of a particular variable over time the middle voltage value is connected to positive (P), negative
Ts . It is assumed that the dc-link voltage (vdc ), the output phase (N), and neutral-point (O) of the dc-link [15]. This requires four
currents, and the reference signals are not varying in a switching switching transitions instead of two for the phase in a switching
period. If the sum of the output phase currents is equal to period as shown in Fig. 3. In addition, a common mode offset
zero, the neutral-point current averaged over a switching period (vc ) needs to be added to the SPWM reference signals. Since
io T s can be given by the phase having middle voltage value requires four transitions,
it switches from N to O and O to P and vice versa in a switching
io Ts = −(dmax p + dmax n ) · ivmax − (dmidp + dmidn ) period. This requires two nonzero reference signals (vmidp and
·ivmid − (dmin p + dmin n ) · ivmin (4) vmidn ) to achieve the waveform pattern as shown in Fig. 3. The
phase having the maximum voltage value switches between
where d denotes the duty cycle for a particular phase; max, mid, O and P, while the phase having the minimum voltage value
and min subscripts represent the phase having maximum, mid- switches between N and O in a switching period, and they need
dle, and minimum fundamental voltage values, respectively; p only one nonzero reference signal each.
and n subscripts indicate that the phase is connected to the pos- The modified reference signals for a carrier-based implemen-
itive (P) and negative (N) terminals of the dc-link, respectively; tation of the PWM with zero average neutral-point current are
e.g., dmax p represents the duty cycle of the phase having the given by
maximum voltage value and connected to positive terminal (P)
m m
of the dc-bus. iv max , ivmid , and iv min are the phase currents vmax p = vmax + vc , vmax n =0
which have the maximum, middle, and minimum fundamental m v mid m vmid
vmidp = + vc1 , vmidn = + vc2
voltage values, respectively. 2 2
m m
For the carrier-based SPWM, the duty cycles in a switching vmin p = 0, vmin n = vmin + vc (7)
period can be given by
where vc1 + vc2 = vc (to add the same common mode offset to
dmax p = vmax all three-phases). Superscript “m” denotes a modified variable.
dmax n = 0 vc1 and vc2 are the common mode offsets added to the two
dmidp = vmid reference signals of the phase having the middle voltage value.
, if vmid > 0 Using (7), the modified duty cycles are given by
dmidn = 0

dmidp = 0 dm dm
, if vmid < 0 max p = vmax + vc , max n = 0
dmidn = −vmid v v 
mid mid
dmin p = 0 dm
midp = + vc1 , dmmidn = − + vc2
2 2
dmin n = −vmin . (5) dmmin p = 0, min n = −(vmin + vc ).
dm (8)
1864 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013

strategy are the same as that of the nearest three virtual space
vector PWM proposed in [15]. A fast carrier-based imple-
mentation of this modulation strategy which is similar to the
carrier-based implementation of the PWM given by (12) was
proposed in [10]. The main advantage of this implementation is
its simplicity and maximum utilization of the modulation index
in the linear range to achieve io T s = 0.

III. M ODEL OF N EUTRAL -P OINT VOLTAGE DYNAMICS

Fig. 4. Reference signals of phase A for carrier-based implementation to
achieve io Ts = 0(m = 1.1547).
To calculate the neutral-point current for the PWM strategy
with modified reference signals, (4) and (8) are used. The
average neutral-point current is given as
io Ts = −(vmax + vc ) · ivmax − (vc1 − vc2 ) · ivmid
+(vmin + vc ) · ivmin .
It can be seen from (9) that there is no neutral-point current
term because of vmid since vc1 and vc2 are added to half of
vmid to obtain the duty cycles dm m will be used as a control variable for the neutral-point voltage
midp and dmidn . For a three-
phase three-wire system, iv max + ivmid + iv min = 0. Using
this relationship, (9) can be simplified as
io Ts = (−vmax −2vc2 ) · ivmax +(vmin +2vc1 ) · ivmin .
The modified reference signals given by (12) ensure the zero
average neutral-point current in a switching period under ideal
conditions of high inductive load, ideal switching devices, etc.
The nonidealities of the components, transients, etc., may cause
the neutral-point voltage variation. A closed-loop controller
is required to maintain the neutral-point voltage balance. To
design a neutral-point voltage controller, a model describing the
dynamic behavior of the neutral-point voltage is required.
It is shown in the previous section that zero average neutral-
point current can be achieved if the common mode offsets given
by (11) are added to the reference signals for SPWM and the
phase having the middle voltage value has four transitions in
(9)
the switching period. The carrier-based implementation of the
PWM with zero neutral-point current is extended in this section
to gain the neutral-point voltage control. A new factor k which
controller is introduced. The reference signals for carrier 1 are
made proportional to k, and the reference signals for carrier 2
are proportional to (1 − k). Using this, the modified phase
(10) reference signals are given as

p =k · (vmax − vmin ), vmax n = 0

m m
The zero average neutral-point current condition (io T s = vmax
0) can be achieved by different values of vc1 and vc2 . One set vmidp =k · (vmid − vmin ), vmidn = −(1 − k) · (vmax − vmid )
m m

p =0, vmin n = −(1 − k) · (vmax − vmin )

m m
of possible and simple choice of vc1 and vc2 is given by vmin (13)
vmin
vc1 = − and the duty cycles are given as
2
vmax
vc2 = − max p = k(vmax − vmin ),
dm dm
max n = 0
2
vmid dmidp = k(vmid − vmin ), dm
m
midn = (1 − k)(vmax − vmid )
⇒ vc = (11)
2 dmmin p = 0, min n = (1 − k)(vmax − vmin ).
dm (14)
and the modified reference signals are given by It can be seen from (13) that the factor k is applied in such a way
m (vmax − vmin ) that the line-to-line voltages are not changed. This ensures that
vmax p = the fundamental component of the line-to-neutral voltages of
m
2
vmax n =0 the load remain unchanged. As a check, the line-to-line voltage
m (vmid − vmin ) between the phase having the maximum voltage value and the
vmidp =
2 phase having the middle voltage value can be derived as
(vmax − vmid )  m   m 
m
vmidn =−
n − vmidp + vmidn
m m
2 vmax p + vmax
m
vmin p =0 = k(vmax −vmin )−k(vmid −vmin ) + (1−k)(vmax −vmid )
(vmax − vmin ) = vmax −vmid . (15)
m
vmin n =− . (12)
2
In this case, the common mode offsets added to the reference
The modified reference signals for phase A are shown in
signals for SPWM are the functions of k as given by
Fig. 4 for the modulation index 1.1547. The reference phase
signals for other phases will be shifted in phase by 2π/3 and vc1 = − k · vmin
4π/3 radians. It can be seen from Fig. 4 that the maximum vc2 = − (1 − k) · vmax . (16)
modulation index achieved in the linear range is 1.1547 which
is equal to the maximum modulation index achieved by space Since the reference signals for the PWM are the function of
vector PWM [18]. The reference signals for this modulation the factor k as given by (13), the average neutral-point current
MAHESHWARI et al.: NEUTRAL-POINT VOLTAGE CONTROLLER OF A NPC INVERTER WITH DC-LINK CAPACITORS 1865

Fig. 6. Neutral-point voltage controller block diagram.

introduced in the dc operating point values. The dc operating

point values are represented by capital letters. Therefore,

pTs = P + p̃
vdc = Vdc + ṽdc
Δvdc Ts = ΔVdc + Δṽdc
Fig. 5. Equivalent circuit diagram of the dc-link in the NPC three-level k = K + k̃. (19)
inverter.
The steady-state solution of (18) can be given by
will also be a function of the factor k. From (4) and (14), an
expression for the neutral-point current is derived as K = 0.5. (20)

io Ts =−k(vmax −vmin )·ivmax −(1−k)(vmax −vmin )·ivmin Using (18)–(20)
−(k.(vmid −vmin ) + (1−k)(vmax −vmid ))·ivmid d 2P
Cdc · (Δṽdc ) = − k̃. (21)
io Ts = − k·(vmax −vmin )·ivmax + (1−2k)·vmid ·ivmid dt Vdc
+ (−k·vmin + (1−k)·vmax )·(ivmax + ivmin ) Equation (21) is the linearized small signal model, and it is an
−(1−k)·(vmax −vmin )·ivmin equation of a first-order system. It shows that the dynamics of
io Ts =(1−2k)(vmax ·ivmax + vmin ·ivmin + vmid ·ivmid ) the neutral-point voltage depends on the factor k. Equation (21)
1−2k can be used as a plant model to design the neutral-point voltage
io Ts = pTs (17) controller based on classical control theories which require the
vdc
transfer function of the plant. Using Laplace transformation of
where p is the inverter output power. Equation (17) shows that (21), the transfer function of the plant, i.e., the transfer function
the neutral-point current is proportional to the inverter output of the control variable k to the output Δ vdc , is given by
power. If k = 0.5, the reference signals given by (13) will be 
Δṽdc (s) 2P 1
the same as the reference signals given by (12), and the average Gvk (s) = =− . (22)
k̃(s) V dc · C dc s
neutral-point current will be zero.
Since the neutral-point voltage variation depends on the The transfer function is proportional to the inverter output
neutral-point current, a model for the neutral-point voltage power. If the power changes, the plant transfer function will
dynamics can be obtained as a function of the factor k. This change. Vdc can be assumed constant since it is determined by
requires an equivalent circuit diagram of the dc-link which is the grid supply voltage.
shown in Fig. 5. The current flowing through the dc-link ca-
pacitors are given by idc1 and idc2 . By applying the Kirchoff’s
Current Law at node O, the average dc-link capacitor voltage IV. C ONTROLLER FOR N EUTRAL -P OINT VOLTAGE
variation in Ts (Δvdc Ts ) can be derived as A high-performance neutral-point voltage controller is re-
quired for the small dc-link capacitor-based NPC three-level
idc1 Ts − idc2 Ts = io Ts inverter. The average neutral-point current can be controlled by
d   1 − 2k changing the factor k which in turn controls the neutral-point
Cdc · vdc1 Ts − vdc2 Ts = pTs
dt vdc voltage. The factor k will be used as a control variable.
d   1 − 2k
Cdc · Δvdc Ts = pTs . (18) The new first-order model of the average neutral-point volt-
dt vdc age variation is given by (21). Classical linear control theories
The dc-link capacitor voltage variation is a continuous func- can be used to design a fast and stable controller using this
tion of the inverter output power, the factor k, and the dc- model. A simple PI controller is used in this paper. The block
link voltage, but it is a nonlinear function. Hence, a linearized diagram of the controller is given in Fig. 6. The transfer
model describing the behavior of the neutral-point voltage function given by (22) can be used to select the PI controller
dynamics for small ac perturbations about a dc operating point parameters.
should be derived. The model can then be treated as a linear The transfer function of the PI controller is given by
system, and linear control theories can be applied. To derive the 1+s·T
linearized model, small ac perturbations represented by “∼” are Gc (s) = Kp (23)
s·T
1866 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Fig. 7. Bode plot of plant, controller, and open-loop transfer function.
where Kp is the proportional gain, and T is the integral time of
the controller.
Using (22) and (23), the open-loop transfer function of the
neutral-point voltage control system is given by
1+s · T 2P
GOL (s) = Gc (s).Gvk (s) = −Kp . (24)
s · T Vdc · Cdc · s
The open-loop transfer function given by (24) can be inter-
preted as a multiplication of two terms; (1 + s · T )/s · T and
(−2Kp · P/(Vdc · Cdc · s)). The gain crossover frequency of
the open-loop transfer function is decided by the term (−2Kp ·
P/(Vdc · Cdc · s)) if T is chosen such that it does not affect
the gain crossover frequency. Therefore, the gain crossover
frequency of the open-loop transfer function is given by
2Kp P
ωc = − . (25)
Vdc · Cdc
From (25), Kp can be given by
Vdc · Cdc
Kp = −ωc . (26)
2P
The PI controller parameters are selected for the maximum
output power condition. The bode plots of the plant (Gvk (s)),
the controller (Gc (s)), and the open-loop (GOL (s)) transfer
functions are shown in Fig. 7. The value of Kp is chosen
in such a way that the gain crossover frequency (ωc ) of the
open-loop transfer function is 1 kHz which corresponds to
one tenth of the switching frequency (10 kHz). The maximum
output power corresponds to the maximum value of ωc . If the
power is reduced, ωc will reduce for a given Kp . If Kp was
selected for the minimum output power condition, ωc could
then become higher than the switching frequency at full-load
condition which is not recommended.
The integral time (T ) of the PI controller is the inverse of
the corner frequency of the PI controller. This corner frequency
should be lower than ωc to have high phase margin for the
whole operating range. The corner frequency of the PI con-
troller is chosen as 2π · 50 rad/s. This will ensure that even if
the minimum output power is reduced to 10% of the maximum
output power, i.e., ωc corresponds to 100 Hz at the minimum
output power, the corner frequency of PI controller will be
lower than the gain crossover frequency (ωc ) of the open-loop
transfer function (GOL (s)). In this way, T does not affect ωc .
Fig. 8. Circuit diagram of the NPC inverter-based drive with small dc-link
capacitors.
The factor k is the control variable, and it is equal to the
output of the PI controller. The PI controller output should be
limited since the control variable k decides the duty cycles
of the switches in the inverter. The maximum and minimum
limits of the PI controller output are given by kmax and kmin .
The control variable k should be limited in such a way that
the reference signals for carrier 1 be between 0 and 1 and the
reference signals for carrier 2 be between 0 and −1 to ensure
PWM operation in the linear range. From (13), the limits for the
controller output are given by

1
kmax = min ,1
vmax − vmin

1
kmin = max 1 − ,0 . (27)
vmax − vmin
V. S MALL DC-L INK C APACITOR -BASED I NVERTER
The drive system under consideration is shown in Fig. 8
where a six-pulse diode bridge rectifier is used as the front-
end converter, and the machine used in the drive system is
an induction machine. The diode bridge rectifier generates
300-Hz dc-link voltage ripple. This requires big dc-link capac-
itors to maintain a constant dc-link voltage. Typically, the dc-
link capacitor is sized in such a way that the dc-link LC filter
cutoff frequency will be less than 300 Hz. In that case, the
capacitor has a value in the order of a few mF, and electrolytic
capacitors are required. Moreover, the input supply current
has high THD if the rectifier has large dc-link capacitors. To
improve the input supply current THD, the dc-link capacitor
value is reduced [20]. Film capacitors are used as the dc-link
capacitors which improve the reliability of the drive system
as well. In this case, the dc-link voltage contains the 300-Hz
ripple, and the minimum and maximum values of the dc-link
voltage are given by
π  3√
min (vdc1 (t) + vdc2 (t)) ≈ vl,peak cos = 2 · vg
6 2
√
max (vdc1 (t) + vdc2 (t)) ≈ vl,peak = 6 · vg (28)
where vl,peak is the amplitude of the grid line-to-line voltage
and vg is the rms value of the grid line-to-neutral voltage.
The voltage drop across the dc-link inductor is neglected for
simplicity.
MAHESHWARI et al.: NEUTRAL-POINT VOLTAGE CONTROLLER OF A NPC INVERTER WITH DC-LINK CAPACITORS 1867

Fig. 9. Block diagram of the drive system with controller.

A space vector PWM strategy for a small dc-link capacitor- TABLE I

I NDUCTION M ACHINE R ATINGS
based two-level inverter is proposed in [20] where the modula-
tion index is time varying and determined by the dc-link voltage
in every switching period in order to get a sinusoidal output
voltage. The maximum modulation index corresponds to the
minimum dc-link voltage avoiding the overmodulation region
in this case. This limits the maximum achievable output voltage
of the inverter. As an example, for 230 Vrms grid line-to-neutral
The maximum rms value of the fundamental component of
voltage, the maximum rms value of the fundamental component
the inverter output phase voltage is increased to 220 V in the
of the inverter output phase voltage for the modulation index of
linear range. The small dc-link capacitor-based inverter im-
1.1547 can be given as
√ proves the input supply current THD, but this modulation strat-
min(vdc1 + vdc2 ) 1.1547 3 · vg egy causes low-order harmonics at the inverter output voltage
vo,max = √ = = 200 V. (29) which in turn causes low-order harmonics in the machine phase
2 2 2
currents. The machine acts as an inductor at those harmonic
The maximum rms value of the fundamental component of frequencies, and the impedance offered by the machine is equal
the inverter output phase voltage can be increased if the modu- to the sum of leakage inductances [21].
lation index is kept constant. If the resistive drop of the dc-link The three-level inverter with stiff dc-link voltage is compared
choke is neglected, the average value of vdc will be equal to half with the small dc-link capacitor-based inverter in terms of the
of the average value of the rectifier output voltage as given by machine current harmonics and the input supply current THD
√
3 6 in the next section. The small dc-link capacitor-based inverter
Vdc = vg . (30) has low stored energy in the dc-link capacitors, and a high-
2π
performance neutral-point voltage controller is required. The
If the dc-link voltage ripple is denoted by vdch , the dc-link performance of the controller is also verified experimentally in
voltage can be given as the next section.
vdc = Vdc + vdch . (31)
Substituting (31) in (3) VI. E XPERMENTAL R ESULTS
The block diagram of the drive system is shown in Fig. 9.
vAO Ts = m · (Vdc + vdch ) · cos(ωs t)
The rms value of the grid line-to-neutral voltage is 230 V which
vBO Ts = m · (Vdc + vdch ) · cos(ωs t − 2π/3)
corresponds to Vdc = 269 V. The induction machine is rated for
vCO Ts = m · (Vdc + vdch ) · cos(ωs t − 4π/3). (32)
7.5-kW power as the shaft output power. This requires an output
Since m · vdch has an average value equal to zero, the rms power of the three-level inverter of P = 8.7 kW approximately.
value of the inverter output voltage is given by The rating of the induction machine is given in Table I. The
three-level inverter is realized using SEMIKRON IGBT module
Vdc
vo = m √ . (33) SK30MLI066. Each module has four IGBTs and six diodes
2 required for one leg of an NPC three-level inverter.
Substituting (30) and m = 1.1547 in (33) The dc-link capacitors used in the inverter are 14 μF each.
√ The drive is controlled using open-loop V /f control. The
3 6 3 maximum modulation index of 1.1547 is used at 50-Hz ma-
vo,max = 1.1547 √ vg = vg = 220 V. (34)
2 2π π chine supply frequency. The experimental results are shown for
1868
Fig. 10. vdc1 , vdc2 , machine phase current (iA ), and machine L-L voltage (vAB ) for ωc = 2π · 500 rad/s and 14 μF dc-link capacitors. (a) Induction machine
at no load. (b) Induction machine at 7.5-kW output mechanical power.
Fig. 11. vdc1 , vdc2 , machine phase current (iA ), and machine L-L voltage (vAB ) for ωc = 2π · 1000 rad/s and 14 μF dc-link capacitors. (a) Induction machine
at no load (b) Induction machine at 7.5-kW output mechanical power.
2π · 500-rad/s and 2π · 1000-rad/s gain crossover frequencies
of the open-loop transfer function at the maximum power
(P = 8.7 kW). Using (26), the values of Kp are calculated as
−0.0007 and −0.0014 for 2π · 500-rad/s and 2π · 1000-rad/s
gain crossover frequencies, respectively. The integral time (T )
of the controller is chosen as 1/(100π) as discussed in the
previous section.
Fig. 10(a) and (b) shows the dc-link voltages (vdc1 , vdc2 ),
the induction machine line current (iA ), and the machine line-
to-line voltage (vAB ) at no load and full load at the induction
machine output. The results shown in Fig. 10 correspond to
Kp = −0.0007. This is selected to obtain the gain crossover
frequency (ωc ) corresponding to 500 Hz at full load. The low
value of ωc corresponds to the high time constant of the closed-
loop transfer function [19]. It can be seen from Fig. 10 that vdc1
and vdc2 are not equal, and it affects the machine input voltage
harmonics which causes 1.9% machine phase current weighted
THD (WTHD) at full load.
The response of the drive system for 2π · 1000-rad/s gain
crossover frequency (ωc ) at the maximum power is shown in
Fig. 11 with Kp = −0.0014. Fig. 11(a) and (b) shows the dc-
link voltages (vdc1 , vdc2 ), the induction machine line current
(iA ), and the machine line-to-line voltage (vAB ) at no load and
full load at the induction machine output. It can be seen that this
choice of Kp = −0.0014 provides a good performance with the
neutral-point voltage balance in the whole power range. The
waveforms for the dc-link voltages (vdc1 , vdc2 ) are equal in
this case, and the induction machine phase current WTHD is
reduced to 1.2% at full load.
The current harmonics in the induction machine depend
on the voltage harmonics applied to the machine and the
impedance offered by the machine which is equal to the leakage
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
Fig. 12. vdc1 , vdc2 , machine phase current (iA ), and machine L-L voltage
(vAB ) for ωc = 2π · 1000 rad/s with induction machine at 7.5-kW output
mechanical power and 3.3-mF dc-link capacitors.
inductances of the machine at those frequencies [21]. Since the
voltage harmonics and the leakage inductances do not change as
the load increases, the current harmonics will also not change.
Since the fundamental current value is lower at no load, the
WTHD at no load increases to 3.3%.
Figs. 10 and 11 show that the 300-Hz ripple exists in the dc-
link voltages because of an equivalent 7 μF dc-link capacitor
(series combination of two 14 μF capacitors) and 200 μH dc-
link choke. This corresponds to the dc-link LC filter cutoff
frequency of 4 kHz. To compare the performance of this
inverter with the inverter having stiff dc-link voltage, the dc-
link capacitor value is changed to 1.65 mF (series combination
of two 3.3-mF capacitors) without changing the dc-link choke.
This corresponds to the dc-link LC filter cutoff frequency of
275 Hz. The dc-link voltages (vdc1 , vdc2 ), the induction ma-
chine line current (iA ), and the machine line-to-line voltage
(vAB ) at full load are shown in Fig. 12. The machine current
waveform is less distorted because the low-order harmonics
are not present in the machine voltage. The machine current
MAHESHWARI et al.: NEUTRAL-POINT VOLTAGE CONTROLLER OF A NPC INVERTER WITH DC-LINK CAPACITORS
Fig. 13. Input phase current (is1 ) and machine L-L voltage (vAB ) with induction machine at 7.5-kW output mechanical power. (a) Cdc = 3.3 mF.
(b) Cdc = 14 μF.
TABLE II
I NPUT L INE C URRENT THD AND O UTPUT M ACHINE
C URRENT WTHD AT 7.5-kW O UTPUT P OWER
WTHD is reduced to 0.9% which is mainly caused by the
switching frequency harmonics. On the other hand, the input
line current waveform is deteriorated as shown in Fig. 13(a)
with 104% input supply current THD. Fig. 13(b) shows the
input line current and the output line-to-line voltage waveform
of the drive system at full-load condition with 14 μF dc-link
capacitors. The input supply current THD is 29.6% for 14 μF
dc-link capacitors. The input supply current THD and the
machine current WTHD are given in Table II.
The results shown in Figs. 10 and 11 are performed with
30 kΩ resistances across the dc-link capacitors as shown in
Fig. 9. To show the dynamic performance of the neutral-
point voltage controller, an unbalance in the dc-link voltages
is created by changing 30 to 25 kΩ across the bottom dc-link
capacitor which creates a voltage difference of 50 V between
the two dc-link voltages. The response of the dc-link voltages
for different choices of Kp are shown in Fig. 14. Fig. 14(a)
shows the response for Kp = −0.0007. A high overshoot, be-
cause of low crossover frequency, causes the overvoltage across
the bottom dc-link capacitor and the inverter is switched off.
Fig. 14(b) shows the response for Kp = −0.0014. The dc-link
voltage balance is achieved within 24 ms after the controller
is turned on. The controller is turned on with the induction
machine at no load since there is no current controller for
the induction machine. This condition corresponds to low gain
crossover frequency (ωc ) for a given Kp . A faster response to
balance the dc-link voltages can be achieved by using a higher
absolute value of Kp as shown in Fig. 14(c) for Kp = −0.0028.
The dc-link balance is achieved within 12 ms in this case
with reduced overshoot. A higher absolute value of Kp is not
used to improve the response further because it corresponds
to very high bandwidth of the open-loop transfer function
(GOL (s)) at the maximum power which is not recommended.
The response of the neutral-point voltage controller can be
improved by changing the PI controller gain. If an online tuning
of the PI controller as a function of power is used, an optimal
1869
performance can be achieved in the whole operating range, but
it needs more computation in a switching period.
The transient performance of the small dc-link capacitor-
based drive is shown in Figs. 15 and 16. The dc-link voltages,
the machine current (iA ), and the machine line-to-line voltage
(vAB ) are shown in Fig. 15 during startup. The machine
supply frequency is varied in such a way that the machine
draws current equal to rated full-load current of the inverter.
Fig. 15 shows the frequency variation from 15 to 45 Hz. This
also demonstrates the performance of the neutral-point voltage
controller for varying frequency and transients. The controller
is able to maintain the neutral-point voltage balance. A step
change in the load is done by exciting the field winding of a
separately excited dc machine which is used as the load to the
induction machine. Since it is not a high-performance drive,
the induction machine current varies from no load to full load
in approximately 2 s as shown in Fig. 16. The neutral-point
voltage controller is also able to maintain the neutral-point
voltage balance in this case.
VII. C ONCLUSION
An NPC three-level inverter with small dc-link capacitors
is presented in this paper. The inverter utilizes a modulation
strategy with zero average neutral-point current in a switching
period. A new model describing the dynamics of the neutral-
point voltage is proposed. This simplified model shows that the
neutral-point current is proportional to the output power of the
inverter. A methodology to design the neutral-point voltage PI
controller is presented. The controller output is used to calculate
the modified reference signals. The modified reference signals
are used for carrier-based implementation of the modulation
strategy. The proposed controller does not require the infor-
mation of output phase current. The controller performance is
verified experimentally for a 7.5-kW induction machine-based
drive with only 14 μF dc-link capacitors. The experimental
results show the operation of the drive at maximum modula-
tion index of 1.1547. The experimental results show that the
controller is able to maintain balanced capacitor voltages with
10-kHz switching frequency in the presence of 300-Hz ripple
of the dc-link voltages caused by a six-pulse rectifier. It is also
shown that the small dc-link capacitor-based inverter improves
the line current THD, but the proposed modulation strategy
causes low-order harmonics in the machine current since av-
erage dc-link voltage is used for duty cycle calculation. The
1870
Fig. 14. vdc1 , vdc2 response under unbalance. (a) Kp = −0.0007. (b) Kp = −0.0014. (c) Kp = −0.0028.
Fig. 15. vdc1 , vdc2 , machine phase current (iA ), and machine L-L voltage
(vAB ) during a start-up transient.
Fig. 16. vdc1 , vdc2 , machine phase current (iA ), and dc machine field
voltage for a step change in load.
performance for dc-link unbalance condition is also studied
for different gains of the PI controller. A fast settling time is
achieved with the higher absolute gain.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013
The simple implementation of the controller and modulation
strategy presented in this paper requires minimal computation.
The presented neutral-point voltage controller is verified for a
small and big dc-link capacitor-based drive, and it shows that
the approach is very general. It can be used for any NPC three-
level inverter in other applications, e.g., for a grid connected
three-level NPC inverter.
ACKNOWLEDGMENT
The authors gratefully acknowledge H. Kragh, P. M. Obel,
B. Henriksen, N. H. Petersen, and T. Kvisgaard from Grundfos
A/S, Bjerringbro, Denmark for their support during the work.
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Ramkrishan Maheshwari (S’10–M’11) was born
in Allahabad, India. He received the M.E. degree
in electrical engineering from the Indian Institute of
Science (IISc), Bangalore, India, in 2005.
From 2005 to 2008, he was with Honeywell Tech-
nology Solution Lab, Bangalore, India. Currently,
he is a Postdoc in the Department of Energy Tech-
nology, Aalborg University, Aalborg, Denmark. His
research interests include modeling and control of
power converters.
Stig Munk-Nielsen (S’92–M’97) received the M.Sc.
and Ph.D. degrees from Aalborg University, Aalborg,
Denmark, in 1991 and 1997, respectively.
Currently, he is with the Department of Energy
Technology, Aalborg University. Over the last 10
years, he has been involved in or managed 12
research projects including national and European
commission projects. He holds patents on resonant
converters. His current research interests include
hard switching and soft switching converters, rec-
tifiers, inverters, reliability, LED technology, dc/dc
converters, and testing and modeling of transistors and diodes.
Sergio Busquets-Monge (S’99–M’06–SM’11) was
born in Barcelona, Spain. He received the B.S. and
Ph.D. degrees in electrical engineering from the
Technical University of Catalonia (UPC), Barcelona,
Spain, in 1999 and 2006, respectively, and the M.S.
degree in electrical engineering from Virginia Poly-
technic Institute and State University, Blacksburg, in
2001.
From 2001 to 2002, he was with Crown Audio,
Inc. Currently, he is an Associate Professor with
the Department of Electronic Engineering, UPC. His
research interests include multilevel conversion and converter integration.