86 Gbit=s SiGe receiver module with high
sensitivity for 160
86 Gbit=s DWDM
system
U. Dümler, M. Möller, A. Bielik, T. Ellermeyer,
H. Langenhagen, W. Walthes and J. Mejri
A 86 Gbit=s SiGe receiver chip with an on-chip phase-locked loop and
a preamplifier is presented. The chip is mounted and measured in a
module assembly with RF-connectors. At the intended system data
rate of 86 Gbit=s bit-error-free operation at a high input sensitivity of
50 mVpp is demonstrated. With an external clock, high-speed capabil-
ity is proven by error-free operation up to 100 Gbit=s.
Introduction: In this Letter we report on a 86 Gbit=s receiver module
intended for use in a 12.8 Tbit=s DWDM system (160
86 Gbit=s).
The system represents an intermediate step in the German research
programme MultiTeraNet, that aims to exhaust the high inherent fibre
bandwidth in excess of 50 Tbit=s. The circuit is realised in a SiGe
laboratory technology with ft=fmax ¼ 200=350 GHz [1] and assembled
in a simple RF-module. To the best of our knowledge, 86 Gbit=s is a
record data rate for an integrated receiver with an on-chip phase-
locked loop (PLL) and clock- and data-recovery in any semiconductor
technology.
Circuit description: Fig. 1 shows the block diagram of the receiver
chip, which was already successfully applied to a 40 Gbit=s receiver
design but without an on-chip PLL [2]. All high-frequency circuit
blocks as well as all I=Os are carried out in differential current-mode
logic.
Fig. 1 Block diagram of receiver chip
At the input, a high-sensitivity 50 O preamplifier with adjustable
threshold is used for distributing the data to the three MS-D-FFs of the
1:2 Demux and the bang-bang phase-detector (PD) circuit. The PD
utilises the Demux and consists of one additional MS-D-FF and two
symmetrical EXOR gates. It drives a charge pump circuit that controls
within the PLL loop the on-chip 43 GHz VCO. For the charge pump
filter, an external RC series connection is used to allow fine-tuning of
the PLL corner frequency. The RC network is connected directly to the
internal charge pump ground rather than to external ground. This avoids
introduction of supply voltage noise into the PLL loop. Other clock
frequencies, e.g. 50 GHz, can be applied to the external-clock input, but
without on-chip PLL functionality. 90 clock phase splitting, required
for the PD functionality, is realised by using the delay of a clock buffer
circuit. Additional phase adjustment is obtained by summing this
delayed and the original clock at adjustable amplitudes. The same
adjustable delay element is placed in the 0 clock path (see Fig. 1) in
order to compensate for commonly introduced delay deviations in both
paths, e.g. owing to temperature change. The delay adjustment allows
optimisation of the data sampling phase via a phase adjustment input.
The sampling phase can be monitored and adaptively adjusted using the
output signal of an additional clock phase detector.
Line driver design considerations: Well-known design aspects [3]
have been considered in chip design. Special care has been taken for
on-chip distribution of high-speed data and clock signals between the
functional blocks in Fig. 1. Most critical data lines are L1 ¼ 150 mm at
the input, and three times L2 ¼ 280 mm at the output of the input
buffer. To save power and increase bandwidth, open-collector current
switches are used to drive differential microstrip lines with the highest
ELECTRONICS LETTERS 5th January 2006 Vol. 42 No. 1
possible characteristic impedance of Z0 ¼ 65 O, given by the
technology. The choice of the termination resistance at the input of
the driven circuits, is a trade-off between high bandwidth and low
driver power. For a given input voltage level, power can be saved with
termination resistances higher than Z0. However, this results in a low
bandwith that can be increased by choosing the termination resis-
tances lower than Z0. Therefore, in the present design, the best trade-
off was obtained by terminating the microstrip lines with Z0.
This optimisation applies in particular also to the 43 GHz clock tree,
where a path from the VCO to the MS-D-FF inputs is 2 mm length in
total. Here, offset is a critical issue, since a path incorporates a lot of
cascaded components, each with a high-frequency gain usually smaller
than DC-gain. Thus, along the path, offset rises significantly compared
to clock amplitude. Owing to offset, the amplifying differential circuits
are biased unsymmetrically. This reduces their high-frequency gain
further and introduces additional offset. The latter is generated, for
example, in current switches by mixing the clock signal with the
common-mode representation of itself that appears due to the unsym-
metrical (biased) circuit. To avoid severe performance degradation
owing to offset, the location, gain and count of each circuit in the
clock tree has to be optimised to keep clock amplitude constant along a
clock path. Therefore, for example in addition to the delay-line
elements, three clock buffers (not shown in Fig. 1) are used in each
path between the VCO and MS-D-FFs to compensate for transmission
line loss (up to 6 dB) as well as for distribution of the clock signal.
Module assembly: For the module assembly shown in Fig. 2, a similar
technique as described in [4] was applied. A thin PTFE substrate
(er ¼ 2.2) with 125 mm thickness is used. This allows realisation of
small coupled 50 O microstrip lines with 300 mm width and 75 mm
spacing. The die is thinned to the substrate thickness yielding small
thermal resistance to the die backside as well as flat and short
(<300 mm) bond wires. The 1.7
2.5 mm die is attached to the
module socket using very thin thermally conductive but electrically
isolating adhesive. Standard K-connectors are used at all RF inter-
faces except for the data input where a 2.4 mm type is preferred.
Measurements at 100 Gbit=s show for this connector an improvement
in eye opening and time jitter by nearly a factor of two compared to
the K-type.
clock
output (43 Gbit/s): data 1 data 2 (43 GHz)
5V
supply
voltage
clock
clock input
output
(43 GHz)
(21.5 GHz)
data input (86 Gbit/s)
Fig. 2 Module assembly with top cover removed (size 80
54 mm)
Measurement setup and results: For testing the receiver module, a
2:1 MUX was developed and realised in the same technology run.
From three of these MUX modules, a 4:1 MUX was built that drives
the receiver module up at data rates of 100 Gbit=s. The input data of
the 4:1 MUX is derived from eight fbit=8 RZ-data channels of an
Agilent ParBert 81250. Each two of these channels were respectively
combined by means of a simple resistive power divider. The
combined data at fbit=4 drives the 4:1 MUX up to the maximum
data rate of 100 Gbit=s, limited by the external 50 GHz clock
generator.
To demonstrate the high sensitivity of the receiver at the intended
data rate of fbit ¼ 86 Gbit=s, the input is driven by a single-ended data
signal with a low voltage swing of 50 mV inner eye opening (shown in
Fig. 3a). The output eye diagram at 43 Gbit=s at one data output, as
well as the recovered 43 GHz clock, are shown in Fig. 3c (both single-
ended measurements). For bit error measurements at this reduced input
amplitude, the data at the receiver output is sampled by an MS-D-FF
with fbit=8 GHz clock frequency. With that sampling frequency, the
MS-D-FF output shows a data sequence, consisting of every fourth bit
of the data stream at the receiver output under measurement. This
operation corresponds to a 1:4 demultiplexer functionality, with the
difference that only the one data channel, that is selected by the clock
phase, is available at a time. Each of the four channels was consecu-
tively selected by adjusting the corresponding MS-D-FF clock phase.
Both receiver outputs were measured applying this method. The bit
error rate of the resulting eight data channels was measured with an
Agilent SerialBert N4901B. On all data channels error-free operation
was confirmed for sequence lengths of 27  1 as well as 231  1 bits.
For the sampling MS-D-FF, one of the two MS-D-FFs in the demulti-
plexer of an additional identical receiver module was used.
Fig. 3 86 Gbit=s single-ended receiver input signal, 30 mV=div., 5 ps=div.
(Fig. 3a); 100 Gbit=s single-ended MUX output signal, 80 mV=div.,
2.5 ps=div. (Fig. 3b); (Fig. 3c) upper trace: recovered single-ended
43 Gbit=s data output signal, lower trace: recovered 43 GHz clock
signal, both traces single-ended 60 mV=div., 10 ps=div.
To demonstrate the inherent high-speed capability of the receiver, the
single-ended 100 Gbit=s signal shown in Fig. 3b, but at reduced
amplitude, was applied to the receiver input. Of course, at this data-
rate the on-chip PLL can no longer be used. Instead, a single-ended
ELECTRONICS LETTERS 5th January 2006
50 GHz clock signal is applied to the external clock input (see Fig. 1).
The measurement result shows error-free operation for input amplitudes
with inner eye opening as low as 80 mVpp . For all measurements power
consumption is 5.5 W at 5 V supply voltage.
Acknowledgments: This work has been supported by the German
BMBF=DLR under the MultiTeraNet programme. The authors thank
Agilent Technologies GmbH, Boeblingen, especially J. Moll, for
support and provision of their high performance measurement equip-
ment, as well as L. Altenhain and the MICRAM Rapid Prototyping
team for development of the measurement setup and performing the
measurements.
# IEE 2006 31 August 2005
Electronics Letters online no: 20063141
doi: 10.1049/el:20063141
M. Möller (Department of Electronics and Circuits, Saarland
University, Germany)
E-mail: michael.moeller@eus.uni-saarland.de
U. Dümler, A. Bielik, T. Ellermeyer and H. Langenhagen (MICRAM
Microelectronic GmbH, Bochum, Germany)
W. Walthes and J. Mejri (Infineon Technologies AG, Munich,
Germany)
M. Möller: Also with MICRAM Microelectronic GmbH
U. Dümler: Now with Rohde & Schwarz GmbH, Munich, Germany
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