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divided into two intervals, i.e., t0 − t1 and t1 − t2 , except for the TABLE I
DESIGN PARAMETERS OF BOOST PFC CONVERTERS
dead time between QB and QS . To perform the mode analysis,
several assumptions are made as follows: 1) D1 and D2 are
Parameters Conventional Proposed
turned OFF because the HB LLC converter has lower voltage
gain than the HBF converter during the hold-up time. 2) VLink , Boost switch, Q S IPP60R125C6
VO , and output current IO , and voltage of input filter capacitor Rectifier devices, D B /Q S D B : SCS206AM Q S : C3M006509J
VC in are constant. Input filter capacitor, Ci n 1μF
Build-up period [t0 -t1 ]: When QB is turned OFF and QS Boost inductor, L B Core: EI3633 × 2B L B -m a x : -
is turned ON at t0 , build-up period begins. Since VLink -VC in 0.35T, L B : 1 mH, N1 :
is applied to LB and LB -lkg , the rectifier diode DA is reverse 27 turns
Boost transformer, T B Core: EI3633 × 2B L B -m a x :
biased, and the currents of LB and LB -lkg are given by -
0.35T, L B : 1 mH, L B -l k g :
6μH, N1 : N2 = 27: 9
VLink -VC i n Link capacitor, CL i n k 250μF
iL B (t) = iB -L lkg (t) = iL B (t0 ) + (t − t0 )
(LB + LB -lkg ) Hold-up time, tH o l d 18ms @ Full load condition
(1) Link voltage, VL i n k 250-400 V (VL i n k −n o m : 390 V)
where VC in is approximately Dfly VLink , nfly and Dfly are the
transformer turns-ratio and duty cycle of the HBF converter,
respectively. A. Boost PFC Converter
Meanwhile, the maximum flux density of the boost trans- The design procedure of the conventional boost PFC con-
former BL B -m ax can be expressed as verter is well described in [17], which can be also applied to
the proposed PFC stage. Table I shows the design parameters
LB iL B - m ax of the conventional and proposed boost PFC converters. The
BL B - m ax = (2)
N1 AL B boost PFC converters employ silicon carbide devices to solve
the reverse recovery problems. The input filter capacitor Cin
where iL B -m ax is the maximum current of iL B , N1 and AL B
is selected as 1 μF to reduce the EMI noise [12]. The boost
are the primary turns and effective cross-section area of the
inductor LB is designed to be about 1 mH using the amorphous
boost transformer, respectively. From (1) and (2), and Fig. 5, it
EI3633 core for 30% inductor current ripple. Meanwhile, the
is obvious that BL B -m ax occurs at t1 .
proposed one has the additional boost leakage inductor LB -lkg ,
Powering period [t1 -t2 ]: When QS is turned OFF and QB
which is measured as 6 μH in the experiment due to the sec-
is turned on at t1 , powering period begins. As shown in
ondary turns N2 designed in the HBF converter part. However,
Fig. 5, LB -lkg and Cin start to resonate. Thus, the difference
it can be negligible because it is much smaller than LB . Further-
of iB -L lkg (t) and iL B (t) is reflected to the secondary current
more, although the proposed one uses the synchronous switch
isec (t), and it can be expressed as follows:
QS , it does not degrade the regulation performance of the boost
PFC converter because QS can be generally controlled only to
isec (t) = nfly [iB -L lkg (t) − iL B (t)]
reduce the conduction loss. Finally, the 450 V/250 μF capacitor
(nfly VO − Dfly VLink ) is used as a link capacitor CLink . Thus, when the nominal link
= nfly sin wR -fly (t − t1 ) (3)
ZR -fly voltage VLink−nom is regulated as 390 V at the normal state, the
maximum ripple voltage ΔVLink-m ax and minimum link voltage
where ZR -fly = (LB -lkg /Cin )0.5 and wR -fly = 1/[(Cin VLink-m in can be calculated by
LB -lkg )0.5 ]. From (3) and Fig. 5, it is noted that if the powering
PO -m ax
period, i.e., (1 − Dfly )TS -fly , is smaller than π/wR -fly , the ΔVLink-m ax = (4)
HBF converter is not able to achieve the zero-current-switching 2πfLine CLink ηdc-dc VLink-nom
(ZCS) operation of DA . VLink-m in
2PO -m ax tHold
III. DESIGN CONSIDERATIONS = (VLink-nom − 0.5ΔVLink-m ax )2 − (5)
CLink ηdc-dc
To illustrate the design procedure of the proposed PSU, the
boost PFC, HB LLC, and HBF converters should be considered. where PO -m ax is the maximum output power, fLine is the line
Moreover, they are compared with the conventional PSU. The frequency, ηdc-dc is the expected efficiency of the dc/dc stage,
design specifications are 180–264 Vrm s ac line and 480 W/48 V and tHold is the hold-up time. Based on Table I, (4), and (5), the
output. link voltage range can be determined as 250–400 V.
VO 1
ML L C = = (6)
VLink 2 2 2
2
f R −L L C
2nL L C 1+ 1
k 1 − f S −L L C + 8nπ 2 Q ffRS −L LC
−L L C
− f R −L L C
f S −L L C
LLC
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7453
TABLE II
TRANSFORMER CORE DESIGN OF HB LLC CONVERTERS
C. HBF Converter
The HBF converter shares the structure of the boost PFC
converter in the proposed PFC stage. Thus, the HBF converter
should not influence the design procedure of the boost PFC
converter. Above all, it has to regulate the output voltage with
designed parameters of the boost PFC converter. Therefore, for
utilizing the HBF converter effectively, the transformer turns
ratio nfly and switching frequency fS -fly of the HBF converter
should be designed considering following features: 1) the dc-
conversion ratio of the HBF converter, 2) the maximum current Fig. 8. Maximum current stresses of L B and D A according to n fl y .
stresses of LB and DA , and 3) the ZCS condition of DA .
1) DC-Conversion Ratio of HBF Converter: The dc-
conversion ratio of the HBF converter MH B F can be varied
by fS -fly or the duty cycle Dfly , which can be respectively ex-
pressed as follows:
VO
2
MH B F = = 1 + A(1 − 1/fn2 −fly )
VLink
2 −0.5
+ B 2 fn −fly − 1/fn −fly (10)
VO Dfly
MH B F = = (11)
VLink nfly
where A = LB -lkg /LB , B = π 2 IO ZR /[2(nfly )2 VO ], fn -fly Fig. 9. Switching frequency for ZCS operation of D A according to n fl y .
= fS -fly /fR -fly , and fR -fly is the resonant frequency of the HBF
converter. As can be seen in (10), the HBF converter is limited this figure, iL B -m ax is increased as nfly is decreased. Especially,
in obtaining a high voltage gain with frequency control because when nfly is smaller than 2.8, iL B -m ax of the HBF converter
A and B are already designed in the boost PFC converter. There- exceeds that of the boost PFC converter at the normal state.
fore, in the proposed PFC stage, the HBF converter should be Thus, it can cause the core saturation of the boost transformer.
designed with variable duty cycle and fixed switching frequency Above all, it has impact on the design procedure of the boost PFC
control based on (11). In this case, nfly should be designed to converter. On the other hand, as nfly is increased, since iD A -m ax
guarantee that MH B F is not to be sensitive to the switching is also increased, too large nfly can result in high current stress
frequency variation for achieving stable operation. Fig. 7 shows on DA . Therefore, medium nfly is appropriate to reduce the
MH B F according to fS -fly and nfly . As shown in this figure, current stresses of LB and DA .
when nfly becomes smaller, MH B F is more sensitive to fS -fly , 3) ZCS Condition of DA : The reverse recovery problem of
which means small variation of fS -fly can affect the operation DA can cause severe EMI noise and high voltage and cur-
of the HBF converter. As a result, a large nfly is recommended rent stresses on the PSU [18], [19]. Thus, to eliminate it, the
to achieve stable output voltage regulation of the HBF converter ZCS condition of DA should be considered. Based on (3),
near its switching frequency. Fig. 9 presents the switching frequency fS -fly to obtain the ZCS
2) Maximum Current Stresses of LB and DA : Using (1), (3), operation of DA according to nfly . From this figure, when nfly
and Table I, the maximum current stress of the boost inductor is smaller than 2.4, the ZCS operation of DA cannot be achieved
LB and secondary diode DA can be depicted in Fig. 8. From because fS -fly is larger than the resonant frequency fR -fly , i.e.,
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7455
TABLE III
DESIGN PARAMETERS OF HB LLC CONVERTERS
Fig. 12. Experimental waveforms under 10% load condition at normal state.
(a) Conventional HB LLC converter. (b) Proposed HB LLC converter.