Analyzing and Designing Logic Circuits

8/16/15
ECE 238L - 3
Computer Logic Design
Dr. Ramiro Jordan

rjordan@ece.unm.edu
ECE 238L – ECE Dept, Fall 2015

1
Introduction to Logic Circuit

Analysis and Design
Dr. Ramiro Jordan

rjordan@ece.unm.edu

2
1
8/16/15
Integrated Circuits

3
Integrated Circuit Chip

4
2
8/16/15
Different Types of ICs
dual-in-line or DIP flat package surface mount
plastic leaded chip carrier

pin grid array
5
Analysing and
Designing Logic
Circuits

6
3
8/16/15
Analysis and Design

Circuit Analysis: the process of obtaining a Boolean function
from a schematic or a circuit diagram.
Circuit Design or Synthesis: the process of obtaining a

schematic or a circuit diagram for a Boolean function.
So far we are dealing with circuit diagrams that are

combinational logic circuits; the outputs depend only on the
external inputs applied. No feedback.

7
Logic Switching Circuit that uses Relays

Used in heavy power equipment.
Control Relays (CR).

8
4
8/16/15
Relay Logic Switching Circuits

Logic switching circuit that uses relays connected up to drive a motor.
Logic switching circuits used in power applications are generally

referred to as ladder logic circuits. ICs cannot drive thus need relays.
F = 1 implies motor is ON.
F = A’BC + D’ + A’BC’ = A’B + D’ (simplified)

9
Analysing IC
Logic Circuits

10
5
8/16/15
Analyzing IC Logic Circuits

Circuit Analysis: the process of obtaining a Boolean
function for a schematic or a circuit diagram.
•  AND/OR format comes from SOP (SOM)
•  OR/AND format comes from POS (POM)
F1 = AB + C’B or F1’ = (A’ + B’)(C + B’)
F2 = (X’ + Y)(X + Z) or F2’ = XY’ + X’Z’

11
Designing IC
Logic Circuits

12
6
8/16/15
Designing IC Logic Circuits

Circuit Design or Synthesis: the process of obtaining a
schematic or a circuit diagram for a Boolean function.
•  AND/OR form implies SOP (SOM)
•  OR/AND form implies POS (POM)
Steps to draw the circuit:

•  Draw the AND and OR gates for the reduced Boolean function;
SOP form
•  Show all signals as non-complemented signal names
•  Interconnect the gates, including NOT gates where necessary
•  Clean-up or reduce the number of NOT gates

13

Design of F1 = A’BC’ + B’C + AB’ (SOP)

14
7
8/16/15
Each IC for a particular logic family such as TTL

(transistor transistor logic) an CMOS
(complementary metal-oxide semiconductor) has
a fan-out and a fan-in.
•  Fan-out: Maximum number of inputs to which the IC
output can be connected without electrically loading
down the output.
•  Fan-in: The number of gate inputs; i.e. the number of
inputs the gate has.

15

Reduce the number of ICs – fan-in reduction.

16
8
8/16/15
Designing IC Logic Circuits: VHDL Listing

17
Designing IC Logic Circuits: Cascading
The resulting cascaded circuit provides an output

that responds more slowly to input changes as the
number of cascaded stages is increased. Timing
delays.

18
9
8/16/15

Design of F2 = (X’ + Y)(X + Y’)(X + Z’) (POS)

19
Designing IC Logic Circuits: VHDL Listing
Design of F2 = (X’ + Y)(X + Y’)(X + Z’) (POS)

20
10
8/16/15
Generating
Detailed
Schematics

21
Detailed Schematics
Design of F1 = A’B + CB’ (SOP) using multiple IC devices.

Show detailed connections (or wiring) required to build a
circuit on a PC board.

22
11
8/16/15
Detailed Schematics
Design of F2 = A’B + AB’ (SOP) using a single gate and IC
device. Show detailed connections (or wiring) required to
build a circuit on a PC board.

23
Detailed Schematics
Important items necessary when drawing a

detailed schematic:
•  Identify the part number for each IC in the circuit.
•  Show the pin numbers (also referred to as pin
assignments) for all ICs in the circuit.
•  Show the power connections (Vcc and GND) for all the ICs
in the circuit.

24
12
8/16/15
VHDL Listing
Design of F1 = A’B + CB’ and F2 = A’B + AB’

25
WAVEFORM
Design of F1 = A’B + CB’ and F2 = A’B + AB’

26
13
8/16/15
Designing Circuits in
NAND/NAND and
NOR/NOR Form

27
DeMorgan Rules
To obtain a De Morgan equivalent gate symbol for an
AND, OR, NAND, or NOR gate:
–  Add bubbles to all inputs
–  Add bubbles to all outputs
–  Change ANDs to ORs
–  Change ORs to ANDs
–  Two bubbles result in no bubble; Double Negation
Theorem

28
14
8/16/15
Equivalent Gate Circuits

29
Designing Circuits with NAND/NAND

and NOR/NOR Form
Why NAND and NOR gates:

•  NAND gates are generally faster than AND gates, and
NOR gates are generally faster then OR gates in the
same logic family.
•  NAND gates and NOR gates are available with a larger
variety of fan-ins to choose from than AND gates or NOR
gates.
•  Fewer IC packages are required to design circuits that use
NAND gates or NOR gates.

30
15
8/16/15
Two-Level Gate Circuits
The maximum number of gates cascaded in series between

a circuit input and output is referred to as the number of
levels.
A function written in SOPs form or POSs form corresponds
directly to a two-level gate circuit.
We assume that all variables and their complements are
available as circuit inputs. Thus, we do not count
inverters which are connected directly to input variables
when determining the number of levels in a circuit.

31
AND-OR to NAND-NAND
Transformation
Design of Minimum Two-Level NAND-NAND
Circuits
Procedure for designing a minimum two-level NAND-

NAND circuit:
1. Find a minimum sum-of-products expression for F.
2. Draw the corresponding two-level AND-OR circuit.
3. Replace all gates with NAND gates leaving the gate
interconnection unchanged. If the output gate has any single literals
as inputs, complement these literals.

32
16
8/16/15
AND-OR to NAND-NAND
Transformation
Circuit
F = l 1 + l 2 + • • • + P 1 + P2 + • • •
F = (l1′l2′ • • • P1′P2′ • • •)′

33
AND-OR to NAND-NAND
Transformation
Circuits
Procedure for designing a minimum two-level NAND-

NAND circuit (another algorithm):
1. Find a minimum sum-of-products expression for F.
2. Draw NAND gate for each product term with at least two
variables. Use for inputs the actual variables.
3. Draw single NAND gate with inputs from outputs of previous
gates.
4. A term with a single literal requires and inverter.

34
17
8/16/15
AND/OR to NAND/NAND

35
AND/OR to NAND/NAND
F1 = A’B’C’ + BC + AC’

36
18
8/16/15
VHDL Design for function F1
F1 = A’B’C’ + BC + AC’

37
OR-AND to NOR-NOR
Transformation
Design of Minimum Two-Level NOR-NOR
Circuits
Procedure for designing a minimum two-level NOR-

NOR circuit:
1. Find a minimum product-of-sums expression for F.
2. Draw the corresponding two-level OR-AND circuit.
3. Replace all gates with NOR gates leaving the gate
interconnection unchanged. If the output gate has any single literals
as inputs, complement these literals.

38
19
8/16/15
OR-AND to NOR-NOR
Transformation
Design of Minimum Two-Level NOR-NOR
Circuits
Procedure for designing a minimum two-level NOR-

NOR circuit (another algorithm):
1. Find a minimum product-of-sums expression for F.
2. Draw NOR gate for each sum term with at least two variables.
Use for inputs the actual variables.
3. Draw single NOR gate with inputs from outputs of previous gates.
4. A term with a single literal requires and inverter.

39
OR/AND to NOR/NOR

40
20
8/16/15
OR/AND to NOR/NOR
F2 = X’Z’ + XZ + Y
F2’ = (X + Y)(X’ + Z’)Y’

41
VHDL Design for function F2
F2 = X’Z’ + XZ + Y
F2’ = (X + Y)(X’ + Z’)Y’

42
21
8/16/15
Propagation Time
Delay

43
Propagation Delay Time

Each wire (connector) and each gate has a propagation
delay: time it takes a signal applied at its input to travel
from the input to the output
Delay on a wire depends on its length and its cross-
sectional area, also the material (gold, silver, copper)
Gates have also propagation delays = tp

44
22
8/16/15
Propagation Delay
tPHL = propagation delay when output changes from High to
Low
tPLH = propagation delay when output changes from Low to
High

45
Propagation Delay
Delays add up!!!!! Fastest circuit have shorter delay times,
have fewest number of cascaded components.
Worst case delay time = tp1 + tp2 + tp3

46
23
8/16/15
Decoders

47
Decoders
Converts n input lines to one of the 2n different
output lines: n-to-2n Decoder.
The most important function!!!!
The decoder is another commonly used type of
integrated circuit.
The decoder generates all of the minterms
(maxterms) of the n input variables. Exactly one of
the 2n output lines will be 1 (0) for each
combination of the values of the input variables.

48
24
8/16/15
Decoders
If n-bit coded information has “don’t cares”, then
the Decoder will output less than 2n outputs. That
is m <= 2n.

49
1-to-2 Decoder

50
25
8/16/15
2-to-4 Decoder

51
Truth Table for 2-to-4 Decoder

52
26
8/16/15
VHDL Design for 2-to-4 Decoder

53
Waveform for 2-to-4 Decoder

54
27
8/16/15
Decoders
The decoder generates all of the minterms
(maxterms) of the n input variables. Exactly one of
the 2n output lines will be 1 (0) for each
combination of the values of the input variables.
•  Active High if outputs are 1s (minterms)
•  Active Low if outputs are 0s (maxterms)

55
3-to-8 Line Decoder

56
28
8/16/15
3-to-8 Line Decoder

57
A 4-to-10 Line Decoder

58
29
8/16/15
A B C D
7442
(b) Block diagram

59
(c) Truth Table

60
30
8/16/15
Decoders
Used as address decoders in microprocesor/
microcontroller systems to select specific devices
such as RAM, ROM, I/O devices, other.
Usually come with one or more enable inputs

(active low or active high)
Decoder with enable input is called a demultiplexer

61
Truth Table for 3-to-8 decoder/demultiplexer

Active High enable G1 and Active Low enable G2
Outputs are maxterms (0s)
EX: F3 = G1G2’B2’B1B0

62
31
8/16/15
VHDL Design for 3-to-8 decoder/demultiplexer

63
Design Procedure for Decoders

n-to-x=2n decoder: n inputs and x AND outputs
1.  Let k = n
2.  k is even
•  k/2
•  Use 2k AND gates driven by two decoders of output
size 2k/2
k is odd
•  (k+1)/2 and (k-1)/2
•  Use 2k AND gates driven by two decoders of output
size 2(k+1)/2 and a decoder of output size 2(k-1)/2
3.  For each decoder resulting from step 2 repeat step 2
with k-1 equal to the values obtained in step 2 until k = 1
•  For k = 1 use a 1-to-2 decoder
64
32
8/16/15
Design 3-to-8 Decoder

65

66
33
8/16/15

67

68
34
8/16/15

69
Designing Logic
Circuits with
Decoders and
Single Gates

70
35
8/16/15
Design F1 with a Decoder
F1 = Σm(2,3,5,7) - SOM

71
Design of F1 = Σm(2,3,5,7) – SOM

a) active High outputs, b) active Low outputs (demulitplexer)

72
36
8/16/15
VHDL Design of F1 = Σm(2,3,5,7) – SOM

73
Design of F1’ = Σm(0,1,4,6) – SOM

a) active High outputs, b) active Low outputs (demulitplexer)

74
37
8/16/15
VHDL Design of F1’ = Σm(0,1,4,6) – SOM

75
Realization of a Multiple-Output
Circuit Using a Decoder
f1(a, b, c, d) = m1 + m2 + m4
f2(a, b, c, d) = m4 + m7 + m9
Rewriting f1 and f2, we have
f1 = (m1′m2′m4′)′
f2 = (m4′m7′m9′)′

76
38
8/16/15
Transfer Data on a
Common Data Bus

77

78
39
8/16/15

79

80
40
8/16/15

81

82
41
8/16/15

83

84
42
8/16/15

85

86
43
8/16/15
Excess-3 to
Decimal Decoder

87

88
44
8/16/15

89

90
45
8/16/15

91
Binary-to-Gray
and
Gray-to-Binary
Decoders

92
46
8/16/15

93

94
47
8/16/15

95

96
48
8/16/15

97

98
49
8/16/15
Multiplexers

99
Multiplexers (MUXs)
Used to direct one of 2n data inputs to a single

output .
•  n select lines needed to select one of 2n outputs
•  MUX also known as data selector

100
50
8/16/15
2-to-1 Multiplexer and

Switch Analog
A multiplexer has a group of data inputs and a group of
control inputs used to select one of the data inputs and
connect it to the output terminal.
Z = A′I0 + AI1

101
2-to-1 Multiplexer
F = D0S0’ + D1S0 = D0 when S0 = 0
F = D0S0’ + D1S0 = D1 when S0 = 1

102
51
8/16/15
Truth Table for 2-to-1 Multiplexer

103
Compressed Truth Table

for 2-to-1 Multiplexer

104
52
8/16/15
VHDL Design for 2-to-1 Multiplexer

105
Active Low 2-to-1 Multiplexer

and 4-to-1 MUX

106
53
8/16/15
Compressed Truth Table

for Active Low 2-to-1 Multiplexer

107
VHDL Design for 4-to-1 Multiplexer

108
54
8/16/15
Multiplexers
8-to-1 MUX equation:

Z = A′B′C′I0 + A′B′CI1 + A′BC′I2 + A′BCI3 + AB′C′I4 + AB′CI5 + ABC′I6 + ABCI7

109
Logic Diagram for 8-to-1 MUX

110
55
8/16/15
Quad Multiplexer Used

to Select Data
Control Variable A selects one of two 4-bit data words.

111
Quad Multiplexer with Bus

Inputs and Output

112
56
8/16/15
Designing
Logic Circuits
with MUXs

113
Designing Logic Circuits

with MUXs
•  Use compact minterm form of the function.
Function does not need to be reduced.
•  Connect the data inputs of the MUX to the
function values Vcc for 1 and GND for 0.
•  Connect select lines of MUX to the input
variables.
•  Need a 2n-to-1 MUX for any n-variable function.

114
57
8/16/15
MUX Design of F1(X,Y,Z) = Σm(1,2,5,7) – SOM

a) with a strobe input, and b) without a strobe input

115
VHDL Design of F1(X,Y,Z) = Σm(1,2,5,7) – SOM

116
58
8/16/15

with MUXs
Two other techniques
Technique 1:
•  For N variables, use N-1 variables as inputs to
select lines. Hence, we need a 2N-1-to-1 MUX.
•  From Truth table determine what the 2N inputs
lines should be.

117

with MUXs

118
59
8/16/15

with MUXs

119

with MUXs

120
60
8/16/15
Designing Logic Circuits with MUXs
Technique 2 (MAP technique):

1) First row: list the inputs to MUX
Second row: list the minterms so that the unused variable is
set to zero
Third row: list the minterms so that the unused variable is set
to one.
2) If minterms results in F=1, circle that minterm.
3) If upper minterm in a column is circled then MUX line Ii = X’.

If lower minterm in a column is circled then Ii = X.
If both minterms in a column are circled then Ii = 1.
If neither minterm in a column is circled then Ii = 0.

121

122
61
8/16/15

123

124
62
8/16/15
Hazards

125
Hazards in
Combinational Logic
A hazard can cause a logic glitch, i,.e. un undesired
momentary pulse that occurs at the output of a
circuit. Circuit failures.
Function Hazard: glitch at the output when two or
more input signals change at the same time. These
transients occur when different paths from input to
output have different propagation delays.

126
63
8/16/15
Hazards in
Combinational Logic
Can be identified by plotting the function in a K-
Map.
Designer has no control over function hazards.
Solution: wait until transients disappear and the

output signal becomes stable. Or use synchronous
circuits, settling occurs between clock ticks.

127
Types of Hazards

128
64
8/16/15
3 Input XOR
Will always contain

function hazards

129
Hazards in
Combinational Logic
Logic Hazard: glitch at the output when one input
signal is changed due to delays in the circuit.
Both static and dynamic hazards can be eliminated

by adding additional product (SOP, POS) terms in
the Boolean expression (consensus terms).

130
65
8/16/15
We can detect hazards in a two-level AND-OR

(OR-AND) circuit using the following procedure:
1.  Write down the sum-of-products (product-of-sums) expression

for the circuit.
2.  Plot each term on the K-Map and loop it.
3.  If any two adjacent 1s (0s) are not covered by the same loop,
a 1-hazard 0-hazard) exists for the transition between the two
1s (0s). For an n-variable map, this transition occurs when one
variable changes and the other n – 1 variables are held
constant.

131
Detection of a 1-Hazard

132
66
8/16/15
Fixing a 1-Hazard

133
Circuit with 1-Hazard Removed

134
67
8/16/15
Detection of a 1-Hazard

135
Circuit with Hazard Removed

136
68
8/16/15
Detection of a Static 0-Hazard

137
Karnaugh Map Removing

Hazards

138
69
8/16/15
A) To design a circuit which is free of static

and dynamic hazards, the following
procedure may be used:
1.  Find a sum-of-products expression (Ft) for the output in which
every pair of adjacent 1′s is covered by a 1-term. (The sum of
all prime implicants will always satisfy this condition.) A two-
level AND-OR circuit based on this Ft will be free of 1-, 0-, and
dynamic hazards.
2.  If a different form of the circuit is desired, manipulate Ft to the
desired form by simple factoring, DeMorgan′s laws, etc. Treat
each xi and xi′ as independent variables to prevent introduction
of hazards.

139
B) To design a circuit which is free of static

1.  Logic hazards may occur for a minimized function

implemented for the 1s or 0s of the function.
2.  For the minimized 1s or 0s of a function, one can add logic
hazard cover terms if required, which are consensus terms, to
eliminate static and dynamic logic hazards.
3.  Cover terms are nonessential product terms (sum terms) that
are used to link each product term (sum term) in the minimized
form in the K-Map for the function.

140
70
8/16/15
B) To design a circuit which is free of static

4.  In some cases, product terms (sum terms) for a minimized

form of the function are linked to each other and require no
additional cover terms.
5.  By chain linking all the minimized product terms (sum terms) in
a K-Map for the function, you will obtain the required cover
terms to add to the minimized form of the function to eliminate
all the static and dynamic logic hazards of the function.
6.  A function that has all its product terms for the 1s and 0s of the
function linked to each other does not have static or dynamic
logic hazards and it is called a logic hazard-free function.

141
Selected
Problems

142
71
8/16/15
FIGURE P3.13

143
FIGURE P3.17

144
72
8/16/15
FIGURE P3.18

145
FIGURE P3.19

146
73
8/16/15
FIGURE P3.83

147
Q&A

148
74

Analyzing and Designing Logic Circuits

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Analyzing and Designing Logic Circuits

Uploaded by

Copyright:

Available Formats

8/16/15

Dr. Ramiro Jordan

ECE 238L – ECE Dept, Fall 2015

Introduction to Logic Circuit

Dr. Ramiro Jordan

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

Integrated Circuit Chip

ECE 238L – ECE Dept, Fall 2015

Different Types of ICs

dual-in-line or DIP flat package surface mount

plastic leaded chip carrier

ECE 238L – ECE Dept, Fall 2015

Analysis and Design

Circuit Design or Synthesis: the process of obtaining a

So far we are dealing with circuit diagrams that are

ECE 238L – ECE Dept, Fall 2015

Logic Switching Circuit that uses Relays

ECE 238L – ECE Dept, Fall 2015

Relay Logic Switching Circuits

Logic switching circuits used in power applications are generally

F = 1 implies motor is ON.

F = A’BC + D’ + A’BC’ = A’B + D’ (simplified)

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

Analyzing IC Logic Circuits

F1 = AB + C’B or F1’ = (A’ + B’)(C + B’)

F2 = (X’ + Y)(X + Z) or F2’ = XY’ + X’Z’

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits

Steps to draw the circuit:

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits

Each IC for a particular logic family such as TTL

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits: VHDL Listing

Design of F1 = A’BC’ + B’C + AB’ (SOP)

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits: Cascading

The resulting cascaded circuit provides an output

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits

ECE 238L – ECE Dept, Fall 2015

Designing IC Logic Circuits: VHDL Listing

Design of F2 = (X’ + Y)(X + Y’)(X + Z’) (POS)

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

Design of F1 = A’B + CB’ (SOP) using multiple IC devices.

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

Important items necessary when drawing a

ECE 238L – ECE Dept, Fall 2015

Design of F1 = A’B + CB’ and F2 = A’B + AB’

ECE 238L – ECE Dept, Fall 2015

Design of F1 = A’B + CB’ and F2 = A’B + AB’

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015

ECE 238L – ECE Dept, Fall 2015