04 Inverter 6up PDF

Course Material for Inverter
Chapter 5, 2nd ed.

P = primair, I = Illustratie, O = overslaan
P 5.1 Introduction 180
P 5.2 The Static CMOS inverter - intuitive 181 – 184
P 1.3.2 Functionality and Robustness 18 – 27
P 5.3 Evaluating the Robustness ... 184 – 191
CMOS INVERTER I
P
5.3.3
1.3.3
Robustness Revisited
Performance
191 – 193
27 – 30
I 5.4 Performance of the CMOS inverter 193 – 213
P 1.3.4 Power and Energy Consumption 30 – 31
I 5.5 Power, Energy, and Energy-Delay 213 – 223
O 5.5.2 Static Consumption 223 – 225
O 5.5.3 Putting it All Together 225 – 227
O 5.5.4 Analyzing Power Consumption using 227 – 229.
SPICE
O 5.6 Perspective: Technology scaling… 229 – 231
P 5.7 Summary 232 – 233
TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 4 inverter 1 TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 4 inverter 2
The CMOS Inverter - Outline The CMOS Inverter:

A First Glance
First Glance
Digital Gate Characterization VDD
Static Behavior (Robustness)
VTC
Switching Threshold
Noise Margins
Dynamic Behavior (Performance)
Capacitances
Vin
Delay Vout
Power
Dynamic Power, Static Power, Metrics CL
CMOS Inverters (1) CMOS Inverter Operation Principle
VDD
PMOS
0 1
1.2 µm
= 2λ 1 0
Out
In
Metal1
Polysilicon
NMOS VOH = V DD VOL = 0

GND § 5.2
1
Digital Gate Fundamental The Ideal Inverter
Parameters
Functionality
Reliability, Robustness
Area
Performance
Speed (delay)
Vout
Power Consumption Ri = ∞
Energy
Ro = 0
g = -∞
Vin
Static CMOS Properties.

Basic inverter belongs to class of static
circuits: output always connected to either Voltage Transfer Characteristic (VTC)
VDD or VSS. Not ideal but:
Rail to rail voltage swing
Ratio less design
Low output impedance
Vout
Extremely high input impedance
No static power dissipation
g = -∞
Good noise properties/margins
Vin § 5.2
Exercise: prioritize the list above
Load Line (Ckt Theory) PMOS Load Lines VDD

2.5 ID [10-4 A]
VGSp - -
2.5V VGS = 2.5V VDSp
Goal: Combine IDn and IDp in one graph +
2.0 B IDp +
R VGS = 2.0V
Vout
1.5 Kirchoff: Vin
A Vin = VDD + VGSp IDn
VGS 1.0 VGS = 1.5V
IDn = - IDp
Vout
Vin 0.5 VGS = 1.0V Vout = V DD + V DSp
0V VDS [V] IDp IDn I Dn

0 0.5 1.0 1.5 2.0 2.5
Vin=0 Vin=0
Vin=3 Vin=3
Exercise:
The blue load line A corresponds to R = 25kΩ VDSp VDSp Vout
VGSp=-2
The orange load line B corresponds to R = 12.5kΩ
VGSp=-5
With load line A and VGS = 1V, Vout = approx 1.6 V Vin = VDD + VGSp
Example: VDD=5V Vout = VDD + VDSp
Draw a graph Vout(V in) for load line A and B
IDn = - IDp
2
CMOS Inverter Load Characteristics CMOS Inverter VTC.
Vout
I n,p
5
Vin= 0 Vin= 5 I n,p
Vin = 5
V in = 0
4
NM OS
NMOS PMOS
PMOS
3
Vin = 4 Vin = 1 Vin = 4
2
Vin= 1 Vin= 4 Vin = 3 Vin = 2 Vin = 3 Vin = 2
V in = 1
1
V in = 4 V in = 3 Vin = 2
Vin = 0
Vin = 5
Vin= 2 Vin= 3
Vin= 3 Vin= 2 Vout
1 2 3 4 5 V in
Vin = 4 Vin= 3 Vin= 2 V =1
in
Vin= 4 Vin= 1 Vin= 0
Vin= 5
Vout
NMOS Operating Need to know for proper dimensioning, PMOS Operating Need to know for proper dimensioning,
Conditions analysis of noise margin, etc. Conditions analysis of noise margin, etc.
↑ Vout ↑ Vout
NMOS
Vdd Vdd Vout = Vin - VTp
1 Vin = VGS < VTn ⇒ off PMOS
4 Vin > V DD + VTp ⇒ off
2 Vout > Vin - VTn
Vout = Vin - VTn VDS > VGS - VTn 5 Vout < Vin - VTp ⇒ saturation
VGD < VTn ⇒ saturation - VTp Vdd - |VTp|
6 Vout > Vin - VTp ⇒ resistive
3 Vout < Vin - VTn ⇒ resistive
VTn Vdd → Vin Vdd → Vin
1 2 3
6 5 4 Exercise: check
results for PMOS
Operating Conditions.
↑ Vout
NMOS 1 off
2 saturation
Vout = Vin - VTp
Vdd 3 resistive Inverter Static Behavior
PMOS 4 off Regeneration
5 saturation
Vout = Vin - VTn 6 resistive
Noise margins
- VTp Vdd - |VTp| Delay metrics
Vout NMOS off
PMOS lin
VTn Vdd → Vin
5
NMOS sat
PMOS lin
4
1 2 3
NMOS sat
3
PMOS sat
6 5 4
2
NMOS lin
PMOS sat NMOS lin § 5.3
1
PMOS off
1 2 3 4 5 Vin
3
The Realistic Inverter The Regenerative Property
Vout [V]
Vout 2.5
Ri = ∞ 2.0 A chain of inverters

Ro = 0 1.5
g = -∞ 1.0
Regenerative
Property: ability to
0.5 regenerate (repair)
VIN [V]
a weak signal in a
0 0.5 1.0 1.5 2.0 2.5 chain of gates
Vin
Ideal Inverter
Realistic Inverter
Ex. 1.4
The regenerative property
The Regenerative Property (2) The regenerative Property (3)
...
v0 v1 v2 v3 v4 v5 v6
Exercise: what is the output voltage of a chain of 4
(a) A chain of inverters. inverters with a piece-wise linear VTC passing through (0,
v1, v3, ... v1, v3, ... 10), (4,8), (6,2) and (10,0) [Volt], as the result of an input
f(v) finv(v) voltage of 5.5 [Volt].
finv(v) f(v) Exercise: discuss the behavior for an input of 5 [Volt]
v0, v2, ... v0, v2, ...

(b) Regenerative gate (c) Non-regenerative gate
Exercise Answer Inverter Switching Treshold
Not the device threshold Vm = f(Ronn, Ronp)

Point of Vin = Vout
Vin Vout
Try to set Wn, Ln, Wp, Lp

so that VTC is symmetric
as this will improve noise
margins
Ongeveer: 5.5 → 3.5 → 8.5 → 0.75 → 9.75 optimize NMOS-PMOS ratio
4
Simulated Gate Switching Threshold Inverter Switching Threshold
Analytical Derivation
Electrical Design Rule VM is V in such that V in = Vout

See Figure 5.7
Wp ≈ 2.5 Wn
VDS = VGS ⇔ VGD = 0 ⇒ saturation
VM (V)
Assumes Lp = Ln Assume VDSAT < VM - VT

Should be applied
consistently (velocity saturation)
Ignore channel length modulation
(for simplicity – is it allowed?)
Wp / Wn
VM follows from
Symmetrical VTC ⇒ V m ≈ ½ VDD ⇒ Wp/Wn ≈ 3.5
IDSATn(VM) = - IDSATp(VM)
In practice: choose somewhat smaller value of Wp/Wn § 5.3.1
Why? Save area with only slight asymmetry
Gate Switching Threshold

Inverter Switching Threshold
Analytical Derivation (ctd)
w/o Velocity Saturation.
Long channel approximation
IDSATn(VM ) = - IDSATp(VM ) (
I D = kVDSAT VGS − VT − VDSAT / 2 ) Applicable with low VDD
⇔ k nVDSATn (VM − VTn − VDSATn / 2) =

4.0
Exercise (Problem 5.1):
− k pVDSATP (VM − VDD − VTp − VDSATp / 2) derive VM for long-
3.0
kp − VDSATn (VM − VTn − VDSATn / 2 ) channel approximation
VM
W '
⇔ = k=
VDSATP (VM − VDD − VTp − VDSATp / 2) L
k as shown below
kn 2.0
k'n VDSATn (VM − VTn − VDSATn / 2 )

( W / L )p
⇒ =
( W / L )n k'p VDSATP (VM − VDD − VTp − VDSATp / 2) 1.00.1 0.3 1.0 3.2 10.0
kp /k n
See Example 5.1:

r ( VDD − VTp + VTn ) − kp
VM = with r =
(W/L)p = 3.5 (W/L)n for typical conditions and VM = ½ VDD 1+ r kn
Usually: Ln = Lp
Noise in Digital Integrated Circuits Noise Margins

VDD
v(t)
i(t)
(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise
Study behavior of static CMOS Gates with noisy VOL = Output Low Voltage
signals § 1.3.2 VIL = Input Low Voltage
VOH, VIH = …
5
Noise Margins Noise Margin for Realistic Gates
NMH = VOH - VIH = High Noise Margin Exercise: explain significance of slope = -1 for noise margin
NML = VIL - VOL = Low Noise Margin
Noise Margin Calculation Noise Margin Calculation (2).

Approximate g as the slope in Vout vs. Vin at Vin = VM
Piece-wise linear
approximation of g = gain factor k nVDSAT n (Vin − VTn − VDSATn / 2 )(1 + λnVout ) +
(slope of VTC)
k pVDSAT P (Vin − VDD − VTp − VDSATp / 2 )(1 + λ pVout − λ pV DD ) = 0
VTC
dVout 1+ r k pVDSATp
g= ≈
We know how dVin Vin =VM
(VM − VT − VDSATp / 2 )(λn − λ p ) r=
k nVDSATn
to compute VM Mostly determined by technology
Next: how to
compute g See example 5.2
(V − VOL ) − VDD
VIH − VIL = − OH = Exercise: verify calculation
g g
V V − VM Exercise: explain why we add channel length
VIH = VM − M VIL = VM + DD
§ 5.3.2 g g modulation to the ID expressions (we did not do
NM H = VDD − VIH NML = VIL this to determine VM )
CMOS Inverters
Dynamic Behavior (Performance) VDD
Capacitances PMOS What causes the

delay?
Delay
What is Ron ?
1.2µm
=2λ Where are the
Out capacitances?
In
Metal1
Which
capacitances
But: we take much simpler model for Polysilicon
determine Tp?
capacitances compared to book.
See the syllabus. NMOS
GND
§ 5.4 § 5.4.1 of book is only illustration.
6
Delay Definitions CMOS Inverter Rise/Fall Delay
Vin
50%
tp =
1
(t
2 pHL
+ t pLH ) t =0 tf
t
t t
pHL pLH
Vout Goal: determine tf, tr and tp
90%
First: compute relevant capacitances
50%
Second: determine equivalent Ron
10% t
tf tr Third: compute RC delay (τ) and scale result
Assume: ideal source, step input
tp : property of gate
§ 1.3.3
tr , tf : property of signal
Modeling Modeling (2)

tf
tf
M2 M4 tf
t =0 M2 M4
t =0 tf M1 M3
t =0 t =0
M1 M3
Ron CD tf
t=0
G G
S D
+ R
CG t=0 R = Ron1
Vs
C C = CD1 + CD2 + CG3 + CG4
-
CS VS = 0
From module 1- devices S
Modeling (3) RC Delay Review (1)

tf
t=0 t=0
+ vR -
+ R + R +
− (t − t0 ) / τ
Vs Vs vC vc (t ) = v c (∞ ) + (v c (t 0 ) − v c (∞ ))e
t =0 tf C C
-
- -
Delay can be modeled using RC circuit Vs

First order simplified model
vC dv c
R is (linearized) on-resistance of active transistor RC = Vs − v c
C is sum of (linearized) C’s that are switched 0.5Vs dt
Typically, CG of driven gate, CD of driving gate t
−
Plus relevant interconnect C v c = Vs ( 1 − e RC )
Might need to include interconnect R in model
Vs is final voltage of delay node (initial voltage determined 0 2RC 4RC 6RC 8RC
t
by previous state)
7
RC Delay Review (2)
= (1 − e − t / τ )
vc
Response can be normalized with respect to τ=RC Vs
and VS = vC(t = ∞) −
t
v c = Vs ( 1 − e RC )
0 .5 = (1 − e − t50% / τ )
= ( 1 − e −t / τ )
−2
Example: (1 − e ) = 0.86
vc
Vs
1.0 0.98 0.99 Each τ -step gives 63% 0 .5 = e − t50% / τ
of remaining swing
vc 0.95
Vs 0.86
0.63 swing time 2 = e t 50 % / τ
0.5
0–50% 0.69τ
0–63% 1.0τ
ln(2) = 0.69 = t 50% / τ
0 10%–90% 2.2τ
2τ 4τ 6τ t 8τ
t50%=0.69τ ??? 0–90% 2.3τ t 50% = 0. 69τ
Inverter Propagation Delay Summary. Propagation Delay w. Wire Resistance

Req Req RW
CW
Cout CW Cin Cout Cin
CL tPHL = 0.69Reqn (Cout + 0.5Cw )

+ 0.69(Reqn + RW )(0.5Cw + Cin )
t pHL = 0.69Reqn CL
t pLH = 0.69ReqpCL
See module 3, interconnect
tp =
1
2
(t pHL + t pLH ) Propagation time
Equivalent Ron (Req) Impact of Rise Time on Delay
VDD
ID
0.35
0.3
(a) Schematic
t pH L(nsec)
0.25
1 VDD V DD 2
Req = +
2 I DSAT (1 + λV DD ) I DSAT (1 + λ VDD 2 )
0.2
3 V DD ⎛ 5 ⎞
≈ ⎜ 1 - λ V DD ⎟ See 3-devices, example 3.8
4 I DSAT ⎝ 6 ⎠ 0.15
0 0.2 0.4 0.6 0.8 1
t rise (nsec)
Empirical from
the first edition of
book
8
Delay as a function of VDD CMOS Inverter Propagation Delay
5.5
Alternative current-based
VDD estimate for Tp, assuming
5
velocity saturation
4.5
tp (Normalized)
Vswing
4 CL
2 CLVDD
TpHL = ≈
3.5 I av 2I DSAT (1 + 3 λVDD )
4
3
Vout
2.5
2 Iav CL
1.5
1 Exercise (Problem 5.4): Derive
Fg.5.17 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Pr. 5.4 the expression above
VDD (V) Vin = V DD
Ring Oscillator Fan-in and Fan-out.

Frequently used to obtain Tp by measurement (or simulation)
N: number of inverters
T p: propagation delay
T: period of oscillation
(a) Fan-out N
v0 v1 v2 v3 v4 v5
M
v0 v1 (b) Fan-in M
N
§ 1.3.3 T= 2 x Tp x N ⇔ Tp = T/2N § 1.3.2
Exercise: explain the factor 2 in the expression above

CMOS Power Dissipation

Power dissipation is a very important circuit
Power (§ 5.5) characteristic
CMOS has relatively low static dissipation
Dynamic Power Power dissipation was the reason that CMOS
Static Power technology won over bipolar and NMOS
Metrics technology for digital IC’s
(Extremely) high clock frequencies increase
dynamic dissipation
Low VT increase leakage
Advanced IC design is a continuous struggle to
contain the power requirements!
§ 1.3.4 § 5.5
9
Power Density Where Does Power Go in CMOS
Dynamic Power Consumption

Charging and discharging capacitors
Short Circuit Currents
Short circuit path between supply rails during
switching
Leakage
Leaking diodes and transistors
Estimate May be important for battery-operated equipment
Furnace: 2000 Watt, r=10cm Î P ≈ 6Watt/cm2
Processor chip: 100 Watt, 3cm2 Î P ≈ 33Watt/cm2
Power-aware design, design for low power, is

blossoming subfield of VLSI Design
Dynamic Power Low-to-High Transition Energy

vDD
Dynamic Power
Equivalent circuit for low-
Ei = energy of switching event i i(t) to-high transition
(to first order) independent of switching speed
depends on process, layout v 0(t)
Power = Energy/Time C
1
P= ∑ Ei
T i EC - Energy stored on C
Ei = Power-Delay-Product P-D ∞ dv 0
EC = ∫ iv 0 dt v 0 = v 0 (t ) i = i (t ) = C
important quality measure dt
0
∞ dv0
Energy-Delay-Product E-D = ∫ Cv0 dt
0 dt
combines power*speed performance VDD DD V
1 1
= ∫ Cv 0dv 0 = Cv 02 = CVDD
2
0 2 0 2
Low-to-High Transition Energy Low-to-High Transition Energy

vDD
i(t) i(t)
vDD
v0(t)
v 0(t)
C
C
EVDD Energy delivered by supply E diss Energy dissipated in transistor

∞ dv VDD ∞
EVDD = ∫ i (t )VDD dt= ∫ CVDD 0 dt= CVDD Ediss = ∫ i (VDD − v 0 )dt
2
0 0 dt
0
2 1 2 ∞ ∞
EVDD = CVDD Ec = CVDD = ∫ iVDDdt − ∫ iv 0dt
2
0 0
Where is the rest? Dissipated in transistor = EVDD − E c
10
High-to-Low Transition Energy CMOS Dynamic Power Dissipation.
Energy = Echarge + Edischarge

i Equivalent circuit
C Energy Energy # transitions
Power = = ×
Time transition time
2 ×f
= CVDD
Exercise: Show that the energy that is dissipated

in the transistor upon discharging C from VDD to Independent of transistor on-resistances
0 equals Ediss = ½CVDD2
Can only reduce C, VDD or f to reduce power
In this formula, f accounts for switching activity
(not necessarily a simple regular waveform)
Summary
First Glance
Digital Gate Characterization (§ 1.3)
Static Behavior (Robustness) (§ 5.3)
VTC
Switching Threshold
Noise Margins
Dynamic Behavior (Performance) (§ 5.4)
Capacitances
Delay
Power (§ 5.5)
Dynamic Power, Static Power, Metrics
TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 4 inverter 63
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Course Material for Inverter

Chapter 5, 2nd ed.

The CMOS Inverter - Outline The CMOS Inverter:

CMOS Inverters (1) CMOS Inverter Operation Principle

NMOS VOH = V DD VOL = 0

Static CMOS Properties.

Load Line (Ckt Theory) PMOS Load Lines VDD

0V VDS [V] IDp IDn I Dn

Ri = ∞ 2.0 A chain of inverters

The Regenerative Property (2) The regenerative Property (3)

finv(v) f(v) Exercise: discuss the behavior for an input of 5 [Volt]

v0, v2, ... v0, v2, ...

Exercise Answer Inverter Switching Treshold

 Not the device threshold Vm = f(Ronn, Ronp)

 Try to set Wn, Ln, Wp, Lp

Electrical Design Rule  VM is V in such that V in = Vout

 Assumes Lp = Ln  Assume VDSAT < VM - VT

Gate Switching Threshold

⇔ k nVDSATn (VM − VTn − VDSATn / 2) =

k'n VDSATn (VM − VTn − VDSATn / 2 )

 See Example 5.1:

Noise in Digital Integrated Circuits Noise Margins

Noise Margin Calculation Noise Margin Calculation (2).

Dynamic Behavior (Performance) VDD

 Capacitances PMOS  What causes the

Modeling Modeling (2)

Modeling (3) RC Delay Review (1)

 Delay can be modeled using RC circuit Vs

Inverter Propagation Delay Summary. Propagation Delay w. Wire Resistance

CL tPHL = 0.69Reqn (Cout + 0.5Cw )

Equivalent Ron (Req) Impact of Rise Time on Delay

Ring Oscillator Fan-in and Fan-out.

§ 1.3.3 T= 2 x Tp x N ⇔ Tp = T/2N § 1.3.2

Exercise: explain the factor 2 in the expression above

CMOS Power Dissipation

 Dynamic Power Consumption

Power-aware design, design for low power, is

Dynamic Power Low-to-High Transition Energy

Low-to-High Transition Energy Low-to-High Transition Energy

EVDD Energy delivered by supply E diss Energy dissipated in transistor

Energy = Echarge + Edischarge

Exercise: Show that the energy that is dissipated

TUD/EE ET1205 D2 0809 - © NvdM 6/7/2009 4 inverter 63

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Not the device threshold Vm = f(Ronn, Ronp)

Try to set Wn, Ln, Wp, Lp

Electrical Design Rule VM is V in such that V in = Vout

Assumes Lp = Ln Assume VDSAT < VM - VT

See Example 5.1:

Capacitances PMOS What causes the

Delay can be modeled using RC circuit Vs

Dynamic Power Consumption