QUIZ #1 DIGITAL

 Question 1
2 out of 2 points
The central control module for the digital subsystem is

 Question 2
2 out of 2 points
A single channel within the digital subsystem is called

 Question 3
2 out of 2 points
The pin cards are resident in the Test Head and are used to provide

 Question 4
2 out of 2 points
A ____ contains the expect and drive data for the device as well as the timing and control information.

 Question 5
2 out of 2 points
The leading edge is the _____ of a vector.

 Question 6
2 out of 2 points
Time high over the total period is called

 Question 7
2 out of 2 points
_____ are used as clocks or triggers for the various digitizers in CTS testers and as
user programmable TTL clocks.

 Question 8
0 out of 2 points
Based on convention of current flow used for the parameters, current flowing into the device are considered to
be _____.

 Question 9
2 out of 2 points
When the value of the transition is higher than the final value _____ occurs.

 Question 10
2 out of 2 points
The _____ is used to run the patterns that will provide the high speed digital I/O required for testing
mixed-signal devices.

 Question 11
0 out of 2 points
 In a differential logic family, the difference in voltage between the signals is called

 Question 12
2 out of 2 points
When the input data to the DUT switches to a logic LOW or HIGH virtually any time during a vector, the
timing is called

 Question 13
2 out of 2 points
The _____ is a set of resources designed to provide the high-speed digital I/O required to test
complex mixed-signal devices.

 Question 14
2 out of 2 points
In single-ended logic families, the voltage produced by the device when it generates a logic high is called

 Question 15
2 out of 2 points
Capture data may be compared with _____ data to determine errors.

 Question 16
2 out of 2 points
The data that will be input to the DUT on a per channel or a per vector basis is called

 Question 17
2 out of 2 points
For _____, the RAM is used to check for errors that occur when the data differs from the expected
output.

 Question 18
0 out of 2 points
The logic LOW output of the pin driver is referred to as

 Question 19
2 out of 2 points
The repetition rate at which vectors are executed is called

 Question 20
2 out of 2 points
The ________ defines the association between pins of the digital subsystem and the digital pins of a device.

 Question 21
0 out of 2 points
 _____ is the time required for an edge to go from (typically) 90% to 10% of its initial voltage value.

 Question 22
2 out of 2 points
The formatter sequencer type D has

 Question 23
2 out of 2 points
Pins with the same capture and drive timing and levels are considered to be

 Question 24
2 out of 2 points
The Formatter contains a ______ which is used to control pattern flow.

 Question 25
2 out of 2 points
The interface device between the digital subsystem and the DUT is called ______.

 Question 26
2 out of 2 points
The _______ contains an internal frequency reference based on an ultra-stable ovenized 10MHz
crystal.

 Question 27
2 out of 2 points
Output voltages that are higher than VTH are considered to be a logic ______.

 Question 28
2 out of 2 points
To group multiple pins from the device map into a single pin list index, __________ are created.

 Question 29
0 out of 2 points
Time during a period that a waveform is in the low state

 Question 30
2 out of 2 points
A _____ is a single bit of digital data.

 Question 31
2 out of 2 points
The active load provides _________ for loading the outputs of the DUT.
 Question 32
0 out of 2 points
Frequency of the patterns can be run

 Question 33
0 out of 2 points
The ____ is used to convert differential ECL data generated by the formatters to a single ended digital signal
with programmable levels.

 Question 34
2 out of 2 points
One of the dividers from PTS#1 is used to divide the clock down to a frequency near 10MHz, this is
then buffered by a bank of eight buffers cabled to the formatters, and are used as the _____ by the
formatters.

 Question 35
2 out of 2 points
______ can be used to do parametric measurement.

 Question 36
2 out of 2 points
The calibration clock (CAL CLOCK) used during the timing calibration of the DSS has a frequency

 Question 37
2 out of 2 points
_______ represent the type of data that the error checking on the formatter will perform after
capturing the data from DUT on a per-vector basis.

 Question 38
2 out of 2 points
Drive formats are considered to be ____, meaning they cannot be changed during pattern execution.

 Question 39
2 out of 2 points
CLOCK TTL1 which is derived from PTS#2 is cabled to

 Question 40
2 out of 2 points
_____ is the the process of converting digital data to digital signals.

 Question 41
2 out of 2 points
The pattern timing is _____, meaning it will remain in effect until it is reprogrammed.

 Question 42
 2 out of 2 points
The parametric unit operates like a ________.

 Question 43
2 out of 2 points
Digital pins that are dynamic

 Question 44
2 out of 2 points
The _____ came from PTS#1 routed to a bank of eight buffers cabled to the formatters in the VXI
card cage.

 Question 45
2 out of 2 points
in this line code binary 0 is represented by no-pulse for one-half the duration of the time slot and the binary 1 is
represented by a pulse with amplitude A for the whole duration of the time slot.

 Question 46
2 out of 2 points
A pair of channels within the digital subsystem is called

 Question 47
2 out of 2 points
____ of the clock section is referred to as the master clock.

 Question 48
2 out of 2 points
__________ for a channel are never active at the same time.

 Question 49
2 out of 2 points
For a signal to considered as a logic LOW, the value must be lower than

 Question 50
0 out of 2 points
In the window comparator, the programmable level for detecting logic LOW levels is referred to as

Saturday, August 19, 2017 10:10:30 PM PHT