Chapter 10

Unbalanced Faults
1 Introduction
A three-phase pre-fault Thevenin equivalent network can be used for the analysis of
unbalanced faults. Figure 10.1 shows such a scheme. In this figure, 𝐸𝑎 , 𝐸𝑏 and 𝐸𝑐 consist the
2
balanced three-phase equivalent pre-fault source seen from Bus k (𝐸𝑏 = 𝛼 . 𝐸𝑎 & 𝐸𝑐 = 𝛼. 𝐸𝑎 ), 𝑍𝑠
is the equivalent impedance per-phase and 𝑍𝑛 is the impedance facing the current that could
flow in the ground.

Figure 10.1- Three-phase Thevenin equivalent network

In the network of Figure 10.1, an unbalanced fault will be implemented at Bus k after the
switches are closed. In the faulted conditions, currents 𝐼𝑎 , 𝐼𝑏 and 𝐼𝑐 will be unsymmetrical. The
sources, however, are assumed to remain unchanged. In such circumstances, writing KVL in the
three main loops of the system will result in:

𝑉𝑎 𝐸𝑎 𝑍𝑠 + 𝑍𝑛 𝑍𝑛 𝑍𝑛 𝐼𝑎 10-1
[𝑉𝑏 ] = [𝐸𝑏 ] − [ 𝑍𝑛 𝑍𝑠 + 𝑍𝑛 𝑍𝑛 ] [𝐼𝑏 ]
𝑉𝑐 𝐸𝑐 𝑍𝑛 𝑍𝑛 𝑍𝑠 + 𝑍𝑛 𝐼𝑐
Or in a compact form we get:

𝑽𝒂𝒃𝒄 = 𝑬𝒂𝒃𝒄 − 𝒁𝒂𝒃𝒄 . 𝑰𝒂𝒃𝒄 10-2

Transforming 10-2 to the sequence networks we get:

𝑽𝟎𝟏𝟐 = 𝑬𝟎𝟏𝟐 − 𝒁𝟎𝟏𝟐 . 𝑰𝟎𝟏𝟐 10-3

where:

0 10-4
𝑬𝟎𝟏𝟐 = [𝐸𝑎 ]
0

𝑍𝑠 + 3𝑍𝑛 0 0 𝑍0 0 0 10-5
𝒁𝟎𝟏𝟐 =[ 0 𝑍𝑠 0] = [0 𝑍1 0]
0 0 𝑍𝑠 0 0 𝑍2

Equations 10-3 through 10-5 indicate that the three sequence networks are independent from
one another. Also, power of the system is only supplied from the positive-sequence network.
These equations can be depicted by the three sequence networks in Figure 10.2.

Figure 10.2- Sequence networks

From Figure 10.2 we get:

𝑉0 = −𝑍0 . 𝐼0 10-6

𝑉1 = 𝐸𝑎 − 𝑍1 . 𝐼1 10-7

𝑉2 = −𝑍2 . 𝐼2 10-8

The sequence equivalent Thevenin impedances viewed from Bus k (the faulted bus) are actually
the diagonal elements of the bus impedance Matrixes at Bus k in the three sequences. Zero and
negative sequence impedance matrixes can be constructed in similar ways to the positive-
sequence impedance matrix.

For the analysis of unbalanced faults, depending on the type of fault, the three sequence
networks depicted in Figure 10.2 need to be connected in certain ways for finding the fault
current (we will talk about these ways in the coming sections). Results of this analysis will
determine the changes in all bus voltages in the zero, positive and negative sequences. These
changes will be added to the pre-fault steady-state voltages (solved through load flow analysis)
to determine after-fault bus voltages. (Note that with the assumption of a balanced pre-fault
network, all zero and negative sequence voltages are zero and only positive-sequence voltages
exist).

In the fault analysis, the following assumptions are made:

- The three sequence networks are independent.

- In balanced conditions, only positive-sequence network exists.
- Voltage sources resulted by the synchronous generators exist only in the positive-
sequence network.
- Since sequence networks are independent, zero-sequence, positive-sequence and
negative-sequence voltage drops are only caused by zero-sequence, positive-sequence
and negative-sequence currents, respectively.
- The reference for positive-sequence and negative-sequence networks is the neutral
point, while the reference for zero-sequence network is the ground. Therefore, the zero-
sequence network can only flow if there are zero-sequence current paths between the
neutral and the ground.
 - No positive or negative sequence network will flow into the ground.
- When neutral point is grounded through impedance 𝑍𝑛 , its reflection in the zero-
sequence network will be through impedance 3𝑍𝑛 .

2 Single-Line to Ground (SLG) Fault

Figure 10.3 depicts a single-line to ground (SLG) fault through impedance 𝑍𝑓 on phase “a” at
Bus k. In order to find how the three sequence networks of Figure 10.2 need to be connected in
the SLG fault, Figure 10.3 can be analyzed considering the fact that the fault current only will
flow through phase “a” which can be found as:
𝐸𝑎 10-9
𝐼𝑎 =
𝑍𝑠 + 𝑍𝑓
The sequence currents can be found using phase currents as:
−1 𝐼𝑎 10-10
𝑰𝟎𝟏𝟐 = 𝑨 . [ 0 ]
0

Figure 10.3- Single-line to ground fault at Bus k

From 10-10 we get:

1 10-11
𝐼𝟎 = 𝐼𝟏 = 𝐼𝟐 = 𝐼𝑎
3
From 10-11 it can be concluded that the three sequence networks are in series. Since 𝑍𝑓 is in the
path of the zero-sequence current, its impedance is reflected by a 3 factor, as depicted in Figure
10.4.
 Figure 10.4- Connection of the three sequence networks in the SLG fault

From Figure 10.4 it can be found that:

𝐸𝑎 𝐸𝑎 /3 10-12
𝐼0 = 𝐼1 = 𝐼2 = =
𝑍0 + 𝑍1 + 𝑍2 + 3𝑍𝑓 𝑍𝑠 + 𝑍𝑛 + 𝑍𝑓

In general, for a SLG fault at Bus k we have:

𝑉𝑘 (0) 10-13
𝐼0 = 𝐼1 = 𝐼2 =
𝑍0,𝑘𝑘 + 𝑍1,𝑘𝑘 + 𝑍2,𝑘𝑘 + 3𝑍𝑓
where 𝑉𝑘 (0) is the pre-fault voltage at Bus k, 𝐼0 , 𝐼1 and 𝐼𝟐 are the sequence fault currents and
𝑍0,𝑘𝑘 , 𝑍1,𝑘𝑘 and 𝑍2,𝑘𝑘 are the k’th diagonal elements of the three sequence bus impedance
matrixes.

3 Double-Line (DL or Line-Line) Fault

Figure 10.5 depicts a double-line (DL) fault through impedance 𝑍𝑓 between phases “a” and “b”
at Bus k. In order to find how the three sequence networks of Figure 10.2 need to be connected
in the DL fault, Figure 10.5 can be analyzed considering the fact that:

𝐼𝑎 = 0 10-14

𝐼𝑏 = −𝐼𝑐 10-15

𝑉𝑏 − 𝑉𝑐 = 𝑍𝑓 . 𝐼𝑏 10-16

From 10-14 and 10-15, the sequence fault currents are found through:
 𝐼0 1 1 1 0 10-17
1 2 𝐼
[𝐼1 ] = [1 𝛼 𝛼 ] [ 𝑏 ]
3 2
𝐼2 1 𝛼 𝛼 −𝐼𝑏
From which we get:

𝐼0 = 0 10-18

1 2 10-19
𝐼1 = + (𝛼 − 𝛼 )𝐼𝑏
3

1 2 10-20
𝐼2 = − (𝛼 − 𝛼 )𝐼𝑏
3

Figure 10.5- Double-line fault at Bus k

Having:

2
𝑉𝑏 = 𝑉0 + 𝛼 . 𝑉1 + 𝛼. 𝑉2 10-21
2
𝑉𝑐 = 𝑉0 + 𝛼. 𝑉1 + 𝛼 . 𝑉2
We get:
 2
𝑉𝑏 − 𝑉𝑐 = (𝛼 − 𝛼). (𝑉1 − 𝑉2 ) = 𝑍𝑓 . 𝐼𝑏 10-22

Substituting 𝑉1 and 𝑉2 from 10-7 and 10-8 into 10-22 we find:

𝐸𝑎 10-23
𝐼1 = −𝐼2 =
𝑍1 + 𝑍2 + 𝑍𝑓
From 10-18 it can be found that the zero-sequence network has no role in the fault current. From
10-23 the connection of the positive and negative sequence networks can be depicted as Figure
10.6, through which it can be seen that the fault impedance 𝑍𝑓 will be located between the two
sequence networks.

Figure 10.6- Connection of the positive and negative sequence networks in the DL fault

In general, for a DL fault at Bus k we have:

𝑉𝑘 (0) 10-24
𝐼1 = −𝐼2 =
𝑍1,𝑘𝑘 + 𝑍2,𝑘𝑘 + 𝑍𝑓

𝐼0 = 0 10-25

where 𝑉𝑘 (0) is the pre-fault voltage at Bus k, 𝐼0 , 𝐼1 and 𝐼𝟐 are the sequence fault currents and
𝑍1,𝑘𝑘 and 𝑍2,𝑘𝑘 are the k’th diagonal elements of the positive and negative sequence bus
impedance matrixes.

4 Double-Line to Ground (DLG) Fault

Figure 10.7 depicts a double-line to ground (DLG) fault through impedance 𝑍𝑓 between phases
“a” and “b” at Bus k. In order to find how the three sequence networks of Figure 10.2 need to be
connected in the DLG fault, Figure 10.7 can be analyzed considering the fact that:
𝐼𝑎 = 0 10-26

𝐼𝑓 = 𝐼𝑏 + 𝐼𝑐 10-27

𝑉𝑏 = 𝑉𝑐 = 𝑍𝑓 . (𝐼𝑏 + 𝐼𝑐 ) 10-28

Figure 10.7- Double-line to ground fault at Bus k

We have:

2
𝑉𝑏 = 𝑉0 + 𝛼 . 𝑉1 + 𝛼. 𝑉2 10-29
2
𝑉𝑐 = 𝑉0 + 𝛼. 𝑉1 + 𝛼 . 𝑉2
Since 𝑉𝑏 = 𝑉𝑐 , from 10-29 it can be found that:

𝑉1 = 𝑉2 10-30

Substituting for the symmetrical components in 10-28:

2 2
𝑉𝑏 = 𝑍𝑓 (𝐼0 + 𝛼 . 𝐼1 + 𝛼. 𝐼2 + 𝐼0 + 𝛼. 𝐼1 + 𝛼 . 𝐼2 ) = 𝑍𝑓 (2𝐼0 − 𝐼1 − 𝐼2 ) 10-31

Since:

𝐼0 + 𝐼1 + 𝐼2 = 𝐼𝑎 = 0 10-32
from 10-31 we can conclude that:

𝑉𝑏 = 3𝑍𝑓 . 𝐼0 10-33

The goal is to find the sequence currents. As a result, by substitution of the equivalent of 𝑉𝑏
from 10-31 into 10-29 and using 10-30 we find:

2
3𝑍𝑓 . 𝐼0 = 𝑉0 + 𝛼 . 𝑉1 + 𝛼. 𝑉1 = 𝑉0 − 𝑉1 10-34

We substitute for 𝑉0 and 𝑉1 from 10-6 and 10-7 into 10-34 to find:

𝐸𝑎 − 𝑍1 . 𝐼1 10-35
𝐼0 = −
𝑍0 + 3𝑍𝑓
From 10-8 we have:

𝑉2 10-36
𝐼2 = −
𝑍2
Since 𝑉1 = 𝑉2 (from 10-30) and using 10-7 we will find:

𝐸𝑎 − 𝑍1 . 𝐼1 10-37
𝐼2 = −
𝑍2
Substituting 𝐼0 and 𝐼2 from 10-35 and 10-37 into 10-32 to solve for 𝐼1 we get:

𝐸𝑎 10-38
𝐼1 =
𝑍2 (𝑍0 + 3𝑍𝑓 )
𝑍1 +
𝑍2 + 𝑍0 + 3𝑍𝑓
From 10-35, 10-37 and 10-38, connection of the three sequence networks can be depicted as
shown in Figure 10.8.

Figure 10.8- Connection of the sequence networks in the DLG fault

In general, for a DLG fault at Bus k we have:
𝑉𝑘 (0) 10-39
𝐼1 =
𝑍2,𝑘𝑘 (𝑍0,𝑘𝑘 + 3𝑍𝑓 )
𝑍1,𝑘𝑘 +
𝑍2,𝑘𝑘 + 𝑍0,𝑘𝑘 + 3𝑍𝑓

𝑉𝑘 (0) − 𝑍1,𝑘𝑘 . 𝐼1 10-40

𝐼0 = −
𝑍0,𝑘𝑘 + 3𝑍𝑓

𝑉𝑘 (0) − 𝑍1,𝑘𝑘 . 𝐼1 10-41

𝐼2 = −
𝑍2,𝑘𝑘
where 𝑉𝑘 (0) is the pre-fault voltage at Bus k, 𝐼0 , 𝐼1 and 𝐼𝟐 are the sequence fault currents and
𝑍0,𝑘𝑘 , 𝑍1,𝑘𝑘 and 𝑍2,𝑘𝑘 are the k’th diagonal elements of the three sequence bus impedance
matrixes.

5 After-Fault Bus Voltages and Line Currents

Once fault currents are found at Bus k, sequence bus voltages at bus i can be found as:

𝑉0𝑖 (𝐹) = −𝑍0,𝑖𝑘 . 𝐼0 10-42

𝑉1𝑖 (𝐹) = 𝑉𝑖 (0) − 𝑍1,𝑖𝑘 . 𝐼1 10-43

𝑉2𝑖 (𝐹) = −𝑍2,𝑖𝑘 . 𝐼2 10-44

In the above equations, 𝑉0𝑖 (𝐹), 𝑉1𝑖 (𝐹) and 𝑉2𝑖 (𝐹) are the after-fault sequence voltages at Bus i,
𝑍0,𝑖𝑘 , 𝑍1,𝑖𝑘 and 𝑍2,𝑖𝑘 are the elements of the sequence impedance matrixes in row i and column k,
and 𝑉𝑖 (0) is the pre-fault voltage at bus k. After finding the sequence voltages at Bus i, phase
voltages at Bus i can be found.

After-fault sequence currents in an arbitrary line between buses i and j can be found as:

𝐼0,𝑖𝑗 (𝐹) = −𝑌0,𝑖𝑗 (𝑉0𝑖 (𝐹) − 𝑉0𝑗 (𝐹)) 10-45

𝐼1,𝑖𝑗 (𝐹) = −𝑌1,𝑖𝑗 (𝑉1𝑖 (𝐹) − 𝑉1𝑗 (𝐹)) 10-46

𝐼2,𝑖𝑗 (𝐹) = −𝑌2,𝑖𝑗 (𝑉2𝑖 (𝐹) − 𝑉2𝑗 (𝐹)) 10-47

In the above equations, 𝐼0,𝑖𝑗 (𝐹), 𝐼1,𝑖𝑗 (𝐹) and 𝐼2,𝑖𝑗 (𝐹) are the after-fault sequence currents from
Bus i to Bus j, 𝑌0,𝑖𝑘 , 𝑌1,𝑖𝑘 and 𝑌2,𝑖𝑘 are the elements of the sequence admittance matrixes in row i
and column k. After finding the sequence currents, the phase currents can be found.

Example 10-1
In the following system the values of sequence impedances are given in the table. The neutral of
each generator is connected to ground via a j0.25/3 pu reactance. Find fault currents at Bus 3 for
balanced, SLG, DL and DLG faults through reactance j0.1 pu. Assume that prior to the fault the
generators are running at no load at their rated voltage of 1 pu and their emfs are in phase.

Solution:
The Thevenin equivalent impedance seen from Bus 3 needs to be found in different sequences.
For this purpose, a Δ-Y transformation as shown below for the positive and negative sequences
can be done.

As a result of this transformation, the Thevenin impedance for positive and negative sequences
is j0.22 pu. Based on this, the positive and negative sequence networks are shown below. Note
that the negative-sequence network has no source:

The zero-sequence network needs to be constructed based on the connection of the

transformers. This procedure is shown in the following figure:
As a result, the equivalent zero-sequence network seen from Bus 3 will have an impedance of
j0.35 pu as shown below:

- For the analysis of balanced fault, only the positive-sequence network will be involved.
The fault current of phase “a” in balanced fault is:

1
𝐼𝑎 (𝐹) = = −𝑗3.125 𝑝𝑢 = 3.125∠−90° 𝑝𝑢
𝑗0.22 + 𝑗0.1

For phases “b” and “c”:

𝐼𝑏 (𝐹) = 3.125∠150° 𝑝𝑢

𝐼𝑐 (𝐹) = 3.125∠30° 𝑝𝑢

- For SLG fault in phase “a” at Bus 3:

𝑉3 (0) 1
𝐼0 = 𝐼1 = 𝐼2 = = = −𝑗0.9174 𝑝𝑢
𝑍0 + 𝑍1 + 𝑍2 + 3𝑍𝑓 𝑗0.35 + 𝑗0.22 + 𝑗0.22 + 3 × 𝑗0.1
= 0.9174∠−90° 𝑝𝑢

The phase currents are:

𝐼𝑎 (𝐹) 1 1 1 𝐼0 −𝑗2.7523 2.7523∠−90°

2
[𝐼𝑏 (𝐹)] = [1 𝛼 𝛼 ] [𝐼1 ] = [ 0 ]=[ 0 ] 𝑝𝑢
2
𝐼𝑐 (𝐹) 1 𝛼 𝛼 𝐼2 0 0

- For DL fault between phases “b” and “c” at Bus 3:

𝐼0 = 0
𝑉3 (0) 1
𝐼1 = −𝐼2 = = = −𝑗1.8519 𝑝𝑢 = 1.8519∠−90° 𝑝𝑢
𝑍1 + 𝑍2 + 𝑍𝑓 𝑗0.22 + 𝑗0.22 + 𝑗0.1

The phase currents are:

 𝐼𝑎 (𝐹) 1 1 1 𝐼0 0 0
2
[𝐼𝑏 (𝐹)] = [1 𝛼 𝛼 ] [𝐼1 ] = [−𝑗1.8519] = [−3.2076] 𝑝𝑢
2 +𝑗1.8519
𝐼𝑐 (𝐹) 1 𝛼 𝛼 𝐼 +3.2076
2

- For DLG fault between phases “b” and “c” at Bus 3:

𝑉3 (0) 1
𝐼1 = = = −𝑗2.6017 𝑝𝑢
𝑍2 (𝑍0 + 3𝑍𝑓 ) (𝑗0.22)(𝑗0.35 + 𝑗0.3)
𝑍1 + 𝑗0.22 +
(𝑗0.22) + (𝑗0.35 + 𝑗0.3)
𝑍2 + 𝑍0 + 3𝑍𝑓
𝑉3 (0) − 𝑍1 . 𝐼1 1 − (𝑗0.22)(−𝑗2.6017)
𝐼2 = − =− = 𝑗1.9438 𝑝𝑢
𝑍2 𝑗0.22
𝑉3 (0) − 𝑍1 . 𝐼1 1 − (𝑗0.22)(−𝑗2.6017)
𝐼0 = − =− = 𝑗0.6579 𝑝𝑢
𝑍0 + 3𝑍𝑓 𝑗0.35 + 𝑗0.3

The phase currents are:

𝐼𝑎 (𝐹) 1 1 1 𝐼0 𝑗0.6579 0
2
[𝐼𝑏 (𝐹)] = [1 𝛼 𝛼 ] [𝐼1 ] = [−𝑗2.6017] = [4.058∠165.93° ] 𝑝𝑢
2
𝐼𝑐 (𝐹) 1 𝛼 𝛼 𝐼 𝑗1.9438 4.058∠14.07°
2

So the fault current through 𝑍𝑓 is:

𝐼𝐹 = 𝐼𝑏 (𝐹) + 𝐼𝑐 (𝐹) = 1.9732∠90° 𝑝𝑢

Reference
 Power System Analysis, 3rd Edition, Hadi Saadat – PSA Publishing 2011.