Chrysler - CCD (Chrysler Collision Detection) Data Bus - Carprog - 博客园

30/6/2017 Chrysler -- CCD (Chrysler Collision Detection) Data Bus - carprog - 博客园
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Chrysler -- CCD (Chrysler Collision Detection) Data Bus
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2 3 4 5 6 7 8 http://articles.mopar1973man.com/general-cummins/34-engine-system/81-ccd-data-bus
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16 17 18 19 20 21 22 CCD (Chrysler Collision Detection) Data Bus
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30 31 1 2 3 4 5 Description
搜索 The Chrysler Collision Detection (also referred to as CCD or C2D ) data bus system is
a multiplex system used for vehicle communications on many Chrysler Corporation vehicles.
谷歌搜索
Within the context of the CCD system, the term “collision“ refers to the system’s ability
最新随笔
to avoid collisions of the electronic data that enters the data bus
1. RealTek WiFi 模块 RTL8710AF
from various electronic control modules at approximately the same time.
RTL8711AF RTL8711AM
RTL8195AM Multiplexing is a system that enables the transmission of several messages over a single channel
2. RTL8710 Flasher or circuit.
3. RTL8710 ROM 符号表函数，常 Many Chrysler vehicles use this principle for communication between the various microprocessor
量，变量 based electronic control modules.
4. Delphi -- Compiler helper for
Many of the electronic control modules in a vehicle require information from the same sensing
initializing/finalizing variable
device.
5. SourceTree - 正在检查源... When
In the past, if information from one sensing device was required by several controllers,
cloning a repository, "Checking
a wire from each controller needed to be connected in parallel to that sensor.
Source" spins forever
6. Bitbucket Repository size limits In addition, each controller utilizing analog sensors required an Analog/Digital (A/D) converter in
7. 人生如坐公交车 order to “read“ these sensor inputs.
8. LPC18xx LPC43xx LPC4370
Multiplexing reduces wire harness complexity, sensor current loads and controller hardware
Bootrom USB DFU FPB - Flash
because each sensing device is connected to only one controller, which reads and distributes the
Patch and Breakpoint Unit
sensor information to the ,
9. FPGA4U FPGA SDRAM Controller
10. FGPA 双向 IO 自动方向控制 other controllers over the data bus. Also, because each controller on the data bus can access the
controller sensor inputs
随笔分类 to every other controller on the data bus, more function and feature capabilities are possible.
ALGO(54)
In addition to reducing wire harness complexity, component sensor current loads and controller
ALTERA(3)
hardware,
Analog(2)
multiplexing offers a diagnostic advantage. A multiplex system allows the information flowing
ANDROID(49)
APP(2) between controllers
ARM(24) to be monitored using a diagnostic scan tool.
ASTYLE(3) The Chrysler system allows an electronic control module to broadcast message data out onto the
AVR(5)
bus
BLUETOOTH(3)
where all other electronic control modules can “hear” the messages that are being sent.
BOARD(3)
C/C++(77) When a module hears a message on the data bus that it requires, it relays that message to its
CANBUS(10) microprocessor.
CHAR ENCODING(5) Each module ignores the messages on the data bus that are being sent to other electronic control
Circuit(211) modules.
Cloud(28)
With a diagnostic scan tool connected into the CCD circuit, a technician is able to observe many
CORTEX(31)
of the electronic control module function
Crypto/Auth(1)
and message outputs while; at the same time, controlling many of the sensor message inputs.
DataBase(4)
DELPHI(105) The CCD data bus, along with the use of a diagnostic scan tool and a logic based approach to test
ECLIPSE(11) procedures,
EEPROM(1) as found in the Diagnostic Procedures manuals, allows the trained automotive technician to more
ENGLISH(12) easily,
EVAL BOARD accurately and efficiently diagnose the many complex and integrated electronic functions
EWARM(26) and features found on today’s vehicles.
FLASH(1)
FONT(5)
FPGA(16) Powertrain Control Module (PCM)
Freescale(13) Transmission Control Module (TCM)
http://www.cnblogs.com/shangdawei/p/3570499.html 1/21
GIT(11) Body Control Module (BCM)
GNU/LINUX(4) Instrument Cluster (IC)
Graphics(6) Controller Antilock Brakes (CAB)
Hardware(1) Overhead console
HTML(1) Automatic Temperature Controller (ATC)
I2C(1) Air Bag Controller
IC(31)
IDA(24)
JAVA(11)
Operation
JLINK(14)
JTAG(67) The CCD data bus system was designed to run at a 7812.5 baud rate (or 7812.5 bits per
KEIL C166(4) second).
KEIL MDK(3) In order to successfully transmit and receive binary messages over the CCD data bus, the system
LCD(3) requires the following:
LINUX(3)
Bus (+) and Bus (–) Circuits
MCU
MISC(40) CCD Chips in Each Electronic Control Module
MULTISIM(1)
Bus Bias and Termination
NXP ARM(42)
OllyDBG Bus Messaging
PCB(6)
Bus Message Coding
PID(9)
RegEx(4) Following are additional details of each of the above system requirements.
RF(32)
Bus Circuits
RTOS(32)
SCSI(5) The two wires (sometimes referred to as the “twisted pair”) that comprise the CCD data bus are
SDCARD(2) the D1 circuit [Bus (+)], and the D2 circuit [Bus (–)].
SmartCard(7)
The "D" in D1 and D2 identify these as diagnostic circuits. Transmission and receipt of binary
SOFTWARE(2)
messages on the CCD data bus
SPI(5)
is accomplished by cycling the voltage differential between the Bus (+) and Bus (–) circuits.
STM32(123)
STM8 The two data bus wires are twisted together in order to shield the wires from the effects of any
Tasker(31) Electro-Magnetic Interference (EMI)
TCP/IP(13) from switched voltage sources.
Transponder(1)
An induced EMI voltage can be generated in any wire by a nearby switched voltage or switched
USB(51)
ground circuit.
VERILOG(1)
By twisting the data bus wires together, the induced voltage spike (either up or down) affects
VHDL(2)
both wires equally.
Visual Studio(7)
Since both wires are affected equally, a voltage differential still exists between the Bus (+) and
Web 编程(8)
WIFI(20)
Bus (–) circuits,
Win32 API(11) and the data bus messages can still be broadcast or received.
WINDOWS(73) The correct specification for data bus wire twisting is one turn for every 44.45 millimeters (1 3⁄4
WordPress(6) inches) of wire.
XILINX(12)
XML(3)
YubiKey(3)
汽车电子(47)
在线支付(3)
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CCD Chips
2014年12月 (2) In order for an electronic control module to communicate on the CCD data bus, it must have a
2014年11月 (106) CCD chip (Fig. 5).
2014年10月 (71)
The CCD chip contains a differential transmitter/receiver (or transceiver), which is used to send
2014年9月 (29)
and receive messages.
2014年8月 (10)
2014年7月 (17) Each module is wired in parallel to the data bus through its CCD chip.
2014年6月 (1)
The differential transceiver sends messages by using two current drivers:
2014年5月 (10)
2014年4月 (10) one current source driver, and one current sink driver.
2014年3月 (12)
The current drivers are matched and allow 0.006 ampere to flow through the data bus circuits.
2014年2月 (20)
When the transceiver drivers are turned On, the Bus (+) voltage increases slightly, and the Bus
2014年1月 (20)
(–) voltage decreases slightly.
2013年12月 (25)
By cycling the drivers On and Off, the CCD chip causes the voltage on the data bus circuit to
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fluctuate to reflect the message.
2013年9月 (48)
2013年8月 (73) Once a message is broadcast over the CCD data bus, all electronic control modules on the data
2013年7月 (57) bus have the ability
2013年6月 (44) to receive it through their CCD chip. Reception of CCD messages is also carried out by the
2013年5月 (53) transceiver in the CCD chip.
2013年4月 (65)
The transceiver monitors the voltage on the data bus for any fluctuations.
2013年3月 (11)
When data bus voltage fluctuations are detected, they are interpreted by the transceiver as
2013年2月 (1)
2013年1月 (4)
binary messages
2012年12月 (3) and sent to the electronic control module’s microprocessor.
2012年11月 (2)
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2011年1月 (7)
Bus Bias And Termination

The voltage network used by the CCD data bus to transmit messages requires both bias and
termination.
At least one electronic control module on the data bus must provide a voltage source for the CCD
data bus network known as bus bias,
and there must be at least one bus termination point for the data bus circuit to be complete.
However, while bias and termination are both required for data bus operation,
they both do not have to be within the same electronic control module.
The CCD data bus is biased to approximately 2.5 volts. With each of the electronic control
modules wired in parallel to the data bus,
all modules utilize the same bus bias. Therefore, based upon vehicle options, the data bus can
accommodate two
or twenty electronic control modules without affecting bus voltage.
The power supplied to the data bus is known as bus biasing.

Bus bias is provided through a series circuit. To properly bias the data bus circuits,
a 5 volt supply is provided through a 13 kilohm resistor to the Bus (–) circuit (Fig. 6).
Voltage from the Bus (–) circuit flows through a 120 ohm termination resistor to the Bus (+)
circuit.
The Bus (+) circuit is grounded through another 13 kilohm resistor.
While at least one termination resistor is required for the system to operate, most Chrysler
systems use two.
The second termination resistor serves as a backup (Fig. 7).
The termination resistor provides a path for the bus bias voltage.
Without a termination point, voltage biasing would not occur.
Voltage would go to 5 volts on one bus wire and 0 volts on the other bus wire.
The voltage drop through the termination resistor creates 2.51 volts on Bus (–), and 2.49 volts
on Bus (+).
The voltage difference between the two circuits is 0.02 volts.
When the data bus voltage differential is a steady 0.02 volts, the CCD system is considered
“idle.”
When no input is received from any module and the ignition switch is in the Off position for a pre-
programmed length of time,
the bus data becomes inactive or enters the ”sleep mode.”
Electronic control modules that provide bus bias can be programmed to ”wake up” the data bus
and become active upon receiving any predetermined input or when the ignition switch is turned
to the On position.
Bus Messaging
The electronic control modules used in the CCD data bus system contain microprocessors.
Digital signals are the means by which microprocessors operate internally and communicate
messages to other microprocessors.
Digital signals are limited to two states, voltage high or voltage low, corresponding to either a
one or a zero.
Unlike conventional binary code, the CCD data bus systems
translate a small voltage difference as a one (1), and a larger voltage difference as a zero (0).
The use of the 0 and 1 is referred to as binary coding.
Each binary number is called a bit, and eight bits make up a byte. For example: 01011101
represents a message.
The controllers in the multiplex system are able to send thousands of these bytes strung together
to communicate a variety of messages.
Through the use of binary data transmission, all electronic control modules on the data bus can
communicate with each other.
The microprocessors in the CCD data bus system translate the binary messages into Hexadecimal
Code (or Hex Code).
Hex code is the means by which microprocessors communicate and interpret messages.
When fault codes are received by the DRBIII scan tool, they are translated into text for display
on the DRBIII screen.
Although not displayed by the DRBIII for Body Systems, hex codes are shown by the DRBIII for
Engine System faults.
When the microprocessor signals the transceiver in the CCD chip to broadcast a message,
the transceiver turns the current drivers On and Off, which cycles the voltage on the CCD data
bus circuits to correspond to the message.
At idle, the CCD system recognizes the 0.02 voltage differential as a binary bit 1.
When the current drivers are actuated, the voltage differential from idle must increase by 0.02
volt for the CCD system to recognize a binary bit 0.
The nominal voltage differential for a 0 bit is 0.100 volts. However, data bus voltage differentials
can range anywhere between 0.02 and 0.120 volt.
Bus Failure
The CCD data bus can be monitored using the DRBIII scan tool.
However, it is possible for the data bus to pass all tests since the voltage parameters will be in
“range“ and false signals are being sent.
There are essentially 12 “hard failures“ that can occur with the CCD data bus:
Bus Shorted to Battery
Bus Shorted to 5 Volts
Bus Shorted to Ground
Bus (+) Shorted to Bus (–)
Bus (–) and Bus (+) Open
Bus (+) Open
Bus (–) Open
No Bus Bias
Bus Bias Level Too High
Bus Bias Level Too Low
No Bus Termination
Not Receiving Bus Messages Correctly
Refer to the appropriate diagnostic procedures for details on how to diagnose these faults using a
DRBIII scan tool.
Bus Failure Visual Symptoms & Diagnosis

The following visible symptoms or customer complaints, alone or in combination, may indicate a
CCD data bus failure:
Airbag Indicator Lamp and Malfuntion Indicator Lamp (MIL) Illuminated
Instrument Cluster Gauges (All) Inoperative
No Compass Mini-Trip Computer (CMTC) Operation
CDP68HC68S1
Features
• Differential Bus for Minimal EMl
• High Common Mode Noise Rejection
• Ideal for Twisted Pair Wiring
• Data Collision Detection
• Bus Arbitration
• Idle Detection
• Programmable Clock Divider
• Power-On Reset
Description
The CDP68HC6SS1 Serial Bus Interface Chip (SBlC) provides a means of interfacing in a Small
Area Network configuration,
various microcomputers (MCU’s) containing serial ports. Such MCU’s include the family of
68HC05 microcontrollers.
The SBlC provides a connection from an MCU’s Serial Communication Interface (asynchronous
UART type interface)
or Serial Peripheral Interface (synchronous) to a medium speed asynchronous two wire
differential signal bus
designed to minimize electromagnetic interference.
This two wire bus forms the network bus to which all MCU’s are connected (through SBI chips).
Each MCU operates independently and may be added or deleted from the bus with little or no
impact on bus operation.
Such a bus is ideal for inter-microcomputer communication in hazardous electrical environments
such as automobiles, aircraft or industrial control systems.
In addition to acting as bus arbitor and interface for microcomputer SCI port to differential bus
communication,
the CDP68HC68S1 contains all the circuitry required to convert and synchronize Non-Return-to-
Zero (NRZ) 8-bit data
received on the differential bus and clock the data into a microcomputer’s SPl port.
Likewise, data to be sent by a microcomputer’s SPI port is converted to asynchronous format

by appending start and stop bits before transmitting to other microcomputers.
Refer to the data sheet for the CDP68HCO5C4 for additional information regarding CDP68HCO5
microcomputers
and their Serial Communications and Serial Peripheral Interfaces.
The CDP68HC68S1 is supplied in a 14 lead dual-in-line plastic package (E suffix), and in a 20

lead small outline plastic package (M suffix).
Operating voltage ranges from 4V to 7V and operating temperature ranges from -40oC to
+105oC.
Differential Transceiver Cell
The differential transceiver is a serial interface device which accepts digital signals and translates
this information for transmitting on the two wire differential bus.
The transmitter section (shown in Figure 4), when transmitting, provides matched constant
current sources to the bus “+” and bus “-” I/O sourcing and sinking respectively.
When transmitting, a logic zero at the “transmit data” input causes the bus “+” I/O to provide
source current and the bus “-” I/O to provide a matched sink current.
A logic one at the “transmit data” input causes the bus “+” and bus “-” I/Os to
simultaneously provide a high impedance state.
The bus depends on external resistor components for bias and termination. Recommended
resistor sizes are shown in Figure 4.
A zero transmitted on the bus will appear as a large voltage drop across the BUS+ and BUS-
pins,
i.e. BUS+ might typically sit at +2.8V and BUS- at +2.2V for a logic zero.
For a logic level one, the SBlC actually three-states the BUS+ and BUS- pins and relies on
external resistors to bias the bus lines.
The lines are both biased to sit at approximately 2.5V with a small (perhaps 20mV) voltage drop
across the two lines.
In this condition the BUS- line actually sits at a slightly higher potential than the BUS+ line. See
Figure 5.
Thus, the bus actually “floats” to a logic level one, but must be driven to a logic level zero.
Logic 0-bits always dominate over logic 1-bits on the bus.
If two MCU’s simultaneously transmit a zero and a one on the bus, the zero will override the one
and the bus will merely appear to be transmitting a zero.
The “marking” or idle signal on the bus is a logic one. If the bus is idle or if a micro is sending a
logic one, then a one will appear on the bus.
In addition to the transmission of data, the differential data transceiver accepts at its bus “+” and
bus “-” I/Os, serial differential data
which is translated into the standard digital logic levels. This reception of data also occurs while
transmitting, thus reflecting the data seen on the bus back into the SBIC data register.
The differential transceiver cell allows bus activity by other devices on the bus “+” and bus “-”
I/Os when power to the cell is shut off.
Therefore, this powered off condition places the transceiver outputs, BUS “+” and BUS “-”, in a
high impedance state.
When the cell is either being powered up or down, with or without bus activity, SCR latch-up
protection is provided such that this activity is not affected.
Receive data is an output from the differential transceiver cell. It is the output of a differential
amplifier which decodes the bus “+” and “-” I/O.
When the bus “+” and “-” has been driven positive and negative respectively to a
differential voltage value greater than VIDH,
the output of the differential amplifier is a logic one, which is inverted and considered a 0-bit
from the bus.
Otherwise, for level below VIDL the differential amplifier output is a logic zero, which, in turn, is
inverted and considered a 1-bit from the bus.
Twisted wire pair (or adjacent PC board traces) is recommended for the two differential bus lines.
The BREAK input, when held at a logic zero, (low) causes the differential transmitter driver to
generate a continuous logic level zero on the differential bus.
This action can generate a data collision which can be either used as a break or a request for
arbitration by the system.
When held at logic one, (high) this input has no effect on the operation of the cell.
The out of range output is normally a logic zero but goes to a logic one when the common mode
voltage
on both differential bus inputs exceeds a voltage value greater than VMAX or less than VMIN (see
device specifications).
This output is used by a latch to hold the received data at the logic level it was before the over
range signal occurred.
Provided on chip is a power-on reset function.
The transceiver cell’s reset output is held to a logic zero on power up and switches to a logic one
at or before VDD rises to 4.0V.
This output is used to ensure that other on-board logic has been properly initiated.
During this reset time, the bus “+” and the bus “-” l/Os provide a high impedance state to the
bus.
Bus Speed
SBlC systems typically use a bus speed of 7812.5 bits/second which is accomplished by using a
1MHz internal clock.
However, no restriction on any other baud rate is designed into the chip, except its upper speed
limit (see device specifications).
Bus Byte Format
All bytes transmitted on the bus follow the standard UART style asynchronous non-return-to zero
data format consisting oft
start bit (logical zero) followed by 8 data bits (LSB first), and 1 stop bit (logical one).
Bus Message Format
All messages transmitted on the bus consist of a number of bytes, from 1 to N, with no
restriction on length.
The user must be aware, however, that the longer the message length, the greater the
probability of collision with messages being transmitted
at random from other masters on the bus.
Typical message lengths of systems now in use range from 1 to 4 bytes.

The actual definition of each byte sent is left for the user to determine, i.e. the user must define
the system protocol.
For instance, a typical (and recommended) protocol might dictate that the first byte of each
message sent be a unique address/identification byte.
The first byte sent by a node (an MCU coupled with an SBl chip) might contain address
information telling
where (to which node[s]) the message is targeted for or where the message came from.
Other possibilities would be to identify the type of message sent (e.g. an instruction or just
information) or the length of the message.
The remaining bytes in each message can be merely data bytes that comprise the actual
message.
The user can even use the last byte as a check sum so that all receiving nodes can check for
errors in transmission.
Messages are normally received by all nodes on the bus and may be processed by one or more
micros,
i.e., each MCU may decide, after receiving the first byte (address/ID byte) that this particular
message is not needed for its operation.
The MCU can then ignore the remainder of the message.
Prioritization Since simultaneous transmission of address/ID bytes from several microcomputers

is a possibility,
a system of prioritization should be determined for bus arbitration.
Due to the electrical characteristics of the differential data bus, each unique address/ID byte can
automatically contain priority information used for bus arbitration.
Merely use “lower” value ID bytes for higher priority messages.
“Lower” value, in the SBlC case, means an ID byte with more zero’s in its least significant
locations.
To further explain, since the differential bus transmits data least significant bit first and a zero
overrides a 1-bit simultaneously transmitted by different nodes,
an ID byte with least significant bit equal to zero will override an ID byte from a micro whose
least significant bit is a one.
If this does occur on-chip bus arbitration will automatically allow only one SBlC chip (with the
highest priority address/ID byte) to continue transmitting.
In this case it is the micro who transmitted the 0-bit. Assuming both ID bytes contain
identical LSBs (bit 0) then arbitration is carried on to the next bit (bit 1),and soon.
Reflected Data
Whenever a microcomputer sends data through the SBIC and onto the differential bus, it will
always receive reflected data back.
The reflected data is the data that was actually seen on the bus.
Keep in mind that during data collisions between simultaneously transmitting micros, zeroes
override ones.
In addition, any noise that may have been induced on the bus may alter the resultant reflected
byte.
Bus Arbitration
Bus arbitration is the attempted transmission onto the differential bus of an initial byte
(preferably an address/ID byte)
by one or more user microcomputers.
The purpose of bus arbitration is to enable a single microcomputer to obtain sole usage of the
bus for the purpose of transmitting a message.
Bus arbitration is accomplished via a combination of methods which include an MCU software
comparison of transmitted bytes to reflected bytes,
the SBlC’s collision detection circuit, and its start bit arbitration detector circuits.
Collision Detection
The SBlC’s collision detector circuit compares the bits being sent from a user microcomputer to
the reflected byte simultaneously received back from the differential bus.
If the collision detector detects a difference in the data, it immediately blocks the user
microcomputer’s transmitted data from further reaching the bus.
This will happen, as stated in the “Prioritization” section, when a micro with a higher
priority address/ID byte attempts “simultaneous” transmission
(actually, i.e. within a time window of 1/4 bit time).That micro, with a higher priority ID byte, is
obviously sending a 0-bit and its reflected byte matches the byte it is sending.
Not detecting a collision, it continues to transmit its message, while the lower priority MCU is cut
off from transmitting on the bus.
The lower priority micro will be inhibited from transmitting on the bus until the message
presently on the bus has ended (EOM = “End of Message” condition).
End of Message Condition
After transmitting the last byte of a message, the transmitting MCU must generate an End of
Message (EOM) condition.
An EOM condition is defined as a 10-bit length idle condition, i.e., the bus must remain idle
(logic1) for a period of 10- bit times (1280 internal clock periods).
This can be done by merely creating a 10-bit delay in MCU software.
Start Bit Arbitration Detection Arbitration, as discussed above, is only necessary when two or
more micros attempt to transmit within 1/4 bit time (32 internal clock periods) of each other.
Otherwise, once a micro begins a transmission on the differential data bus, all other SBl chips
sense the start bit and inhibit their microcomputers from transmitting
(again, after a 32 clock period arbitration window delay). Once the arbitration detector circuit has
blocked an MCU’s transmission, access to the bus will be blocked until an End of Message
condition.
Start of Message Delay
In order to properly synchronize various MCU’s (which may be using different modes of
operation) for impartial arbitration, each node must delay 2-bit times (256 internal clock periods)
after detecting the IDLE signal drop low before transmitting, i.e., before the start bit of the next
message reaches the bus.
When using the SPI or Buffered SPl modes, this delay is automatically designed into the SBl chip.
However, when using the SCl mode, the MCU must support this required delay.
Fortunately, 68HC05 microcomputers using the SCI port will inherently experience a
delay between the time
that the SCl data register is loaded and the time that the start bit actually appears on the SCl
port transmit pin (TxD).
At a baud rate of 7812.5 bps this delay can be as long as 256 SBl chip internal clock periods. If
this is so, then the user MCU does not have to worry about providing this delay.
Idle Detection
An idle detector circuit is used to detect when the differential bus is in the idle condition, i.e., no
user microcomputer has control of the bus and the bus is sitting at a mark condition (a logic
one).
The idle detector senses a received stop bit and delays for a short idle period of 10-bit times,
during which the bus must remain idle. The idle output pin is then set to a logic zero (true).
It is later set to a logic one by receiving a start bit. During the 10-bit time delay, if a non-idle
condition such as noise is detected on the bus, the delay period counter will be restarted.
Due to the 10-bit time idle delay period, once an MCU wins bus arbitration, it should send the
next data byte to be transmitted within a period of 10-bit times (1280 internal clock periods).
Each subsequent data byte to be sent should also not exceed the interbyte maximum of 10-bit
times.
If this maximum is exceeded, all SBlC chips will have detected the idle condition and now pull
their idle lines low and reset their bus arbitration and collision detection circuits,
thereby allowing other SBl chips with messages to send to arbitrate for the bus. Figure 6 shows
the detailed operation of the serial bus interface chip during bus arbitration.
This example shows the arbitration of a single byte (e.g. the address/ID byte) from three
different user microcomputers. Two full arbitration cycles are shown.
Break Generator
A request for arbitration can be generated by a node that needs to interrupt transmission of a
long data string.
This can be accomplished by forcing the SBlC’s IDLE pin to a logic zero; this forces a data
collision (by sending 0-bits) after three data bytes have been transmitted,
and the transmitting MCU is required to detect this break condition and stop transmitting.
It is, however, allowed to re-arbitrate for the bus and the interrupting mode may not generate a
second break condition if it loses arbitration.
Using the CDP68HC68S1
Following are some hardware and software recommendations for using CDP68HC68S1 Serial Bus
Interface Chip.
Requirements may vary depending upon the user’s system configuration.
Hardware (General)
The differential bus lines (BUS+ and BUS-) must be terminated with external resistors as shown
in Figure 4.
This applies, however, only to one node (an MCU/SBlC pair) along the bus. Since all SBl chips are
wired in parallel across the network bus,
there is no need for additional 13K bias resistors at each node. The 120Ω termination
resistors should, however, be present at two nodes if the network does indeed contain two or
more nodes.
The 120Ω resistor provides the voltage drop across which the SBl chip senses logic zero and logic
1-bits.
If two nodes each utilize 120Ω termination resistors as shown in Figure 7A, the effective
resistance across the BUS+ and BUS- pins drop to 60Ω total (due to the parallel wiring method).
Any less resistance would not provide an ample voltage drop for the receiver cell op amp
to sense. Following these guidelines, typical systems might look like those shown in Figure 7.
NOTE: Hardware configuration for a network consisting of two microcomputers. Notice that the
pullup resistor is connected to the BUS- pin and the pulldown to BUS+.
NOTE: Hardware configuration for a network consisting of 3 or more MCU’s. Notice that the bus
utilizes no more than 1 set of 13K bias resistors and no more than two 120Ω termination
resistors.
Wiring Diagrams
1998.5 to 2002 Dodge Cummins CCD Network Wiring Map
http://www.justanswer.com/jeep/5nomb-jeep-1998-1998-grand-cherokee-limited-5-9l.html
DRB III DLC
Well, the CCD bus network is used in this vehicle for the various controllers to communicate with
each other, and the BCM does use this network to communicate information to the Drivers Door
Module (DDM) and Passenger Door Module (PDM). One of the things the features of this is that
the BCM can tell the DDM and PDM to still allow power window operation after the ignition has
been turned off for several seconds. You may have a problem with the BCM, or maybe with the
ignition switch contacts. Now I don't think this is a bus issue yet, but could be. The best way to
test it is with a scan tool. However, a basic bus voltage test can be done at the data link
connector. Use a digital voltmeter and test the ccd bus voltage at the data link connector. You
should have about 2.5 volts on cavities 3 and 11. Go ahead and check this with the ignition on,
and let me know what your voltage readings are.
Chris
DATA LINK CONNECTOR CAV CIRCUIT FUNCTION

1--
2--
3 D1 18VT/BR CCD BUS(+)
4 Z1 18BK GROUND
5 Z2 18BK/OR GROUND
6 D84 20BK/WT SCI TRANSMIT
7 D83 20BK/PK SCI RECEIVE
8--
9--
10 - -
11 D2 18WT/BK CCD BUS (-)
12 D98 20WT SCI TRANSMIT
13 - -
14 - -
15 - -
16 F756 18VT FUSED B(+)
Chrysler 6-Pin CCD Cable for Mastertech
Required for MTS 3100 Mastertech/ Tech 1A diagnosis of 1988 to 1995 Chrysler
Electronic Automatic Transmissions (EATX) that communicate through the CCD Bus.
This adapter is also used on 1993 to 1995 LH-body cars that route engine system SCI
data through the CCD connector.
Note: This adapter must be used with the Chrysler Engine/CCD VIM (02002192)
http://mdhmotors.com/can-communications-vehicle-network-protocols/
Chrysler CCD
Chrysler Collision Detection
Also called C2D

Introduced on the 1988 Dodge Dynasty
Transmission and body control networks
Handles a max of 13 Modules
12+ Scan tools
Chrysler Collision Detection, CCD, was one of the fi rst widely used vehicle-wide multiplexing
protocols used in the US. Introduced in 1988 on the Dodge Dynasty and Chrysler New Yorker,
CCD was originally used for transmission controller to engine controller communications and data
sharing. Soon thereafter, body control functions were added to the CCD bus.
CCD Bias Voltage Key Factors:

Bias voltage provides power to the bus
Bias voltage varies slightly between vehicles
Bias supplied by one or more modules, typically by the module that “wakes-up” first
Bias voltage must be between 1.5 volts and 3.5 volts, otherwise controllers may not be able
to interpret messages
CCD Bus Termination

Besides power, the bus also needs ground. The CCD Bus Termination ground is:
Provided through one or more 120 ohm termination resistors

Located in one or more modules
Bias and termination are not necessarily supplied by the same module
CCD Bias and Termination

Bias can be provided by either the BCM, PCM, ETAX, VIC or VTA. Any module can provide
termination and the PCM may provide backup termination. If PCM and TCM are the only modules
the TCM provides Bias and the PCM provides termination.
CCD Bus Resistance Values

Typical CCD bus resistance values:
Single termination resistor 100-140 ohms

Dual termination resistors 40-80 ohms
The termination resistor resistance should not be either 0 ohms or infinity. Without termination,
bus voltage will be 5.0 volts on one wire and 0.0 volts on the other. CCD bus termination
resistance can be measured with an ohm meter (battery disconnected) at either CCD pin at the
DLC. Because the number of termination resistors can vary, an exact resistance specification is
not possible. However, the resistance should not read 0 ohms (shorted) or infinity (open).
Without termination, bus voltage will be 5.0 volts on one wire and 0.0 volts on the other, as
opposed to the proper 2.51 volts on CCD- and 2.49 volts on CCD+.
Testing Note:
Remember when testing the CCD bus that it uses a floating ground, not vehicle ground. To see
an accurate representation of the bus voltage on the lab scope you must connect across CCD+
and CCD-, not CCD+ to ground.
The two wires of the CCD bus are connected in parallel; however, the manner in which the
connections are made varies. Either standard splices may be used, or the bus can be connected
at a joint connector or splice pack. The joint connector can make bus diagnosis significantly
easier by having access to all modules on the bus in one location. Splices, on the other hand ,can
be located anywhere on the vehicle.
分类: 汽车电子
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ARM(24) to be monitored using a diagnostic scan tool.

2012年12月 (3) and sent to the electronic control module’s microprocessor.

Bus Bias And Termination

The power supplied to the data bus is known as bus biasing.

Unlike conventional binary code, the CCD data bus systems

The use of the 0 and 1 is referred to as binary coding.

Bus Shorted to Battery

Bus Shorted to 5 Volts

Bus Shorted to Ground

Bus (+) Shorted to Bus (–)

Bus (–) and Bus (+) Open

Bus (+) Open

Bus (–) Open

Bus Bias Level Too High

Bus Bias Level Too Low

Not Receiving Bus Messages Correctly

Bus Failure Visual Symptoms & Diagnosis

Airbag Indicator Lamp and Malfuntion Indicator Lamp (MIL) Illuminated

Instrument Cluster Gauges (All) Inoperative

No Compass Mini-Trip Computer (CMTC) Operation

Likewise, data to be sent by a microcomputer’s SPI port is converted to asynchronous format

The CDP68HC68S1 is supplied in a 14 lead dual-in-line plastic package (E suffix), and in a 20

Differential Transceiver Cell

Logic 0-bits always dominate over logic 1-bits on the bus.

Provided on chip is a power-on reset function.

Bus Byte Format

Bus Message Format

at random from other masters on the bus.

Typical message lengths of systems now in use range from 1 to 4 bytes.

The MCU can then ignore the remainder of the message.

Prioritization Since simultaneous transmission of address/ID bytes from several microcomputers

a system of prioritization should be determined for bus arbitration.

Merely use “lower” value ID bytes for higher priority messages.

by one or more user microcomputers.

End of Message Condition

This can be done by merely creating a 10-bit delay in MCU software.

Start of Message Delay

Using the CDP68HC68S1

DRB III DLC

DATA LINK CONNECTOR CAV CIRCUIT FUNCTION

Chrysler 6-Pin CCD Cable for Mastertech

Also called C2D

Handles a max of 13 Modules

12+ Scan tools

CCD Bias Voltage Key Factors:

CCD Bus Termination

Provided through one or more 120 ohm termination resistors

CCD Bias and Termination

CCD Bus Resistance Values

Single termination resistor 100-140 ohms

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