ENTUPLE TECHNOLOGIES A SHORT TERM COURSE on Analog IC Design - Circuit and Layout Design Methodologies Using CADENCE ANALOG DESIGN FLOW PIV e Lite p Heo PY AN Aa) SS December 18th - 22nd, 2017 Organized by ENTUPLE TECHNOLOGIES Pvt. Ltd. eho ie ous: Who should Attend? This Shor Term Course (STC) is designed to provide deeper insights | Research scholars pursuing research in Analog circuit in Analog Circuit Design, layout concepts. The program provides the Gia aie Fees industry ways of working environment fr participants. It progressively. (gy students aspiring to get started with concepts of builds the concepts witha kick start on functional biocks such as Rsseateaeay andl erent Rinaaln ard isminn to current mirrors, repeaters, operational amplifiers and delivers deep career in semiconductor industry insights on characterization. This program benefits students to fine tune their skill and explore the opportunities in analog circuit and layout design more effectively through mini projects, projects, research activities & comprehensive skill development to boost the employment in core semiconductor industry. The program also caters to the needs of research scholars pursuing their research in custom IC Design/ Analog circuit and Layout % rs . A at Key Learning Outcomes: ft d ‘tthe end of the program you will be able to + Analyze the performance specification requirements and identify the suitable cicult topologies ~ * Characterize the PDK for device analog model parameters + TSynthesize basic and OP-AMP amplifier circuit topologies = = + Design CMOS Ampifie circuits for given DC and AC performance parameters + Develop programmed spread sheets for ampifier design automation + Design and characterize a seven ~ pack CMOS Compensated OP-AMP at the schematic design entry level + Derive layout constrains forthe physical design ofthe OP-AMP and carry out DRC and LVS + Carry out the physical verification and parasitic extraction + Back Annotate and carry out Post Layout Simulation! Characterization — 1 Wa Mie WHAT OUR CUSTOMERS SAY: 1 | got motivated so will work on more myself on the domain. iharika, Student, IIT Roorkee {learnt Designing of biasing differential amplifier circuit. — Ajishek Raj, Student, DTU, Delhi Learning was better matched by linking practical to theory concepts. —~ Akhilesh Naik, Research Scholar, BITS GoaCourse Outline: Day 1: Fundamentals of Analog Signal Processing - CMOS Amplifier Topologies and Performance + Review of the generic amplifier performance parameters — Gain, Power Dissipation, Frequency Response, (Noise — optional, time permitting) + Synthesis of Basic Amplifier Circuit Topologies - Basic Amplifier Circuit Topologies: CS, CD and CG + Large and Small Signal DC Performance Analysis and Design of Basic Amplifiers * Single and Differential Ended Signaling - Concept Illustration - What really is a common mode signal? + The Basic Ideal OP-AMP and its properties - What really is virtual short and virtual ground? + Labt: PDK Device Characterization for Analog Model Parameters Lab 2: Hands — on Tutorial on Design and Simulation of a CS Amplifier for Large and Small Signal DC performance + Lab 3: Design and Simulation of the Bias Circuit for the CS amplifier: Hands — on Tutorial Day 2: Small Signal DC Design and Simulation of the Basic Differential Pair / Analog Layout Design Concepts + Interpreting the Design Specifications + Design Methodology and Flow -Large Signal and Small Signal DC Design + Lab 4: Design and Performance Characterization of CMOS Current Mirror (Schematic Design and Simulation) + Lab 5: DC Performance Characterization of the Basi¢ CMOS Differential Amplifier (5- Pack OP-AMP) Day 3-4: Frequency Response and Compensation of Amplifiers - Performance Analysis + Effect of the Amplifier BW limitations on Analog Signal Processing — Ilustration + Review of Transfer Functions and Frequency Response Plots; FB concepts and Effect of FB on Frequency Response, Stability and Compensation + Gain - BW Enhancement Techniques — The CASCODE Stage + Small Signal AC Performance of CS and Differential Pair + Lab 7: Design and Characterization of the CS amplifier for Small Signal DC and AC Performance + Lab 8: Design and Characterization of Differential Pair for Small Signal DC and AC Performance Day 5: Design and Performance Characterization of a 7 - Pack OPAMP + AHands-on Tutorial for Schematic and Layout Design of a CMOS OP-AMP for the given Specifications and Characterization About Entuple: Entuple is a next generation solutions enabler in, cutting edge technologies. Entuple delivers world class simulation solutions in Applied Electromagnetics, ‘Semiconductor (VLSI), System Design & Reliability, Mechanical, CFD and RF. Our product solutions Coens include PCB Prototyping, Planer Antenna prototyping BUC Ou eRe) systems, Entuple has developed its own range of Serer semiconductor based power drives and process Ree R Gerry control solutions, We cater to wide range of Seer) customers in semiconductor, manufacturing, defense & aerospace and academia reo) Registration Fee: Practicing engineers: INR 25,000.00 Teaching Faculty / Research Scholars / PG / UG students: INR 10,000.00 Lab Technician / Instructors: INR 7,000.00 Note: DD / Cheque in favour of Entuple Technologies Pvt. Ltd., Bangalore. (Tea and working lunch will be provided at the venue during the program. Prices are inclusive of all taxes.) Venue: ENTUPLE TECHNOLOGIES Pvt. Ltd. #2730, 80 Feet Road, HAL 3rd Stage, Indiranagar, Bangalore - 560 038 Tel: +91 80 42028111, Fax: +91 80 30723692, Web: www.entuple.com