DEPARTMENT OF ELECTRICAL AND ELECTROINC ENGINEERING

BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY

EEE 304 : Digital Electronics Laboratory

EXPERIMENT NO. 2: INTRODUCTION TO DIGITAL CIRCUIT

DESIGN CONCEPT.

PRELAB

Submit your Prelab before starting the experiment.

1. Show the truth table of a two input AND, NAND, OR and NOR gate.
2. Show the truth table of the following function

F(A,B,C) = AC+BC

3. What is a Complex Programmable Logic Device (CPLD) ? Show the

address and the corresponding data of the 16x1 SRAM look-up table
which will implement the following four variable function

F(A,B,C,D) = AB+CD

1. INTRODUCTION:

The design of a digital system begins with a set of specification. Here the essential
features of the product are identified. From a complete set of specification, a general
structure of the design is defined which is more commonly known as architecture
design. As the general structure is established, CAD tools are used to work out the
details. CAD tools enables the designer to simulate the behavior of incredibly complex
products, and such simulations are used to determine whether the obtained design
meets the required specifications. If errors are found, then appropriate changes are
made and the verification of the new design is repeated through simulation. When the
simulation indicates that the design is correct, a complete physical prototype of the
product is constructed. The prototype is thoroughly tested for conformation with the
specification. When the prototype passes all the tests, then the product goes to
production.

Experiment 1

Design a two way multiplexer circuit such that the output will be connected to the data
source X1 when the control signal S is High, and the output will be connected to the
data signal X2 when the control signal S is low.

Simulate the design to verify its functionality and implement it in a FLEX10K

Complex Programmable Logic Device (CPLD) chip.

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Experimental Procedure

In this experiment we will use ALTERA corporations Quartus II software for the
design, simulation and implementation of our design. We will go through the following
steps-

1. Design entry using schematic

2. Compilation and error location
3. Functional simulation
4. Floorplan
5. Design Compilation for the generation and conversion of configuration data
6. Download the design (configuration data) to LP2900 development board which
contain FLEX10K CPLD based design platform.
7. Test and verify the functionality of the circuit.

2. Design Entry Using Graphic Editor

The standard procedure for the schematic based design entry in Quartus II is as follows.

.
Create a New Project
1. In the menu bar select “File” and click “New Project Wizard”
2. Click Next and “Set working directory” and “Project Name”
3. In “Set the family and device you want to target for compilation” select the
device “FLEX10K”, select package “TQFP”, Pin “144”, speed category “3”
and select the device “EPF10K10TC144-3”.
4. Select “Next” click “Finish”.

Creating the Schematic file

1. Select “File > New > Block diagram/schematic file”. A new file with .bdf
extension will be opened. Save the file with same name as the project name.

Design Entry in the schematic file

When your are in blank spaces in Graphic Editor window, click the left mouse button
twice. The “../quartus60/libraries” will be open. Go to the “primitives/logic”
directory and enter the necessary gates and I/O pins. You may also enter the logic gates
from the left side icons of your schematic editor window.

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 Fig. 1 The Schematic window

3. Synthesis

After design entry we have to perform analysis and synthesis. Analysis and synthesis
builds a single project database that integrates all the design files in a design entity or
project hierarchy. As it create the database, the Analysis stage of Analysis & Synthesis
examine the logical completeness and consistency of the project, and check for
boundary connectivity and syntax error. It also synthesize and performs technology
mapping on the logic in the design entity or project’s file.

To do analysis and synthesis go to Processing from the toolbar and click start. Go to
the submenu and perform Start Analysis and Synthesis.

4. Fitter

Fitter assignments allow you to achieve an optimal fit for the design and achieve timing
closure. In order to achieve timing closure, you may need to adjust the default settings
of the Fitter. A common use of fitting assignments is to control the use of different
resources on the device. For example, you may want to control the location for RAM
blocks in order for the design to fit in the device.
To perform fitting go through the following steps

“Processing> Start > Start Fitter”

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5. Assembler

The Assembler is the Compiler module that completes project processing by generating
a device programming image. For the FPGAs, this programming image is in the form
of one or more Programmer Object Files (.pof), SRAM Object Files (.sof),
Hexadecimal (Intel-Format) Output Files (.hexout), Tabular Text Files (.ttf), and Raw
Binary Files (.rbf), from a successful fit (that is, place and route).

To perform the assembly task go through the following steps

“Processing> Start > Start Assembler”

5. Timing Analysis

The Quartus II timing analyzers provide a method of analyzing, debugging, and

validating the performance of a design. Timing analysis measures the delay along the
various timing paths and verifies the performance and operation of the design. You can
specify constraints and assignments that help the design meet timing requirements. If
you specify constraints or assignments, the Fitter optimizes the placement of logic in
the device in order to meet those constraints.

To perform the assembly task go through the following steps

“Processing> Start > Start Timing Analyzer”

6. Simulation

i) Simulation
You can perform Functional and timing simulation of your design by using the Quartus
II simulator.

To perform the simulation task go through the following steps

“Processing> Start Simulation”

ii) Viewing result

The Waveform Editor is a tool for entering simulation vectors and viewing simulation
results in a graphical waveform format. You can use the Waveform Editor to create
Vector Waveform Files (.vwf) or Compressed Vector Waveform File (.cvwf) that
contain input vectors for simulation.

To view the simulation data in the waveform file, open a waveform file. Go through the
following steps –

File àNew àOther FileàVector Waveform File

Save the waveform file in the same name as the top level design name. To insert the
input and output signals on the waveform editor go through the following steps-

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 1. Right click on the left column of waveform editor window.
2. Choose Insert Node or BUS
3. Click Node Finder
4. Choose Pins-all and click Select >>. All the input output signals will be loaded
on the Waveform file.

Now perform “Processing> Start Simulation” and the updated waveform will be
displayed in the simulation waveform.

Fig. Viewing the simulation result in the waveform editor

7. Floorplan and Design Compilation

Floorplan is the arrangement of circuit into CPLD chip, which includes chip
assignment, the assignment of input and output pins, and the assignment of Logic Array
Block (LAB) of the circuits etc. All Floorplans are managed by Floorplan Editor which
can be done by “Assignment > Timing Closure Floorplan”. Identify your signal pins
from “View Package Top”.

If you are not really satisfied with your pin arrangement or even would like to make
any change, you could re-plan the pin assignment by “Assignments>Assign Pins”
Make sure that the input Signal of your circuit i.e. signal X1, X2 and S are connected
to any three of the four pulse switches PS1( pin 54), PS2( pin 56), PS3( pin 124) and
PS4( pin 126). Also note down to which pin your output is connected.

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5. Device Programming and Circuit Testing

For ALTERA device programming, it requires users check what type of the
reconfigurable element is used in the selected device. The type of the reconfigurable
element could be EPROM, EEPROM, FLASH or SRAM. Different types will use
different programming approaches. Since we already used EPF10K10TC144-3 device
we will use it as our programming example. EPF10K10TC144-3 CPLD is an ALTERA
SRAM device. All the configuration data has to be installed into the circuit completely
after the system power is on. In another words, FLEX10K family offers users a great
flexibility to reconfigure different circuits with different re-configuration data.

Download circuit to the CPLD via printer parallel port:

We will use ByteBlaster connection bus to download the configuration data to the
target CPLD chip EPF10K10TC144. ByteBlaster connection bus can connect between
PC printer parallel ports and ByteBlaster plugs on the CPLD-EPF10K10 device board.
It also require Quartus II Programmer on PC to send “configuration data”. We will
follow the following procedure

1. Use connection bus to connect between PC printer parallel port and LP-
2900 experimental platforms.
2. After power on the experimental platform , LED D1 at the upper-left
corner is lightened up, and then press RESET button.
3. In Qurartus II, start programmer window by selecting “Tools >
Programmer”.
4. Open a chain description file (.cdf) which stores device name, device
order, and optional programming file name information for a design. You
can use CDFs to program or configure a device with one or more SRAM
Object Files (.sof), Programmer Object Files (.pof),
5. Add the file “mux.sof” in your cdf file.
6. Set “Hardware setup” to “ByteBlaserMV” set port to LPT1. Also set
mode to “JTAG” and give a tick to “Program/Configure”.
7. Press start in the programmer window. The circuit will be downloaded to
the CPLD chip.
8. Test the functionality of your circuit by giving different input through the
pulse switch and observing the output.

EXPERIMENT 2

Create a symbol of your 2 Way multiplexer. From the above design unit design a 4 way
multiplexer. Simulate the design to verify its functionality and implement it in a
FLEX10K Complex Programmable Logic Device (CPLD) chip. Compare the truth
table obtained in the simulation with that of the implemented chip.

EXPERIMENT 3

Suppose that there are 4 doors in a large room. There is a light in the middle of the
room. Design a digital logic circuit such that any person entering through any one of
the door will be able to ON or OFF the light.

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REPORT

Your report should also cover the following in addition to all the standard items.
• The schematic diagram of your circuit from Quartus II graphic editor.
• The waveform diagram from the Waveform editor of Quartus II
• The truth table obtained from the Waveform editor and the truth table obtained
from the prototype circuit built on the FLEX 10K chip.
• Discussions
• The answer of all the questions.

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