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2, FEBRUARY 2017
I. I NTRODUCTION
power is current reuse technique, like paper [6] and [7] do.
Paper [7] employed only one cross coupling to increase gm of
input MOSFETs, then the new design employed two cross
coupling at input (which increase gm of single M1 by a
factor 4) to save more power. A similar idea was employed
by Ref. [1], but the drawback is a very large inductor: 33nH,
making the chip area larger than the new design. Paper [2]
employed active cross coupling, so it got high voltage gain but
cost more power. Another idea is Positive–Negative Feedback,
employed by [6]: however it cannot isolate the inputs and the
outputs like the proposed design does. And when the size of
MOSFETs is the same, the new circuit has higher voltage gain Fig. 3. Equivalent circuit of the positive feedback stage.
than paper [6]. Moreover, the MOSFETs of second stage of
the proposed design work near subthreshold region compared
with [6] (saturation region), so the new circuit costs less power.
The last idea is active shunt feedback, which was employed
by [8], but it got lower voltage gain and cost higher power
compared with the proposed design.
In order to make the chip size small enough, inductorless
topology has been employed, by using active bias at the
sources of the input MOSFETs with two NMOSFETs. The
output loads are resistive load with MOSFETs cross cou-
pling to enhance the voltage gain to average 17 dB between
400 MHz and 1 GHz.
When MOSFETs work in the subthreshold region (gm11
and gm13 have same sign), the circuit has worse linearity
than saturation region does. However, current reuse can be Fig. 4. kf of the LNA.
employed to improve it, but limited. So this time triple cross-
coupling is employed. The first feedback loop is widely
known as the cross-coupled common gate (CCCG) topology.
By using capacitive cross coupling increases the gate-source
voltage of M1 , then the drain current and gm1 too. Besides,
the feedback loop can increase the first order signal by a
factor 2 (2gm1 ), and it also reduces the amplification of the
second order of signal, so they can reduce the second-order
harmonic feedback effect on the IIP3, then it improves IIP3 .
The second one is voltage-current feedback by another cross- Fig. 5. Microphotograph of the LNANKI.
coupling between output and input ports, by using capacitors
too which can also improve the gm1 and IIP3 [1]. The third be expressed as [9]–[10]
cross-coupling in the second stage is used to improve the
linearity and also the quality, gain, and isolate the input and VX Vgs2R − Vgs2L
ZX = = (1 + gm2 Z 1 )
output, so ports matching can be adjusted, respectively. IX gm2 Vgs2L
Another drawback of MOSFETs in the subthreshold region 2 1
is poor noise performance (NF will increase sharply). By using = (1 + gm2 Z 1 ) − = −2 + Z1
gm2 gm2
double cross-coupling, the gm is increased by a factor of 4 = RX + j X X (2)
(compare with single M1 without boosting), and noise factor
can be reduced to [6]–[8] R X is a negative impedance. Assuming the equivalent
impedance of load is R L , in order to prevent the circuit from
1 1 1
F −1 = = → F = 1+ (1) oscillating, R L must be smaller than (- R X ).
αgm1 R S α=4 4gm1 R S 4gm1 R S
As simulation results show: input matching is from 50
The last point is positive feedback. The third cross-coupling to 200 , output matching is from 80 to 150 , so k f
in the second stage is a positive feedback, which is used to (stability factor, the definition is given as below) is simply
enhance the voltage gain, improve the linearity and isolation. chosen to check the stability of the circuit [9]–[10]. When
But it may also cause the circuit to become unstable, so the k f > 1, it shows the circuit is unconditional stable. Fig. 4
stability must be investigated. The equivalent circuit of the shows the results of k f .
positive feedback stage is shown in Fig. 3.
Under balance condition, the analysis circuit is shown 1 + |S11 |2 − |S22 |2 + |S11 S22 − S12 S21 |2
kf ≈ (3)
in Fig. 3, the equivalent impedance from the drain of M2 can 2 |S12 S21 |
176 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 27, NO. 2, FEBRUARY 2017
TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON WITH P REVIOUS W ORKS
IV. C ONCLUSION
Fig. 6. S11 and S22 of simulated and measured. In this letter, an ultra-low power low noise amplifier (LNA)
employing subthreshold region and triple cross-coupling tech-
niques is proposed for WPAN applications. The trade-offs
among Power, NF and IIP3 of the circuit have been discussed
above. In order to save power, MOSFETs are made to work
in the subthreshold region, but they have poor NF and IIP3 ,
so triple-feedback has been employed to improve them. The
measured results show a very good S11 and S22 during
400 MHz∼1 GHz. And it also reaches an average 4.2 dB
NF and average gain of 17 dB between 400 MHz and 1 GHz,
whiling consuming only 0.2 mW (without buffer, buffer costs
6 mW power) from 1 V supply. As inductorless topology is
employed, the size of the chip area is only 0.27 mm2 . So it
makes the device more portable than usual devices for WPAN
Fig. 7. NF and S21 simulated and measured. applications. As comparisons show below, the FOM can be
expressed as [2]
BW (GHz) · GV (lin) · IIP3 (mW )
FOM = 20 log10 (4)
PDC (mW ) · (F − 1) · A(mm2 )
R EFERENCES
[1] H. G. Han, D. H. Jung, and T. W. Kim, “A 2.88 mW +9.06 dBm IIP3
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[3] W. Zhuo et al., “A capacitor cross-coupled common-gate low-noise
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0.18μm CMOS technology. And the microphotograph is IEEE Design Test Symp., vol. 6. Jun. 2013, pp. 1–6.
[6] S. Woo, W. Kim, C.-H. Lee, H. Kim, and J. Laskar, “A wideband low-
shown in Fig. 5, which occupies 580μm × 470μm, exclud- power CMOS LNA with positive–negative feedback for noise, gain, and
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[7] J. Liu, H. Liao, and R. Huang, “0.5 V ultra-low power wideband
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the bandwidth. Noise figure and S21 are shown in Fig. 7. [8] M. Parvizi, K. Allidina, and M. N. El Gamal, “An ultra-low-power
wideband inductorless CMOS LNA with tunable active shunt-feedback,”
The NF (4.2 dB) also can be accepted when considering the IEEE Trans. Microw. Theory Techn., vol. 64, no. 6, pp. 1843–1853,
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LNA and differential colpitts VCO/ QVCO in 0.18-μm CMOS,” IEEE
about −10 dBm for buffer). Table 1 shows a summary of J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
the measured results and comparison with previous works. [10] B. Razavi, RF Microelectronics, 2nd ed. Beijing, China: Publishing
(Sim & Meas: simulated and measured result.) House Electronics Industry, 2012.