EC2354/VLSI DESIGN

UNIT 1 – CMOS TECHNOLOGY

1. What are the different operating regions for a MOS transistor?
(or) Brief the different operating regions for a MOS system.

Cutoff region or sub threshold region.

Non-saturated region or linear region.
Saturation region.

2. What are the modes of MOS transistor? (or) different operating

modes for a MOS System.
Accumulation mode
Depletion mode.
Inversion mode

3. What is cut off region?

The region where the current flow is essentially zero,
Vgs < Vt ; Ids=0.

4. Determine whether an NMOS transistor with a threshold voltage

of 0.7V is operating in saturation region if Vgs=2V and Vds=3V.

NMOS transistor will operate in saturation region if Vds>Vgs – Vt.

Since 3>2-1.7, the transistor is operating in the saturation region.

5. Define threshold voltage (Vt) in MOS?

It defined as the voltage Vt is applied between the gate and the
source of the MOS transistor below which the drain to source
current (Ids) effectively drops to zero.

6. What is Body effect (or) Define Body effect coefficient (or) What
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is substrate-bias effect?
The threshold voltage Vt is not a constant with respect to the
voltage difference between the substrate and the source of MOS
transistor. This effect is called substrate-bias effect or body effect.

7. What is channel-length modulation?

The current between drain and source terminals is constant and
independent of the applied voltage over the terminals. This is not
entirely correct. The effective length of the conductive channel is
actually modulated by the applied Vds, increasing Vds causes the
depletion region at the drain junction to grow, reducing the
length of the effective channel.

8. Why the tunneling current is higher for NMOS transistor than

PMOS transistors with silica gate?

Tunneling current is an order of magnitude higher for NMOS than

PMOS transistors with SIO2 gate dielectrics because the electron
tunnel from the conduction band while the holes tunnel from the
valance band.
9. What are the advantages of CMOS process?
Low input impedance
Low delay sensitivity to load
Low power dissipation
10. What is stick diagram?
It is used to convey information through the use of color code.
Also it is the cartoon of a chip layout.
11. What are the uses of stick diagram?
it can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large
cells.

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12. Give the various color coding used in stick diagram?
Green – n-diffusion
Red – poly silicon
Blue – metal
Yellow-implant
Black-contact areas.

13. What are the objectives of layout design rule?

The main objective of design rules is to build reliably functional
circuit in smallest area. The design rule is also termed as
compromise between performance and yield.

14. What are the advantages of silicon on insulator process?

No latch-up
Due to absence of bulks transistor structure are denser than
bulk silicon.

15. List the various issues in technology CAD.

Design rule check (DRC).
Circuit extraction.

UNIT- 2/CIRCUIT CHARACTERIZATION AND SIMULATION

1. Define rise time.

Rise time is the time taken for a waveform to rise from 10% t0
90% of its steady-state value.
2. Define delay time.

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 Delay time is the time difference between input transition (50%)
and the 50% output level. This is the time taken for a logic
transition to pass from input to output.
3. Define fall time.
Fall time is the time taken for a waveform to fall from 90% - 10%
of its steady state value.
4. Define slope rate.
The time taken for a waveform raise between 20% - 80% its
steady state value.
5. What is aspect ratio?
The thickness to width ration is known as aspect ration.
6. Define logical effect.
It defined as the ratio of the input capacitance of the gate to the
input capacitance of an inverter.
7. Define interconnect.
The wire which connects transistor is known as interconnect.
8. Why does the interconnect increase the circuit delay?
 The wire capacitance adds loading to each gate.
 The wire resistance adds to distribute RC delay.
9. What are the sources of design margin?
 Supply voltage
 Operating temperature.
 Process variation.
10. What is the influence of voltage scaling on power and
delay?
 Due to voltage scaling the power dissipation will be reduced
with the speed.

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  Delay will be increased.
11. What is PSPICE?
PSPICE stands for simulation program with integrated circuit
emphasis. It is used to analyze the various circuits.

UNIT-3/COMBINATIONAL AND SEQUENTIAL CIRCUIT

DESIGN
1. What are the advantages of dynamic circuit family?

 It has low input capacitance.

 No contention during switching.
 It has zero static power dissipation.

2. What are the two operating modes of dynamic circuit?

 Percentage mode
 Evaluate mode

3. What is pass transistor?

A single MOSFET which passes the signal between the drain

and source terminals instead of a fixed power supply value.

4. What are the advantages of differential flip-flop?

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  It can rapidly respond to small differential input voltage.
 It works low switching inputs and buses.

5. State the reasons for speed advantages of CVSL family.

All of the logic is performed with MOSFET transistor, thus
reducing the input capacitance.

6. What are the sequence methods?

 Flip flop system.

 Two phased latches system
 Pulsed latch system.

7. What is meant by time borrowing?

Certain path take longer time if other path less time. This
technique is called time borrowing.

UNIT-4/CMOS TESTING
1. Mention the levels at which testing of a chip can be done?

 At the wafer level

 At the packaged chip level
 At the board level
 At the system level
 In the field

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2. What are the categories of testing? Or need for testing?

 Functionality tests
 Manufacturing tests

3. Write notes on manufacturing tests?

Manufacturing tests verify that every gate and register in the chip
functions correctly. These tests are used after the chip is
manufacturing to verify that the put silicon is instact.

4. What is meant by fault models?

Fault model is a model for how faults occur and their impact on
circuits.

5. What is meant by controllability?

It is an internal circuit node with in the chip is measure of each of
setting node 1 to 0.

6. Mentions to increase the speed of fault simulation.

 Parallel simulation
 Serial simulation

7. Explain system level test technique?

 Boundary scan

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  Test access port
 Test architecture
 TAP Control
 Instruction register
 Boundary scan register

UNIT 5 –SPECIFICATION USING VERILOG HDL

1. What is HDL? And classify it’s types.(or) short notes on HDL.
Hardware Description Language is language which describes
the hardware of digital system.
Types:
1.VHDL (Very high speed integrated circuit hardware
description language)
2. Verilog Hardware Description Language.

2. List the operator in Verilog HDL.

Arithmetic operator
Logical operator
Bitwise operator
Conditional operator
Relational operator
Shift operator
Reduction operator

3. What are the data types in Verilog HDL?

NET TYPE: it represents physical connection between structural
elements.
REGISTER TYPE: it represents data storage elements.

4. What is gate delay?

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The signal propagation delay from the gate input to the output is
specified by using delay.

5. What are resistive primitives?

rnmos,rpmos,rcmos.

6. What is subprogram overloading?

If two or more subprograms had the same name, then, both
functions are overloaded. This is called subprogram overloading.

7. What are the various modeling used in voltage?

Gate level modeling
Data flow modeling
Switch level modeling
Behavioral modeling.

8. What are the types of gate delay?

Rise delay
Fall delay
Turn off delay.

9. Write short note on port?

Port can be declared as input and output & inout.
e.g:
module name (c,a,b,s);
input a,b;
output c,s;

10. Write short notes on transport delay?

It is a delay the change in the output by the specified in the after

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clause. The transport delay of the inter delay model by adding the
keyword transport to the signal assignment statement.

11. Give an example of implicit continuous assignment?

Verilog HDL provides a shortcut by which a continuous assignment
can be placed on a net when it is declared.
Ex: wire out=in 1 and in 2;

…..::::: All the best ::::::….

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