1.

ADDSUB_seg ADD8
ADD4 module ADD8(A,B,Cin,S,Cout);
module ADD4(A,B,Cin,S,Cout); input[7:0]A,B;
input [3:0]A,B; input Cin;
input Cin; output[7:0]S;
output [3:0]S; output Cout;
output Cout; wire co;
wire C0,C1,C2; CADD4 U0(A[3:0],B[3:0],Cin,S[3:0],co);
wire[3:0] p,g; CADD4 U1(A[7:4],B[7:4],co,S[7:4],Cout);
//Cout problem
assign p[0] = A[0]|B[0];
assign p[1] = A[1]|B[1]; endmodule
assign p[2] = A[2]|B[2];
assign p[3] = A[3]|B[3]; ADDSUB8
module ADDSUB8(A,B,op,S,Cout);
assign g[0] = A[0]&B[0]; input[7:0]A,B;
assign g[1] = A[1]&B[1]; input op;
assign g[2] = A[2]&B[2]; output[7:0]S;
assign g[3] = A[3]&B[3]; output Cout;
assign C0 = g[0]|(Cin&p[0]); wire[7:0]_B;
assign C1 = ADD8 U0(A,_B,op,S,Cout);
g[1]|(p[1]&g[0])|(Cin&p[1]&p[0]); assign _B = (op)?~B:B; //MUX2to1_8
assign C2 = endmodule
g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|
(Cin&p[2]&p[1]&p[0]);
assign Cout =
g[3]|(g[2]&p[3])|(g[1]&p[3]&p[2])|
(g[0]&p[3]&p[2]&p[1])|(Cin&p[3]&
p[2]&p[1]&p[0]);

assign S[0] = A[0]^B[0]^Cin;

assign S[1] = A[1]^B[1]^C0;
assign S[2] = A[2]^B[2]^C1;
assign S[3] = A[3]^B[3]^C2;

endmodule
7_seg 2. MUX
module _7seg(A,F); MUX2to1
input[3:0]A; module MUX2to1(A,sel,f);
output[7:0]F; input[1:0]A;
reg[7:0]F; input sel;
always@(A) output f;
case(A) assign f=(sel)?A[1]:A[0];
4'd0:F=8'b01000000; endmodule
4'd1:F=8'b01111001;
4'd2:F=8'b00100100; MUX4to1
4'd3:F=8'b00110000; module MUX4to1(A,sel,f);
4'd4:F=8'b00011001; input[3:0]A;
4'd5:F=8'b00010010; input[1:0]sel;
4'd6:F=8'b00000010; output f;
4'd7:F=8'b01011000; assign f = (sel[1])?((sel[0])? A[3]:A[2]) :
4'd8:F=8'b00000000; (sel[0]? A[1]:A[0]);
4'd9:F=8'b00010000; endmodule
4'd10:F=8'b00001000; //a
4'd11:F=8'b00000011; //b MUX8to1
4'd12:F=8'b01000110; //c module MUX8to1(A,sel,f);
4'd13:F=8'b00100001; //d input[7:0]A;
4'd14:F=8'b00000110; input[2:0]sel;
4'd15:F=8'b00001110; output f;
default:F = 8'b10000000; wire f0,f1;
endcase MUX4to1 U0(A[3:0],sel[1:0],f0);
endmodule MUX4to1 U1(A[7:4],sel[1:0],f1);
ADDSUB_7seg MUX2to1 U2({f1,f0},sel[2],f);
module endmodule
ADDSUB_7seg(A,B,op,F1,F2,Cout);
input[7:0]A,B;
input op;
output[7:0]F1,F2;
output Cout;
wire[7:0]S;
ADDSUB8 U0(A,B,op,S,Cout);
_7seg U1(S[3:0],F1);
_7seg U2(S[7:4],F2);
endmodule
3. MF_Reg8
module
MF_Reg8(Din,load,clk,SROp,RL,Dout);
input [7:0]Din;
input clk;
input load,SROp,RL;
output [7:0]Dout;
wire [7:0]Dsr,Dsl,Drr,Drl;
wire [7:0]D,D0,Ds,Dr;
//reg D;
reg [7:0]Dout;
assign Dsr={1'b0,Dout[7:1]};
assign Dsl={Dout[6:0],1'b0};
assign Drr={Dout[0],Dout[7:1]};
assign Drl={Dout[6:0],Dout[7]};

always @(posedge clk)

Dout <= D;
assign D=load?Din:D0;
assign D0=SROp?Ds:Dr;
assign Ds=RL?Dsr:Dsl;
assign Dr=RL?Drr:Drl;

endmodule