QM_XC6SLX16_SDRAM CORE BOARD

USER MANUAL

Preface

The QMTech® XC6SLX16 SDRAM core board uses Xilinx’s Spartan®-6 XC6SLX16-2FTG256C device to
demonstrate industry leading connectivity features such as high logic-to-pin ratios, small form-factor
packaging, MicroBlaze™ soft processor, 800Mb/s DDR3 support, and a diverse number of supported I/O
protocols. Built on 45nm technology, the devices are ideally suited for advanced bridging applications found
in automotive infotainment, consumer, and industrial automation.

QM_XC6SLX16_SDRAM Core Board User Manual V01

 Table of Contents

1. INTRODUCTION ............................................................................... 3
1.1 DOCUMENT SCOPE ....................................................................... 3
1.2 KIT OVERVIEW ............................................................................. 3
2. GETTING STARTED ........................................................................... 4
2.1 INSTALL DEVELOPMENT TOOLS ........................................................ 5
2.2 QM_XC6SLX16_SDRAM HARDWARE DESIGN................................ 6
2.2.1 QM_XC6SLX16_SDRAM Power Supply......................... 6
2.2.2 QM_XC6SLX16_SDRAM SPI Boot ................................. 7
2.2.3 QM_XC6SLX16_SDRAM Memory................................. 8
2.2.4 QM_XC6SLX16_SDRAM System Clock ......................... 8
2.2.5 QM_XC6SLX16 Extension IO ........................................ 9
2.2.1 QM_XC6SLX16_SDRAM 3.3V Power Supply .............. 10
2.2.2 QM_XC6SLX16_SDRAM JTAG Port............................. 10
2.2.3 QM_XC6SLX16_SDRAM User LED .............................. 10
2.2.4 QM_XC6SLX16_SDRAM User Key .............................. 11
3. REFERENCE .................................................................................... 12
4. REVISION ....................................................................................... 13

QM_XC6SLX16_SDRAM Core Board User Manual V01

1. Introduction

1.1 Document Scope

This demo user manual introduces the QM_XC6SLX16_SDRAM core board and describes how to setup
the core board running with application software Xilinx ISE 14.7. Users may employee the on board rich
logic resource FPGA XC6SLX16-2FTG256C and large SDRAM memory MT48LC16M16 to implement
various applications. The core board also has 108 non-multiplexed FPGA IOs for extending customized
modules, such as UART module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.

1.2 Kit Overview

Below section lists the parameters of the QM_XC6SLX16_SDRAM core board:
 On-Board FPGA: XC6SLX16-2FTG256C;
 On-Board FPGA external crystal frequency: 50MHz;
 XC6SLX16-2FTG256C has rich block RAM resource up to 576Kb;
 XC6SLX16-2FTG256C has 14,579 logic cells;
 On-Board M25P80 SPI Flash，1M bytes for user configuration code;
 On-Board 32MB Micron SDRAM，MT48LC16M16A2-75;
 On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC;
 XC6SLX16 development board has two 64p, 2.54mm pitch headers for extending user IOs. All IOs
are precisely designed with length matching;
 XC6SLX16 development board has 3 user switches;
 XC6SLX16 development board has 4 user LEDs;
 XC6SLX16 development board has JTAG interface, by using 6p, 2.54mm pitch header;
 XC6SLX16 development board PCB size is: 6.7cm x 8.4cm;
 Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;

Figure 1-1. QM_XC6SLX16_SDRAM Core Board Overview

QM_XC6SLX16_SDRAM Core Board User Manual V01

2. Getting Started
The QM_XC6SLX16_SDRAM core board includes below item:

Figure 2-1. QM_XC6SLX16_SDRAM Top View

Below image shows the dimension of the QM_XC6SLX16_SDRAM core board: 6.7cm x 8.4cm. The unit
in below is millimeter(mm).

Figure 2-2. QM_XC6SLX16_SDRAM Core Board Dimension

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.1 Install Development Tools
The QM_XC6SLX16_SDRAM core board tool chain consists of Xilinx ISE 14.7, Xilinx USB platform cable,
XC6SLX16 core board and 5V DC power supply. Below image shows the Xilinx ISE14.7 development
environment which could be downloaded from Xilinx office website:

Figure 2-3. ISE 14.7

Below image shows the JTAG connection between Xilinx USB platform cable and XC6SLX16 core board:

TMS (Green)
TDI (Purple)
TDO (White)
TCK (Yellow)
GND (Black)
VREF (Red)

5V DC

Figure 2-4. JTAG Connection and Power Supply

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2 QM_XC6SLX16_SDRAM Hardware Design

2.2.1 QM_XC6SLX16_SDRAM Power Supply

The core board needs 5V DC input as power supply which could be directly injected from power header or the 64P
female header U7/U8. Users may refer to the hardware schematic for the detailed design. The on board LED D4
indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default status, all the FPGA banks
IO power level is 3.3V because bank power supply is 3.3V. However, BANK1 IO’s power level could be changed
according to detailed custom requirement. There’re three 0 ohm resisters could be removed:R223/R224/R225, and
instead the BANK1’s power supply could be injected from 64P female header U7. Detailed design refer to hardware
schematic.
Note: FPGA core supply 1.2V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A
current.
U2F
A1
GND_0 A16
GND_1 B11
GND_2 B7
GND_3 D13
GND_4 D4
GND_5 E9
GND_6 G15
GND_7 G2
GND_8 G8
GND_9 H12
GND_10 H7
GND_11 H9
GND_12 J5
GND_13 J8
GND_14 K7 3V3
GND_15 K9
GND_16 L15
GND_17 L2
GND_18 M8 C53
GND_19 N13
GND_20 P3 4.7uF
GND_21 R10 10V
GND_22 R6 C28 C29
GND_23 C19
T1 100NF 100NF 100NF
GND_24 T16 C20 C22
GND_25 E5 100NF 100NF
VCCAUX_0 F11 VCCO_1
VCCAUX_1 F8
VCCAUX_2 G10
VCCAUX_3 H6
VCCAUX_4 J10 C61
VCCAUX_5 L6
VCCAUX_6 L9 4.7uF
VCCAUX_7 G7 3V3
10V
VCCINT_0 G9 C63
VCCINT_1 H10 100NF
VCCINT_2 H8 C62
VCCINT_3 J7 1V2 100NF
VCCINT_4 J9
VCCINT_5 K10
VCCINT_6 K8
VCCINT_7 B13 1V2
C35
VCCO_0_0 B4
VCCO_0_1 B9 4.7uF
VCCO_0_2 D10 10V
VCCO_0_3 D7 C36
VCCO_0_4 D15 3V3
100NF
VCCO_1_0 G13 C37
VCCO_1_1 J15 100NF
VCCO_1_2 K13
VCCO_1_3 N15
VCCO_1_4 R13
VCCO_1_5 N10 VCCO_1
VCCO_2_0 N7
VCCO_2_1 R4
VCCO_2_2 R8
VCCO_2_3 D2
VCCO_3_0 G4
VCCO_3_1 J2
VCCO_3_2 K4
VCCO_3_3 N2
VCCO_3_4 3V3

Spartan-6_XC6SLX16_FTG256

Figure 2-5. Power Supply for the FPGA

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2.2 QM_XC6SLX16_SDRAM SPI Boot
In default, QM_XC6SLX16 boots from external SPI Flash, detailed hardware design is shown in below figure.
The SPI flash is using M25P80 manufactured by Micron, with 8Mbit memory storage.
3V3

3V3
U6
4.7K R15FPGA_CSO_B 1 8 C44 100NF R16
3V3 nCE VDD 1K
FPGA_MISO R17 0R 2 7 R18 4.7K
SO HOLD 3V3
4.7K R20 3 6 FPGA_CCLK
3V3 WP SCK
4 5 FPGA_MOSI
VSS SI R24
M25P80 1K

Figure 2-6. SPI Flash

The FPGA boot sequence setting M0:M1 is configured as 1:0 which indicates FPGA will boot from SPI Flash
after power on.

U2E
C4 R11 4.7K
IO_L1P_HSWAPEN_0
C14 TCK
TCK C12 TDI
TDI A15 TMS
TMS E14 TDO
TDO
P14
SUSPEND
L11
CMPCS_B_2
P13 FPGA_DONE
DONE_2
R11 FPGA_CCLK
IO_L1P_CCLK_2 P10 FPGA_MISO
IO_L3P_D0_DIN_MISO_MISO1_2 T10 FPGA_MOSI
IO_L3N_MOSI_CSI_B_MISO0_2 T3 FPGA_CSO_B
IO_L65N_CSO_B_2
R3 R19 4.7K
IO_L65P_INIT_B_2 3V3
T2 PROG_BR22 4.7K
PROGRAM_B_2 T11 3V3
R23 4.7K 3V3
IO_L1N_M0_CMPMISO_2 N11
IO_L13P_M1_2

Spartan-6_XC6SLX16_FTG256

Figure 2-7. M0:M1 Hardware Settings

The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during
power on stage. In this case, LED D2 could be used as FPGA loading status indicator.
3V3

R13
1K

FPGA_DONE
1

D2

Red
2

R25
1K

Figure 2-8. FPGA_DONE Status Indicator

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2.3 QM_XC6SLX16_SDRAM Memory
QM_XC6SLX16 has on board 16bit width data bus, 32MB memory size SDRAM MT48LC16M16 provided by
Micron. Below image shows the detailed hardware design:
MN1
A0 23 2 D0
A1 24 A0 MT48LC16M16A2
DQ0 4 D1
A2 25 A1 DQ1 5 D2
A3 26 A2 DQ2 7 D3
A4 29 A3 DQ3 8 D4
A5 30 A4 DQ4 10 D5
A6 31 A5 DQ5 11 D6
A7 32 A6 DQ6 13 D7
A8 33 A7 DQ7 42 D8
A9 34 A8 DQ8 44 D9
A10 22 A9 DQ9 45 D10
A11 35 A10 DQ10 47 D11
A11 DQ11 48 D12
A13 20 DQ12 50 D13
A14 21 BA0 DQ13 51 D14
BA1 DQ14 53 D15
A12 36 DQ15
40 A12 1 3V3
N.C VDD 14
SDCKE0 37 VDD 27
CKE VDD 3
SDCLK0 38 VDDQ 9
CLK VDDQ 43
DQML 15 VDDQ 49
DQMH 39 DQML VDDQ
DQMH 28
CAS 17 VSS 41
RAS 18 CAS VSS 54
RAS VSS 6 C3 C5 C7 C9
VSSQ 12 100NF 100NF 100NF 100NF
SDWE 16 VSSQ 46 C4 C6 C8
SD_NCS0 19 WE VSSQ 52 100NF 100NF 100NF
CS VSSQ
256 M bit s

Figure 2-9. SDRAM

2.2.4 QM_XC6SLX16_SDRAM System Clock

FPGA chip XC6SLX16-2FTG256C has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/°c. Below
image shows the detailed hardware design:

3V3
R9 4.7K

1 OE VDD 4
50 MHz
C42
100NF
2 VSS OUT 3 SY S_CLK

Y1

SG-8002JC-50.0000M-PCB

Figure 2-10. 50MHz System Clock

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2.5 QM_XC6SLX16 Extension IO
The core board has two 64P 2.54mm pitch female headers which are used for extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.

U7
1 2
VCCO_1 3 4 VCCO_1
5 6
BANK1 Voltage BANK1_E12
7 8
BANK1_E13
BANK1_B15 BANK1_B16
Supply Pins. BANK1_C15 9 10 BANK1_C16
BANK1_D14 11 12 BANK1_D16
BANK1_E15 13 14 BANK1_E16
BANK1_F15 15 16 BANK1_F16
BANK1_G11 17 18 BANK1_F12
BANK1_F14 19 20 BANK1_F13
BANK1_G16 21 22 BANK1_G14
BANK1_H15 23 24 BANK1_H16
BANK1_G12 25 26 BANK1_H11
BANK1_H13 27 28 BANK1_H14
BANK1_J14 29 30 BANK1_J16
BANK1_J11 31 32 BANK1_J12
BANK1_K14 33 34 BANK1_J13
BANK1_K15 35 36 BANK1_K16
BANK1_L16 37 38 BANK1_L14
BANK1_K11 39 40 BANK1_K12
BANK1_M15 41 42 BANK1_M16
BANK1_N14 43 44 BANK1_N16
BANK1_M13 45 46 BANK1_M14
BANK1_L12 47 48 BANK1_L13
BANK1_P15 49 50 BANK1_P16
BANK1_R15 51 52 BANK1_R16
BANK1_R14 53 54 BANK1_T15
BANK1_T13 55 56 BANK1_T14
BANK1_T12 57 58 BANK1_R12
59 60
61 62
5V_IN 63 64 5V_IN
Connected to 5V_IN HDR_32X2
power header.

U8
1 2
3V3 3 4 3V3
BANK0_IO_A14 5 6 BANK0_IO_B14
BANK0_IO_C13 7 8 BANK0_IO_A13
BANK0_IO_B12 9 10 BANK0_IO_A12
BANK0_IO_C11 11 12 BANK0_IO_A11
BANK0_IO_B10 13 14 BANK0_IO_A9
BANK0_IO_C9 15 16 BANK0_IO_A8
BANK0_IO_B8 17 18 BANK0_IO_A7
BANK0_IO_C7 19 20 BANK0_IO_A6
BANK0_IO_B6 21 22 BANK0_IO_A5
BANK0_IO_B5 23 24 BANK0_IO_A4
BANK0_IO_E10 25 26 BANK0_IO_C10
BANK0_IO_E11 27 28 BANK0_IO_F10
BANK0_IO_F9 29 30 BANK0_IO_D9
BANK0_IO_C8 31 32 BANK0_IO_D8
BANK0_IO_E7 33 34 BANK0_IO_E6
BANK0_IO_F7 35 36 BANK0_IO_C6
BANK0_IO_D6 37 38 BANK2_IO_M6
BANK2_IO_P4 39 40 BANK2_IO_N5
BANK2_IO_P5 41 42 BANK2_IO_N6
BANK2_IO_M7 43 44 BANK2_IO_P6
BANK2_IO_N8 45 46 BANK2_IO_L7
BANK2_IO_P9 47 48 BANK2_IO_T4
BANK2_IO_T5 49 50 BANK2_IO_R5
BANK2_IO_T6 51 52 BANK2_IO_T7
BANK2_IO_N9 53 54 BANK2_IO_M9
BANK2_IO_M10 55 56 BANK2_IO_P11
BANK2_IO_P12 57 58 BANK2_IO_M11
59 60
61 62
5V_IN 63 64 5V_IN
HDR_32X2
Connected to 5V_IN
power header.
Figure 2-11. Extension IO

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2.1 QM_XC6SLX16_SDRAM 3.3V Power Supply
The core board’s 3.3V power supply is using high efficiency DC/DC chip MP2359 provided by MPS Inc. The
MP2359 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power supply is
suggested to be applied on the board. Below image shows the MP2359 hardware design:

3V3 VCCO_1
L6
C67 10nF R223 0R
R224 0R

2
3.3uH C69 R225 0R
D5
IN5819 4.7uF
U4
1 6
REG ULATED

1
C60 R128 BST SW 5V_IN
5V O NLY

DNP 100K
2 5
GND VIN 4
R126 3
3 4 100K 2
FB EN +

C58 1
MP2359 JP5
47uF C68 Power_Header_SMT
R129 R127 100nF
33K DNP

Figure 2-12. MP2359 Hardware Design

2.2.2 QM_XC6SLX16_SDRAM JTAG Port

The on board JTAG port uses 6P 2.54mm pitch header which could be easily connected to Xilinx USB platform
cable. Below image shows the hardware design of the JTAG port:

3V3
J2
1
2 TCK
3 TDO
4 TDI
5 TMS
6
JTAG

Figure 2-13. JTAG Port

2.2.3 QM_XC6SLX16_SDRAM User LED

Below image shows two user LEDs and 3.3V power supply indicator:
3V3 3V3 3V3

R131 R218 R217

1K 1K 1K

1 2 BANK2_IO_T9
D1
1 2 BANK2_IO_R9
D3
1 2
D4

Figure 2-14. LEDs

QM_XC6SLX16_SDRAM Core Board User Manual V01

2.2.4 QM_XC6SLX16_SDRAM User Key
Below image shows the PROGRAM_B key and two user keys:

3V3 3V3

R221 R222
4.7K 4.7K

PROG_B BANK2_IO_T8 BANK2_IO_R7

2 2 2

SW1 SW2 SW3

1 1 1

Figure 2-15. Keys

QM_XC6SLX16_SDRAM Core Board User Manual V01

3. Reference
[1] ug380-Configuration.pdf
[2] ug385-Package.pdf
[3] ug394-Power Managment.pdf
[4] M25P80.pdf
[5] LPC-Link-II_Rev_C.pdf
[6] QM_XC6SLX16.pdf

QM_XC6SLX16_SDRAM Core Board User Manual V01

4. Revision
Doc. Rev. Date Comments
0.1 05/10/2017 Initial Version.
1.0 05/14/2017 V1.0 Formal Release.

QM_XC6SLX16_SDRAM Core Board User Manual V01