First Three and Last Three Experiments

c

To study the Simulation tools.

c

! "#$

In this section, you will create a test bench waveform containing input
stimulus you can use to simulate the counter module. This test bench waveform is
a graphical view of a test bench. It is used with a simulator to verify that the
counter design meets both behavioral and timing design requirements. You will
use the Waveform Editor to create a test bench
waveform (TBW) file.
1. Select the #HDL file in the Sources in Project window.
2. Create a new source by selecting %&_ ' #.
3. In the New Source window, select

()!"as the source type,
and type * in the File Name field.
4. Click .
5. The Source File dialog box shows that you are associating the test bench with
the source file: counter. Click .
6. Click . You need to set initial values for your test bench waveform in the
Initialize Timing dialog box before the test bench waveform editing window
opens.
7. Fill in the fields in the Initialize Timing dialog box using the information below:
? Clock Time High: ( ns.
? Clock Time Low: ( ns.
? Input Setup Time: ns.
? Output Valid Delay: ns.
? Initial Offset: ns
? Global Signals: · +%·,
Leave the remaining fields with their default values.
8. Click -to open the waveform editor. The blue shaded areas are associated
with each input signal and correspond to the Input Setup Time in the Initialize
Timing dialog box. In this tutorial, the input transitions occur at the edge of the
blue cells located under each rising edge of the CLOCK input.
(?()!"c./

0()!"c./c .#$
9. In this design, the only stimulus that you will provide is on the DIRECTION
port. Make the transitions as shown below for the DIRECTION port:
? Click on the blue cell at approximately the 300 ns clock transition. The
signal switches to high at this point.
signal switches back to low.
signal switches to high again.
10. Select $_ )to save the waveform. In the Sources in Project window, the
TBW file is automatically added to your project.
11. Close the Waveform Editor window.
..c .#$
()!"

In this step you will create a self-checking test bench with expected outputs
that correspond to your inputs. The input setup and output delay numbers that were
entered into the Initialize Timing dialog when you started the waveform editor are
evaluated against actual results when the design is simulated. This can be useful in
the Simulate Post- Place & Route HDL Model process, to verify that the design
behaves as expected in the target device both in terms of functionality and timing.
To create a self-checking test bench, you can edit output transitions manually, or
you can run the Generate Expected Results process:
1. Select the * *'file in the Sources in Project window.
2. Double-click the ·c . "#$#$process. This process

converts the TBW into HDL and then simulates it in a background process.
3. The c .#$dialog box will open. Select to post the results in the
waveform editor.
4. Click the ³1´ to expand the COUNT_OUT bus and view the transitions that
correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing
dialog box.
5. Select $_ )to save the waveform.
6. Close the Waveform Editor. Now that you have a test bench, you are ready to
simulate your design.

"#$ )$.$+ c "#$,
If you are using ISE Base or Foundation, you can simulate your design with
the ISE Simulator. If you wish to simulate your design with a ModelSim simulator,
skip this section and proceed to the ³Simulating the Behavioral Model
(ModelSim)´ section.
2 "#$%!

3 )$ "#$ c "#$

To run the integrated simulation processes in ISE:

1. Select the * waveform in the Sources in Project window. You can see
the Xilinx ISE Simulator processes in the Processes for Source window.
2. Double-click the "#$ )$.$process. The ISE Simulator

opens and runs the simulation to the end of the test bench.
3. To see your simulation results, select the * tab and zoom in on the
transitions. You can use the zoom icons in the waveform view, or right click and
select a zoom command.The ISE window, including the waveform view.
4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is
counting up and down as directed by the stimulus on the DIRECTION port.
5. Close the waveform view window. You have completed simulation of your
design using the ISE Simulator. Skip past the ModelSim section below and
proceed to the ³Creating and Editing Timing and Area
Constraints´ section.
"#$ )$.$+.$ ",

If you have a ModelSim simulator installed, you can simulate your design
using the integrated ModelSim flow. You can run processes from within ISE which
launches the installed ModelSim simulator.
To run the integrated simulation processes in ISE:
1.? Select the * in the Sources in Project window. You can see
ModelSim Simulator processes in the Processes for Source window in Fig
6.
4 "#$%!

5 )$ "#$.$ "
2. Double-click the "#$ )$.$process. The ModelSim simulator

opens and runs your simulation to the end of the test bench.
The ModelSim window, including the waveform, should look like Fig 7.
To see your simulation results, view the Wave window.
1. Right-click in the Wave window and select a zoom command.
3. Close the ModelSim window.

c

c (

c

To á ? ? áá?

á.

c
?
Now that you have created the source files, verified the design¶s behavior with
simulation, and added constraints, you are ready to synthesize and implement the
design.
"$"
1. Select the #source file in the Sources in Project window.
2. In the Processes for Source window, click the ³1´ sign next to
"$" . The Translate, Map, and Place & Route processes are
displayed. Expand those processes as well by clicking on the ³1´ sign. You can see
that there are many sub-processes and options that can be run during design
implementation.
3. Double-click the top level "$" process.ISE determines the

current state of your design and runs the processes needed to pull your design
through implementation. In this case, ISE runs the Translate, Map and PAR
processes. Your design is now pulled through to a placed-and-routed state. This
feature is called the ³pull through model.´
4. After the processes have finished running, notice the status markers in the
Processes for Source window. You should see green checkmarks next to several of
the processes, indicating that they ran successfully. If there are any yellow
exclamation points, check the warnings in the Console tab or the Warnings tab
within the Transcript window. If a red X appears next to a process, you must locate
and fix the error before you can continue.
6!! 7

Your synthesized design can be viewed as a schematic in the Register
Transfer Level (RTL) Viewer. The schematic view shows gates and elements
independent of the targeted Xilinx® device.
1.? In the Processes for Source window, double-click 6'
"
found in the Synthesize - XST process group. The top level schematic
representation of your synthesized design opens in the workspace
2. Right-click on the symbol and select %# $. to
view the schematic in detail. The Design tab appears in the Sources in Project
window, enabling you to view the design hierarchy. In the schematic, you can
see the design components you created in the HDL source, and you can ³push
into´ symbols to view increasing levels of detail.
3. Close the schematic window.

#p?
6'/$.6'

c

c8%0
-

%·

To study the Place and Root and Back annotation for FPGAs.

c
?
After implementation is complete, you can verify your design before downloading
it to a device.
6'%$"

In this section, you will use the Floor planner to verify your pin outs and
placement. Floor planner is also very useful for creating area groups for designs
1. Select the #source file in the Sources in Project window.
2. Click the ³1´ sign to expand the %$9#group of processes.
3. Double-click the 6':c.%$.+$$,process. The Floor

planner view opens.
4. Select 6'_ ;"_

and then use the mouse to draw a box around the
counter instance, shown in green on the right side of the chip.
5. This Fig 1 shows where the entire design was placed. Click on any of the
components listed in the Design Hierarchy window to see where each component
is placed.
6. Zoom in to the right side of the chip even more, and place your mouse over the
K13pad. You can see that your pinout constraint was applied - the DIRECTION
pin is placed at K13.
7. Close the Floor planner without saving.
6'#$<

Many ISE processes produce summary reports which enable you to check
information about your design after each process is run. Detailed reports are
available from the Processes for Source window. You can also view summary
information and access most often-utilized reports in the Design Summary.
1. Click on the #""7tab at the bottom of the window. If you closed
the summary during this tutorial, you can reopen it by double-clicking the 6'
#""7process.
Figure 3:?
"$7</
" #""7
Figure 4:?%·c./$.6'
2. In the Device Utilization Summary section, observe the number of Slice Flip
Flops that were used during implementation. You should see 4 flip flops, since you
implemented a 4-bit counter.
3. To see other reports, scroll to the bottom of the Design Summary. You can click
on a report from here to view it in the ISE Text Editor.

"$#

In this section, you will run timing analysis on your design to verify that
your timing constraints were met. Timing closure is the process of working on
your design to ensure that it meets your necessary timing requirements. ISE
provides several tools to assist with timing closure.
1. In the Processes for Source window, under the Place & Route group of
processes, expand the ·%/%$9#
"group by
clicking the ³1´sign.
2. Double-click the $7<%/%$9#

"process. The
Timing Analyzer opens.
3. To analyze the design, select $7<
" The
Analyze with Timing Constraints dialog box opens.
4. Click -. When analysis is complete, the timing report opens.
5. Select
"#""7from the Timing Report Description tree in the left
window. This displays the summary section of the timing report, where you can
see that no timing errors were reported.
6. Close the Timing Analyzer without saving.
6' %$..#.

In this section, you will use the FPGA Editor to view the design. You can
view your design on the FPGA device, as well as edit the placement and routing
with the FPGA Editor.
1. Double-click the 6':c.#.+%·c.,process found in

the Place & Route group of processes. Your implemented design opens in the
FPGA Editor.
2. Look in the window to examine your design components.
3. Click on the
=
-(IOB in the List window to select the row. This
is one of the outputs in your design.
4. With the COUNT_OUT K12 row selected, select 6'_ ;" $. In
the editor window, you can see the COUNT_OUT<0> IOB highlighted in red.
5. Push into (double-click) the red-highlighted
=
-(IOB. You
should see Fig 4.
6. Enlarge the window and zoom in so you can see more detail. This view shows
the inside of an FPGA at the lowest viewable level. The blue line shows the route
that is used through the IOB. The red lines show the routes that are available.
Figure 5:? "#$%!

Figure 6:?
" "#$ c "#$
7. Verify that the signal goes to the pad as an output.
8. Close the FPGA Editor.
" "#$+ c "#$,
You can verify that your design meets your timing requirements by running
a timing simulation. You can use the same test bench waveform that was used
earlier in the design flow for behavioral simulation. When running timing
simulation, the ISE tools create a structural HDL file which includes timing
information available after Place and Route is run. The simulator will run on a
model that is created based on the design to be downloaded to the FPGA. If you
are using ISE Base or Foundation, you can simulate your design with the ISE
Simulator. To simulate your design with ModelSim, skip to the ³Timing
Simulation (ModelSim)´ section.
To run the integrated simulation processes:
1. Select the * waveform in the Sources in Project window. You can see
the ISE Simulator processes in the Processes for Source window.
2. Double-click the "#$ %/%$ 9 # .$ process. This process

generates a timing-annotated net list from the implemented design and simulates it.
The resulting simulation is displayed in the Waveform Viewer. These results look
different than those you saw in the behavioral simulation earlier in this tutorial.
These results show timing delays.
3. To see your simulation results, zoom in on the transitions and view the area
between 300 ns and 900 ns to verify that the counter is counting up and down as
directed by the stimulus on the DIRECTION port.
4. Zoom in again to see the timing delay between a rising clock edge and an output
transition.
5. Click the #>button and then click near the 300 ns mark. Drag
the second marker to the point where the output becomes stable to see the time
delay between the clock edge and the transition.
6. Close the waveform view window. You have completed timing simulation of
your design using the ISE Simulator. Skip past the ModelSim section below, and
proceed to the ³Creating Configuration Data´ section.
?
" "#$+.$ ",
If you have a ModelSim simulator installed, you can simulate your design using
the integrated ModelSim flow. You can run processes from within ISE which
launches the installed ModelSim simulator.
1. To run the integrated simulation processes, select the * in the Sources
in Project window. You can see the ModelSim Simulator processes in the
Processes for Source window.

Figure 7:? "#$%!

Figure 8:
" "#$.$ "

2. Double-click the "#$%/%$9#6:6$.$process.
4. Zoom in on the rising clock edges to see that the output transitions occur slightly
later due to the timing delay.
5. Close the ModelSim window.

c

%c ·cc
c 0

To design and simulate the parallel signed adder using verilog HDL .
%%
c?c
? Xilinx ISE 10.1.

-·

%$..!$$$..

%·

ss PARALLEL SIGNED ADDER.
module adder12s ( clk,n0,n1,n2,n3,n4,n5,n6,n7,sum) ;

input clk ;
input [11:0] n0 ;
input [11:0] n1 ;
input [11:0] n2 ;
input [11:0] n3 ;
input [11:0] n4 ;
input [11:0] n5 ;
input [11:0] n6 ;
input [11:0] n7 ;
output [14:0] sum ;
wire [7:0] s00_lsb ;
wire [5:0] s00_msb ;
reg [11:7] n0_reg1 ;
reg [11:7] n1_reg1 ;
reg [11:7] n2_reg1 ;
reg [11:7] n3_reg1 ;
reg [11:7] n4_reg1 ;
reg [11:7] n5_reg1 ;
reg [11:7] n6_reg1 ;
reg [11:7] n7_reg1 ;
reg [7:0] s00_lsbreg1 ;
reg [5:0] s00_msbreg2 ;
reg s20_lsbreg5cy ;
ss First Stage Addition
assign s00_lsb[7:0] = n0[6:0]+n1[6:0] ;
ss Add lsb first - s00_lsb[7] is the carry
assign s01_lsb[7:0] = n2[6:0]+n3[6:0] ;
ss n0-n7 lsb need not be registered since addition is already carried out here.
assign s02_lsb[7:0] = n4[6:0]+n5[6:0] ;
assign s03_lsb[7:0] = n6[6:0]+n7[6:0] ;
always @ (posedge clk)
ss Pipeline 1: clk (1). Register msb to continue
ss addition of msb.
begin
n0_reg1[11:7] <= n0[11:7] ;
ss Preserve all inputs for msb addition during the clk(2).
n1_reg1[11:7] <= n1[11:7] ;
n2_reg1[11:7] <= n2[11:7] ;
n3_reg1[11:7] <= n3[11:7] ;
n4_reg1[11:7] <= n4[11:7] ;
n5_reg1[11:7] <= n5[11:7] ;
n6_reg1[11:7] <= n6[11:7] ;
n7_reg1[11:7] <= n7[11:7] ;
s00_lsbreg1[7:0] <= s00_lsb[7:0] ;
ss Preserve all lsb sum. s00_lsbreg1[7] is the registered carry from lsb addition.
s01_lsbreg1[7:0] <= s01_lsb[7:0] ;
s02_lsbreg1[7:0] <= s02_lsb[7:0] ;
s03_lsbreg1[7:0] <= s03_lsb[7:0] ;
end
ss Sign extended & msb added with carry.
assign s00_msb[5:0] = {n0_reg1[11], n0_reg1[11:7]}+
{n1_reg1[11], n1_reg1[11:7]}+s00_lsbreg1[7];
sss00_msb[6] is ignored.
ss10.3 Signed Adder Design 387
ss Pipeline 2: clk (2). Register msb to continue addition of msb.
begin
s00_msbreg2[5:0] <= s00_msb[5:0] ; ss Preserve all msb sum.
s01_msbreg2[5:0] <= s01_msb[5:0] ;
s02_msbreg2[5:0] <= s02_msb[5:0] ;
s03_msbreg2[5:0] <= s03_msb[5:0] ;
s00_lsbreg2[6:0] <= s00_lsbreg1[6:0] ; ss Preserve all lsb sum.
s01_lsbreg2[6:0] <= s01_lsbreg1[6:0] ;
s02_lsbreg2[6:0] <= s02_lsbreg1[6:0] ;
s03_lsbreg2[6:0] <= s03_lsbreg1[6:0] ;
end
ss Second Stage Addition
assign s10_lsb[7:0] = s00_lsbreg2[6:0]+s01_lsbreg2[6:0] ;
ssAdd lsb first : s10_lsb[7] is the carry.
assign s11_lsb[7:0] = s02_lsbreg2[6:0] +s03_lsbreg2[6:0] ;
sss00, s01 lsbs need not be registered
sssince addition is already carried out here.
begin
s10_lsbreg3[7:0] <= s10_lsb[7:0] ; ss Preserve all lsb sum.
s11_lsbreg3[7:0] <= s11_lsb[7:0] ;
s00_msbreg3[5:0] <= s00_msbreg2[5:0];
ss Preserve all msb sum.
s01_msbreg3[5:0] <= s01_msbreg2[5:0] ;
s02_msbreg3[5:0] <= s02_msbreg2[5:0] ;
s03_msbreg3[5:0] <= s03_msbreg2[5:0] ;
end
assign s10_msb[6:0] =
{s00_msbreg3[5],s00_msbreg3[5:0]}+{s01_msbreg3[5],s01_msbreg3[5:0]}+s10_l
sbreg3[7] ;
ss Add MSB of second stage with sign extension and carry in from LSB.
ss s10_msb[7] is ignored.
assign s11_msb[6:0] = {s02_msbreg3[5], s02_msbreg3[5:0]}+{s03_msbreg3[5],
s03_msbreg3[5:0]}+s11_lsbreg3[7] ;
ss388 Arithmetic Circuit Designs
begin
s10_lsbreg4[6:0] <= s10_lsbreg3[6:0] ; ss Preserve all lsb sum.
s11_lsbreg4[6:0] <= s11_lsbreg3[6:0] ;
s10_msbreg4[6:0] <= s10_msb[6:0] ; ss Preserve all msb sum.
s11_msbreg4[6:0] <= s11_msb[6:0] ;
end
ss Third Stage Addition
assign s20_lsb[7:0] = s10_lsbreg4[6:0]+ s11_lsbreg4[6:0] ;
ssAdd lsb first : s20_lsb[7] is the carry.
begin
s10_msbreg5[6:0] <= s10_msbreg4[6:0]; ssPreserve all msb sum.
s11_msbreg5[6:0] <= s11_msbreg4[6:0] ;
s20_lsbreg5cy <= s20_lsb[7]; ss Preserve all lsb sum.
s20_lsbreg5[6:0] <= s20_lsb[6:0];
end
ss Add third stage MSB results and concatenate
ss with LSB result to get the final result.
assign sum[14:0] = {({s10_msbreg5[6], s10_msbreg5[6:0]}+
{s11_msbreg5[6], s11_msbreg5[6:0]}+
s20_lsbreg5cy), s20_lsbreg5[6:0]};
endmodule

::
c
c%cc
`define clkperiodby2 10 ss Frequency of operation is 50 MHz.
module adder12s_test(sum);
output [14:0] sum;
reg clk ;
reg [11:0] n0 ;
reg [11:0] n1 ;
reg [11:0] n2 ;
reg [11:0] n3 ;
reg [11:0] n4 ;
reg [11:0] n5 ;
reg [11:0] n6 ;
reg [11:0] n7 ;
adder12s u1( .clk(clk),.n0(n0),.n1(n1),.n2(n2),.n3(n3),.n4(n4),
.n5(n5),.n6(n6),.n7(n7),.sum(sum));
initial
begin
clk = 1'b0 ; ss Initialize the clock.
n0 = 12'h0 ; ss Apply the first set of inputs.
n1 = 12'h0 ;
n2 = 12'h0 ;
n3 = 12'h0 ;
n4 = 12'h0 ;
n5 = 12'h0 ;
n6 = 12'h0 ;
n7 = 12'h0 ;
#17 n0 = 12'hfff ; ss Apply the second set of inputs.
n1 = 12'hfff ;
n2 = 12'hfff ;
n3 = 12'hfff ;
n4 = 12'hfff ;
n5 = 12'hfff ;
n6 = 12'hfff ;
n7 = 12'hfff ;
#20 n0 = 12'h7ff ; ss Apply the third set of inputs.
n1 = 12'h7ff ;
n2 = 12'h7ff ;
n3 = 12'h7ff ;
n4 = 12'h7ff ;
n5 = 12'h7ff ;
n6 = 12'h7ff ;
n7 = 12'h7ff ;
#20 n0 = 12'h800 ; ss Apply the fourth set of inputs.
n1 = 12'h800 ;
n2 = 12'h800 ;
n3 = 12'h800 ;
n4 = 12'h800 ;
n5 = 12'h800 ;
n6 = 12'h800 ;
n7 = 12'h800 ;
#20 n0 = 12'h001 ; ss Apply the fifth set of inputs.
n1 = 12'h001 ;
n2 = 12'h001 ;
n3 = 12'h001 ;
n4 = 12'h001 ;
n5 = 12'h001 ;
n6 = 12'h001 ;
n7 = 12'h001 ;
#20 n0 = 12'h001 ; ss Apply the sixth set of inputs.
n1 = 12'hfff ;
n2 = 12'h001 ;
n3 = 12'hfff ;
n4 = 12'h001 ;
n5 = 12'hfff ;
n6 = 12'h001 ;
n7 = 12'hfff ;
#20 n0 = 12'h7ff ; ss Apply the seventh set of inputs.
n1 = 12'h7ff ;
n2 = 12'h7ff ;
n3 = 12'h7ff ;
n4 = 12'h801 ;
n5 = 12'h801 ;
n6 = 12'h801 ;
n7 = 12'h801 ;
#20 n0 = 12'haaa ; ss Apply the eighth set of inputs.
n1 = 12'h555 ;
n2 = 12'haaa ;
n3 = 12'h555 ;
n4 = 12'haaa ;
ss10.3 Signed Adder Design 391
n5 = 12'h555 ;
n6 = 12'haaa ;
n7 = 12'h555 ;
#20 n0 = 12'h0 ; ss Apply one more set of inputs.
n1 = 12'h0 ;
n2 = 12'h0 ;
n3 = 12'h0 ;
n4 = 12'h0 ;
n5 = 12'h0 ;
n6 = 12'h0 ;
n7 = 12'h0 ;
#400 ss Wait for some time before stopping.
$stop ;
end
always
#`clkperiodby2 clk <= ~clk ; ss Toggle the clock.
endmodule

%
(6c

c

%%cc cc
c 2

To design and simulate the pipelined serial adder using verilog HDL .
%%
c?c
? Xilinx ISE 10.1.

-·

%c

S.NO PIN DETAILS
1.? n0-n7 Eight input data from n0 to n7, and the width is
12-bits.
2.? Sum[14:0] Accumulated result available in this register.
3.? Sum_valid This signal will be enable when the output is
valid.
4.? enable This input signal will enable the adder when
enable=1.
5.? clk Clock input signal.

%·

::%%cc cc

module serial_adder12s ( clk,enable,n,sum,sum_valid,result) ;
input clk ;
input enable ;
input [11:0] n ;
output [14:0] sum ;
output sum_valid ;
output [14:0] result ; ss Prolong the result till it is overwritten by a new result.
wire [14:0] sum_next ; ss Declare nets in the design.
wire [2:0] cnt_next ;
wire sum_val ;
reg [14:0] sum;
reg [2:0] cnt ;
reg sum_valid ;
reg [14:0] result ;
assign sum_next [14:0] = enable ? ({{3{n[11]}}, n[11:0]} + sum[14:0]) : 0 ;
ss Sign extend & accumulate.
assign cnt_next [2:0] = enable ? (cnt + 1) : 0 ;
ss Pre-advance the counter.
assign sum_val = (cnt == 7) ? 1 : 0 ; ss Pre-determine the validity of the sum.
always @ (posedge clk) ss Pipeline ? Register the sum.
begin
sum [14:0] <= sum_next [14:0] ; ss Register the sum.
cnt [2:0] <= cnt_next [2:0] ; ss Advance the count.
sum_valid <= sum_val ; ss Register the signal.
end
ss Prolong the result till it is overwritten by the new result.
result[14:0] <= sum_valid ? sum[14:0] : result[14:0] ;
ss Register the sum.
endmodule

::
c
c%%cc cc

`define clkperiodby2 10
`include "serial_adder12s.v"
module serial_adder12s_test ( );sssum,sum_valid,result);
wire [14:0] sum;
wire sum_valid ;
wire [14:0] result;
reg clk ;
reg enable ;
reg [11:0] n ;
serial_adder12s u1( .clk(clk),
.enable(enable),
.n(n),
.sum(sum),
.sum_valid(sum_valid),
.result(result)
);
initial
begin
clk = 0 ;
ss Apply first set of inputs sequentially every 20 ns.
n = 12'h0 ; ss n0 @ 0 ns.
enable = 0 ;
#20 enable = 1 ;
#17 n = 12'hfff ; ss n1 @ 37 ns.
#20 n = 12'h7ff ; ss n2 @ 57 ns, etc.
#20 n = 12'h800 ;
#20 n = 12'h001 ;
#20 n = 12'h001 ;
#20 n = 12'h7ff ;
#20 n = 12'haaa ; ss n7 @ 157 ns.
#20 n = 12'h0 ;
enable = 0 ;
ss Disable before applying the next set of inputs
ss so that the accumulated ?sum? is cleared.
#20 enable = 1 ; ss Apply the next set of inputs.
n = 100 ; ss n0
#20 n = 200 ;
#20 n = 300 ;
#20 n = 400 ;
#20 n = 500 ;
#20 n = 100 ;
#20 n = 200 ;
#20 n = 247 ; ss n7
#20 enable = 0 ;
#100 $stop ;
end
always
#`clkperiodby2 clk <= ~clk ; ss Run the clock at 50 MHz.
endmodule

%
(6c

c

·

c
c 3

To design and synthesis the traffic light controller using verilog HDL .
%%
c?c
? Xilinx ISE 10.1.

%·

module traffic(clk,en,south,east,north,west,chip4_en);
input clk,en;
output [6:0]south;
output [6:0]north;
output [6:0]east;
output [6:0]west;
output chip4_en;
reg [6:0]south;
reg [6:0]north;
reg [6:0]east;
reg [6:0]west;
reg chip4_en;
reg term_count;
reg start_count;
reg[27:0]count;
reg[3:0]nstate;
parameter [3:0]idle=4'b0000,
step1_amber=4'b0001,
step1=4'b0010,
step2=4'b0100,
step3=4'b0110,
step4=4'b1000;
always @(posedge clk or posedge en)
begin
if(en)
begin
count=0;
term_count=1'b0;
end
else
begin
term_count=1'b0;
if(start_count)
begin
count=count+1;
if(count==25000000)
begin
term_count=1'b1;
count=0;
end
end
end
end
always@(posedge clk)
begin
if(en)
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=idle;
end
else
chip4_en=0;
case(nstate)
idle:
begin
south=7'b1000011;
east=7'b1000011;
north=7'b1000011;
west=7'b1000011;
nstate=idle;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step1_amber;
end
end
step1_amber:
begin
south=7'b0100000;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=step1_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step1;
end
end
step1:
begin
south=7'b0011100;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=step1;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step2_amber;
end
end
step2_amber:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b0100000;
nstate=step2_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step2;
end
end
step2:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b0011100;
nstate=step2;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step3_amber;
end
end
step3_amber:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b0100000;
west=7'b1000000;
nstate=step3_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step3;
end
end
step3:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b0011100;
west=7'b1000000;
nstate=step3;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step4_amber;
end
end
step4_amber:
begin
south=7'b1000000;
north=7'b0100000;
east=7'b1000000;
west=7'b1000000;
nstate=step4_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step4;
end
end
step4:
begin
south=7'b1000000;
north=7'b0011100;
east=7'b1000000;
west=7'b1000000;
nstate=step4;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=idle;
end
end
endcase
end
endmodulemodule traffic(clk,en,south,east,north,west,chip4_en);
input clk,en;
output [6:0]south;
output [6:0]north;
output [6:0]east;
output [6:0]west;
output chip4_en;
reg [6:0]south;
reg [6:0]north;
reg [6:0]east;
reg [6:0]west;
reg chip4_en;
reg term_count;
reg start_count;
reg[27:0]count;
reg[3:0]nstate;
parameter [3:0]idle=4'b0000,
step1=4'b0010,
step2=4'b0100,
step3=4'b0110,
step4=4'b1000;
always @(posedge clk or posedge en)
begin
if(en)
begin
count=0;
term_count=1'b0;
end
else
begin
term_count=1'b0;
if(start_count)
begin
count=count+1;
if(count==25000000)
begin
term_count=1'b1;
count=0;
end
end
end
end
always@(posedge clk)
begin
if(en)
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=idle;
end
else
chip4_en=0;
case(nstate)
idle:
begin
south=7'b1000011;
east=7'b1000011;
north=7'b1000011;
west=7'b1000011;
nstate=idle;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step1_amber;
end
end
step1_amber:
begin
south=7'b0100000;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=step1_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step1;
end
end
step1:
begin
south=7'b0011100;
north=7'b1000000;
east=7'b1000000;
west=7'b1000000;
nstate=step1;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step2_amber;
end
end
step2_amber:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b0100000;
nstate=step2_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step2;
end
end
step2:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b1000000;
west=7'b0011100;
nstate=step2;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step3_amber;
end
end
step3_amber:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b0100000;
west=7'b1000000;
nstate=step3_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step3;
end
end
step3:
begin
south=7'b1000000;
north=7'b1000000;
east=7'b0011100;
west=7'b1000000;
nstate=step3;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step4_amber;
end
end
step4_amber:
begin
south=7'b1000000;
north=7'b0100000;
east=7'b1000000;
west=7'b1000000;
nstate=step4_amber;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=step4;
end
end
step4:
begin
south=7'b1000000;
north=7'b0011100;
east=7'b1000000;
west=7'b1000000;
nstate=step4;
start_count=1'b1;
if(term_count)
begin
start_count=1'b0;
nstate=idle;
end
end
endcase
end
endmodule

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First Three and Last Three Experiments

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First Three and Last Three Experiments

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? Xilinx ISE 10.1.

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? Xilinx ISE 10.1.

? Xilinx ISE 10.1.

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