RC-SCR: verv-low-voltaae ESD protection

circuit in plain CMOS

- design, C = IOpF and R = 1 kQ arc the optimised values. The new
H. Feng, R. Zhan, Q. Wu, G . Chen and A.Z. Wang
A simple, novel RC-coupled very-low-voltage silicon controlled
rectifier, electmsfatic discharge protection circuit is repolle4 imple-
mented in 0.35 pm CMOS, which is confirmed by transient electro-
static dischwge simulation and measurement, and results in a very low
mggenng of 7 V, a 60% reduction over bvditional silicon controlled
rectifiers.
design was implemented in plain 0.35 bm production CMOS. Figs. 3
and 4 show typical I-V curves by transient ESD simulation and
measurement by transmission-line pulsing (TLP) testing for the plain
SCR, LVSCR and RC-SCR, respectively, which clearly demonstrate
the expected reduction in V,, from 17.7 V to 9.91 V to 7.05 Y as
summarised in Table I.This V,, reduction of -60% and -28% over
SCR and LVSCR, respectively, makes RC-SCR a valuablc solution for
plain CMOS.

Introduction: On-chip electrostatic discharge (ESD) protection S ~ N C -

tures usually rely on a snapback I-V characteristic to form a Iow-
impedance (RoJ conducting path to discharge ESD pulses safely and
feature a triggering point (V,,, I C , ) ,corresponding to tum-on of an
ESD device, a holding point (Vh, I,,) and a thermal breakdown
threshold (V,,, I,z) [I]. Compared with other ~ t r u ~ t ~ re.g.
e s ,NMOS
or diodes, a silicon controlled rectifier (SCR) protection structure can
handle much higher ESD currents and delivers a larger ESD protec-
tion-to-size ratio, which makes it attractive to area and parasitic p substrate
sensitive mixed-signal and RF ICs, given that the latch-up problem a
is resolved in design. However, the relatively higher V,, of SCR
structures usually makes them not useful in CMOS. The high V,, of
the SCR is due to its high well/substrate junction breakdown voltage
as initial triggering mechanism [I, 21. Sevcral trigger-assisting tech-
niques have been devised to reduce the V,, of the SCR. For example,
an MVSCR [2] uses an inserted N+ region and an LVSCR uses a
grounded-NMOS to initiate triggering far lower V,, [3]. Gate-coupled
NMOS triggered SCR were reported to further reduce V,, [4, 51.
Simulation results of a pwell-coupled SCR was reported for a special
triple-well CMOS [6]. However, there V,, reduction tcchniques either
rely on limited substratc current, or resort to exotic process
features. In addition, the gate of the NMOS in LVSCR is vulnerable b
due to direct exposure to ESD pulses.
In this Lener, a simple, novel RC-coupling based low-V,, Fig. 1 Cross-reetions for various RC-SCR ESD protection network
ESD protection circuit (RC-SCR) is devised to fmrther rcduce V,, in u Conventional SCR
plain CMOS. Table I summariscs the data of the RC-SCR along with a h ggNMOS-mggered LVSCR
plain SCR, MVSCR and LVSCR, implcmented in a conventional
production 0.35 pm CMOS.

Table 1 :Data summary of V,, for plain SCR, LVSCR and RC-SCR
from simulation and TLP tests

-_.___- ~

R2 :'
I'
1; IRq--!s:!.-:
J
'2 R2 /
4
R

K K

RC-SCR ESDprotecrion circuit de.@ and experiment: Fig. I shows Fig. 2 Equivalent circuits fhRC-SCR ESD protection network ofFig. I
two versions of the new RC-SCR based on a plain SCR (a) and an 1.5
LVSCR (b), where an external trigger-assisting RC sub-network is
added between the anode (A) and cathode (K) in each original ESD
protection structire. Fig. 2 shows their equivalent circuits. The basic
-- ESDP: LVSCR
ES03: RC-SCR
idea is to use an external RC net to quickly turn on the emittcr of the
1.o
vertical xpn, Ql, with the following triggering mechanism: consider-
ing the SCR triggering operation under ESD, Iruh flows through the 4
c

substrate in the cathode region and is collected by terminal K , which $!

builds enough potcntial to turn on the BE junction of the lateral NPN, 5
Q2, then the Q l , and finally the SCR to discharge ESD pulses. With 0.5
the addition of the RC-coupling sub-nehvork, an ultra fast ESD pulse
couples through the capacitor, C, into the resistor, R, and builds up the
potential, RI,, to turn on Q2, in parallel with the original R&,,
therefore accelerates the triggering procedure of the SCR signifi- 0 .. ..
0 4 8 12 16 20
cantly. Hcnce, RC-SCR can realise a much-reduced V,, value as
uo1tage. v
desired far olain CMOS without comdicated measures. In oractical
design, several issues must be addressed. First, the criteria for ~ i3 ~~ - ~. ~ h ~ ~ ~ ~ ~ ~ ~SCR, t i ~ ~ / uRC-SCR
i ~ LVSCR r p l ubyi transient
n
selecting the R and C values are to ensure that the RC sub-net ESD s ~ m u ~ o l i o n
responds to an pulse promptly but insensitive to Rising and falling portions of curves correspond 10 "sing and falling of transient
normal signals, a task done by simulation. Secondly, parasitic junction g may not be always achiwed in transient ESD
ESD pulse. ~ ~ l d i npoint
capacitance must be included far accurate mgger timing. In this simulation. All device are 20 pm wide

ELECTRONlCS LE7TERS 12th September 2002 Vol. 38 No. 79 1099

 0.5
*ESDt:SCR
-ESD2: LVSCR
0.4- -ESD3: RC-SCR
voltage, v
Fig. 4 I-Vchnmcteristicsforplnin SCR, LVSCR ond RC-SCR by TLP tests
Conclusions: A simple, novel RC-coupling-based ESD protection
circuit is designed and implemented in 0.35 pm plain CMOS to
realise ultra low triggering. The new concept is proved by both
simulation and tests. The low V,, of 7 V, a 60% and 28% reduction
over a plain SCR and LVSCR, respectively, makes RC-SCR a viable
ESD protection solution for CMOS mixed-signal and RF ICs.
Acknowledgment: The authors wish to acknowledge Avant! for CAD
s o h a r e , AKM for fabrication and Barth Electronics TLP tests.
0 IEE 2002 26 June 2002
Electronics Letters Online No: 20020758
D o l : 10.1049/el:20020758
H. Feng, R. Zhan, Q. Wu, G. Chen and A.Z. Wang (Integrated
Elecmnics Laboratory. Dept. of Electrical & Computer Engineering.
Illinois lnstihde of Technologv. 3301 S. Dearborn St., Chicago. IL.
USA)
E-mail: awang@ece.iit.edu
References
I WANG, A,: 'On-chip ESD protection for integrated circuits' (Kluwer
Academic Publishes, 2002)O-7923-7647-1
2 AMERASEKERA, A,, and DWURY, c.: 'ESD in silicon integrated circuits'
(Wiley, New Yoh, 1995)
3 CHATTERIEE, A , and POLGREEN. T.: 'A low voltage triggering SCR for 0"
chip ESD protection at output and input pad', IEEE Elecmn. Device
Lett., Jan. 1991, 12, pp. 21-22
4 CHATTEWEE. A,, DUYWRY, c., YANG, P., and AMERASEKERA, E.: 'Gate
coupled SCR for ESD protection circuits' (US)59074621999
5 KER, M., and CHANG, H.: 'How to safely apply the LVSCR far CMOS
whole chip ESD pmtection without being accidentally triggered on'.
Fmc. IEEE EOSJESD Symp, 1998, pp. 72-85
6 NIKOLAIDIS,T., and PAPADAS,c.: 'A novel SCR ESD protection for triple
well CMOS technologies', IEEE Electron. Dorice Lett., 2001, 22, (4),
pp. 185-187
Digital-domain self-calibration technique for
video-rate pipeline A/D converters using
Gaussian white noise
J. Goes, N. Paulino and M.D. Ortigueim
A digital-domain selfsalibmtion technique for video-rate pipeline
AID converters based an a Gaussian white noise input signal is
presented. The pmposed algorithm is simple and efficient.A design
example is shown 10 illustrate that the overall linemiry of a pipeline
ADC can be highly improved using this technique.
Introduction: A broad area of applications with enhanced perfor-
(ADCs) employ pipelining as a means of relaxing the speed require-
ments of the analogue components. Such architectures use a cascade
of stages comprising a low-resolution flash quantiser and a multi-
plying digital-to-analogue converter (MDAC), which computes and
amplifies the residue for the next stages. As a consequence, the
precision requirements are more critical in the Front-end stage of
the pipeline, which must exhibit the accuracy ofthe overall ADC, and
are progressively relaxed towards the last stage. Without using either
trimming or self-calibration techniques, the overall resolution of lhese
ADCs is limited by the linearity and gain errors of the front-end
MDACs. These errors are bounded around the 8 to 10 bit level by the
component matching accuracy of most CMOS processes available
today. As trimming is expensive, self-calibration either in the analo-
gue or in the digital domain must be considered for extending the
resolution of such ADCs above 10 bits. The analogue techniques
proposed in the literature require separate calihration DACs and
precision analogue components [ I , 21. Although, digital calibration
techniques do not require sophisticated analogue circuiw they put an
extra burden on the digital part [ 3 , 41. Furthermore, the MDAC of a
calibrated stage has to be modified (introduction of many addilional
switches) to perform the required code-error measurements [ 4 ] .
Moreover, the technique proposed in [ 3 ] can only be employed in
1.5 bit MDACs an4 therefore, it is not suitable fix power-optirnised
high-resolution architectures where multihit rather than single-bit
front-end stages are preferred [ S I .
Proposed technique: The technique proposed in this Letter consists
of applying a Gaussian white noise (GWNj stimulus to the ADC and
calculating the calibrating codes from the histogram of the output
codes. There are several advantages of this digital-domain self-
calibration technique when compared with those reported in [3, 41:
(i) the entire ADC does not need to be modified; (ii) it is suitable for
ADCs with multibit front-end stages; (iii) wideband (2FJ GWN is
relatively easy to generate on-chip using a lateral PNP transistor
followed by a gain-stage and by a switched-capacitor programmable-
gain amplifier (PGA) for standard-deviation adjustment; on-chip self-
testing can be performed; (iv) GWN having a uniform power spectral
density allows a full-speed characterisation of the ADC [ 6 ] ; and (v)
the use of a cumulative technique (histogram) will eliminate uncer-
tainties from the calibrating codes due to noise.
In an N-bit pipeline ADC comprising an M,-bit front-end stage and
Ns stages, the overall linearity is mainly limited by the mismatches in
the first stage. A typical conversion characteristic consists basically on
ZM' segments dislocated from an 'almost' ideal straight line. The digital
amounts of dislocation can be measured during a calibration cycle and
stored in a memory These ZM' calibrating codes can be addressed later
and recalled during normal conversion mode, using the c o m e digital
outputs from the first stage MI-bit quantiser, ;md the conversion
characteristic moved back to the ideal line by digitally submcting
these codes. Applying centred GWN to the input of the ADC, a 2(''t2'
bins histogram can be computed by counting the number of occurrences
of the output codes inside the corresponding bins defined by the
(MI + 2 ) bits of the output code. This histogram, m i ] , will have a
Gaussian shape, more or less 'distorted' by the existing deviativns of
the segments. Assume now that there is a specific table, nil, with
2""" values, truncated and stored in a memory, and defined by
where A[i] represents the ideal 2(M1+2Jhistogram produced mathema-
tically using a Gaussian distribution function with p=2"" and
0 = 2 ( ~ - ' ) / 2 .n i l is used to normalise mi], resulting, in the ideal
case, in a histogram with 2'"-'M1+2)) occurrences in each bin. The
differences from this expected value can be used to calculate the
calibrating codes. Thus, assuming a large number of samples, n,
these differences are given by
~ [ ~~[ il] /.2 M t Z-) 2(n-(MI+V)
D[i] =