AMERICAN MICROSYSTEMS. INC, Features Ultra Low Standby Power Data Retention at 2V (L Version) Single +5V Power Supply Completely Static Operation Completely TTL Compatible Inputs ThreeState TTL Compatible Outputs Available in Commercial, Industrial, and Military Temperature Range c 40 $5101 1024 BIT (256 X4) STATIC CMOS RAM General Description ‘The AMI $5101 family of 256x 4-bit ultra low power CMOS RAMs offers fully static operation with a single +5 volt power supply. All inputs and outputs are direct- ly TTL compatible. With data inputs and outputs on adjacent pins, ether separate or common data 1/0 opera- tions can easily be implemented for maximum design flexibility. The three-state outputs will drive one full TTL load and are disabled (high impedance statel by output disable (OD), either chip enable (CE1 or CE2), or in a write cycle (R/W=LOW). This facilitates the control of common data 1/0 systems. Block Diagram t Logie Symbol Pin Configuration agi nh Sete wpe sas fies Truth Table Ge] ce2 | ov | nwo [output | node WE Lx | x |X | tana | Notseivcea x fa] x | x |x | tienz | Notseeena x] ox | | oa | x | atgnz | ovtpue Dinbied cla] a |e] x | ainz| wate cla fe | cl x | oimz | woe cf afe | a] x | pow | rad Pin Names Ao- Ay Address Inpats hip Boabie Diy-Diy Data Inputs = CEZ_— Chip Enable DO;-DO4 Dats Outputs «JW Read/Write Input op Output Diaable Voc *8 Volt Power Supply 83AMI $5101 General Description (Continued) The stored data is read out nondestructively and is she same polarity as the original input data. The 85101 's totally static, making clocks unnecessary for a new address to be accepted. The device has two chip enable inputs (CE1 and CE2) allowing easy system expansion, CE2 disables the entire device but CE1 does not dis- able the address buffers and decoders. Thus, minimum power dissipation is achieved when CE2 is low. Absolute Maximum Ratings* ‘The 1. version of the $5101 has the additional feature of guaranteed data retention with the power supply as low as 2volts. This makes the device an ideal choice when battery augmented non-volatile RAM storage is mandatory. The $5101 is fabricated using a silicon gate CMOS process suitable for high volume production of ultra low power, high performance memories. ‘Ambient Temperature Under Bias—Ty (Standard Part) (Industrial temp part) (Military temp part) Storage Temperature 226-2605 Voltage on Any Pin with Respect to Ground Maximum Power Supply Voltage Power Dissipation + 0°C to 70°C = 40°C to +85°C 55°C to +125°C 85°C to 150°C =0.3V to Vor +0.3V ey, 1w SCOMMENT. Stresses above those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Thisis a stress ‘ating otly and funetional operation of the device at these or at any other condition above those indicated in the operation tons of this {pecilcation snot implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability D.C. Characteristics: T,=0°C to +70°C (Standard part; 5V 5% (unless otherwise specified) +125°C (Military temp part), Voc: 40°C to +85°C (Industrial temp part); 55°C to Limits Symbol_| Parameter Min. | Max. | Units | Conditions It Input Leakage Current 1 [ua [Way = 0Vt0 Veo CET= Vai tro | Output Leakage Current 1 HA | Vous = OV to Voc ; a Outputs = Open, lec Operating Supply Current ; 22 ma | ye to Veo S5101L1, S5I0IL 10 [HA | Vin = OV to Voc Toc. | Standby Supply Current [S51011.3 140_[wA_| except S5101L8, S8101-6) 500_|uA | CE2<0.2V Vin Tnput Low Voltage 0.65 | V Vin Input High Voltage 7 Voc _[V Vou Output Low Voltage 04 _[V__| Tor, Vou ‘Output High Voltage : 2a V__[Tow Capacitance Symbol_| Parameter Units | Conditions Gy Input Capacitance - 3 | pF __| Vay = OV, on all Input Pins Go, Output Capacitance 12 | pF [Vo =0V 84AM I $5101 PTS A.C. Characteristics for Read Cycle: T,=0°C to + 70°C (Standard part); — 40°C to +.85°C (Industrial temp part}; —85°C to +125°C (Military temp part), Voc=5V+5% (unless otherwise specified) Sir Soria ss1oiLa ss101L3 5101-8 Symbol | Parameter Limits Limits Limite [Units] Conditions Min, [Max [Mim] Max [Min [Na Taq | Red Oye Tne 350 350 300) im Taco | Access Time 350 3 300 me Toor | CEI to Outpt Delay $00, 3007 500 ne Too2 | CEP to Output Dela 305 700 350 [ns] See AC Top | Output Diable to Enatied Concitions Output Delay amu 450 [ms] or Test and Tr | Outnut Disabte to Outpnt AG. Test HZ State Delay ° 180 ° 150 _ aera lee Load Tomi | Ouiput Data Valid Toto Next Cycle with respect to . o ° = ‘Ades Tone) Outoue Date Valid Into ‘Next Cycle with respect ° ° ° ns to Chip Enable Read Cycle «| ——} | Note 1. OD may be tied low for seaprate 1/0 information, 2. The output will yo into & high impedance state if either CE1 is high, CEQ is low, OD is high or R/W is low 85