ECE 2300


Digital Logic & Computer Organization

Spring 2018

CMOS Logic

Lecture 4: 1
 NAND Logic Gate

X (X•Y)’
Y =
NAND

Using De Morgan’s Law: (X•Y)’ = X’+Y’

X X’
X’+Y’
=
Y Y’
Also a NAND

We can build circuits from NAND only!

Lecture 4: 2
 We Can Build Circuits from NAND Only!

•  NOT

•  AND

•  OR

Lecture 4: 3
 NOR Logic Gate

X X+Y (X+Y)’
Y
=
NOR

Using De Morgan’s Law: (X+Y)’ = X’•Y’

X X’
X’•Y’
=
Y
Y’ Also a NOR

We can build circuits from NOR only!

Lecture 4: 4
 Sum-of-Products Revisited

AND-OR

NAND-NAND
Lecture 4: 5
 Product-of-Sums Revisited

OR-AND

NOR-NOR
Lecture 4: 6
 A Little Bit of History
•  Transistors
–  Invented by John Bardeen, Walter Brattain, and William
Shockley at Bell Labs in 1947
•  Integrated circuits
–  Independently developed by Jack Kilby (at TI) and Robert
Noyce (at Fairchild) in the 1950s
–  Noyce and Gordon Moore founded Intel in 1968
, and architecture. At TABLE 1. INTEL PROCESSORS, 1971–1993.
ion level, the verifica-
PROCESSOR INTRO DATE PROCESS TRANSISTORS FREQUENCY
was typically the most
e it was addressed first. 4004 1971 10 mm 2,300 108 KHz
s problem at that level 8080 1974 6 mm 6,000 2 MHz
d much later. 8086 1978 3 mm 29,000 10 MHz
le is the story of the
80286 1982 1.5 mm 134,000 12 MHz
of design methodolo-
es, and CAD tools in 80386 1985 1.5 mm 275,000 16 MHz
n environment as it Intel 486 DX 1989 1 mm 1.2 M 33 MHz
creasing complexity in Pentium 1993 0.8 mm 3.1 M 60 MHz
1980s and up through
It is interesting to noteSource:
theirPatrick Gelsinger,
way into the EDADesmond
industry asKirkpatrick, Avinoam
originated Kolodny,
in Don and group
Pederson’s Gadi Singer.
ginning of this process"Such keya CAD!."
enablersIEEE Solid-State
of many Circuits
EDA tools and Magazine,
at Berkeley 2010.
and later on was refined Lecture 4: 7
ing culture was advo- today’s fabless ASIC/SOC semicon- by Richard Newton, Alberto, and
thin design. Nowadays, ductor industry. their students (Intel’s version was
 Era of Billion-Transistor Chips

Apple A11
 Intel Haswell-EP Xeon E5 
 IBM Power9 


~4B transistors ~7B transistors ~8B transistors

NVIDIA V100 Pascal
 Intel/Altera Stratix 10


Oracle SPARC M7 

~21B transistors ~30B transistors
~10B transistors
Lecture 4: 8
 MOS Transistors
Our Switches: MOS Transistors
•  •Metal-Oxide
MOSFETs Semiconductor Field-Effect
Transistors (MOSFETS)
– Metal-Oxide Semiconductor Field-Effect Transistors
–  –MOS transistors
Shortened fortransistors
to MOS short

gate source
source
source
gate
gate Carriers
Carriers
VIN (holes
(holesoror
W electrons)
electrons)
L
drain
drain
drain
A 3-terminal device controlled by the gate voltage
Voltage-controlled resistance (switch)
that acts like a switch
• Extreme changes in resistance (0 to ∞) make
transistors
•  Extreme act likeinswitches
changes resistance (0 to ∞) make
transistors act like switches Lecture 4: 9
ENGRD 2300 L2 – CMOS 9
 NOT Gate Input & Output Voltages
A Y A Y A Y
0 1 L H 0V 5V
1 0 H L 5V 0V

•  When the input voltage is low, the output

should be connected to the voltage supply
(e.g., VDD, VCC)

•  When the input voltage is high, the output

should be connected to ground (i.e., GND)

Lecture 4: 10
NOT Using Switches
A Y A Y A Y
0 1 L H 0V 5V
1 0 H L 5V 0V

•  Can build a NOT using two

types of switches
–  Type 1: Closed when input = 0,
open when input = 1
–  Type 2: Closed when input = 1,
open when input = 0

Lecture 4: 11
 NAND Using Switches
5V Inputs Output
A B Y

Type 1: closed
L L H

Y=H

A=L
Type 2: open

B=L

Lecture 4: 12
 NAND Using Switches
5V Inputs Output
A B Y

H L H

Y=H

A=H

B=L

Lecture 4: 13
 NAND Using Switches
5V Inputs Output
A B Y

H H L

Y=L

A=H

B=H

Lecture 4: 14
 MOS Transistors
•  Current flows when ON (conducting)
•  No current flows when OFF (not conducting)

•  Type 1 and Type 2 switches

S D
PMOS NMOS
G or G or
p-channel n-channel
D S
Type 1 Type 2

Bubble: LOW closes the switch G: Gate; S: Source; D: Drain

Lecture 4: 15
 MOS Transistors
•  PMOS S
–  Closed when input is low [1]
G
–  Open when input is high
–  Passes a good one (but a poor D
zero) [2]
PMOS and NMOS
have
•  NMOS complementary
–  Closed when input is high [1] properties
–  Open when input is low D

–  Passes a good zero (but a poor G

one) [2]
S

[1] In both cases, the voltage difference between the gate and source must exceed certain threshold
voltage before the the transistor starts having any effect
[2] Optional reading: vlsimsee.blogspot.com/2013/05/why-cant-nmos-pass-1-and-pmos-pass-0.html
Lecture 4: 16
 CMOS Logic Gates
•  Complementary MOS (CMOS)
–  CMOS dominates the digital IC market VDD

•  Uses both NMOS and PMOS P

…
devices such that there is no direct
supply-ground path
–  Dissipates little power when the
inputs don’t change … N

•  Our focus: Static CMOS gates

–  Other types exist as well (pseudo- GND
NMOS, domino, ...)
Lecture 4: 17
 CMOS Inverter
VDD
Vin Vout
S
G
T1
D
Vin is high
Vout T1 is off
D
T2 is on
G
Vout is low
Vin T2
S
Vin is low
T1 is on
T2 is off
Vout is high
Lecture 4: 18
CMOS NAND Gate

Lecture 4: 19
3 Input CMOS NAND Gate

An n-input NAND uses 2n transistors

Lecture 4: 20
Exercise: A “Mystery” Gate

(1) Fill out the missing entries in

the above table (on/off);
(2) Identify the logic gate that is
implemented by the CMOS
network

Lecture 4: 21
 2-Input AND Gate
•  CMOS gates produce inherent inversion
•  Need to add an inverter to a 2-Input NAND to
form AND gate

Lecture 4: 22
 Structure of Transistor Networks
•  Two complementary
Pull-up
networks: network
–  A pull-up network composed
of PMOS, with sources tied
to voltage supply

–  A pull-down network
composed of NMOS, with
sources tied to ground

–  Equal number of NMOS and

PMOS transistors

Pull-down
network
Lecture 4: 23
 Structure of Transistor Networks
•  The pull-up and pull-down Parallel
networks are always duals subnet

•  To construct the dual of a

network:
–  Exchange NMOS for PMOS
(and vice versa)
–  Exchange series subnets for
parallel subnets (and vice
versa)
•  This transformation applies
to hierarchical structures

Series
subnet
Lecture 4: 24
Duality of Parallel/Series Subnets
F
A
B
Pull-down series subnet
F pulls down to 0 when A and
B are high => F = (A•B)’
F
A B
Pull-down parallel subnet
F pulls down to 0 when A
or B is high => F = (A+B)’
A B
F
Pull-up parallel subnet
F pulls up to 1 when A or B
is low => F = A’+B’ = (A•B)’
A
B
F
Pull-up series subnet
F pulls up to 1 when A and B
are low => F = A’B’ = (A+B)’
Lecture 4: 25
 Analysis of Transistor Networks
•  Transistor states
–  Determine all possible
input combinations
–  Figure out the state of
each transistor
–  Determine final output

•  or by inspection
–  Figure out what input
combinations cause a 1
(or a 0) output

Lecture 4: 26
 Analysis of Transistor Networks
•  Build the truth table

INPUTS TRANSISTORS OUTPUT

ABC Q1 Q2 Q3 Q4 Q5 Q6 Z
000
001
010
011
100
101
110
111

Lecture 4: 27
Analysis of Transistor Networks
•  By inspection
–  Inspect either pull-up (PMOS)
or pull-down (NMOS) network
–  Translate the series (parallel)
subnets into product (sum)
terms
–  For pull-down network, negate
the combined expression

Pull-up: (A’+B’)C’

Pull-down: (A•B + C)’

Lecture 4: 28
 Recipe for Constructing CMOS Gate
F = (A(B+C))’
Step 1. Figure out pull- Step 3. Combine PMOS pull-up network
down network that from Step 2 with NMOS pull-down network
does what you want A from Step 1 to form fully-complementary
(e.g., what combination CMOS gate.
of inputs generates a
low output) B C

B
A
C

Step 2. Walk the

hierarchy replacing A
NMOS with PMOS,
series subnets with B
parallel subnets, and A
B C
parallel subnets with C
series subnets

Lecture 4: 29
 CMOS Sanity Checks
•  Equal number of NMOS and
PMOS

•  NMOS sources tied to ground

or to drain of another NMOS

•  PMOS sources tied to Vdd or

drain of another PMOS

•  Inputs tied to pairs of PMOS

and NMOS transistors

Lecture 4: 30
A More Complicated Circuit

Lecture 4: 31
 Next Time

Combinational Building Blocks

Lecture 4: 32