ID No.

: Birla Institute ofName:

Technology and Science (BITS) Pilani Sec:
1st Semester 2014-2015
EEE F214/INSTR F214/ EEE C381
Electronic Devices/Electronic Devices and Integrated Circuits (EDIC)
Reading Assignment Assesment

Date: 23.11.2014 Duration: 40 Mins MM: 30

ID No.: Name: Sec:

Note: Each question carries 1 Mark. Attempt as many questions as you can. Choose (Tick)
the correct alternative/ Choose (Tick) the correct pair of alternatives/ Properly write “T”/
“F” against true/ false statements.

1. In a typical bipolar transistor ohmic contacts are made on both sides of the emitter to
reduce the
(a) Emitter resistance (b) Base resistance (c) Collector resistance.

2. Any patterend sub-region is grown on the substrate by the process of

(a) Oxidation (b) Ion implantation (c) Diffusion.

3. The process used to make the shallow emitter region is

(a) Oxidation (b) Ion implantation (c) Diffusion

4. Due to shallow emitter effects decreasing emitter depth influences the base current and
current agin as,

(a) Base current and current gain both decreases.

(b) Base current increases and current gain decreases.
(c) Decreases the base current and increases the current gain.

5. In a BJT large collector area leads to

(a) Large depletion width on collector-side (b) Large capacitance (c) Large built-in-
potential.

whereas large overall device area makes the transistor not suitable for

(a) Switching applications (b) Memory applications (c) Heat resistive applications.

6. Higher doping concentration of a collector just underneath the emitter but a lower doping
elsewhere in the collector affects the base-collector junction capacitance in pedestal-
collector transistor as,

(a) Capacitance minimizes (b) Capacitance maximizes (c) Capacitance first increases
and then decreases after a ceratin peak value.

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7. Self aligned poly Si base contact scheme in BJT minimizes base-collector junction area
and allow the metal-to-base contact to be located over the

(a) Gate oxide (b) Field oxide (c) Depletion oxide.

8. In advanced Si bipolar transistor heavily doped n-type poly Si emitter is formed directly on
the p-type base layer to obtain

(a) Higher base resistance (b) Lower emitter resistance (c) Higher collector resistance .

9. In a heterojunction bipolar transistor higher emitter injection efficiency can be obtained by

(a) Wide bandgap emitter and narrow base.

(b) Wide band gap emitter and heaviliy doped base.
(c) Heavily doped emitter and wider base than emitter.

10. In a double poly Si self aligned bipolar transistor, the load capacitance delay copmponent
is reduced sufficiently so that any of the following effect can easily dominate circuit
delays.

(a) Base widening (b) Emitter crowdening (c) Early effect

11. Transistor with thick collector region has following advantage(s);

(a) Larger base-collector junction capacitance and minority carrier storage volume in
collector.
(b) Smaller base-collector junction capacitance and larger minority carrier storage
volume in collector.
(c) Larger base-collector junction capacitance and smaller majority carrier storage
volume in collector.

12. Indicate T or F: Deep trench isolation can provide

(a) Significant increase in isolation area. (F)

(b) A definite pattern is required to design the sub collector of a HBT. (F)

13. According to scaling theory in a Si bipolar transistor, voltages remain constant while
(a) Base current density remains constant and doping concentration decreases.
(b) Emitter current density remains constant and doping concentration increases.
(c) Collector current density remains constant and doping concentration increases.

14. In Si-Ge base bipolar transistor, poly Si emitter is used to achiev adequate
(a) Voltage gain (b) Current gain (c) Avalanche gain.

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15. Base current of a bipolar transistor is independent of

(a) Base and emitter parameters (b) Base and collector parameters (c) Emiiter and
collector parameters.

16. Indicate T or F: Gate delay is scaled by a factor of 1/α [where, α is the Dimensional
Scaling Parameter] both for Constant Electric-Field Scaling and Generalized Scaling. (T)

17. In transfer characteristics for MOSFET, subthreshold slope cannot be scaled, since it is

(a) Related to the bandgap energy of semiconductor

(b) Dictated by the thermodynamics of the Boltzmann distribution of carriers

(c) Tied to fundamental Planck's constant.

18. Lightly doped drain (LDD) technology was used to reduce

(a) Surface scattering (b) Subthreshold leakage (c) Hot carrier-induced device
degradation.

19. Indicate T or F: The predecessors of submicron MOSFET introduced the sidewall

spacer (enabled by reactive ion etching). (F)

20. Indicate T or F: Application of halo implants at the source and drain edges results in more
VT roll off . (F)

21. Indicate T or F: Al is preferred over Cu (for wiring) due to reduce electromigration (F)

22. Indicate T or F: Confining the channel to a thin silicon layer introduces a potential
problem, called quantization modulated threshold voltage. (T)

23. For the double-gate MOSFET structure , with a very thin undoped silicon channel,

(a) Precise dopant placement in the channel region is not necessary, but steep lateral
junction dopant profile is necessary.

(b) steep lateral junction dopant profile is not necessary, but precise dopant placement
in the channel region is necessary.

(c) Both are necessary

24. The nonvolatile FLASH/EEPROM chip, which uses floating-gate transistor

(a) is not highly scalable but is highly integratable with logic.

(b) is highly scalable and but is not highly integratable with logic.

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(c) is highly scalable and is highly integratable with logic.

25. In order to avoid uncertainties due to random dopant fluctuations, silicon nanoscale
MOSFET’s are often designed with a

(a) Thin undoped channel (b) Thick undoped channel (c) Thin highly-doped channel.

26. Indicate T or F: The minimum channel length, for bulk CMOS and/or DG CMOS, is not
limited by the lithography and patterning capabilities. (F)

27. SIMOX process is related to making of

(a) Bulk MOSFET (b) SOI MOSFET (c) Bulk and SOI MOSFET.

28. Indicate T or F: For a device with multiple dots in the gate, the number of stored
electrons per dot may be reduced by increasing number of dots helps to mediate variations
on any single dot. (T)

29. Spin LEDs have following properties in comparison with ordinary LEDs :

(a) Higher series resistance and lower electroluminescence intensity.

(b) Higher series resistance and higher electroluminescence intensity.

(c) Lower series resistance and higher electroluminescence intensity.

30. With existing semiconductor technology conventional ferromagnetic metals are

(a) Seldom incompatible (b) Often incompatible (c) Can never be incompatible

31. Choose the right option :

(a) If the two ferromagnets are anti-aligned, a spin-polarised current (for spin FET) will
behave like a normal FET current; and if the ferromagnets are aligned the transistor will be
shut off.

(b) If the two ferromagnets are aligned, a spin-polarised current (for spin FET) will behave
like a normal FET current; and if the ferromagnets are anti-aligned the transistor will be
shut off.

(c) Behavior does not depend on alignment.

32. "Spin-based devices will be faster and consume less power than their electronic counterparts"-------
---- As per Bandyopadhyay and Cahay, this statement is

(i) Always untrue (ii) Generally untrue (iii) Never untrue.

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