VEDA IIT:GRADUATE ENGINEERS

Engineer Trainee Recruitment

 All India Exam

 Preliminary Test for 1 hour – 30 Marks

 Electronics and Aptitude

 Main Technical Test for 2 hours – 70 Marks

 Eligibility – BE or ME or MSc with Electronics

 Training Interface – VEDAIIT

 Selection - Written Test, Interview

 Compensation – Purely Based on Performance

 Evaluation – Written Test, Interview, Training

 Bond Agreement - 3 years with 3L Bank Guarantee

Engineer Trainee (Analog Design)

 Main Technical Test

 Analog Design –40 Marks

 Circuit basics – 30 Marks

 Job Description –

 AMS Design in 14 nm FinFET, 22nm for blocks like PLL, DLL, CDR,
Equalizers, Drivers, LDO, etc.

 Design of high speed SerDes like USB3, SATA, PCI

 ADC, Memory, Standard Cell designs

 Training - 6 Months Sponsored Training

 Salary Range – 3 to 6 Lakhs per annum

 Technology – 14nm FinFET, 22nm

Engineer Trainee (Logic/Physical Design)

 Main Technical Test

 Digital Design - 30 Marks

 C Programming - 20 Marks

 Aptitude - 20 Marks

 Job Description –

 LD – RTL implementation, Design Verification, DFT

 PD – Place & Route, Physical Verification

 Training - 6 Months Sponsored Training

 Salary Range – 2.4 to 3.6 Lakhs per annum

 Technology – Mobile/Computing/IOT SoCs, DSM technologies till 14 nm

 Engineer Trainee (Custom Layout)

 Main Technical Test

 Analog Design – 40 Marks

 Circuit Basics – 30 Marks

 Job Description –

 Layout and physical verification for Analog IP, Custom circuits

 Training - 6 Months Sponsored Training

 Salary Range – 2.4 to 3.6 Lakhs per annum

 Technology – 14nm FinFET, 22nm

Engineer Trainee (Embedded System Design)
 Main Technical Test

 Digital Design, Microprocessors, Microcontrollers, Interfaces - 30 Marks

Assembly Programming, Peripherals, System & Hardware design

 C Programming – 20 Marks

 Aptitude – 20 Marks

 Job Description –

 Drivers, Firmware development

 Multimedia, Platform & Application Software development

 Board Design, Layout, SoC Validation, Platform Engg.

 Training - 4 Months Sponsored Training

 Salary Range – 2.4 to 3.6 Lakhs per annum

 Technology – Mobile/Wearable/Ultra Low power computing/ IOT products, SoC

reference platforms

Engineer Trainee (SW Testing)

 Main Technical Test

 Digital Design, Microprocessors, Microcontrollers, Interfaces - 30 Marks

Assembly Programming, Peripherals, System & Hardware design

 C Programming – 20 Marks

 Aptitude – 20 Marks

 Job Description – Testing & QA for applications, drivers, core software, platform
software and end products in embedded technologies.

 Training – 3 Months Training at VEDA/SoCtronics

 Salary Range – 1.85 to 2.4 Lakhs per annum

 Technology – Testing of Embedded products for Mobile, Wearables, IOT, Ultra low
power computing