CODE NO: 11498/CBCS

FACULTY OF ENGINEERING
BE V Semester (CBCS) (ECE) MAIN EXAMINATION, Nov/Dec 2018
Subject: Digital System Design with Verilog HDL
QUESTION PAPER KEY:
Prepared by M MOHAMMED SABIR HUSSAIN, ECED,MJCET.
PART – A (2x10=20 Marks)

1. Draw a typical design flow for designing VLSI IC circuits.

Ans:

2. Give the value set and nets supported by verilog.

Ans: Value sets

DSD using Verilog KEY 2018-19 V Sem

Nets: Nets are declared primarily with keyword “wire”

3. Write Verilog code for NAND gate in switch level modelling

module nand_s (out,a,b) pmos(out,a,vdd);
input a,b; pmos(out,b,vdd);
output out; nmos(c,a,out);
supply0 gnd; nmos(c,b,gnd);
supply1 vdd; endmodule
wire c;

4. What is meant by logic synthesis?

Ans:
Logic synthesis tools converts RTL description to gate level netlist.
5. Write Verilog code for T flip flop in behavioural modelling.
module tff(t,clk,rst,q,qbar); else
input t,clk,rst; case(t)
output reg q,qbar; 0: begin q=q; qbar=~q; end
always@(posedge clk) 1: begin q=~q; qbar=~q; end
begin
endcase
if(~rst)
begin q=0; end
qbar=~q; endmodule

end

6. Explain need of state minimization technique in FSM.

Ans : To reduce complexity of circuit, to reduce hardware requirement of circuit, To
improve performance of the circuit.
7. Explain hazards in combinational circuit with example
Ans: Two types of hazards 1.Static hazards, it classify into static 0 and static 1
hazards. 2. Dynamic Hzards
8. Differentiate between state table and flow table.
Ans: Flow table available with stability information of the states whereas in state table
consist only state information without stability information.

DSD using Verilog KEY 2018-19 V Sem

9. Describe types Semi- Customs ASICs.
Ans: Standard cell based ASICs , Gate array based ASICs and Programmable ASICs
10. Realize 1 bit full adder using PLA.
Ans: S= AxorBxorC = A’B’C+A’BC’+AB’C’+ABC =P0+P1+P2+P3
Carry = AB+BC+CA=P4+P5+P6

PART –B (5x10=50 Marks)

11. (a) What are the system task and compiler directives supported by verilog (4)
Ans: system task are $display, $monitor etc..and compiler directives are
`timescale,`define etc
(b) Write the program for full adder module using arithmetic operators and verify its

functionality using stimulus. (6)

Full adder programme in data flow modelling:

module fa(a,b,sum,cin,co);

input a,b,cin;

output sum,co;

assign bbar= !b;

assign abar = !a;
assign cinbar = !cin;

assign sum= a*bbar*Cinbar+ abar*bbar*Cin + a*b*Cin + abar*b*Cinbar;

assign co=a*b+b*c+c*a;

endmodule

Test bench:

fa fadder(a,b,cin,sum,co);
initial begin
{a,b,cin}=3’b000; #5 {a,b,cin}=3’b101; #5
{a,b,cin}=3’b100; #5 {a,b,cin}=3’b101;
#5 $finish; end

DSD using Verilog KEY 2018-19 V Sem

endmodule

12. (a) Explain initial and always block in verilog (5)

Ans:

A typical initial block as shown below.

always block:

Example:
always@(posedge clk)
if(rst)
q<=0;
else if(ud)
q<=q+1;
else
q<=q-1;

(b) Write a verilog code for BCD-to-7-segment decoder in behavioral modelling (5)
Ans: Verilog code for BCD-to-7-segment decoder

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 13.(a) Differentiate between mealy and moore FSM (2)
Ans: S(t) is PS ,S(t+1) is NS z(t) is output x(t) is input

(b) Design synchronous sequential circuit using one hot encoding method for the
State table shown in Table 1. (8)

Table 1

DSD using Verilog KEY 2018-19 V Sem

 Input (x)
Present state(y)
0 1
A B/0 C/1
B C/0 A/1
C B/1 B/0
Ans:
State assignment using one hot encoding
A= 001
B=010
C=100
D Flip flop Transition table:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table:
PS INPUT NS FF input OUTPUT
y3y1y0 X Y3 Y1Y0 D2 D1 D0 Z
001 0 010 0 1 0 0
001 1 100 1 0 0 1
010 0 100 1 0 0 0
010 1 001 0 0 1 1
100 0 010 0 1 0 1
100 1 010 0 1 0 0

Get logic equations for D2, D1,D0 and Z in terms of y3y1y0 and X using K map
simplification method and design the circuit...

Get logic equations using K map simplification method.

K map for J3 use 5 variable k map shown below, similarly obtain for remaining flip
flop
14. (a) Describe steps involved in a analysis procedure of asynchronous sequential

DSD using Verilog KEY 2018-19 V Sem

 circuit
Ans: (3)

(b) Design vending machine controller. Draw its ASM chart and implement verilog
program. (7)
Ans: Illustration example :

Block Diagram:

State digram:

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ASM chart:
Verilog Code:
15. Tabulate the PLA programming table for the four Boolean functions listed below.
Minimize the numbers of product terms, A(x, y, z) =∑m(1, 3, 5, 6),B(x, y, z) =∑m (0,
1, 6, 7), C(x, y, z) =∑m (3, 5) and D(x, y, z) =∑m (1, 2, 4, 5, 7)
Ans:

DSD using Verilog KEY 2018-19 V Sem

DSD using Verilog KEY 2018-19 V Sem
16. Minimize the state table shown in table 2 using partitioning method and design
sequential circuit using D flip flop for obtain minimize table.

DSD using Verilog KEY 2018-19 V Sem

 Table 2
Input (x)
Present sate (y)
0 1
A C/1 B/0
B C/1 E/0
C B/1 E/0
D D/0 B/1
E E/0 A/1

Ans: Partitioning method

Here B and C are equivalent, therefore C can be replace with B.

Input (x)
Present sate (y)
0 1
A B/1 B/0

DSD using Verilog KEY 2018-19 V Sem

 B B/1 E/0
D D/0 B/1
E E/0 A/1

Simplified table :A=A’ B=B’ D=C’ E=D’

Input (x)
Present sate (y)
0 1
A’ B’/1 B’/0
B’ B’/1 D’/0
C’ C’/0 B’/1
D’ D’/0 A’/1
Design sequential circuit using D Flip flop:
State assignment using one hot encoding
A’= 00
B=’01
C’=10
D’=11
D Flip flop Transition table:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation table:
PS INPUT NS FF input OUTPUT
y1y0 X Y1Y0 D1 D0 Z
00 0 01 0 1 1
00 1 01 0 1 0
01 0 01 0 1 1
01 1 11 1 1 0
10 0 10 1 0 0
10 1 01 0 1 1

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 11 0 11 1 1 0
11 1 00 0 0 1

Get logic equations for D1,D0 and Z in terms of y1y0 and X using K map
simplification method and design the circuit...

17. (a) Design arithmetic and logic unit (ALU) with minimum 8 instruction in verilog
and verify functionality using stimulus. Draw its waveforms. (5)

Test bench:
Waveforms:
(b) Explain simplified architectures of CPLD and FPGA (5)
CPLD:

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FPGA:

DSD using Verilog KEY 2018-19 V Sem