FPGA Implementation of a Pixel

Auto-configuration System for an

NDB-encoder Sensor
Nicolás Calarco∗1 , Federico Zacchigna†2 , Fabian Vargas‡3 , Ariel Lutenberg†¶4 ,
José Lipovetzky§¶5 and Fernando Perez Quintián∗¶6
∗ Facultad
de Ingenierı́a, Universidad Nacional del Comahue
Buenos Aires 1400, Neuquén Capital, Argentina
1
nicolas.calarco@fain.uncoma.edu.ar
6
fernando.perezq@fain.uncoma.edu.ar
† Facultadde Ingenierı́a, Universidad de Buenos Aires
Paseo Colón 850. Capital Federal, Argentina
2
fzacchigna@fi.uba.ar
4
lse@fi.uba.ar
‡ Catholic
University - PUCRS
Av. Ipiranga 6681, Porto Alegre, Brazil
3
vargas@computer.org
§ Comisión Nacional de Energı́a Atómica and Instituto Balseiro - Centro Atómico Bariloche
Av. Bustillo 9500, Bariloche, Rı́o Negro, Argentina
5
jose.lipovetzky@ieee.org
¶ Consejo Nacional de investigaciones Cientı́ficas y Técnicas - CONICET

Abstract—In previous works we introduced optical encoders
based on non-diffractive beams (NDB) and showed that they
extend the mechanical tolerance limits beyond the marks of
the optical encoders technologies currently in use. However,
in order to make it suitable for commercial fabrication,
the alignment of the light sensor with the NDB should be
automatized. In this work we present a new design for
the pixels and an algorithm implemented in an FPGA that
finds the center of the beam. This algorithm is the first
step to automatically align the sensor and is validated using
commercial simulation tools.
Resumen— En trabajos anteriores presentamos los
codificadores ópticos basados en haces no difractivos y
mostramos que extienden los lı́mites de tolerancia mecánica
más allá de las tecnologı́as de los codificadores ópticos
actuales. Sin embargo, con el fin de hacerlo adecuado para
fabricación comercial, la alinieación del sensor de luz con
el haz no difractivo debe ser automatizada. En este trabajo
presentamos un nuevo diseño de pixeles y un algoritmo que
encuentra el centro del haz, implementado en FPGA. Este
algoritmo es el primer paso para alinear automáticamente
el sensor y es validado usando herramientas de simulación
comerciales.
I. I NTRODUCTION
Optical encoders are displacement and rotation sensors
that are used in a broad variety of equipments and appli-
cations [1]. For example, they are used in domestic appli-
cations like home printers, in the automotive industry for
the measurement system, in industrial equipment’s motion
control and factory automation, in medicine for imaging
systems, or in high technology equipments such as radars or
robotics [2], [3]. Typically, optical encoders are composed
by a moving head and a fixed scale, such that the head
movement produces light intensity variations over a set
of photodetectors located at the head, which generates a
pair of electrical signals that codifies the movement [4]–
[6]. Non-diffractive beam (NDB) optical encoders (Fig. 1)
present a remarkable performance [7]–[9] by means of using
a special detection geometry with an ad-hoc detectivity
function, consisting of a set of concentric annular pixels
with a programmable gain [10]–[13], as it is shown in Fig.
1. The scale is a typical Ronchi grating used in standard
optical encoders. In order to work properly, the NDB has to
be centered with the photodetector. This is not a trivial issue,
because the beam size is just a few micrometers. In order to
automatize the alignment of the photodetector, we propose
a new sensor that it is able to execute an auto-alignment
algorithm. To reach this goal, the proposed sensor consists
of a photodetector array made of hexagonal configurable
pixels (see Fig. 1), that are driven by an IP-core. In this way,
once the beam impinges on the sensor, the system is able
to find the center of the beam and configure the detection
pattern around it.
FPGAs are increasingly being used in image sensor appli-
cations such as image processing, due to its reconfiguration
capability and the possibility of processing the information
in parallel hardware architectures. They provide a much
more flexible and faster design capabilities that a standard
processor. Some examples of this are the usage of FPGA for
object tracking [14], [15], target recognition [16], real time
stereo vision applications [17] or optical flow algorithms
[18]. However, all these applications work with information
provided by the sensor, but do not modify the internal
sensor configuration. Instead, we introduce a CMOS pixel
photodetector array that can be externally configured in
order to obtain a particular detection geometry and a detector
pattern associated. The FPGA is used to program the sensor
behavior and not just to process the information it provides.
In this work, we describe the specifications of the system
configuration and the implementation of the algorithm to
find the center of the beam. The paper is organized as
follows: in section II the proposed detector is introduced,
in section III the design to be implemented in the FPGA is
presented, which is described in detail in section IV. Finally,
in section V the conclusions are presented.
II. P HOTODETECTOR ARRAY PROPOSED DESIGN
The proposed photodetector is an array of hexagonal
pixels, similar to a honeycomb array. One of the major
advantages of hexagonal arrays is that all of the six first
neighbors are at the same distance. This, along with the sim-
ple fact that hexagons are “rounder” than squares, provides
a better representation of circularly symmetric images than
under square pixels. Each pixel of the array will be described
by coordinates x and y of two axis at an angle of 120◦ .
An illustrative diagram is shown in Fig. 2, together with a
representation of a particular detection pattern. The detection
pattern representation is as follows: The group of pixels that
have the same color must be interconnected (that is, they
must act as a monolithic detector) and the different colors
mean that a different gain factor is needed for each group
of pixels. With this technique the system is able to form
the desired detection pattern around the center of the beam,
as was mentioned in section I. For these purposes, each
pixel needs a configuration signal in order to know how to
connect to its neighbors and, eventually, to the amplification
system. The configuration signals are directed to every pixel
by parallel lines, one per row, as can also be seen in Fig. 2.
To achieve the interconnection, each pixel has three
switches that allows it to connect to three of its neighbors:
the West (W), the NorthEast (NE) and the SouthEast (SE)
switches, as it is shown in Fig. 3. In this way, each pixel can
be connected with any of its neighbors. To read the current
of each group of pixels, reading bitlines (BL) are disposed
in one row out of five, as it is shown in Fig. 4. In that row,
some pixels (those with a black point in Fig. 4) have the
chance to be connected to the bitline. Those pixels have an
extra register that drives the connection switch, named as
“Bitline Connection” in Fig. 3. In this way, one pixel out
of twenty-five (one pixel out of five from one row out of
five) has the possibility of being connected to a BL. It is
Fig. 1. Diagram of an NDB encoder, along with the desired detector
geometry and its implementation by using hexagonal pixels.
Fig. 2. Scheme of the proposed photodetector array, the honeycomb array,
with the representation of a particular detection pattern. The configuration
lines of the pixels can also be seen.
not necessary for our purpose to connect every pixel to a
bitline. Once the array is configured, each group of pixels
is connected to a bitline. The value of the current of this
group of pixels can be read trough the ADC by selecting
the appropriated entry of the MUX.
III. S EARCH ALGORITHM
There are several types of NDB [19], but the best perfor-
mance of the encoder is achieved with a zero order Bessel
NDB [9]. Fig. 5 shows the profile of the NDB that is used
in the experimental set up to validate the proposed design
[13]. It can be seen that the beam has circular symmetry,
and its center is much more brighter than any other part of
it. Thus our goal is to find the more illuminated pixel.
The algorithm used to find the brightest pixel is illustrated
in Fig. 6. Considering the disposition of the bit-lines, at the
beginning we can make a quick search to limit the zone of
interest: First, each bitline is connected to all the pixels in its
row and in the next four rows below it, collecting therefore
all the current in the horizontal stripe consisting of these
five rows. In the figure, the stripes are delimited by thick
borders and the points of connection to the bit-lines by pink
dots. The current from the bit-lines are then read one by one
and compared, and the information of the more illuminated
horizontal stripe is stored. This is called ”vertical search”,
because it gives us information about the vertical position of
the center of the beam. Then, a similar procedure is carried
out in the ”horizontal search” and the information of the
Fig. 3. Diagram of the pixel interconnection system and how it looks into
an array, with a bitline connection register.
 (a) (b)

Fig. 4. Diagram of the connections for the reading operation of the sensor.

(c) (d)
more illuminated vertical stripe is saved. At the end of this
procedure the zone of 5x5 pixels that contains the center of Fig. 6. Illustration of the first search. (a) Search of the horizontal
the beam is identified. It can be seen in the figure that the stripe more illuminated (Vertical Search). (b) Search of the vertical stripe
more illuminated (Horizontal Search). (c) Brighter zone. (d) Pixel more
current reading value of the stripe that contains the center illuminated. The numbers on the BL represent the reading values.
of the beam is bigger than the others.
The images shown in Fig. 6 are illustrative, in order to
show the process described above. The size of the pixels
logic in the SoC were simulated. How this simulation was
and the width of the stripes not represent the real ones. In
performed is explained in section IV-B.
order to show quantitative results, a more realistic simulation
was made. The results are showed in Fig. 7. The histogram The IP-core that configures the sensor has been developed
shows the sum of the currents of each stripe that is read by using VHDL and ISE software, the Xilinx synthesys tool
the corresponding bitline, in arbitrary units (AU). It can be for Xilinx FPGAs. A Xilinx Spartan 3E FPGA XC3S500E
seen that the current obtained from the stripe that contains model, has been used for the synthesis and implementation
the center of the beam is clearly higher than the others. of the IP-core. From the Xilinx ISE software reports, some
metrics related to the design, have been extracted. Regarding
After this ”brighter zone” is found, a pixel-by-pixel search
the timing parameters, the minimum period that can be used
is made. First just one pixel, the one that has connection
for the clock (maximum delay) is 9.084ns, which means
to the bit-line, is read and its value is stored. Then, the
that the implementation can work at a Maximum Frequency
contiguous pixel is connected and the value of the bit-line
of 110.084MHz. Although this frequency implies that the
is read again. The new reading, that corresponds to the
sensor can be configured very quickly, this is not the more
sum of the two connected pixels, is stored. Both values are
remarkable feature, because it is only performed during
subtracted in order to obtain the current of the last pixel. The
the sensor initialization, just once every time the sensor
coordinates and the reading value of the higher current pixel
is powered on. Table I shows other important parameters
are stored. This procedure is repeated with the 25 pixels of
involved in the use of the IP-core.
the area of interest, connecting one more pixel each time.
At the end of the process the value and coordinates of the As it can also be seen in the table, the occupation area
more illuminated pixel are known. of the IP-core is extremely low (2%), so that a bottleneck
of the design, if there is one, could reside in the number
IV. I MPLEMENTATION
A. Architecture
Fig. 8(a) shows a diagram of a System on Chip (SoC) im-
plementation: the light sensor plus de IP-core. In this work
the IP-core was implemented in an FPGA to be interfaced to
the photodector array. The proposed architecture is shown in
8(b). The pixels array and the ADC as well as the remaining

(a) (b)
Fig. 7. Histogram that shows the sum of the currents over the stripes
Fig. 5. Representation of the NDB used. (a) Profile. (b) Bidimensional formed in the horizontal and vertical search when the NDB impinges the
representation. Units in microns. photodetector array.
 Fig. 9. Data exchange interface between C emulated sensor and VHDL
IP-core.

program and the IP-core. The data exchange between VHDL

and the C code is performed through two pipes, named “from
C to VHDL” and “from VHDL to C”. This is represented in
(a) Fig. 9.
The VHDL module writes the data in the “from VHDL to
C” pipe, which is read by the C program and used as input
for the sensor emulator. After the sensed value is calculated,
the C program writes the response in the “from C to VHDL”
pipe, which is then read by the VHDL module. Every time,
new configuration data is sent to the sensor, this process is
repeated and a new sensed value is obtained.
The testbench emulates an N by N photodetector array,
which is represented by a matrix array of the same size.
Each value represents the amount of light impinging on
the corresponding pixel. Pixels are arranged as explained
in section II and a scheme of how it is emulated for the
simulations is shown in Fig. 10.

(b)
Fig. 8. Diagrams of the architecture of the design. (a) IP-core SoC
implementation (b) Hardware implementation aimed for this work.
of IOs needed, that depends on the size of the sensor (i.e.
the number of needed bitlines). This issue can be sorted out
by using a Serial-Parallel interface, what would increment
the execution time of the algorithm. However, this would
not be a problem, because it will only be executed once
at the beginning, as a starting routine. The low area occu-
pation also make the design particularly suitable for SoC
implementations. The best solution is a trade off between
occupation area and performance.
B. Testbench
A C program that emulates the photodetector array be-
havior was written, with the purpose of being used during
the IP-core testbenching. Also, a VHDL module has been
developed to represent the sensor, and interfaces with the
C. Simulations
Simulations were made using ISIM, the simulation tool
of the ISE software package [20]. The search algorithm
was emulated by using different sensor values and con-
figurations. As it was explained in section III, after this
initialization process, the center of the beam is found and
the more illuminated pixel is identified. Fig. 11 shows the
state of some relevant variables at the end of the search for
an arbitrary array representation. The internal variables br x
and br y, marked in red, indicates the x and y coordinates
of the brighter pixel in the pixel array. This information
remains available for the final configuration of the chip. The
state register status indicates that the system is ready for the
next stage, called sensor mode (sm, blue mark in Fig. 11)
For the evaluation of the system functionality, many con-
figurations of light intensities distributions were analyzed.
Fig. 12 illustrates the more relevant cases. Figs. 12(a)
and 12(b) show the case of a distribution that represent
a non-diffractive beam (NDB) centered an non centered,

TABLE I
D EVICE UTILIZATION SUMMARY

Selected Device : 3s500efg320-4 Occupation

Number of Slices: 142 out of 4656 3%
Number of Slice Flip Flops: 96 out of 9312 1%
Number of 4 input LUTs: 260 out of 9312 2%
Number of IOs: 29
Number of bonded IOBs: 29 out of 232 12%
Fig. 10. Scheme of the array used to represent the values read from the
Number of GCLKs: 1 out of 24 4% pixels in the simulations

Fig. 11. Illustration of the results of the simulations for an arbitrary array.
The coordinates of the more illuminated pixel at the end of the simulation
process are remarked in red.
respectively. The case of the representation of an NDB with
noise is shown in Fig. 12(c), and Fig. 12(d) shows the
case of a random noise. The hexagonal arrays shown in
Fig. 12 correspond to the region of interest of the detector.
The region covers an area of approximately 260µm by
260µm, discretized in 7µm side hexagonal pixels. The NDB
representations are correspondent with the beams used in
[13].
In cases in which a strong NDB is impinging over the
sensor (Figs. 12(a) and 12(b)) the algorithm yields the right
position coordinates, regardless the location of the center of
the beam. Fig. 12(c) shows the case of a weak NDB plus
environmental noise. Despite the fact that the noise is of
the same intensity level than the NDB rings, the system
accurately retrieves the coordinates of the center. These
results indicate that the system is adequate for our purpose.
Finally, for arrays representing random distributions of light,
such as the shown in Fig. 12(d), the algorithm yields
wrong results. This is because regardless the location of
the more illuminated pixel, the algorithm first found the
(a) (b)
(c) (d)
Fig. 12. Simulated illumination representations. (a) A centered NDB. (b)
A non centered NDB. (c) An NDB with noise. (d) A random distribution.
The bars at the right side of the image are the colormaps of light intensities.
more illuminated zone of 5 by 5 pixels, as was discussed
in section III. However, this extreme simulated case of a
random distribution of light is not expected for a properly
designed optical encoder based on an NDB.
V. C ONCLUSIONS
In this work a new approach of pixel design with an auto-
configuration system has been presented.
The system that auto-configures the hexagonal pixel array
accordingly to the position of the NDB center was imple-
mented by means of a new algorithm and synthesized by
using an FPGA. For the prototype validation, a C program
was written to represent the sensor behavior. These two
achievements endow the hexagonal photodotector array with
the auto-configuration abilities that it was necessary to reach
for the functionality of the NDB encoder.
In the other hand, the IP-core generated has a good
performance in terms of stability, reliability and operation
frequency, and accomplish perfectly with the requirements
of the system. Its main advantages compared to existing
approaches found in the literature is the extremely low area
overhead, that make it specially convenient for implementa-
tions in either commercial low cost FPGA or SoC designs.
Future works will include the full implementation of the
design, including the final configuration of the sensor for
the operation mode, the physical implementation of the pixel
array (now in process) and the external circuitry for the gain
system.
ACKNOWLEDGMENT
The authors want to thank to Consejo Nacional de Inves-
tigaciones Cientı́ficas y Técnicas CONICET. This work has
been done in the context of research project ANPCyT PICT
2013-0951 and the Programa de Centros Asociados para el
Fortalecimiento de Posgrados Brasil/Argentina (CAFP-BA).
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