Homework Assignment 12

Question 1 Provide a schematic that shown how to use an analog multiplier, one or more op-amps and
resistors to divide two signals: ⁄ . What will happen to the circuit when ? (10 points)

Solution

The voltage at is and KCL at the inverting input gives

Further, and the solution to the KCL equation is

⁄ . If the output will saturate at either of
the power supply rails or the circuit may oscillate.

Question 2 (PLLs) It is sometimes desirable to use an XOR-type PD (which requires 50% duty-cycle
inputs) with signals that are not 50% duty cycle. Provide a simple work-around this problem. Assume
you have a selection of standard logic gates (AND, NOR, XOR, dividers, etc.) available. (4 points)

Solution A simple solution is to divide pass the input signal through a binary divider (÷2), which one can
easily construct is a variety of ways. For example, by feeding the output of D flip-flop back to the input,
one can make a T (toggle) flip-flop or a binary divider. The T flip-flop responds to the input’s lowhigh
transitions, and the output is 50% duty cycle, see (a) of the figure below. One would of course divide the
output from the VCO also by 2 to make sure the inputs to the PD are at the same frequency, see (b)
below.

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Question 3 (PLLs) Consider the linear model for a locked PLL below. Derive an expression for the open
loop gain and be sure to supply the units. Then, derive an expression for the closed loop gain
⁄ . Finally, show that ⁄ . (20 points)

Solution

Break the loop after the VCO (i.e., at the inverting input of the PD), the over all gain experienced by
in going around the loop and emerging as is ⁄ . Thus

is the desired open-loop gain in radian per radian, and is the gain factor in . With the loop
closed

Referring back to the block diagram, ⁄ , and ⁄ gives

⁄
⁄

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Question 4 In a first-order PLL with Kv =104 s-1 uses a VCO with free-running f0 = 10 kHz and
sensitivity of 5 kHz/V (a) What control voltage is needed to lock the PLL to on a 20 kHz signal? (b)
Find ve(t) if the input frequency is (10 + u(t)) kHz where u(t) is the unit step function.

Solution

(a) The control voltage must shift the VCO from 10 kHz to 20 kHz. In other words, it must shift it by
10 kHz. With ⁄ , it follows a control voltage of 2 V is required.
(b) The input frequency changes by 1 kHz, which means that after the circuit transient dies away, the
control voltage will be ⁄ . The time constant of the first order loop is ⁄ , so
that

( )

Question 5 Consider the PLL shown where and ⁄ .

(a) What is the order of the loop? (1 point)

1st order

(b) What is the time constant of the loop? (1 point)

(c) What is the 3-dB bandwidth of the loop in Hz? (1 point)

(d) If the input frequency changes with a step, what is the rise time of the VCO control voltage assuming
the loop stays in lock? (1 point)

(e) Write down an expression for the transfer function ⁄ . (2 points)

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(f) Write down an expression for the transfer function ⁄ (3 points)

(g) Write down the units for the transfer function ⁄ (1 point)

V/(rad/s) or V s

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Question 6 Draw a block diagram showing how one would use a PLL to synthesize a 10 MHz
frequency from a very stable 1 MHz reference. (4 points)

Simply insert a block after the VCO

Question 7 What is FSK and where would one use it? (2 points)

Answer: FSK is an abbreviation for Frequency-Shift Keying and it is a method for sending
digital data. Logic 1s are sent as one frequency and logic zeros are sent as another. FSK is
analogous to FM and is useful to combat noise in data transmission.

Question 8 A second-order PLL has the following

⁄ ⁄ ⁄ ⁄

Make a sketch of the change in VCO control voltage when the input frequency changes abruptly by
1 kHz. Provide as much details as you can, but you are NOT expected to perform lengthy calculations.
(4 points)

Step Response
1.5

1
Amplitude (V)

0.5 This frequency Step size = 1 V

is

0
0 1 2 3 4 5
Time (seconds) -3
x 10

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Question 9 You are to design a PLL-based frequency synthesizer, using a high-quality,
temperature-compensated oscillator as a reference. You have a choice of PDs: Type I, Type II,
Type III, etc. Which of the PDs will you use? Explain your answer in detail. (4 points)

Solution One would use the Type II (charge-pump) PD for the following reasons. It has a larger
phase detector conversion constant which increases the loop gain. PLLs with Type II PDs
have a large lock range, and such PLLs can make large jumps from one frequency to another and
the large loop gain will reduce the settling time. By contrast, Type I (XOR) PDs have limited
lock range. Further, even in lock, Type I PDs produce output which the loop filter smoothes out,
but there is always residual ripple at the VCO control voltage. Consequently, the output of the
VCO will have modulation sidebands. On the other hand, when the loop is in lock the Type II
PD output is tristate, there is no output, and the VCO control voltage is a clean dc voltage. Thus,
the VCO output is much cleaner than the Type I PD.

Question 10 You are to design a PLL-based FSK demodulator. The SNR of the signal is high.
You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you use?
Explain your answer in detail. (4 points)

Solution One would use the Type II (charge-pump) PD for the following reasons. It has a larger
phase detector conversion constant which increases the loop gain. PLLs with Type II PDs
have a large lock range, and such PLLs can make large jumps from one frequency to another and
the large loop gain will reduce the settling time. This will allow one to have higher FSK data
rates. Type II PDs have lower noise immunity compared to Type I PDs, but that it not important
in this instance, since the SNR is high.

Question 11 (PLLs) You are to design a PLL-based FM demodulator. The input is low-quality
(small SNR) audio. You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs
will you use? Explain your answer in detail. (4 points)

Solution Type I PDs have better noise rejection performance which suggests using a Type I PD
for this application. The Type I PD has a smaller capture range than the Type II PD. However,
in this instance this is most likely not a consideration, since one probably knows the FM
frequency precisely and one can set the VCO center frequency accordingly.

Question 12 You are to design a PLL-based detector for demodulating telemetry data that are
FSK-encoded. The data come from a transmitter on a spacecraft and the SNR is low. You have
a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you use? Explain your
answer in detail. (4 points)

Solution This calls for a Type I (XOR) PD since it is less sensitive to noise than the Type II
PD. The Type I PD has a smaller capture range than the Type II PD. However, in this instance
this is most likely not a consideration, since one probably knows the FSK frequencies precisely
and one can set the VCO center frequency accordingly.

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Question 13 You are to design a PLL-based circuit that lock onto the 60-Hz mains frequency.
You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you use?
Explain your answer in detail. (4 points)

Solution Large mechanical generators generate the mains power. These generators have large
inertia and cannot change their rotational speed quickly. Thus, while the 60-Hz main frequency
drifts, it drifts slowly. However, the mains line can be quite noisy, considering transients that
household appliances can generate. Thus, a PLL that locks on to the mains frequency should be
narrowband and noise resistant. This implies the Type I (XOR) PD, which is more resistant to
noise than the Type II PD. The Type I PD has a smaller capture range, but in this instance that
does not matter.

Question 14 Complete the following table. (10 points)

Type I PD Type II PD

Mechanism XOR or Multiplier Charge Pump

No input signal VCO adjusts to center VCO adjusts to minimum frequency

frequency

Phase difference between PD inputs Always zero

when loop is locked

PLL can lock onto harmonics of free- Yes No

running frequency?

Rejection of input signal noise High Low

Lock and capture ranges Identical