Homework Assignment 07

Question 1 (PLLs) It is sometimes desirable to use an XOR-type PD (which requires 50% duty-
cycle inputs) with signals that are not 50% duty cycle. Provide a simple work-around this
problem. Assume you have a selection of standard logic gates (AND, NOR, XOR, dividers, etc.)
available. (4 points)

Solution A simple solution is to divide pass the input signal through a binary divider (÷2),
which one can easily construct is a variety of ways. For example, by feeding the output of D
flip-flop back to the input, one can make a T (toggle) flip-flop or a binary divider. The T flip-
flop responds to the input’s lowhigh transitions, and the output is 50% duty cycle, see (a) of
the figure below. One would of course divide the output from the VCO also by 2 to make sure
the inputs to the PD are at the same frequency, see (b) below.

Question 2 (PLLs) You are to design a PLL-based frequency synthesizer, using a high-quality,
temperature-compensated oscillator as a reference. You have a choice of PDs: Type I, Type II,
Type III, etc. Which of the PDs will you use? Explain your answer in detail. (4 points)

Solution One would use the Type II (charge-pump) PD for the following reasons. It has a larger
phase detector conversion constant which increases the loop gain. PLLs with Type II PDs
have a large lock range, and such PLLs can make large jumps from one frequency to another and
the large loop gain will reduce the settling time. By contrast, Type I (XOR) PDs have limited
lock range. Further, even in lock, Type I PDs produce output which the loop filter smoothes out,
but there is always residual ripple at the VCO control voltage. Consequently, the output of the
VCO will have modulation sidebands. On the other hand, when the loop is in lock the Type II
PD output is tristate, there is no output, and the VCO control voltage is a clean dc voltage. Thus,
the VCO output is much cleaner than the Type I PD.

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Question 3 (PLLs) You are to design a PLL-based FSK demodulator. The SNR of the signal is
high. You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you use?
Explain your answer in detail. (4 points)

Solution One would use the Type II (charge-pump) PD for the following reasons. It has a larger
phase detector conversion constant which increases the loop gain. PLLs with Type II PDs
have a large lock range, and such PLLs can make large jumps from one frequency to another and
the large loop gain will reduce the settling time. This will allow one to have higher FSK data
rates. Type II PDs have lower noise immunity compared to Type I PDs, but that it not important
in this instance, since the SNR is high.

Question 4 (PLLs) You are to design a PLL-based FM demodulator. The input is low-quality
(small SNR) audio. You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs
will you use? Explain your answer in detail. (4 points)

Solution Type I PDs have better noise rejection performance which suggests using a Type I PD
for this application. The Type I PD has a smaller capture range than the Type II PD. However,
in this instance this is most likely not a consideration, since one probably knows the FM
frequency precisely and one can set the VCO center frequency accordingly.

Question 5 (PLLs) You are to design a PLL-based detector for demodulating telemetry data that
are FSK-encoded. The data come from a transmitter on a spacecraft and the SNR is low. You
have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you use? Explain
your answer in detail. (4 points)

Solution This calls for a Type I (XOR) PD since it is less sensitive to noise than the Type II
PD. The Type I PD has a smaller capture range than the Type II PD. However, in this instance
this is most likely not a consideration, since one probably knows the FSK frequencies precisely
and one can set the VCO center frequency accordingly.

Question 6 (PLLs) You are to design a PLL-based circuit that lock onto the 60-Hz mains
frequency. You have a choice of PDs: Type I, Type II, Type III, etc. Which of the PDs will you
use? Explain your answer in detail. (4 points)

Solution Large mechanical generators generate the mains power. These generators have large
inertia and cannot change their rotational speed quickly. Thus, while the 60-Hz main frequency
drifts, it drifts slowly. However, the mains line can be quite noisy, considering transients that
household appliances can generate. Thus, a PLL that locks on to the mains frequency should be
narrowband and noise resistant. This implies the Type I (XOR) PD, which is more resistant to
noise than the Type II PD. The Type I PD has a smaller capture range, but in this instance that
does not matter.

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Question 7 (PLLs) The 4046 PLL has a long history, has gone through a number of
improvements, and many manufacturers produce the chip. In the course, we use the CD4046B
version. “CD” implies CMOS, and the “B” means the B-series, which has 2, rather than 3 phase
comparators. Two resistors and a timing capacitor determine the VCO center frequency. The
4046 data sheets typically contain graphs and some guidelines on how to pick the resistors and
capacitor. Unfortunately, the VCO frequency is a function of the supply voltage. Further, the
quality of the graphs that some manufacturers supply, are of poor quality. Consequently, setting
the VCO frequency is perhaps not as straightforward as it could be. Given the nature of a PLL
and its applications, in many cases, setting the center VCO frequency extremely precisely is not
required.

Use the CD4046B datasheet, and determine the VCO center frequency for the combinations
listed in the table, where , and are the VCO timing resistor and capacitor. Assume that
. Note that the center frequency is when the VCO control voltage is
.

Hint: search for a CD4046B equivalent data sheet that has high-quality plots, for example,
NXP’s HEF4046B PLL. (9 points)

Center Frequency
10K 1 nF 125 kHz
10K 10 nF 15 kHz
100K 470 pF 38 kHz
100K 1 nF 18 kHz
100K 10K 10 nF 24 kHz
100K 100 K 10 nF 5.5 kHz
100K 1M 10 nF 2.5 kHz
100K 10 nF 2.2 kHz
100 K 100 nF 200 Hz

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Question 8 (PLLs) Rather than using the low-quality graphs in the CD4046B data sheet, it may
be more convenient to have a formula such as

Using the data from the table you completed in the previous problem, determine such a formula.
You may want to pick convenient units for the “inputs” to you formula. For example, assume
the resistor values will be in and capacitor values in nF. The following figure may be useful.
(10 points)

Solution One can follow several approaches. One is to perform a least-squares fit of the model
( ⁄( ) ⁄( )) to the data, using Matlab, Excel, or other software. Another
approach is the following. For we have , where
resistor values are in , the capacitor value is in nF, and the frequency is in kHz. With
, we have ⁄( ) and one can solve for . One can repeat this process for
other combinations of while and then determine an average so that

Next, determine an average from the three cases where . This gives , so
the final formula is

The values of and will depend on the values in the table from the previous problem. The
table below compares measured with model frequencies.

(kHz) 125 15 38 18 24 5.5 2.5 2.2 0.2

(kHz) 176 17.6 37.5 17.6 29.8 4.6 2.0 1.8 0.2

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Question 9 (PLLs) Complete the following table. (10 points)

Type I PD Type II PD

Mechanism XOR or Multiplier Charge Pump

No input signal VCO adjusts to center VCO adjusts to minimum frequency

frequency

Phase difference between PD inputs Always zero

when loop is locked

PLL can lock onto harmonics of free- Yes No

running frequency?

Rejection of input signal noise High Low

Lock ( ) and capture ranges ( ) Identical

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Question 10 (PLLs) The input voltage to a PLL is a sine wave of frequency that starts at
. At the frequency jumps to and then decreases exponentially back to
with a time constant of 1 ms.

(a) Make plot that shows the instantaneous input frequency versus time. (2 points)
(b) Write an expression for the instantaneous frequency ( ). (4 points)
(c) Write an expression for the Laplace transform of ( ) (8 points)
(d) Write an expression for the PLL control voltage ( ) assuming that the loop filter is a first-
order LPF with a 2 ms time constant and the loop is locked. (16 points)
(e) Explain, using the result from (d), how to solve for the control voltage ( ) (2 points)

Solution

Part (a)

𝜔𝐹𝑅 Δω

𝜔𝐹𝑅

t (s)
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Part (b)

Translating from the English description of the input signal to a mathematical description gives

( )
( ) ( ) ( )( ) ( ) ( )( )

where ( ) is the unit step function.

Part (c) Consulting a table of Laplace transforms, we find the following Laplace transform pairs

( )

( )
( )

Appling these transforms give

( )
( ) ( )( )

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Part (d) The loop filter’s transfer function is ( ) ⁄( ), and for a PLL

( ) ( )
( ) ( )

Thus

( ) ( )
( ) ( ) [ ]
( ) ( )
⁄( )
[ ]
⁄( )

[ ]
( )

Part (e) To obtain the time response ( ) one would take the inverse Laplace transform.

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Question 11 (PLLs) The PLL below has idealized components and ( )
⁄ and ⁄ .

(a) What is the numerical value of the loop gain? Be sure to supply the units. (2 points)
(b) Write an expression for and then sketch the impulse response of the loop when the output
variable is frequency. (10 points)
(c) Write an expression for and then sketch the impulse response of the loop when the output
variable is voltage. (10 points)

Solution

Part (a) The loop gain is ( )( )

Part (b) The transfer function ( ) ( )⁄ ( ) is

( )
( )
( )

Since ⁄ and ⁄ (see PLL block diagram above), it follows that ( )

( )⁄ ( ) ( )⁄ ( ). The Laplace transform for an impulse is 1, so that

( )
( ) ( )
( )

The inverse Laplace transform is

( ) ( ) ( )

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Question 12 (PLLs) The PLL below has idealized components and ( )
⁄ and ⁄ .

Find ( ) if the loop is in lock at the free-running frequency, and the input frequency is given
by

( ) ( )

where ( ) is the unit step function and is the deviation from the free-running frequency.
(20 points)

Solution

The transfer function ( )⁄ ( ) ( ) ( )⁄( ( )), and

( ) ( )
( )
( ) ( )

Substituting the values provided gives

( )
( )

Consulting a table of Laplace transforms show that

( )

Thus

( ) [ ][ ]

Using partial-fraction expansion techniques, we find

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 |

and

Thus

( ) ( )( )[ ]

Taking the inverse Laplace transform gives

( ) [ ]

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