84 / Hardwired Contol 379
requires excessive work to obtain the simplified input equations for the flip-flops.
Here, the design can be simplified if we take into consideration the fact that the
decoder outputs are available for use in the design. Instead of using flip-flop out-
puts as the present state conditions, we might as well use the outputs of the
decoder to obiain this information. These outputs supply a single signal repre
senting each of the possible present states of the circuit. Moreover, instead of
using maps to simplify the fip-flop equations, we can obtain them directly by
inspection of the state table. For example, from the next-state conditions in the
table, we find that the next state of My is equal to 1 when the present state is
IDLE and input G is equal to 1 or when the present state is MULI and input Z is
‘equal to 0. These conditions give
Dy, =IDLE-G+MULI-Z
for the D input of the Mo flip-flop. Similarly the D input of the M,; flip-flop is
Dy, = MULO
Note that these equations derived by inspection from the state table use the state
‘names rather than the state variable names, since the decoder producing the state
symbols is present. In some cases, it may be possible to find simpler D flip-flop
input equations by using the state variables directly instead of the states. We can
remove redundancy and reduce cost by writing the Boolean equations for the
decoder and applying a simplification program to the set of control equations.
‘The logic diagram for the control appears in Figure 8-10. It consists of a two-
bit register with flip-flops M, and My and a 2-to-4-line decoder. The three outputs
De te
ye ctenes
DECODER
tag MULO
sau Shif_dec
am
«|!
bp
| c
o Dees
eck
FIGURE 8-10
Control Unit for Binary Multiplier Using « Sequence Register and a Decoder380 C1 CHAPTER § / SEQUENCING AND CONTROL,
of the decoder are used to generate the control outputs, as well as inputs 10 the
extstate logic. ‘The outputs Initialize, Clear_C, Shift_dec, and Load are deter.
tmined from Table 8-1, Initialize and Shift_dec are already available as signals, so.
that only labeled output lines are added. However, as shown in the figure, we must
‘add logie gates for Clear_C and Load. We complete the binary multiplier design by
connecting the outputs of the control unit to the control inputs of the datapath.
‘One Flip-Flop per State
Another possible method of control logic design is the use of ane flip-flop per state.
A Tlip-flop is assigned to each of the states, and at any time, only one of the flip
flops contains a 1, with all the rest containing 0. When the | is in the flip-flop
assigned (0 a particular state, the sequential circuit is in that same state, The single
1 propagates from one flip-op to another under the control of decision logic. 1
such a configuration, each flip-flop represents a state that is present only when the
single 1 is stored in the flip-flop.
It is obvious that, short of some error detection or correction techniques, this
method uses the maximum number of flip-flops for the sequential circuit. For
example, @ sequential circuit with 12 states using minimum variable encoding
needs four flip-flops. With one flip-flop per state, the circuit requires 12 flip-flops,
one for each state. At first glance, it may seem that this method would increase the
cost of the system, since more flip-flops are used, Bt the method offers some cost
advantages that may not be apparent. One advantage is the simplicity with wich
the logic can be designed—merely by inspection of the ASM chart or state dia
gram, No state or excitation tables are needed if D flip-flops are employed, This
offers a savings in design effort.
Figure 8-11 shows the symbol replacement rules for transforming an ASM
chart into a sequential circuit with one flip-flop per state. These rules are most
easily applied to an ASM chart representing only Sequencing information, such as
that of Figure 8-9, Each rule specifies the replacement of a component of an ASM
chart with a logic circuit. As shown in Figure 8-11(a), the state box is replaced by
4D flip-top labeled with the name of the state. The entry to the state box corres-
Ponds to the D input to the flip-flop. The exit of the state box corresponds to the
output of the Mlip-lop.
In Figure 8-11(b), the scalar decision box is replaced by a 2-way demult
plexer. The signal corresponding to the entry to the decision bos is sent to one of
‘Wo exit lines, depending on the value of signal X. If X is 0, the signal is sent to the
exit 0 line: if X is 1, the signal is sent to the exit I line. So, for example, if the single
1 in the circuit is on the entry to the decision box and X is O, the 1 Is passed to the
exit ( line. The demultiplexer acis like a switch that dizeets the I through the paths
in the circuit corresponding to paths in the ASM chart.
In Figure 8-11(c), the vector decision box is replaced by an n-way domulti
plexer. The signal corresponding to the entry to the decision box is sent to one of the
2"—1 lines, depending on the Value of the signal vector X'= Xj... Xy-1- EX Bs 0, the
signal is sent to the exit 0 line; if X is 9, the signal is sent to the exit 9 line, So, for
‘example, if the single 1 in the circuit is on the entry to the decision bos, and X is 9,S-4 / Hardwired Conzol 381
rey
| Enuy
suse oe
Lb
bes
] a
ea (a) State box
Eaey Entry
1 psa
Eee |
ei 1 x Ae dD ]
{ |
whe a saa
(sere Bot
ey Entry
ree
Bit
(6) Yetor Devision Box
Entry 1 Batry? try 1 Entry?
Exit
4) Junction Esit
Entry ®
Entry
)
1 Y
Exit Control
Ext
(¢} Conditional Ouipat Box
CO FIGURE 8-11
“Transformation Rules for Control Unit with One Flip-Flop per State