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Abstract—This paper presents a means to overcome the high
sensitivity of continuous-time sigma–delta ( ) modulators to
clock jitter by using a modified switched-capacitor structure with
resistive element in the continuous-time feedback digital–analog
converter (DAC). The reduced sensitivity to jitter is both sim-
ulated and proven by measured results from two implemented
third-order modulators. Additionally, the nonideal behavior is
analyzed analytically and by simulations.
Fig. 1. Relevant forms of clock jitter.
61
Index Terms—Clock jitter, continuous time (CT), switched-ca-
pacitor resistor (SCR) feedback, sigma–delta ( ) modulator.
This paper is organized as follows. In Section II, the vari-
ations of the system clock by jitter will be reviewed and the
I. INTRODUCTION jitter error sources in typical DT and CT modulators are
analyzed. In Section IV the SCR technique is introduced and
C ONTINUOUS-TIME (CT) modulators have received in-
creasing attention over the last years due to some mean-
ingful advantages over their discrete-time (DT) counterparts [1]
the modulator scaling procedure is exemplarily performed by a
DT-to-CT conversion. In Section IV-D, simulation results prove
the feasibility of the SCR concept and in Section V, the nonideal
and [2]: e.g., speed advantages, an implicit anti aliasing filter
behavior is analyzed. Section VI presents experimental results
and no front-end sample and hold (S/H).
and Section VII gives a conclusion and an outlook.
On the other hand, CT modulators are harder to design and
suffer more from several nonidealities of the integrated building
II. CLOCK JITTER
blocks of CT filters [2]–[7]. One of the most critical nonideal-
ities is clock jitter. In a CT sigma–delta ( ) modulator, the In Fig. 1, a typical two-phase clock is given. Here, the clock
digital–analog converter (DAC) in the feedback path shapes the interval limits should be ideally multiples of the sampling
signal into a given pattern; typically return to zero (RZ) or non- time of the modulator. In a pulse series as in Fig. 1 every
return to zero (NRZ) have been used and implemented. Clock pulse edge may be jittered, having different influences on the
jitter varies this feedback signal with regard to the pulse delay as performance of a modulator. Therefore, we have to consider
well as to the pulsewidth. Reference [7] showed that a variation
of the pulsewidth is by far the worst of all other timing effects, Pulse-Delay Jitter
heavily degrading the performance of the CT modulator at or- Pulsewidth Jitter
ders of clock jitter magnitudes lower than in the DT case [5]. Sampling Jitter (1)
Recently, a technique has been introduced, where a sloping
pulse form is chosen in a CT modulator to reduce the sensitivity Jittered position or width of the clock pulse and are
to clock jitter [6], [8]. Therefore, the feedback DAC of the CT only important in a CT implementation, where the exact pulse
modulator is realized by a capacitor which is discharged form is shaped in the feedback DAC [7].
through an additional resistor . This switched-capacitor re- Jittered sampling instants cause a nonuniformly sampled
sistor (SCR) feedback configuration is useful threefold: first, it signal, but which will be processed further in the digital part as
allows an exact definition of the temporal shape of the feedback being acquired at the average sampling rate and will there-
waveform, which is necessary in the case of a CT integration fore influence the performance of the DT as well as the CT mod-
over time. Second, the time constant of the pulse ulator.
defines the jitter sensitivity. Finally, the speed requirements of Concerning the sampling jitter, note that two forms of jitter
the integrators can be relaxed due to the limitation of the feed- have to be considered: the independent, white clock jitter and
back current by . additionally the accumulated, VCO clock jitter [9]. In the first
case, the deviation of the sampling instants from periodic in-
stants are independent random variables, while in the second
Manuscript received October 14, 2002; revised November 18, 2004. This
paper was recommended by Associate Editor G. Cauwenberghs. case, the sampling intervals are independent random variables,
M. Ortmanns is with sci-worx GmbH, Hannover 30419, Germany (e-mail: but the jitter of the sampling instants is accumulated [4]. The in-
maurits.ortmanns@sci-worx.com). fluence of both jitter forms on CT and DT modulators can
F. Gerfers is with Philips Semiconductors, Starnberg 82319, Germany.
Y. Manoli is with the Albert Ludwigs University, Freiburg 79110, Germany. be different [10]. It extends the scope of this paper to examine
Digital Object Identifier 10.1109/TCSI.2005.846227 both clock jitter forms in detail, thus throughout the following
1057-7122/$20.00 © 2005 IEEE
876 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005
TABLE I
CT EQUIVALENCES FOR DT LOOP FILTER POLES WITH SCR FEEDBACK
which is a mathematical operation much more common than the C. Synthesis Example of a Third-Order LP Modulator
modified -transformation. With SCR Feedback
Beside this DT-to-CT conversion based CT modulator Exemplarily, a third-order LP modulator is synthesized. As
design, also the direct synthesis currently becomes popular [15], a starting point a DT loop filter has to be chosen. In [13], an
and the presented SCR feedback DAC could also be readily “optimal” third-order modulator with common feedback archi-
adopted in these methods. tecture has been found being composed of 3 DT integrators
with an integrator scaling
B. Time-Invariant Transformation With SCR Feedback and unity feedback. The loop filter corre-
In Fig. 5, a DT-to-CT equivalence is achieved, if the inputs sponding to this architecture yields
to both quantizers and are the same at the sampling
instants [3]. This translates directly into the condition for the
loop filter impulse responses (12)
(10) (13)
with as the impulse response of the specific DAC. This A comparison of the coefficients of the desired CT loop filter
has been a rectangular feedback pulse form in [3] but has to be and the filter implemented in (13) results in the CT
modified for the SCR realization integrator scaling coefficients for a third-order modulator
as in Fig. 3, but with the SCR feedback DAC. Note that
for fast feedback pulses, i.e., , the exponential terms
(11) can be neglected (since ). For
otherwise
the given third-order DT modulator, an equivalent CT SCR
with corresponding to a decaying RC pulse modulator scaling yields
form with a time constant , a maximum pulse magnitude of 1
at the starting point and a duration of .
In Table I, similar to [3], the -domain equivalences for
simple -domain loop-filter poles up to the third order are
given. Due to reasons of clarity of the presentation only low
pass usable poles (at dc) are given, but an extension to general
DT poles can be performed easily following the condition in
(10). The calculations were done using the symbolic math
program MAPLE. (14)
ORTMANNS et al.: CONTINUOUS-TIME MODULATOR 879
(15)
(16)
61
Fig. 8. Simulated IBN of CT modulators with SCR under the influence of
Fig. 7. Simulated IBN of different third-order modulators under clock jitter
010 = OSR = 48
integrator gain variations. ;P = 09 23
= dB and f = 5
f = .
influence, at dB and f f = 0 07
: T . Original and downscaled version.
Fig. 9. Output of a finite GBW integrator upon an SCR-pulse. Fig. 10. Relative increase of the time constant due to finite GBW.
(20)
In the case of the SCR feedback, the influence of finite GBW has
to be examined more carefully, because the pulse is designed to
be fast, so that the integrator may not be able to follow. This
is shown in Fig. 9, where the output of an integrator is simu-
Fig. 11. Circuit level simulated IBN of CT 61 modulators with NRZ, SCR,
lated on circuit level upon an SCR pulse derived from a circuit
and SCR-V feedback under the influence of finite GBW. OSR = 48;P =
equivalent to Fig. 4 with illustrative values of ns, 015 dB and f = f = 5
% ns, and V. The tangents to the
integrator output waveforms show that the SCR pulse response
of the ideal integrator has a time constant as chosen, approxi- results yield from a combination of (19) and (18). The simula-
mately 10 ns, while for smaller bandwidths the integrator pulse tions were performed for three different modulator feedbacks: a
response gets slower. Thus, the effective discharge time constant modulator with rectangular feedback waveform, the modulator
increases. with SCR feedback as shown in Fig. 4, and additionally a mod-
The behavior in Fig. 9 has been considered analytically [17]. ulator for comparison, where the feedback is generated by an
Therefore a differential equation for the voltage over the feed- ideal voltage-controlled voltage source (VCVS), whose input is
back capacitor is derived out of Fig. 4. This equation has an ideal SCR pulse. The latter makes the SCR discharge pulse
been solved with an initial condition . Due to independent from the virtual ground movement.
complexity reasons, the general solution is not given. For the The performance of the NRZ modulator in Fig. 11 approx-
ideal case, this generla solution reduces to a simple first-order imately decreases below [2], while the modulator with
differential equation and can be solved to ideal SCR pulse generated with the VCVS approximately needs
a factor of 2 higher bandwidth. This matches also well with the
(21) calculation result from (19). In contrast, the pure SCR feedback
shows a slightly lower GBW requirement than the NRZ modu-
lator, which is due to charge conservation on the feedback ca-
which is the ideal voltage over a capacitor, charged on , and
pacitor. and thus the lack of a feedback gain error through finite
discharged over to (virtual) ground.
GBW. Nonetheless, at low GBW values and high input ampli-
The nonideal solution yields a multipole system, which can
tudes distortion appears, and for similar SNR performance ap-
be modeled by a delayed single pole system in the time domain,
proximately the same GBW value as for the NRZ implementa-
which is a well-known technique in control systems theory [16].
tion is required.
It turns out that especially the induced change of the effective
time constant of the SCR pulse discharged on a finite GBW
integrator is significant. C. Finite Slew Rate of the Integrators
Fig. 10 graphically illustrates the calculated, relative increase To our knowledge, all publications on CT modulators
of the resulting feedback time constant due to finite GBW of deal with finite slew rate only in simulations. It would go beyond
the integrators for different designed values of . Note that the the scope of this paper to give a general theory on this topic,
calculated results match well with the simulations: E.g., in Fig. 9 therefore only the following considerations are given to provide
with and the tangent is crossing at ns a basic insight.
. For and Fig. 10 gives . In modulator designs, the first integrator shows the
This increase of the effective time constant of the SCR pulse highest power consumption [2], [18]. Therefore, the achieve-
will decrease the possible reduction of the jitter sensitivity, ment of a certain slew rate at this point will require the most
which is exponentially dependent on in (8). effort. Furthermore, any errors entering at later integrators are
The influence of finite GBW on the IBN of an SCR-feedback highly suppressed. Thus, in the following, only the slew rate of
modulator is shown in Fig. 11, where the shown calculation the first integrator is taken into account.
882 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005
(22)
its maximum SNR could not be achieved [8]. In contrast, the low power integrator implementation [8], as discussed in Sec-
second SCR implementation shows an almost ideal behavior tion V-B. The integrators were implemented as in [2]. This is
and gives a large increase of both the maximum SNR and the also the reason, why the second SCR modulator with the higher
dynamic range over the NRZ feedback implementation, since sampling frequency, but with almost the same GBW of the in-
it lacks the large feedback resistors and their noise contribution tegrators, shows an increased jitter sensitivity compared to the
in the NRZ modulator. 1st implementation.
Fig. 17 shows the measured spectrum and the corresponding
integrated IBN for the original NRZ feedback modulator and
VII. CONCLUSION AND OUTLOOK
the first implementation of the SCR modulator [8] under the
influence of white clock jitter with % . Obviously, In this paper, we have shown a possibility to avoid the disad-
the IBN floor of the NRZ modulator is severely increased. In vantage of increased clock jitter sensitivity in CT modulators by
contrast, the SCR feedback shows still the ideal IBN floor due using an exponentially pulse shaped feedback waveform derived
to circuit noise from Fig. 15. from a modified SC circuit. The new architecture has been given
In Fig. 18, the measured IBN over clock jitter is plotted for the the name SCR feedback. The ideal modulator behavior as well
NRZ feedback modulator [2] as well as for the first [8] and the as the nonidealities of concern were regarded analytically and by
second SCR modulator. The NRZ modulator starts to decrease simulations. Additionally, successful implementation and mea-
from its ideal resolution [2] for % . In contrast, the surement results confirm the approach.
SCR feedback modulators show a factor of 10 or even a factor The given SCR feedback architecture should be seen as an
of 20 less clock jitter sensitivity. exemplary implementation of a pulse shaped feedback DAC in
Compared to the ideal jitter behavior, the increased measured CT modulators in order to reduce the jitter sensitivity, while
sensitivity of the SCR modulators arises from the finite GBW, other implementations are possible:
884 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005
[21] theoretically derived a sine-wave shaped feedback DAC, Maurits Ortmanns (S’04–M’05) received the
while [20] used the SCR feedback in combination with a simple Dipl.-Ing. (M.Sc.) degree in electrical engineering
from the Saarland University, Saarbruecken, Ger-
current source DAC. Additionally, a square root or linearly de- many, in 1999, and and the Dr.-Ing. (Ph.D.) degree
caying pulse form can easily be derived. Also combinations with from the Albert Ludwigs University, Freiburg,
more sophisticated voltage controlled current or voltage sources Germany, in 2004, both with highest honors.
In 1997 and 1998, he was with the Research
would be promising approaches. Nonetheless the main idea re- Center Karlsruhe, Germany, and with EXAR, Inc.,
mains, which is having a decaying pulse shaped feedback wave Fremont, CA, as an Engineering Intern. In 1999, he
form in a CT modulator to reduce its sensitivity to clock joined the Institute of Microelectronics, Saarland
University, where he was a Research Assistant. In
jitter. 2001, he moved to the Institute of Microsystem Technology, Albert Ludwigs
University, where he worked in the field of continuous-time sigma–delta
modulator design until March 2004. Since April 2004, he is with sci-worx
REFERENCES GmbH, Hannover, Germany, where he is working in the field of mixed-signal
[1] E. J. van der Zwan and E. C. Dijkmans, “A 0.2-mW CMOS 61 modu- and analog circuits for biomedical implants and high-speed circuits. His main
lator for speech coding with 80 dB dynamic range,” IEEE J. Solid-State research interests include mixed-signal circuit design, smart microsensors, and
Circuits, vol. 31, no. 12, pp. 1873–1880, Dec. 1996. biomedical applications.
[2] F. Gerfers, M. Ortmanns, and Y. Manoli, “A 1.5-V, 12-bit power effi-
cient continuous-time third-order 61 modulator,” IEEE J. Solid-State
Dr. Ortmanns received the German Association of Engineers (VDI) Award
for the best Master’s degree and the German Association of Electrical Engi-
Circuits, vol. 38, no. 8, pp. 1343–1352, Aug. 2003. neers (VDE) Award for the best Master’s thesis in electrical engineering at the
[3] J. A. Cherry and W. M. Snelgrove, “Excess loop delay in contin- University of Saarland in 1999. He is member of the German National Aca-
uous-time delta-sigma modulators,” IEEE Trans. Circuits Syst. II, demic Foundation since 1994.
Analog Digit. Signal Process., Analog Digit. Signal Process., vol. 46,
no. 4, pp. 376–389, Apr. 1999.
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sigma modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal
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[5] H. Tao, L. Toth, and J. M. Khoury, “Analysis of timing jitter in bandpass (M.Sc.) degree in electrical engineering from the
sigma-delta modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Gerhard Mercator Universiy, Duisburg, Germany,
Signal Process., vol. 46, no. 8, pp. 991–1001, Aug. 1999. in 1996, and the Ph.D. degree form Albert-Ludwigs
[6] M. Ortmanns, F. Gerfers, and Y. Manoli, “Jitter insensitive feedback
DAC for continuous-time 61 modulators,” in Proc. IEEE Int. Conf.
University, Freiburg, Germany, in 2005.
In 1997, he joined the Institute of Micro-
Electronics, Circuits, and Systems, 2001, pp. 1049–1052.
[7] O. Oliaei and H. Aboushady, “Jitter effects in continuous time 61 mod- electronics, Saarland University, Saarbruecken,
Germany, where he was engaged in analog and
ulators with delayed return-to-zero feedback,” in Proc. Int. Conf.Elec-
tronics, Circuits, and Systems, Sep. 1998, pp. 351–354. mixed-signal circuit design. In 2002, he joined the
[8] M. Ortmanns, F. Gerfers, and Y. Manoli, “A continuous-time 61 mod- Institute of Micro System Technique (IMTEK),
Albert Ludwigs University, Freiburg, Germany.
ulator with reduced jitter sensitivity,” in Proc. Eur. Solid-State Circuits
Conf., 2002, pp. 287–290. Since April 2003, he is with Philips Semiconductor Starnberg, Germany, where
[9] A. Berkovitz and I. Rusnak, “FFT processing of randomly sampled he is currently working on high-speed low-power clock and data recovery
harmonic signals,” IEEE Trans. Signal Process., vol. 40, no. 11, pp. (CDR) circuits for high-speed video receivers. His main research interests
2816–2819, Nov. 1992. are low-voltage, low-power analog circuit design, sigma–delta modulation,
[10] M. Ortmanns, F. Gerfers, and Y. Manoli, “Fundamental limits of insen-
sitivity in discrete and continuous-time 61 modulators,” in Proc. IEEE
analog-to-digital conversion, clock and data recovery circuits and sensor
readout.
Int. Symp. on Circuits and Systems, 2003. Mr. Gerfers is member of the German Association of Electrical Engineers
[11] L. Doerrer, “A 10-bit, 3 mW continuous-time sigma-delta ADC for (VDE).
UMTS in a 0.12 um CMOS process,” in Proc. Eur. Solid-State Circuits
Conf., 2003.
[12] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Con-
verters. New York: IEEE Press, 1997.
[13] A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, “Optimal Yiannos Manoli (M’82) received the B.A. degree
parameters for AS modulators topologies,” IEEE Trans. Circuits Syst. (summa cum laude) in physics and mathematics from
II, Analog Digit. Signal Process., vol. 45, no. 9, pp. 1232–1241, Sep. Lawrence University, Appleton, WI, the M.S. degree
1998. in electrical engineering and computer science
[14] O. Oliaei, “Design of continuous-time sigma-delta modulators with ar- from the University of California, Berkeley, and the
bitrary feedback waveform,” IEEE Trans. Circuits Syst. II, Analog Digit. Dr.-Ing. degree in electrical engineering from the
Signal Process., vol. 50, no. 8, pp. 437–444, Aug. 2003.
Gerhard Mercator University, Duisburg, Germany,
[15] G. Gielen, K. Francken, E. Martens, and M. Vogels, “An analytical inte-
gration method for the simulation of continuous-time 16 modulators,” in 1978, 1980, and 1987, respectively.
From 1980 to 1984, he was at the University of
IEEE Trans. Computer-Aided Design, vol. 23, no. 3, pp. 389–399, Mar.
2004. Dortmund, Germany, working in the field of digital
[16] M. Ortmanns, F. Gerfers, and Y. Manoli, “Compensation of finite gain- and analog MOS integrated circuit design with an
bandwidth induced errors in continuous-time sigma-delta modulators,” emphasis on analog–digital (A/D) and digital–analog (D/A) converters. In 1985,
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 51, no. he joined the Fraunhofer Institute of Microelectronic Circuits and Systems,
6, pp. 1088–1100, Jun. 2004. Duisburg, where he established a design group for microsystem and micro-
[17] , “Influence of finite integrator gain bandwidth on CT sigma delta controller integrated circuits. In 1996, he joined the Department of Electrical
modulators,” in Proc. IEEE Int. Symp. on Circuits and Systems, 2003. Engineering, University of Saarland, Saarbruecken, Germany, where he held
[18] F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vazquez, Top-Down the Chair of Microelectronics. His research interests were focused on the design
Design of High-Performance Sigma-Delta Modulators. Norwell, MA: of low-voltage/low-power mixed-signal CMOS circuits and very large-scale
Kluwer , 1999.
[19] R. van Veldhoven, “Triple-mode continuous-time 61 modu-
integration embedded system design and design methodology. In July 2001,
he was appointed Chair of Microelectronics at the Institute of Microsystem
lator with switched-capacitor feedback DAC for GSM-EDGE/
Technology (IMTEK) of the Albert Ludwig University, Freiburg, Germany. His
CDMA2000/UMTS receiver,” IEEE J. Solid-State Circuits, vol. 38, no.
12, pp. 2069–2076, Dec. 2003. current research interests are the design of low-voltage/low-power mixed-signal
[20] M. Ortmanns, F. Gerfers, and Y. Manoli, “A continuous-time 61 mod- CMOS circuits, sensor read-out and A/D and D/A converters.
Prof. Manoli has served on the committees of a number of conferences and
ulator with switched capacitor controlled current mode feedback,” in
Proc. Eur. Solid-State Circuits Conf., 2003. was Program Chair (2001) and General Chair (2002) of the IEEE International
[21] S. Luschas and H.-S. Lee, “High-speed 61 modulators with reduced Conference on Computer Design (ICCD). He is a member of Mortar Board, Phi
timing jitter sensitivity,” IEEE Trans. Circuits Syst. II, Analog Digit. Beta Kappa, German Association of Electrical Engineers (VDE), and German
Signal Process., vol. 49, no. 11, pp. 712–720, Nov. 2002. Association of Engineers (VDI).