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6, December 2011
762
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
0.75
1 M = Ar / Ac Modulation Index
3
0.75 Ar For Q 1 & Q3
Ar Scope 1
, ,… 1 Ac For Q 2 & Q4
Ac Scope 2
Single Pulse Width
Modulation
Scope
g
C
C
The DF of each (or nth) harmonic component is defined as IGBT /Diode
Voltage
IGBT /Diode 1
m
- v
E
E
Measurement
+
DC 1
Load
g
C
C
1 4 IGBT /Diode 2 IGBT /Diode 3
m
E
E
D. Lowest Order Harmonic
Vout
THD signal
Total Harmonic
Vo11
Vo1
Vo3
Vo5
Vo7
Vo9
Vo
than or equal to 3% of the fundamental component.
Scope 8
300
TABLE I: RESULTS FOR SPWM
n Von HFn DFn THD 250
1 258.78 200
763
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
The pulses for each half cycle are shown in fig. 9 and 10.
0.14
0.1
0.08
0.06
0.04
0.02
0
3 4 5 6 7 8 9 10 11 12 13
Fig. 9. Q1 and Q3 gating signal for MPWM
0.014
0.012
0.01
0.004
0.002
0
3 4 5 6 7 8 9 10 11 12 13
Ac 200
Scope
0.86 Ar For Q 2 & Q4
Ar
Multiple Pulse Width 150
Modulation Scope 1
100
Scope 2
g
C
g
C
50
IGBT /Diode 1
IGBT /Diode
Voltage
- v
m
E
m
Measurement
E
0
0 2 4 6 8 10 12 14
DC 1
Fig. 12. Von for MPWM
Load
g
g
C
0.35
IGBT /Diode 2 IGBT /Diode 3
m
m
E
0.3
0.25
0.2
Vout
THD signal
Total Harmonic
Von 0.15
Distorsion
Vo11
0.1
Vo1
Vo3
Vo5
Vo7
Vo9
Vo
0.05
Scope 26 0
3 4 5 6 7 8 9 10 11 12 13
of multiple pulse width is high but is lower than that of single 0.025
0.01
0
TABLE II: RESULTS FOR MPWM 3 4 5 6 7 8 9 10 11 12 13
764
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
180
120
1 Ac For Q 2 & Q4
60
g
C
C
40
m
E
E
0
DC 1 0 2 4 6 8 10 12 14
Load
g
C
C
IGBT /Diode 2 IGBT /Diode 3
v+
Voltage
-
m
m
E
E
Measurement
0.4
0.35
Vout
0.3
THD signal
Von Total Harmonic
Distorsion 0.25
Vo11
Vo1
Vo3
Vo5
Vo7
Vo9
Vo
0.2
0.15
Scope 22
Scope 17
Scope 18
Scope 19
Scope 20
Scope 21
Scope 23 Scope 1 Scope 26
0.1
0
3 4 5 6 7 8 9 10 11 12 13
TABLE III: RESULTS FOR SIPWM Fig. 20. HFn for SiPWM
n Von HFn DFn THD
-3
x 10
2.5
1 176
3 0.003 1.7046E-05 1.8939E-06 2
The pulses for each half cycle are shown in fig.16 and 17. 0
3 4 5 6 7 8 9 10 11 12 13
Fig. 18 contains output voltage waveform. Fig. 21. DFn for SiPWM
0.8
M = Ar / Ac Modulation Index
Ac Scope
.8 Ar For Q 2 & Q4
Ar Scope 1
Modified Sinusoidal Pulse
C
g
distortion is 21.81% at modulation index of 0.8. The AC gain IGBT /Diode IGBT /Dio de 1
m
m
E
E
Lo ad
g
C
C
+
-
Voltage
v
Measurement
IGBT /Diode 2 IGBT /Dio de 3
m
E
THD signal
Von
Vo3
Vo5
Vo7
Vo9
Vo
applied at input. Spectrum for Von, HFn and DFn are shown in Scope 2
Scope 26
fig. 19, 20, and 21 respectively. Scope 22Scope 17Scope 18Scope 19Scope 20Scope 21Scope 23
765
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
IGBT /Diode 2 Pulse IGBT /Diode 3 IGBT /Diode 6 Pulse IGBT /Diod
de 7
v+
-
Voltage Measurement
THD signal
Total Ha
armonic
Von
Vo11
Vo1
Vo3
Vo5
Vo7
Vo9
Vo
coompared to that
t of sinussoidal pulse width modullation Scope
w
when 220 VDCC is applied at input.
i Spectruum for Von, HF
Fn and
D n are shown in fig. 26, 27,, and 28 respeectively.
DF Fig. 29. Sim
mulink model for pphase displacemeent control
250
200
Fiig. 30 and 31 contains
c the gaating signals for
fo inverter 1 and
a
Fig. 32 and 33 conntains the gatiing signals forr inverter 2.
150
100
50
0
0 2 4 6 8 10 12 14
0.3
0.25
0.2
0.15
Fig. 31. Gating
G Q2 and Q4 for inv
signal for Q verter 1
0.1
0.05
0
3 4 5 6 7 8 9 10 11 12 13
Fig. 27. HF
Fn for MSiPWM
0.01
0.009
0.008
0.007
0.004
0.003
0.002
0.001
0
3 4 5 6 7 8 9 10 11 12 13
Fig. 28. DF
Fn for MSiPWM
Fig. 33. Gating
G signal for Q
Q2 and Q4 for inv
verter 2
766
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
140
and compared by other signal known as modulating signal,
120 frequency of modulated signal is the desired output
100 frequency. The projected plan is to change the straight
80
technique by means of microcontroller. The adaptation of the
60
40
microcontroller gets the elasticity to modify the real-time
20 control program without extra modifications in hardware. It
0
0 2 4 6 8 10 12 14 is of small size and low cost control circuit for the single
Fig. 35. Von for phase displacement control phase inverter.
0.35
To achieve the control system an Atmel AT89S52
0.3
microcontroller was used [7]. Fig. 38 offered the AT89S52
assignment of pins for the control scheme of SiPWM in
single phase full bridge inverter system. The Atmel
0.25
0.2
microcontroller is used as the compensator circuit to build the
0.15 plan of controller easier, more trustworthy and mainly to
0.1
decrease their size and components. The control circuit that
can do all for a whole circuit is implemented with the help of
0.05
small separate Atmel microcontroller entrenched in the
0
3 4 5 6 7 8 9 10 11 12 13 DC-AC converter system.
Fig. 36. HFn for phase displacement control
B. Single Phase Full Bridge Inverter
0.04
0.01
0.005
waveform. Fig. 39 presents the circuit for a single phase full
0
3 4 5 6 7 8 9 10 11 12 13
bridge inverter. It is an electronic power converter that is
important as a boundary between the power input and the
Fig. 37. DFn for phase displacement control load. The inverter presented in fig. 39 has a DC voltage
source, four switching elements Q1, Q2, Q3 and Q4 and load.
F. Comparison of Voltage Control Signal Techniques
The switching element accessible now a day, such as BJTs,
Table. 6 present the comparison of voltage control signal GTOs, MOSFETs, IGBTs, MCT’s and SIT’s can be worn as
techniques with the help of their performance parameter a switch. They are substituting the relays, magnetic switches
especially amplitude of the fundamental component and and other magnetic components as the inverter switching
THD.
devices. This makes use of microcontroller becomes more
TABLE VI: COMPARISON OF VOLTAGE CONTROL SIGNAL TECHNIQUES significant. The full bridge single phase inverter has two legs,
Performance SPWM MPWM SiPWM MSiPWM PDM left or right or ‘A’ phase leg and ‘B’ phase leg.
Parameter Each leg consists of two power semiconductor devices
Vo1 258.78 230 176 208.78 198.02
THD 46.16% 38.60% 21.81% 28.88% 48.35%
connect in series. The output is taken from the midpoints of
the phase leg A and phase leg B. Each power semiconductor
767
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
switch has an anti-parallel diode. The diodes provide another environment. After that outputs are provided to gate driving
pathway for the output ac current if the power devices are circuit which includes four self-directed electrically-isolated
forced to turn OFF. For example, if lower IGBT in the ‘A’ IGBT drivers. At input side 220 VAC is rectified to produce
phase leg is conducting and carrying current towards the DC voltages which acts as DC supply voltage for Single
negative DC bus, this current would ‘commutate’ into the Phase Full Bridge Inverter for conversion from VDC to VAC.
diode across the upper IGBT of the’ A’ phase leg, if the lower Capacitor is used as a filter to minimize the ripples in DC
IGBT is OFF. Control of inverter’s circuit is done by voltages to get almost pure DC voltages. Capacitor is
changing the on time of the phase leg A and phase leg B connected on DC bus parallel to Inverter circuit. Fig.41.
lower and upper IGBT by the provision of, both are not shows the over-all diagram of the system.
turned ON at the similar time, to keep away from a short
D. Isolation Circuit
circuit of DC link.
To provide isolation between the microcontroller circuit,
that is operated at 5V and inverter circuit, which has high
voltage and current rating, isolation circuits are used. This is
implemented with the help of opto-coupler 817c. Fig. 42
presents the opto-coupler circuit.
Q2
Q1 Fig. 40. Switching plan for single phase full bridge inverter
switching plan that is worn in this research. The turn OFF and
ON device 1 (Q1) and device 4 (Q4) are restricted by SiPWM
1 obtained from port 2.2 of Atmel microcontroller. Whereas Isolation Circuit using
Opto-Isolators
the turn OFF and ON device 2 (Q2) and device 3 (Q3) are
restricted by SPWM 2 obtained from port 2.3 of Atmel
microcontroller. Both SiPWM 1 and SiPWM 2 worn the
similar voltage control signal produced through the AT89S52 Gate Driver Circuit
of microcontroller desires to be separated for safety and Fig. 41. Flow of hardware development
protection between a potentially unsafe and a secure
768
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
G Experimentaal Results
G.
Fig. 47 annd 48 show ws the gating pulses using Fig. 47. Ouutput AC
m r and fig. 49 shows the AC
microcontroller A output vooltage
w
waveform.
VCC 33pF
VI. CONC
CLUSION
GND
10uF
1k Thhis paper pressents analysiss of different voltage contrrol
signaal techniques used for singgle phase full bridge invertter.
Matllab models forfo voltage coontrol signal techniques and a
31
30
29
18
19
8
7
6
5
4
3
2
1
9
P1 7
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
EA
AL E
PS EN
RST
XTAL2
XTAL1
P3.0/RXD
P3.1/TX D
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
P0
P3.6/WR
P2.7 /A1 5
P2.6 /A1 4
P2.5 /A1 3
P2.4 /A1 2
P2.3 /A1 1
P2.2 /A1 0
P3.7/RD
P3
P2.1/A9
P2.0/A8
P3.5/T1
P3.4/T0
technniques for thhe single phaase full brid dge inverter area
0/AD0
7/RD
28
27
26
25
24
23
22
21
32
33
34
35
36
37
38
39
SiPWM 2
SiPW M1
funddamental com mponent of A AC load volltage and tootal
monic distortioon. Best voltaage control siignal techniquue,
harm
sinussoidal pulsee width m modulation, is practicaally
100k
+5V
100k
+5V
100k
+5V
100k
+5V impllemented for single
s phase innverter of full bridge type and
a
100 100 100 100 expeerimental results are presentted.
ACKNOWLEEDGMENT
+15V +15V
ndeed we coulld not have acchieved anyth
In hing without thet
+15V +15V
guiddance of Allahh Almighty, m most mercifull of all. We are a
thank kful for the paatience and coourage he has given us duriing
+5V
HO
O
HO
VDD +5V the course
c of this project and bbesides it. Thaanks are due, to
VDD VB
HIN
VB
B
VSS
0.47uF 0.47uF
VS
HIN ALL LAH, the Merrciful; Truly H HE is the besst provider. Best
SD LOAD
SD
LIN
wishhes and prayerrs of parents aalways play an n important roole
++15V VCC
LIN
VSS COM
M
VC
CC +15V
0.47uF
0.47uF
COM
VSS in th
he success. We W are very thhankful to ourr parents whoom
LO
O
LO
prayyers and encouuragement givve us courage to t come up with
w
Fig. 44. Over-all
O circuit wortth reporting reesult. May AL LLAH Almig ghty keep in thhis
worlld and here aftfter (AMEEN)). Finally, worrds alone cannnot
exprress the Thankks we owe to our Parents for f their endleess
efforrts, encourageement and Assistance. Witho out their help we
w
could d not have reached
r this ffar. Their paatience, suppoort,
tolerrance and blesssings were the driving forcce for us.
REFEREENCES
[1] M. H. Rashid, “P Power Electronicss Circuits, Devicees, and Applicatioons,”
3rd ed, Prentice Hall
H Intl, ch.6, pp.. 248-260. 2007.
[2] D. N. Sonawane, M. S. Sutaone, B. N. Choudharii, and A. Badurkkar,
“FPGA Implemeentation of Simpllified SVPWM Algorithm
A for Thhree
Phase Voltage Source
S Inverter,” International Jo ournal of Compuuter
Fig. 45. Gating signal for Q1and Q3
769
International Journal of Computer and Electrical Engineering, Vol. 3, No. 6, December 2011
and Electrical Engineering, Vol.2, No.6, December, pp. 1010-1017. Athar Hanif, is Assistant Professor of Electrical Engineering Department,
2010. The University of Lahore, Pakistan, since 2004. He has Bachelor Degree in
[3] S. L. Jung, M. Y. Chang, J. Y. Jyang, H.-S. Huang, L.C. Yeh, and Y. Y. Electrical Engineering from UET, Taxila, Pakistan in the year of 2003; he
Tzou, “Design and implementation of an FPGA-based control IC for received Master Degree from UET, Lahore, Pakistan in the year of 2008. He
the single-phase PWM inverter used in an UPS,” in Proc. 2nd Int.Conf. is currently pursuing doctoral research at UET, Lahore. He has eight years of
Power Electronic Drive Syst. (PEDS’97), May 1997, pp. 344–349. teaching experience. His fields of interest include Power Electronics,
[4] A. M. Trzynadlowski; “Introduction to modern power electronics,” Control Systems, Robotics, Control for Power Electronics Circuits, and
Wiley Inter-science, 1998. Simulation and Modeling.
[5] S. Jeevananthan, P. Dananjayan, and S. Venkatesan, “A Novel Asim Mukhtar, has obtained his Bachelor Degree in Electrical Engineering
Modified Carrier PWM Switching Strategy for Single-Phase from the University of Lahore, Pakistan in the year of 2009. He is presently a
Full-Bridge Inverter,” Iranian Journal of Electrical and Computer research scholar. He is working in the area of DC to AC converters.
Engineering, Summer Fall - Special Section on Power Engineering,
Vol. 4, No. 2, pp. 101-108, Tehran, Iran, 2005. Umar Farooq, did his B.Sc. and M.Sc. both in Electrical Engineering from
[6] N. Aphiratsakun, S. R. Bhaganagarapu, and K. Techakittiroj, University of Engineering & Technology Lahore in 2004 and 2010
“Implementation of a Single-phase Unipolar Inverter Using DSP respectively. He is currently with the Department of Electrical Engineering,
TMS320F241,” AU J.T. Vol.8, No. 4, pp 191-195, Apr. 2005. University of The Punjab Lahore. His research interests include the
[7] “Atmel AT89s52 datasheet” .[Online] Available: application of intelligent techniques to problems in control engineering,
http://www.atmel.com/dyn/resources/prod_documents/doc1919.pdf robotics and power electronics
[8] B. Ismail and S. T, “Development of a Single Phase SPWM
Microcontroller-Based Inverter,” First International power and Abid Javed, has obtained his Bachelor and Master Degree in Electrical
Energy conference PEC, November, 2006, p. 437. Putrajaya, Malaysia: Engineering from UET Lahore, Pakistan in 2000 and 2004 respectively.
IEEE. Now he is work towards PhD degree in Electrical Engineering in UET
[9] Rectifier, I. IR2110(-1-2) (S) PbF/IR2113(-1-2) (S) PbF HIGH AND Lahore. His areas of interest are Power Electronics, Analysis of Electrical
LOW SIDE DRIVER Data Sheet. Data Sheet No. PD60147 rev.U. Machines, Artificial Intelligence, and Machine Learning.
770