Ex.No.

: 1 Date :

SIMULATION OF BASIC LOGIC GATES USING VERILOG HDL

Aim:
To study the simulation of basic logic gates.

Software required:
Xilinx ISE 9.2i

Theory:

Simulation is a functional emulation of circuit design through software program that

uses modules to replicate how a system will perform in terms of timing and results. Here we
use xilinx ISE simulation.

 AND:

This gate performs logical multiplication. It has two or more inputs and a single
output. This will give a high input only when all the inputs are high and if anyone of the
input is low the output will be low.

 OR:

This gate performs logical addition. It has two or more inputs and single output. This
will give a high output, when anyone input is high. It will give a low output only when all
inputs are low.

 NOT:

This gate performs the operation of complementary or inversion. It has one input and
one output. When the given input is low, the output will be high. If the input is high, the
output will be low.

 XOR:

This gate performs comparison operation. It has two or more inputs and single output.
This will give a high output when the two inputs are different. It produces the output zero
when the inputs are same.
Procedure:
 To study the xilinx ISE simulation tool, open xilinx project navigator.
 Create a new project and choose FPGA device as Spartan 3E. Then create new
verilog program file.
 After creating verilog program, save the program file into project.
 Select behavioral simulation in the source window.
 Right click the verilog file to create a test bench waveform. In the test bench
waveform, assign the input values and save it.
 In the process window expand the design utilities and run the ISE simulator.
 At the end of simulation we will get a report such as simulation was successful in the
report window. Simulation result is verified with the functionality of the circuit.

Result:
Thus the simulation of logic gates was studied using verilog HDL.
 SIMULATION OF BASIC LOGIC GATES USING VERILOG HDL

AND GATE
Program

OR GATE

Program

NOT GATE

Program
EX-OR GATE

Program

AND GATE

LOGIC SYMBOL
OR GATE

LOGIC SYMBOL

EX-OR GATE
NOT GATE

LOGIC SYMBOL
Ex.no : 2 Date:

SYNTHESIS OF COMBINATIONAL CIRCUITS

Aim:
To study the synthesis tools of combinational circuits.
Software required:
Xilinx ISE 9.2i

Theory:
Synthesis is an automatic method of converting a higher level abstraction synthesis
tools convert the design description in HDL to gate level net list. This gate level net list
consists of information regarding gates used in the design and interconnection between gates.
To convert the HDL description to gate level net list, three steps typically occur
 HDL description is translated to an optimized Boolean description usually consisting
of primitive gates such as AND and OR gates, flip flops and latches. This is
functionality correct hit.
 Boolean optimized algorithm is executed. This Boolean equivalent description is to
procedure optimized Boolean description.
 This optimized Boolean description mapped to actual logic gates by making use of a
technology library of a process.

Procedure:
 Open xilinx project navigator.
 Create a new project and choose FPGA devices as Spartan 3Eor Spartan ISE (xcs
3s4001 XC 3s500E).
 Then create new dialog verilog program file.
 After creating verilog program, save this program file into project.
 Select behavioral simulation in the source window.
 In the source window get the sources for synthesis and implementation.
 Expand the design utilities in the process window and run the synthesis tool.
 The model is converted into net list file.
 Under synthesis tool, we have several options such as view synthesis tool view RTL
mapping.
  After synthesis we can view synthesis report, RTL schematic, technological mapping
using above option.
 Synthesis report and RTL schematics are enclosed.

Result
Thus the synthesis of combinational circuits was studied using verilog HDL.
 HALF ADDER

Program
 FULL ADDER
Program

CODE CONVERTERS
BINARY TO GRAY
Program
 GRAY TO BINARY
Program

PARALLEL ADDER
Program
 2 TO 4 DECODER
Program

3 TO 8 DECODER
Program
 HALF ADDER
DATA FLOW MODELLIG

GATE LEVEL MODELLING

BEHAVIOURAL MODELLING

Full adder

DATA FLOW MODELLING

GATE LEVEL MODELLING

BEHAVIOURAL MODELLING
Binary to gray

Gray to binary
3 to 8 decoder

2 to 4 decoder
Parallel adder
Ex.no.3 Date:

SIMULATION OF D-FLIPFLOP,T-FLIPFLOP,PRIORITY ENCODER,RIPPLE

COUNTER

AIM:
To study the simulation of D-FF and T-FF ripple counter and ripple adder.

APPARATUS REQUIRED:
Xilinx ISE 9.21

THEORY:
Simulation is a functional emulation of circuit design through software program that
uses modules to replicate how a system will perform in terms of timing and results. Here we
use Xilinx Ise software.

PROOCEDURE:
 To study the xilinx ISE simulation tool, open xilinx project navigator.
 Create a new project and choose FPGA device as Spartan 3E. Then create new
verilog program file.
 After creating verilog program, save the program file into project.
 Select behavioral simulation in the source window.
 Right click the verilog file to create a test bench waveform. In the test bench
waveform, assign the input values and save it.
 In the process window expand the design utilities and run the ISE simulator.
 At the end of simulation we will get a report such as simulation was successful in the
report window. Simulation result is verified with the functionality of the circuit.

RESULT:
Thus the simulation of D-flipflop,T-flipflop,Ripple Counter and Priority Encoder
were Studied using VERILOG HDL
D FLIP-FLOP:

T FLIP-FLOP:

PRIORITY ENCODER:

1) Data flow modeling:

RIPPLE COUNTER:
Module t_ripple_counter_4bit;
Reg count,reset;
Wire a0,a1,a2,a3;
Ripplr mo(a3,a2,a1,a0,count,reset);
Always
# 5 count =count;
Initial
Begin
Count=1’b0;
Reset=1’b1;
#4 reset=1’b0;
End
Initial # 170 finish
End module
Module ripplr(a3,a2,a1,a0,count,reset);
Output a3,a2,a1,a0;
Input count,reset;
Comp_D_flipflop(a0,count,reset());
Comp_D_flipflop(a1,count,reset());
Comp_D_flipflop(a2,count,reset());
Comp_D_flipflop(a3,count,reset());
Endmodule
Module
Comp_D_flipflop(Q,CLK,reset);
Output Q;
Input CLK,reset;
Reg Q;
Input CLK,reset;
Reg Q;
If(reset)Q<=1’b0;
Else Q<=#2 Q;
endmodule

D FLIP-FLOP
T FLIP FLOP:

RIPPLE COUNTER
INPUT
A0=0
A1=0
A2=1
A3=0

PRIORITY ENCODER:
EX.NO: 4 DATE:

SIMULATION OF HALF ADDER,2 TO 1 MUX, 4 TO1 MUX,1 TO 2 DEMUX,

1 TO 4 DEMUX

AIM
To study the simulation of Half adder,2 to 1 mux,4 to1 mux,1 to 2 demux,1 to 4
demux.
SOFTWARE REQUIRED
Xilinx ISE 9.2i
THEORY
Simulation is a functional emulation of circuit design through software program that
uses modules to replicate how a system will perform in terms of timing and results. Here we
use xilinx ISE simulation.

PROCEDURE
 To study the xilinx ISE simulation tool, open xilinx project navigator.
 Create a new project and choose FPGA device as Spartan 3E. Then create new
verilog program file.
 After creating verilog program, save the program file into project.
 Select behavioral simulation in the source window.
 Right click the verilog file to create a test bench waveform. In the test bench
waveform, assign the input values and save it.
 In the process window expand the design utilities and run the ISE simulator.
 At the end of simulation we will get a report such as simulation was successful in the
report window. Simulation result is verified with the functionality of the circuit.

RESULT
Thus the simulation of Half adder,2 to 1 mux,4 to1 mux,1 to 2 demux,1 to 4 demux
using verilog HDL.
PROGRAM

HALF ADDER

Dataflow modelling:

module half(a,b,s,c);
input a,b;
xor ha(s,a,b);
and ha1(c,a,b);
endmodule

Structural modeling:

module half(a,b, s,c);

input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Behavioural modelling:

module half(a,b,s,c);
input a,bb;
output s,c;
reg s,c;
always@(a,b)
begin
if(a==0 & b==0)
begin s=0;c=0;end
if(a==0 & b==1)
begin s=1;c=0;end
if(a==1 & b==0)
begin s=1;c=0;end
if(a==1 & b==1)
begin s=0;c=1;end
end
endmodule

2 TO 1 MUX:

Dataflow modelling:

module mux(i0,i1,s0, y);

input i0,i1,s0;
output y;
assign y=(~s0)&i0|s0&i1;
endmodule
Structural modelling:
module mux(s,a,b,c)
input s,a,b;
output c;
wire a1,a2;
and mux1(a1,~s,a);
and mux2(a2,s,b);
or mux3(c,a1,a2);
endmodule

Behavioural modelling:
module mux(s0,s1,i0,i1,i2,i3,a)
input s0,s1,i0,i1,i2,i3,a)
output a;
wire a1,a2,a3,a4;
and mux1(a1,~s0,~s1,i0);
and mux2(a2,~s0,s1,i1);
and mux3(a3,s0,~s1,i2);
and mux4(a4,s0,s1,i3);
or mux5(c,a1,a2,a3,a4);
end module

4 TO 1 MUX
Program
Dataflow modeling
module mux(i0,i1,i2,i3,s0,s1, y);
input i0,i1,i2,i3,s0,s1;
output y;
assign y=(~s0)&(~s1)&i0|(~s0)&s1&i1|s0&(~s1)&i2|s0&s1&i3;
endmodule

Structural modeling
module mux(s0,s1,i0,i1,i2,i3,a)
input s0,s1,i0,i1,i2,i3;
output a;
wire a1,a2,a3,a4;
and mux1(a1,~s0,~s1,i0);
and mux2(a2,~s0,s1,i1);
and mux3(a3,s0,`s1,i2);
and mux4(a4,s0,s1,i3);
or mux5(c,a1,a2,a3,a4);
endmodule
Behavioural modelling:
module mux(i0,i1,i2,i3,s0,s1,y);
input i0,i1,i2,i3,s0,s1;
output y;
reg y;
always@(i0,i1,i2,i3,s0,s1);
begin
if(s0==0 & s1==0)
begin y=i0;end
if(s0==0 & s1==1)
begin y=i1;end
if(s0==1 & s1==0)
begin y=i2;end
if(s0==1 & s1==1)
begin y=i3;end
end
endmodule

1 TO 2 DEMUX:

Dataflow modelling:

module demux1(d,s0, y0,y1);

input d,s0;
output y0,y1;
assign y0=d&(~s0);
assign y1=d&s0;
endmodule

Structural modeling:
module demux(d,s0,y0,y1)
input d,s0;
output y0,y1;
wire y2;
not d1(y2,s0);
and d2(y0,y2,d);
and d3(y1,d,s0);
endmodule

Behavioural modelling:
module dem(d,s0,y0,y1);
input d,s0;
output y0,y1;
always@(d,s0)
begin
if(s0==0)
begin y0=d;y1=0;end
if(s1==1)
begin y0=0;y1=d;end
endmodule

1 TO 4 DEMUX:
Data flow modeling:
module demux2(d,s0,s1, y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
assign y0=d&(~s0)&(~s1);
assign y1=d&(~s0)&s1;
assign y2=d&s0&(~s1);
assign y3=d&s0&s1;
end module

Structural modelleing:
module dem(d,s,s1,y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
wire y4,y5;
not d1(y4,s0);
not d2(y5,s1);
and d3(y0,y4,y5);
and d4(y1,d,y4,s1);
and d5(y2,d,s0,y5);
and d6(y3,d,s0,s1);
endmodule

Behavioural modelling:
module dem(d,s0,s1,y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
reg y0,y1,y2,y3;
always@(d,s0,s1)
begin
if(s0==0 & s1==0)
begin y0=d;end
if(s0==0 & s1==1)
begin y1=d;end
if(s0==1 & s1==0)
begin y2=d;end
if(s0==1 & s1==1)
begin y3=d;end end
endmodule
OUTPUT:

2:1 mux

4:1 mux
1:4 demux

1:2 demux
Half adder
EX.NO: DATE:

SIMULATION OF HALF ADDER,2 TO 1 MUX,

4 TO1 MUX,1 TO 2 DEMUX,1 TO 4 DEMUX

AIM
To study the simulation of Half adder,2 to 1 mux,4 to1 mux,1 to 2 demux,1 to 4
demux.

SOFTWARE REQUIRED
Xilinx ISE 9.2i

THEORY
Simulation is a functional emulation of circuit design through software program that
uses modules to replicate how a system will perform in terms of timing and results. Here we
use xilinx ISE simulation.

PROCEDURE
 To study the xilinx ISE simulation tool, open xilinx project navigator.
 Create a new project and choose FPGA device as Spartan 3E. Then create new
verilog program file.
 After creating verilog program, save the program file into project.
 Select behavioral simulation in the source window.
 Right click the verilog file to create a test bench waveform. In the test bench
waveform, assign the input values and save it.
 In the process window expand the design utilities and run the ISE simulator.
 At the end of simulation we will get a report such as simulation was successful in the
report window. Simulation result is verified with the functionality of the circuit.

RESULT
Thus the simulation of Half adder,2 to 1 mux,4 to1 mux,1 to 2 demux,1 to 4 demux
using verilog HDL.
Program:

HALF ADDER:

Dataflow modelling:

module half(a,b,s,c);
input a,b;
xor ha(s,a,b);
and ha1(c,a,b);
endmodule

Structural modeling:

module half(a,b, s,c);

input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Behavioural modelling:

module half(a,b,s,c);
input a,bb;
output s,c;
reg s,c;
always@(a,b)
begin
if(a==0 & b==0)
begin s=0;c=0;end
if(a==0 & b==1)
begin s=1;c=0;end
if(a==1 & b==0)
begin s=1;c=0;end
if(a==1 & b==1)
begin s=0;c=1;end
end
endmodule

2 TO 1 MUX:
Dataflow modelling:
module mux(i0,i1,s0, y);
input i0,i1,s0;
output y;
assign y=(~s0)&i0|s0&i1;
endmodule
Structural modelling:

module mux(s,a,b,c)
input s,a,b;
output c;
wire a1,a2;
and mux1(a1,~s,a);
and mux2(a2,s,b);
or mux3(c,a1,a2);
endmodule

Behavioural modelling:
module mux(s0,s1,i0,i1,i2,i3,a)
input s0,s1,i0,i1,i2,i3,a)
output a;
wire a1,a2,a3,a4;
and mux1(a1,~s0,~s1,i0);
and mux2(a2,~s0,s1,i1);
and mux3(a3,s0,~s1,i2);
and mux4(a4,s0,s1,i3);
or mux5(c,a1,a2,a3,a4);
end module

4 TO 1 MUX:

Program:

Dataflow modeling:

module mux(i0,i1,i2,i3,s0,s1, y);

input i0,i1,i2,i3,s0,s1;
output y;
assign y=(~s0)&(~s1)&i0|(~s0)&s1&i1|s0&(~s1)&i2|s0&s1&i3;
endmodule

Structural modeling:

module mux(s0,s1,i0,i1,i2,i3,a)
input s0,s1,i0,i1,i2,i3;
output a;
wire a1,a2,a3,a4;
and mux1(a1,~s0,~s1,i0);
and mux2(a2,~s0,s1,i1);
and mux3(a3,s0,`s1,i2);
and mux4(a4,s0,s1,i3);
or mux5(c,a1,a2,a3,a4);
endmodule
Behavioural modelling:

module mux(i0,i1,i2,i3,s0,s1,y);
input i0,i1,i2,i3,s0,s1;
output y;
reg y;
always@(i0,i1,i2,i3,s0,s1);
begin
if(s0==0 & s1==0)
begin y=i0;end
if(s0==0 & s1==1)
begin y=i1;end
if(s0==1 & s1==0)
begin y=i2;end
if(s0==1 & s1==1)
begin y=i3;end
end
endmodule

1 TO 2 DEMUX:

Dataflow modelling:

module demux1(d,s0, y0,y1);

input d,s0;
output y0,y1;
assign y0=d&(~s0);
assign y1=d&s0;
endmodule

Structural modeling:

module demux(d,s0,y0,y1)
input d,s0;
output y0,y1;
wire y2;
not d1(y2,s0);
and d2(y0,y2,d);
and d3(y1,d,s0);
endmodule

Behavioural modelling:
module dem(d,s0,y0,y1);
input d,s0;
output y0,y1;
always@(d,s0)
begin
if(s0==0)
begin y0=d;y1=0;end
if(s1==1)
begin y0=0;y1=d;end
endmodule

1 TO 4 DEMUX:
Data flow modeling:
module demux2(d,s0,s1, y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
assign y0=d&(~s0)&(~s1);
assign y1=d&(~s0)&s1;
assign y2=d&s0&(~s1);
assign y3=d&s0&s1;
endmodule

Structural modelleing:
module dem(d,s,s1,y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
wire y4,y5;
not d1(y4,s0);
not d2(y5,s1);
and d3(y0,y4,y5);
and d4(y1,d,y4,s1);
and d5(y2,d,s0,y5);
and d6(y3,d,s0,s1);
endmodule

Behavioural modelling:
module dem(d,s0,s1,y0,y1,y2,y3);
input d,s0,s1;
output y0,y1,y2,y3;
reg y0,y1,y2,y3;
always@(d,s0,s1)
begin
if(s0==0 & s1==0)
begin y0=d;end
if(s0==0 & s1==1)
begin y1=d;end
if(s0==1 & s1==0)
begin y2=d;end
if(s0==1 & s1==1)
begin y3=d;end end
endmodule
OUTPUT:

2:1 mux

4:1 mux
1:4 demux

1:2 demux
Half adder