ASSIGNMENTS

MSc (IT)

SEMESTER-I

Student Name : HAILAY KIDU TEKLEHAIMANOT

Registration Number :10A03PIT10016
Subject Name : Computer Architecture
Subject Code : PITA
Country Name :ETHIOPIA
Faculty Name : K.Banu

Signature :

Date : 25/09/2010

Name:Hailay Kidu Teklehaimanot

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 Assignment – A
Answer all the Questions
(Answer Each Questions not less than 500 words)

1. What are status flags? How they are useful in determining the status of the CPU?

2. Explain about instruction pipeline and its associated difficulties?

Answers of Assignment A for the Course of Computer Architecture

Answer for Question No. 1

An instruction pipeline is a technique used in the design of computers and other digital
electronic devices to increase their instruction throughput (the number of instructions that can be
executed in a unit of time).

It is a technique for overlapping the execution of several instructions to reduce the execution
time of a set of instructions.

The fundamental idea is to split the processing of a computer instruction into a series of
independent steps, with storage at the end of each step. This allows the computer's control
circuitry to issue instructions at the processing rate of the slowest step, which is much faster than
the time needed to perform all steps at once. The term pipeline refers to the fact that each step is
carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)

An instruction pipeline reads consecutive instructions from memory while previous instructions
are being executed in other segments this causes instruction fetch and execute phases to overlap
and perform simultaneous operations.
One possible digression associated with such a scheme is that an instruction may cause a branch
out of sequence. In that case the pipeline must be emptied and all the instructions that have been
read from memory after the branch instructions must be discarded.

In order to speed up the operation of a computer system beyond what is possible with sequential
execution, methods must be found to perform more than one task at a time. One method for
gaining significant speedup with modest hardware cost is the technique of pipelining. In this
technique, A task is broken down into multiple steps, and independent processing units are
assigned to each step. Once a task has completed its initial step, another task may enter that step
while the original task moves on to the following step. The process is much like an assembly
line, with a different task in progress at each stage. In theory, a pipeline which breaks a process
into N steps could achieve an N-fold increase in processing speed. Due to various practical
problems, the actual gain may be significantly less.

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The concept of pipelines can be extended to various structures of interconnected processing
elements, including those in which data flows from more than one source or to more than one
destination, or may be fed back into an earlier stage. We will limit our attention to linear
sequential pipelines in which all data flows through the stages in the same sequence, and data
remains in the same order in which it originally entered.

Pipelining is most suited for tasks in which essentially the same sequence of steps must be
repeated many times for different data.

Instruction processing

The first step in applying pipelining techniques to instruction processing is to divide the task into
steps that may be performed with independent hardware. The most obvious division is between
the FETCH cycle (fetch and interpret instructions) and the EXECUTE cycle (access operands
and perform operation). If these two activities are to run simultaneously, they must use
independent registers and processing circuits, including independent access to memory (separate
MAR and MBR).

It is possible to further divide FETCH into fetching and interpreting, but since interpreting is
very fast this is not generally done. To gain the benefits of pipelining it is desirable that each
stage take a comparable amount of time.

A more practical division would split the EXECUTE cycle into three parts: Fetch operands,
perform operation, and store results. A typical pipeline might then have four stages through
which instructions pass, and each stage could be processing a different instruction at the same
time. The result of each stage is passed on to the next stage.

Several difficulties prevent instruction pipelining from being as simple as the above description
suggests. The principal problems are:

TIMING VARIATIONS: Not all stages take the same amount of time. This means that the speed
gain of a pipeline will be determined by its slowest stage. This problem is particularly acute in
instruction processing, since different instructions have different operand requirements and
sometimes vastly different processing time. Moreover, synchronization mechanisms are required
to ensure that data is passed from stage to stage only when both stages are ready.

DATA HAZARDS: When several instructions are in partial execution, a problem arises if they
reference the same data. We must ensure that a later instruction does not attempt to access data
sooner than a preceding instruction, if this will lead to incorrect results. For example, instruction
N+1 must not be permitted to fetch an operand that is yet to be stored into by instruction N.

BRANCHING: In order to fetch the "next" instruction, we must know which one is required. If
the present instruction is a conditional branch, the next instruction may not be known until the
current one is processed.

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INTERRUPTS: Interrupts insert unplanned "extra" instructions into the instruction stream. The
interrupt must take effect between instructions, that is, when one instruction has completed and
the next has not yet begun. With pipelining, the next instruction has usually begun before the
current one has completed.

Answer for Question No 2

It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit condition can be stored for further analysis. Status bits are also called condition-
code bits or flag bits.
The Figure 1 below shows the block diagram of an 8-bit ALU with a 4-bit status register. The
four status bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result of an
operation performed in the ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the bit is 0.
3. Bit Z (Zero) is set to 1 if the output of the ALU contains all O’s. It is cleared to 0
otherwise. In other words, Z = 1 if the output is zero and
Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two caries is equal to 1, and
cleared to 0 otherwise. This is the condition for an overflow when negative numbers are
in 2’s complement For the 8-bit ALU, V= 1 if the output greater than +127 or less than -
128.

Figure 1: Status register bit.

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 The status bits can be checked after an ALU operation to determine certain relationships
that exist between the values of A and B . If bit V is set after the addition of two signed
numbers, it indicates an overflow condition. If A is set after an exclusive-OR operation, it
indicates that A = B. This is so because x A x = 0, and the exclusive-OR of two equal
operands gives an all -O’s result which sets the Z bit. A single bit in A can be checked to
determine if it is 0 or a by masking all bits except the bit in question and then checking
the Z status bit. For example, let A = 101x1100, where x us the bit to be checked. The
AND operation of A with B = 00010000 produces a result 000x0000. If x =0, the Z status
bit is set, but if x =1, the Z bit is cleared since the result is not zero.

Example: A
Processor status flag

The 6510 CPU has an internal status register that consists of eight processor status flags, of
which seven are actually used. These flags are set or unset by the processor to give information
about the results of the latest executed machine language command. Many branch commands
for example make heavy use of the flags.

The flags are:

C - Carry: This flag shows when the result of the executed operation exceeds or goes below the
value range of one byte (00-FF)

Z - Zero: Will be set when the result equals zero

I -interrupt: This flag allows or disables maskable interrupts

D - Decimal: Switches the processor to decimal mode (BCD)

B - Break: This flag will be set when the processor is stopped due to a BRK command

- - Expansion bit: Not used, thus always set to 1.

V - Overflow: Shows when the result exceeds or goes below the value range of one byte (00-FF)
when the carry flag is already set. When executing the BIT command, the overflow flag shows
the sixth bit of thested byte.

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N - Negative: Is set when the result is bigger than 127 respectively if the highest bit is set. This is
needed for working with values in two’s complement.

Example : B

Flags
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.The most commonly used flags are
Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example,
after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-
flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an arithmetic
operation results in zero, the flip-flop called the Zero(Z) flag is set to one. Let say that the flags
are stored in the 8-bit register so that the programmer can examine these flags (data conditions)
by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor.
The conditions (set or reset) of the flags are tested through the software instructions. For
example, the instruction JC (Jump on Carry) is implemented to change the sequence of a
program when CY flag is set. The thorough understanding of flag is essential in writing assembly
language programs.

Example: C

CPU Flags and Data Manipulation

1. Adding and Subtracting Integers

 The ADD, INC (Increment), SUB, and DEC (Decrement) instructions have two
requirements:
o If there are two operands, only one operand can be a memory operand.
o If there are two operands, both must be the same size. For example,
 add ebx, eax ; Add two registers, result stored in EBX
 add eax, [ebx] ; Add register and a doubleword in memory
 add [value], 10h ; Add immediate value to a doubleword

2. The Processor Flags (Condition Codes)

 Processor status is described as condition codes, or status flags.

 Condition codes refer to the information about most recently executed instruction.
 For example, if decrementing a register produces zero value, the zero flag ZF is set by
the processor.
o (A programmer might say: zero condition has occurred.)
 Each flag is a single bit in the flag register, EFLAGS.
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  If last addition or subtraction produced a negative result, the sign flag SF is set.
 Sign flag SF is equal to the high-order bit of the result of an operation:
o 0 is positive,
o 1 is negative.

3. Carry Flag

 When numbers are added and subtracted, carry flag CF represents

o 9th bit, if 8-bit numbers added
o 17th bit, if 16-bit numbers added
o 33rd bit, if 32-bit numbers added
o and so on.
 With addition, the carry flag CF records a carry out of the high order bit. For example,
 mov al, -1
 add al, 1 ; AL = 0, ZF and CF flags are set to 1
 When a larger number is subtracted from the smaller one, the carry flag CF indicates a
borrow. For example,
 mov al, 6
 sub al, 9 ; AL = -3, SF and CF flags are set to 1

The result is -3, represented internally as 0FDh (binary 11111101).

4. Overflow Condition

 Arithmetic operations have a potential to run into a condition known as overflow.

 Overflow occurs with respect to the size of the data type that must accommodate the
result.
 Overflow indicates that the result was
o too large, if positive, or
o too small, if negative,

to fit in the original data type.

5. Overflow Condition, Cont

 When two signed 2's complement numbers are added, the overflow flag OF indicates one
of the following:
1. both operands are positive and the result is negative, or
2. both operands are negative and the result is positive.
 When two unsigned numbers are added, the carry flag CF indicates an overflow, that is,
o there is a carry out of the leftmost (most significant) bit.

6. Overflow Condition, Cont

 Computers don't know the difference between signed and unsigned binary numbers.

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  This is a good thing, because it makes logic circuits fast.
 This is also a bad thing, because distinguishing between signed and unsigned becomes
programmer's responsibility.
 Distinction between signed and unsigned data types is very important when detecting an
overflow after addition or subtraction.
 Correct approach to detect the overflow is to consider two separate cases:
1. Overflow when adding signed numbers is indicated by the overflow flag, OF.
2. Overflow when adding unsigned numbers is indicated by the carry flag, CF.

7. INC and DEC Instructions

 The INC instruction adds one to the destination operand,

while preserving the state of the carry flag CF:
o The destination operand can be a register or a memory location.
o This instruction allows a loop counter to be updated without disturbing the CF
flag.
 (Use ADD instruction with an immediate operand of 1 to perform an
increment operation that does update the CF flag.)
 The DEC instruction subtracts one from the destination operand,
while preserving the state of the CF flag.
o (To perform a decrement operation that does update the CF flag, use a SUB
instruction with an immediate operand of 1.)

8. INC and DEC Instructions, Cont.

 Especially useful for incrementing and decrementing counters.

 A register is the best place to keep a counter.
 The INC and DEC instructions
o always treat integers as unsigned values
o never update the carry flag CF, which would otherwise (i.e. ADD and SUB) be
updated for carries and borrows.
 The instructions affect the OF, SF, ZF, AF, and PF flags just like addition and subtraction
of one.

9. INC and DEC Example

 xor al, al ; Sets AL = 0. XOR instruction always clears OF and CF flags.

 mov bl, 0FEh
 inc bl ; 0FFh SF = 1, CF flag not affected.
 inc bl ; 000h SF = 0, ZF = 1, CF flag not affected.


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 

10. CLC, STC, CMC - Direct Carry Flag Manipulation

 The following instructions allow direct carry flag manipulation:

o CLC clears Carry Flag, CF = 0
o STC sets Carry Flag, CF = 1
o CMC complements Carry Flag, CF = NOT( CF ).

11. Overflow Flag Examples

 Examples of 8-bit signed and unsigned addition and subtraction:

 .DATA
 mem8 BYTE 39 ; 0010 0111 27
 ;
 .CODE
 ; Addition + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
++
 ; signed unsigned binary hex
 mov al, 26 ; Start with register 26 26 0001 1010 1A
 inc al ; Increment +1 +1
 ; ---- ----
 ; 27 27 0001 1011 1B
 add al, 76 ; Add immediate +76 +76 0100 1100 4C
 ; ---- ----
 ; 103 103 0110 0111 67
 add al, [mem8] ; Add memory +39 +39 0010 0111 27
 ; ---- ----
 mov ah, al ; Copy to AH -114 142 1000 1110 8E (OF)(SF)

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  add al, ah ; Add register + -114 +142 1000 1110 8E
 ; ---- ----
 ; 28 28 0001 1100 1C (OF)(CF)
 ; Subtraction- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 ; signed unsigned binary hex
 mov al, 95 ; Load register 95 95 0101 1111 5F
 dec al ; Decrement - 1 - 1
 ; ---- ----
 ; 94 94 0101 1110 5E
 sub al, 23 ; Subtract immediate - 23 - 23 1110 1001 E9
 ; ---- ----
 ; 71 71 0100 0111 47
 mov [mem8],122 ; Load memory
 sub al, [mem8] ; Subtract memory - 122 - 122 0111 1010 7A
 ; ---- ----
 ; -51 205 1100 1101 CD (SF)(CF):borrow
 mov ah, 119 ; Load register
 sub al, ah ; and subtract - 119 - 119 0111 0111 77
 ; ---- ----
 ; 86 86 0101 0110 56(OF)

 (OF) overflow flag indicates that result is too large to fit in the 8-bit destination operand:
o The sum of two positive signed operands exceeds 127.
o The difference of two negative operands is less than -128.
 (CF) carry flag indicates that the sum of two unsigned operands exceeded 255.
 (SF) sign flag indicates that result goes below 0.

12. The LAHF and SAHF Instructions

 LAHF instruction loads lower byte of the EFLAGS register into AH register.
 The lowest 8 bits of the flags are transferred:
o Sign
o Zero
o Auxiliary Carry
o Parity
o Carry
 Instruction format:
 lahf
 SAHF restores the value of lower byte flags. Format:
 sahf

13. The NEG Instruction

 The NEG instruction negates a value by finding 2's complement of its single operand.
 This simply means multiply operand by -1.
 When a positive value is negated the result is negative.
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  A negative value will become positive.
 Zero remains zero.
 For example,
 mov al, -1 ; Load register
 neg al ; AL now has 1

14. The SHL Instruction, Shift Logical Bit Left

 SHL is one of the Bit  Execution of SHL AL, CL :

Manipulation
Instructions:
 mov al, 75h
 mov cl, 3
 shl al, cl
 The instruction format is
o SHL destination,
count

where 1 <= count <= 31.

 All bits in the destination

operand are shifted left
count times.
 The less-significant bit
(LSB) is filled with 0 each
time.
 The most-significant bit
(MSB) is placed into carry
flag CF.
 Other flags are modified
according to the final
result.

 SHL is very useful for computing powers of 2 and multiplication by 2, since each time
binary number is shifted left, its numeric value doubles.

15. The SHR Instruction, Shift Logical Bit Right

 SHR does the opposite of SHL.

 Zeroes are shifted in from the left, right bits moved to CF.
o Operation of SHR:

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16. The SAR Instruction, Shift Arithmetic Right

 Same as SHR, except that  Operation of SAR CL, 1 :

most-significant bit (MSB) is
shifted back to itself.
 This preserves the original
sign of the destination
operand, because MSB is the
sign bit.
 Each shift divides the
destination operand by 2,
while preserving the sign.
 For example,
 mov cl, -74 ; 2's
complement of -74 is 0B6h
 sar cl, 1 ; CL is now -37,
or 0DBh
 Note that LSB is shifted into
the carry flag CF.

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